Command verification method, device, system, equipment, medium and program

Abstract

The embodiment of the invention provides a command verification method, device and system, equipment, a medium and a program. The method comprises the steps that a WRP verification configuration request is acquired; based on the WRP verification configuration request, configuring verification configuration information of a WRP command; wherein the verification configuration information at least comprises a data mode of a WRP command and a data width type of a memory; the data mode supports arbitrary configuration under a data mode bit width, and the data width type support configuration is any data width type in a plurality of data width types; wherein the configured data mode and the data width type are used for generating WRP data of the WRP command, and the WRP data serve as write-in data when the WRP command is verified. According to the embodiment of the invention, the verification flexibility and compatibility of the WRP command can be improved, and a basis is provided for improving the verification performance of the WRP command.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of design and testing technology, and specifically to a command verification method, apparatus, system, equipment, medium and program. Background Art

[0002] Logical system design (design for short) is the design of integrated circuits such as ASIC (Application Specific Integrated Circuit) and SOC (System On Chip); the design integrates a storage controller for access control to the memory, for example, the SOC design integrates a memory controller for access control to the memory. As a key component of the design, the storage controller's commands need to be verified when the design is tested.

[0003] In this context, as a command of the storage controller, how to provide a technical solution to verify the WRP (Write Pattern) command has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0004] In view of this, embodiments of the present application provide a command verification method, apparatus, system, device, medium, and program to verify the WRP command.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a command verification method, including:

[0007] Get WRP verification configuration request;

[0008] Based on the WRP check configuration request, configure the check configuration information of the WRP command; wherein the check configuration information at least includes a data mode of the WRP command and a data width type of the memory; the data mode supports arbitrary configuration under the data mode bit width, and the data width type supports configuration as any data width type among multiple data width types;

[0009] The configured data mode and data width type are used to generate WRP data of the WRP command, and the WRP data is used as write data when verifying the WRP command.

[0010] In a second aspect, an embodiment of the present application provides a command verification method, including:

[0011] Get WRP command;

[0012] Read the verification configuration information of the configured WRP command, the verification configuration information at least including the data mode of the WRP command and the data width type of the memory; wherein the data mode supports arbitrary configuration under the data mode bit width, and the data width type supports configuration as any data width type among multiple data width types;

[0013] Generate WRP data of the WRP command according to the data mode of the WRP command and the data width type of the memory;

[0014] The WRP data is written to the memory in order to verify the WRP command.

[0015] In a third aspect, an embodiment of the present application provides a command verification device, comprising at least: a register configuration module and a WRP writing module;

[0016] The register configuration module is used to configure the verification configuration information of the WRP command based on the WRP verification configuration request when the command verification device obtains the WRP verification configuration request; the verification configuration information at least includes the data mode of the configured WRP command and the data width type of the memory, wherein the data mode supports arbitrary configuration under the data mode bit width, and the data width type supports configuration as any data width type among multiple data width types;

[0017] The WRP write module is used to obtain a WRP command, read the verification configuration information of the configured WRP command; generate WRP data of the WRP command according to the data mode of the configured WRP command and the data width type of the memory; and write the WRP data into the memory to verify the WRP command.

[0018] In a fourth aspect, an embodiment of the present application provides a command verification system, comprising: a design to be tested and a verification device; the verification device is the command verification device as described in the third aspect above.

[0019] In a fifth aspect, an embodiment of the present application provides an electronic device comprising at least one memory and at least one processor, wherein the memory stores one or more computer execution instructions, and the processor calls the computer execution instructions to execute the command verification method as described in the first aspect above, and / or the command verification method as described in the second aspect above.

[0020] In a sixth aspect, an embodiment of the present application provides a storage medium, which stores one or more computer execution instructions, and when the computer execution instructions are executed, implement the command verification method as described in the first aspect above, and / or the command verification method as described in the second aspect above.

[0021] In the seventh aspect, an embodiment of the present application provides a computer program product, comprising one or more computer execution instructions, which, when executed, implement the command verification method as described in the first aspect above, and / or the command verification method as described in the second aspect above.

[0022] The command verification scheme provided by the embodiment of the present application can configure at least the data mode of the WRP command and the data width type of the memory based on the WRP verification configuration request during the configuration stage of the verification configuration information, wherein the data mode of the WRP command supports arbitrary configuration under the data mode bit width, and the data width type of the memory supports configuration as any data width type in a plurality of data width types; since the verification configuration information of the WRP command at least includes the configured data mode of the WRP command and the data width type of the memory, and the configured data mode and data width type can be used to generate the WRP data of the WRP command, and the WRP data is used as the write data when verifying the WRP command, the arbitrary configuration of the data mode of the WRP command and the data width type of the memory can make the verification of the WRP command applicable to the verification scenarios of memories with different data bit widths and arbitrary data modes, thereby increasing the verification scenarios supported by the verification WRP command, so that the verification flexibility and compatibility of the WRP command are improved. Therefore, the embodiment of the present application can improve the verification flexibility and compatibility of the WRP command, and provide a basis for improving the verification performance of the WRP command. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0024] Figure 1 An example diagram of a computer system.

[0025] Figure 2 An example diagram of a command verification system provided in an embodiment of the present application.

[0026] Figure 3 A flowchart of a command verification method provided in an embodiment of the present application.

[0027] Figure 4A A block diagram of a register configuration module provided in an embodiment of the present application.

[0028] Figure 4B A block diagram of a configuration register provided in an embodiment of the present application.

[0029] Figure 5Another flowchart of the command verification method provided in an embodiment of the present application.

[0030] Figure 6 A block diagram of the WRP write module provided in an embodiment of the present application.

[0031] Fig. 7A A block diagram of a WRP data slice generator provided in an embodiment of the present application.

[0032] Figure 7B An example diagram of generating a data slice provided in an embodiment of the present application.

[0033] Figure 7C Another example diagram of generating a data slice provided in an embodiment of the present application.

[0034] Fig.7D Another example diagram of generating a data slice provided in an embodiment of the present application.

[0035] Figure 8 A block diagram of a reading module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] In the case of designing an integrated storage controller, the WRP command is used as a command for the storage controller to write data to the memory. When the data written to the memory is repeated data (such as all zeros or all ones), the WRP command allows the data to be updated directly on the memory side without transmitting data through buses such as DQ (data line) and DQS (data strobe line), thereby achieving the purpose of reducing power consumption.

[0038] In an optional implementation, the storage to which the WRP command is applicable may be a memory, such as a DDR (Double Data Rate) memory, in particular a DDR5 SDRAM (Synchronous Dynamic Random-Access Memory); the corresponding storage controller may be a memory controller, such as a DDR memory controller, in particular a DDR5 memory controller. In other optional implementations, the storage to which the WRP command is applicable may also be a hard disk driven by a HDD (Hard Disk Drive), a NAND (NAND Flash Memory), an HBM (High Bandwidth Memory), and the like.

[0039] For ease of understanding, Figure 1 An exemplary diagram of a computer system is shown as follows: Figure 1 As shown, the design 110 is integrated with a storage controller 120, and the design 110 can perform access control on the memory 130 through the storage controller 120. For example, the design 110 can read and write data to the memory 130 through the storage controller 120. The design 110 is a logic system design such as a SOC design.

[0040] When the storage controller 120 reads and writes data to the memory 130, the bus can be used to transmit data, for example, DQ is used to transmit data, and DQS is used to synchronize data in the read and write operations to ensure accurate data transmission. If the data written to the memory is repeated data (for example, all zeros or all ones), then transmitting the data through buses such as DQ and DQS will cause unnecessary power consumption due to the frequent flipping of buses such as DQ and DQS. Therefore, the storage controller is designed with a WRP command, which is used to update the data directly at the memory end when the data written to the memory is repeated data, without transmitting the data through buses such as DQ and DQS, thereby reducing the flipping of buses such as DQ and DQS, and achieving the purpose of reducing power consumption.

[0041] That is to say, the WRP command is designed to save power consumption. It is a command that can update data in the storage (such as memory) without transmitting data to the storage (such as memory) through the bus. As a write command of a storage controller such as a memory controller, the WRP command can be written into the storage protocol. For example, the memory protocol of the memory controller (such as the DDR5 protocol) is written with the WRP command; and the WRP command can have a unique encoding (for example, the WRP command has a unique identifier or code in the command set of the storage controller such as the memory controller) to distinguish it from other commands of the storage controller.

[0042] Further integration Figure 1As shown, the memory 130 may be provided with a dedicated mode register 131 for the WRP command, and a storage array 132 for storing data; wherein the dedicated mode register 131 is used to define the data mode written into the memory by the WRP command, and the data mode may be all zeros, all ones or other preset repetitive data forms.

[0043] The value of the dedicated mode register of the WRP command can determine the data mode of the memory (such as the memory) to update the data when the WRP command is executed. That is to say, when executing the WRP command, the memory (such as the memory) can determine the data mode of the WRP command by checking the dedicated mode register, and update the data according to the data mode, so as to directly update the data on the memory side without having to transmit the data through DQ and DQS.

[0044] For example, if the value of the dedicated mode register of the WRP command is set to all zeros (i.e., the data mode of the WRP command is all zeros), the data repetition form of the data written to the memory is zero, so that when the WRP command is executed, all zeros can be written to the address specified by the WRP command, and the address here can be a data storage address in the storage array (such as a memory address, etc.); if the value of the dedicated mode register of the WRP command is set to all ones (i.e., the data mode of the WRP command is all ones), the data repetition form of the data written to the memory is one, so that when the WRP command is executed, all ones can be written to the address specified by the WRP command, and so on.

[0045] In one example, the dedicated mode register of the WRP command may be a MR (Model Register) 48 in a memory (e.g., memory), such as a mode register numbered 48 in the memory (e.g., memory). Furthermore, the dedicated mode register of the WRP command may have a data mode field to define the value of the data mode, thereby defining the data repetition form; the data mode field may be implemented by a preset bit range of the OP (Operation) of the dedicated mode register, for example, the preset bit range of the OP of the dedicated mode register may be used to define the value of the data mode. For example, the bit range of OP[7:0] of MR48 may be used as a data mode field to define the value of the data mode, wherein OP[7:0] may be regarded as a bit range from the 0th bit to the 7th bit (a total of 8 bits) of the OP of MR48.

[0046] It should be noted that the mode register may be a register in a memory (such as a memory) for storing configuration settings; accordingly, the dedicated mode register of the WRP command may be a register in a memory (such as a memory) for storing configuration settings such as data mode to control the operation of the memory (such as a memory) when the WRP command is executed. There may be multiple dedicated mode registers for the WRP command.

[0047] The WRP command is a write command introduced by the storage controller. During the operation of the storage controller (such as the memory controller), whether the WRP command can be correctly executed as expected has an important impact on the working performance of the storage controller (such as the memory controller). Therefore, when testing the design, it is necessary to verify the WRP command of the storage controller (such as the memory controller).

[0048] Based on this, the embodiment of the present application provides a solution for dynamically adjusting the verification configuration information of the WRP command to at least support the dynamic adjustment of the data mode of the WRP command and the data width type of the memory, so that the verification of the WRP command can be applicable to the verification scenarios of memories with different data bit widths and arbitrary data modes (that is, the data repetition form can be arbitrary, not limited to all zeros or all ones), thereby increasing the verification scenarios supported by the verification WRP command, so that the verification flexibility and compatibility of the WRP command can be improved. Accordingly, on the basis of dynamically adjusting the data mode of the WRP command and the data width type of the memory, the embodiment of the present application provides a corresponding WRP command verification solution to implement the verification process of the WRP command based on the verification configuration information of the WRP command.

[0049] Furthermore, the embodiment of the present application can also introduce dynamically adjustable WRP timing information into the verification configuration information of the WRP command to implement timing control in the verification process of the WRP command. Accordingly, the embodiment of the present application provides a WRP command verification scheme with timing control, so that the verification process of the WRP command can introduce timing verification to implement the timing correctness verification of the WRP command running process.

[0050] Based on the above ideas, the command verification scheme provided in the embodiment of the present application is introduced from the verification configuration process of the WRP command (the process of configuring the verification configuration information of the WRP command) and the verification process of the WRP command (the process of running the WRP command and performing verification).

[0051] As an optional implementation, Figure 2 An example diagram of a command verification system provided by an embodiment of the present application is shown as follows: Figure 2 As shown, the command verification system may include: a design to be tested 210 and a verification device 220. The design to be tested 210 may be regarded as a design to be tested, such as a SOC design to be tested; when the design to be tested 210 is tested, the WRP command of the storage controller 120 in the design to be tested 210 may be verified. The verification device 220 may be a device for verifying the WRP command, and the verification device may be a program device in a verification device (electronic device for verification), or a circuit device.

[0052] In an embodiment of the present application, the design to be tested 210 can set the verification configuration information of the WRP command for the verification device 220; accordingly, the verification device 220 can save the verification configuration information for verifying the WRP command, thereby providing a configuration basis for the verification process during the subsequent WRP command execution.

[0053] As an optional implementation, Figure 3 An optional flowchart of the command verification method provided in an embodiment of the present application is shown as an example. Figure 3 The method shown can be regarded as the process steps executed by the command verification method in the configuration stage of verifying the configuration information. It should be noted that the steps executed by each module device involved in the command verification method provided in the embodiment of the present application can be regarded as the functional content of each module device; that is, the functional content of each module device and the content of the described method can be referred to each other.

[0054] Combination Figure 2 and Figure 3 As shown, the command verification method (configuration phase of verifying configuration information) may include the following steps.

[0055] In step S310, the design to be tested transmits a WRP verification configuration request to the verification device.

[0056] In step S311, the verification device configures the verification configuration information of the WRP command based on the WRP verification configuration request; wherein the verification configuration information at least includes the data mode of the WRP command and the data width type of the memory.

[0057] In the embodiment of the present application, the WRP verification configuration request is used to request configuration of the verification configuration information of the WRP command. Optionally, the WRP verification configuration request can be a command signal and value information for setting the verification configuration information of the WRP command transmitted by the design under test to the verification device.

[0058] In an optional implementation, before verifying the WRP command, the design to be tested may transmit a WRP verification configuration request to the verification device, so that the verification configuration information for verifying the WRP command is saved in the verification device.

[0059] In an optional implementation, the verification configuration information may include at least the data mode of the WRP command and the data width type of the memory. Thus, the WRP verification configuration request transmitted by the design to be tested may include an MRW command (Model RegisterWrite) and value configuration information. Among them, the MRW command is used to configure the data mode of the WRP command, and the value configuration information is at least used to configure the data width type of the memory. Furthermore, when the verification device configures the verification configuration information of the WRP command based on the WRP verification configuration request, it may configure the data mode of the WRP command based on the MRW command; and, based on the value configuration information, at least configure the data width type of the memory.

[0060] It should be noted that the data mode of the WRP command configured by the verification device and the data width type of the memory can be used to generate WRP data of the WRP command, that is, the WRP data can be used as write data when verifying the WRP command, that is, the data written into the memory by the WRP command.

[0061] Furthermore, the verification configuration information may also include WRP timing information; the WRP timing information is used to control the timing when the WRP data is written. In an optional implementation, the value configuration information in the WRP verification configuration request may be used to configure the WRP timing information, so that when the verification device configures the verification configuration information of the WRP command based on the WRP verification configuration request, it may also configure the WRP timing information based on the value configuration information.

[0062] The following further describes the data mode of configuring the WRP command, the data width type of the memory, and the content of the WRP timing information.

[0063] For the relevant introduction of the data mode of the WRP command, reference can be made to the description of the corresponding part of the previous text, and an example thereof can be the value of MR48. When configuring the verification configuration information of the WRP command, the embodiment of the present application can configure the data mode of the WRP command, and the data mode of the WRP command supports arbitrary configuration under the data mode bit width. For example, the data mode of the WRP command can be configured as any data repetition form under the data mode bit width; wherein the data mode bit width can correspond to the bit width of the dedicated mode register, such as the 8-bit bit width of MR48. In other words, unlike the method of only being able to configure the data mode as a fixed all-0 or all-1, the embodiment of the present application can configure the data mode to any form under the data mode bit width, not limited to all-0 or all-1.

[0064] For example, taking the data pattern bit width as 8 bits and the data as binary, the data pattern can be any 8-bit value composed of 0 and 1 to express the data repetition form, not limited to all 0 or all 1; that is, all 0 or all 1 is only a form of data pattern, and the embodiment of the present application supports any 8-bit binary number composed of 0 and 1 as a data pattern, such as 11110000, 01010101, 10100101, etc. Of course, binary is only an optional data system form, and 8 bits is only an optional form of data pattern bit width. The embodiment of the present application can also support data patterns with other possible data system forms and data pattern bit width lengths, which can be determined according to actual conditions, and the embodiment of the present application is not limited.

[0065] In an optional implementation, the WRP verification configuration request of the design to be tested may include an MRW command for configuring a data mode; thus, the verification device may configure the data mode of the WRP command based on the MRW command. The MRW command is a command that can change the data mode of the WRP command (e.g., the value of a dedicated mode register of the WRP command); for example, the value in the dedicated mode register of the WRP command can be modified by the MRW command.

[0066] In an optional implementation, the data mode based on the WRP command supports configuration of any data repetition form under the data mode bit width, so that the data mode carried by the MRW command can be any data value under the data mode bit width. Furthermore, when the verification device obtains the WRP verification configuration request of the design to be tested, it can configure the data mode of the WRP command based on the MRW command in the WRP verification configuration request, such as configuring the value in the dedicated mode register of the WRP command (for example, the value of MR48).

[0067] The data width of a memory refers to the number of data bits that the memory supports transmitting in a unit clock cycle. Different numbers of data bits that the memory supports transmitting in a unit clock cycle may correspond to different data width types of the memory. For example, for memory (especially DRAM memory), the memory may have different data width types such as x4 (4bit), x8 (8bit), and x16 (16bit). Among them, x4 indicates that the memory supports transmitting 4 bits of data in a unit clock cycle, i.e., 4bit data; x8 indicates that the memory supports transmitting 8 bits of data in a unit clock cycle; and x16 indicates that the memory supports transmitting 16 bits of data in a unit time cycle.

[0068] When configuring the checksum configuration information of the WRP command, the embodiment of the present application can configure the data width type of the memory, and the data width type of the memory can be configured as any data width type among multiple data width types. In other words, unlike the way that the checksum of the WRP command is limited to the fixed data width type of the memory, the embodiment of the present application can implement the checksum support of the WRP command for any data width type among multiple data width types of the memory. For example, the embodiment of the present application can support the configuration of x4 、 Any data width type such as x8, x16, etc. to support x4 、 Perform WRP command verification on any memory data width type such as x8, x16, etc.

[0069] In an optional implementation, the WRP verification configuration request transmitted by the design under test may carry value configuration information, and the value configuration information may be used to configure at least the data width type of the memory. For example, the value configuration information may include at least a configuration value as the data width type of the memory to at least configure the data width type of the memory.

[0070] In an optional implementation, the data width type of the memory supports configuration as any data width type, so that the configuration value of the data width type of the memory carried by the value configuration information can be any data width type. Furthermore, when the verification device obtains the WRP verification configuration request of the design to be tested, it can configure the data width type of the memory based on the value configuration information in the WRP verification configuration request (specifically, it can be the configuration value of the data width type of the memory).

[0071] In an embodiment of the present application, the verification configuration information may include at least the data mode of the WRP command and the data width type of the memory, that is, after configuring the data mode of the WRP command and the data width type of the memory, the configured data mode and the data width type of the memory may at least form the verification configuration information.

[0072] In an optional implementation, whether the data pattern (such as the value of the MR48 mode register) expresses the data repetition form as a whole or as repeated data can be determined by the data width type of the memory. For example, for the data width type of x4, since each data storage unit of the memory outputs or receives 4-bit data (4-bit data), the data repetition form can be expressed by repeated data in the data pattern, for example, the lower 4-bit data and the upper 4-bit data in the 8-bit data pattern are repeated to express the data repetition form, so as to write the lower 4-bit data or the upper 4-bit data in the 8-bit data pattern to each data storage unit to achieve writing the repeated data to the memory. For another example, for the data width type of x8 or x16, since each data storage unit of the memory outputs or receives 8 bits or 16 bits of data, the data pattern can express the data repetition form as a whole (for example, the 8-bit data of the data pattern expresses the data repetition form as a whole), or can express the data repetition form by repeated data in the data pattern (for example, the lower 4-bit data and the upper 4-bit data in the data pattern are repeated), so as to write 8-bit repeated data or 16-bit repeated data to each data storage unit to achieve writing the repeated data to the memory.

[0073] In a further optional implementation, the verification configuration information may also include WRP timing information. For example, after configuring the data mode of the WRP command, the data width type of the memory and the WRP timing information, the configured data mode, the data width type of the memory and the WRP timing information may form the verification configuration information.

[0074] The WRP timing information can be the write operation timing of the WRP command, which is used to control the timing when the WRP data is written. In an optional implementation, the WRP timing information can determine the response time and efficiency of the write operation of the WRP command, such as the timing between the WRP write command and the timing between the WRP write command and the write data. Among them, the timing between the WRP write command and the write command refers to the time delay between the continuous write operations of the WRP command; the timing between the WRP write command and the write data refers to the time delay between the write command (used to activate a specific column address for data writing) and the actual start of writing data inside the memory. In an example, the WRP timing information can be expressed as CWL (CAS Write Latency, column address selection write delay), which can be understood as the time delay between the write command (used to activate a specific column address for data writing) and the write data in units of clock cycles inside the memory, that is, the delay for data to start writing to the memory after the column address is selected.

[0075] If the verification configuration information can also include WRP timing information, the value configuration information carried by the WRP verification configuration request transmitted by the design under test can also be used to configure the WRP timing information; for example, the value configuration information can also include a configuration value as the WRP timing information to at least configure the WRP timing information. Thus, the verification device can configure the WRP timing information based on the value configuration information.

[0076] The command verification scheme provided by the embodiment of the present application can configure at least the data mode of the WRP command and the data width type of the memory based on the WRP verification configuration request during the configuration stage of the verification configuration information, wherein the data mode of the WRP command supports arbitrary configuration under the data mode bit width, and the data width type of the memory supports configuration as any data width type in a plurality of data width types; since the verification configuration information of the WRP command at least includes the configured data mode of the WRP command and the data width type of the memory, and the configured data mode and data width type can be used to generate the WRP data of the WRP command, and the WRP data is used as the write data when verifying the WRP command, the arbitrary configuration of the data mode of the WRP command and the data width type of the memory can make the verification of the WRP command applicable to the verification scenarios of memories with different data bit widths and arbitrary data modes, thereby increasing the verification scenarios supported by the verification WRP command, so that the verification flexibility and compatibility of the WRP command are improved. Therefore, the embodiment of the present application can improve the verification flexibility and compatibility of the WRP command, and provide a basis for improving the verification performance of the WRP command.

[0077] In an optional implementation, the command verification method (configuration phase of verifying configuration information) provided in the embodiment of the present application is combined with Figure 2 As shown, the design under test 210 can set a configuration logic module 211, and the configuration logic module 211 can set part of the verification configuration information of the WRP command. Another part of the verification configuration information of the WRP command can be set by the storage controller 120 in the design under test 210.

[0078] As an optional implementation, the data mode of the WRP command (for example, the value of MR48) can be set by the storage controller 120 in the design under test 210. For example, the storage controller can configure the data mode of the WRP command through the MRW command; thus, the MRW command in the WRP verification configuration request transmitted by the design under test can be issued by the storage controller 120 in the design under test 210.

[0079] As an optional implementation, the data width type of the memory can be set by the configuration logic module 211 of the design under test 210; further, the WRP timing information can also be set by the configuration logic module 211 of the design under test 210. For example, the configuration logic module 211 can configure the data width type of the memory through the value configuration information, and further configure the WRP timing information. Thus, the value configuration information in the WRP verification configuration request transmitted by the design under test can be issued by the configuration logic module 211 in the design under test 210.

[0080] In an optional implementation, the verification device can obtain WRP command and value configuration information through different interfaces. As an optional implementation, combined with Figure 2 As shown, the verification device 220 may be provided with a storage control interface 221 and a data communication interface 222. Thus, when obtaining a WRP verification configuration request, the verification device may obtain an MRW command through the storage control interface 221 and obtain value configuration information through the data communication interface 222.

[0081] The storage control interface is an interface for transmitting commands of the storage controller, such as a communication interface between the storage controller and the physical layer; in one example, taking the storage device as a memory and the storage controller as a memory controller as an example, the storage control interface can be a memory control interface, such as an interface between the memory controller and the physical layer, such as DFI (DDR PHYInterface, DDR physical layer interface). That is to say, when the MRW command is issued by the storage controller, the MRW command can be regarded as a command of the storage controller to modify the data mode, so that the verification device can obtain the MRW command through the storage control interface (such as the DFI interface).

[0082] The data communication interface is an interface for transmitting data between components of a computer system, such as AXI (Advanced Extensible Interface). That is to say, when the value configuration information is sent by the configuration logic module, the value configuration information is regarded as data transmitted between components of a computer system, so that the verification device can obtain the value configuration information through the data communication interface (such as the AXI interface).

[0083] In an optional implementation, the verification configuration information can be configured in a register of the verification device, thereby combining Figure 2 As shown, the verification device 220 can be provided with a register configuration module 223, which is used to configure the verification configuration information based on the WRP verification configuration request when the verification device is commanded to obtain the WRP verification configuration request. The functional content of the register configuration module can be referred to Figure 3The steps and related introductions performed by the verification device in the method. For example, the register configuration module can configure the data mode of the WRP command based on the MRW command, and at least configure the data width type of the memory based on the value configuration information.

[0084] Example, combined Figure 2 As shown, the verification device 220 can further set a command decoder 224, so that the command decoder 224 can identify the command type of the command after obtaining the command transmitted by the storage controller of the design to be tested; if the command is identified as an MRW command, the MRW command can be transmitted to the register configuration module 223, so that the register configuration module 223 configures the data mode of the WRP command based on the MRW command. For example, the command decoder 224 can identify the command type of the command transmitted by the storage control interface (such as the DFI interface).

[0085] In an optional implementation, combined with Figure 2 As shown, the value configuration information transmitted by the configuration logic module of the design to be tested can be directly imported into the register configuration module, so that the register configuration module configures at least the data width type of the memory (and can also configure the WRP timing information) based on the value configuration information. For example, there can be a direct data channel between the data communication interface (such as the AXI interface) and the register configuration module, so that the value configuration information transmitted through the data communication interface (such as the AXI interface) can be directly imported into the register configuration module.

[0086] In a further optional implementation, the register configuration module can configure various verification configuration information through multiple registers. For example, the data mode of the WRP command, the data width type of the memory, and the WRP timing information can have corresponding registers in the register configuration module. Furthermore, the data mode based on the WRP command is configured in the form of a command using the MRW command, while the data width type and WRP timing information of the memory are configured by value configuration. Therefore, the register configuration module can set a corresponding MRW transmitter for the MRW command to identify the data mode carried by the MRW command and configure specific values ​​for the register corresponding to the data mode of the WRP command. As an optional implementation, Figure 4A An optional block diagram of a register configuration module provided in an embodiment of the present application is shown as an example. Figure 4A As shown, the register configuration module 223 may include: a configuration register 410 and a MRW transmitter 420 .

[0087] The MRW transmitter 420 may identify a data pattern carried by the MRW command, and configure the identified data pattern to the configuration register 410 .

[0088] The configuration register 410 can save the data mode of the MRW command configured by the MRW transmitter 420, and at least configure and save the data width type of the memory based on the value configuration information. Further, the configuration register 410 can also configure and save the WRP timing information based on the value configuration information.

[0089] In an optional implementation, combined with Figure 4A As shown, the configuration register 410 may include: a dedicated mode register 411 of the WRP command, a data width type register 412, and a timing register (such as a CWL register) 413.

[0090] For example, after the command decoder 224 identifies that the command transmitted by the storage control interface (such as the DFI interface) is an MRW command, the command decoder 224 can transmit the MRW command to the MRW transmitter in the register configuration module; thereby, the MRW transmitter can identify the instructions and operation code of the MRW command, that is, the MRW command can include the instructions and operation code of the MRW command, the instruction of the MRW command can indicate to perform a write operation to a dedicated mode register, and the operation code can specify the value to be written, that is, the data mode; further, the MRW transmitter can configure the data mode of the WRP command to the dedicated mode register, so as to enable the register configuration module to configure the data mode of the WRP command based on the MRW command.

[0091] The dedicated mode register 411 of the WRP command may be a register in the configuration register 410 for storing the data mode of the WRP command, such as MR48. The data mode of the WRP command stored in the dedicated mode register 411 may be arbitrarily configured under the data mode bit width.

[0092] The data width type register 412 may be a register in the configuration register 410 for storing the data width type of the memory. The data width type stored in the data width type register may be configured arbitrarily from a variety of data width types, such as x4. 、 Any one of the data width types such as x8, x16, etc. For example, the data width type stored in the data width type register can be set by the value configuration information, for example, the configuration value of the data width type of the memory in the value configuration information can set the data width type stored in the data width type register.

[0093] The timing register 413 may be a register in the configuration register 410 for storing WRP timing information; the timing register is applicable when the verification configuration information includes WRP timing information. For example, the WRP timing information stored in the timing register may be set by the value configuration information, for example, the configuration value of the WRP timing information in the value configuration information may set the WRP timing information stored in the timing register.

[0094] In an optional implementation, the configuration register 410 may have multiple dedicated mode registers, such as dedicated mode registers for multiple memory channels. Taking the memory as a memory as an example, the configuration register 410 may have dedicated mode registers for multiple memory channels. For example, taking the memory as a DRAM (Dynamic Random Access Memory, dynamic random access memory) memory as an example, and the dedicated mode register as an MR48, Figure 4B The optional block diagram of the configuration register provided in the embodiment of the present application is shown as an example. Figure 4A and Figure 4B As shown, MR48 may include MR48 of multiple DRAM channels, such as Figure 4B Taking 8 DRAM channels as an example, they are divided into DRAM0_MR48 (MR48 of the zeroth DRAM channel), DRAM1_MR48 (MR48 of the first DRAM channel), DRAM2_MR48 (MR48 of the second DRAM channel), DRAM3_MR48 (MR48 of the third DRAM channel), DRAM4_MR48 (MR48 of the fourth DRAM channel), DRAM5_MR48 (MR48 of the fifth DRAM channel), DRAM6_MR48 (MR48 of the sixth DRAM channel), and DRAM7_MR48 (MR48 of the seventh DRAM channel). The MR48 of a DRAM channel can have an 8-bit width, for example Figure 4B Bits 0 to 7 of the example can be used to store the configured data mode.

[0095] It should be noted that Figure 4B MR48 of 8 DRAM channels is only an example. The number of memory channels (such as DRAM channels) and the number of dedicated mode registers (such as MR48) set by the configuration register can be set according to actual conditions, and the embodiments of the present application are not limited thereto.

[0096] In further optional implementations, the embodiments of the present application may also perform other configurations of the WRP command, such as power management configuration (based on the WRP command, power consumption can be reduced, and the WRP command may also involve configuration of power management policies, such as adjustment configuration of power supply voltage and frequency, etc.), priority configuration (for example, configuring the priority of data written by the WRP command, etc.). Thus, in an optional implementation, the configuration register may also include other configurations (such as other configuration registers).

[0097] It can be seen that the embodiments of the present application can make the verification of the WRP command applicable to the verification scenarios of memories with different data bit widths and arbitrary data patterns, thereby increasing the verification scenarios supported by the verification WRP command, improving the verification flexibility and compatibility of the WRP command, and providing a basis for improving the verification performance of the WRP command.

[0098] As an optional implementation, based on the command verification scheme provided by the embodiment of the present application in the configuration stage of verifying the configuration information, the embodiment of the present application provides a command verification scheme when the WRP command is running to realize the verification of the WRP command. In the optional implementation, running the WRP command is to write data to the memory (the data is in a repeated form). After the data is written to the memory, the correctness of the WRP command can be verified by reading the data of the memory and comparing whether the read data is consistent with the expected written data. Thus, as an optional implementation, when the WRP command needs to be verified, the design to be tested (specifically, it can be the storage controller in the design to be tested) can send the WRP command to the verification device; thus, the verification device runs the WRP command to write data to the memory, and runs the read command corresponding to the WRP command to read data from the memory and output; then, the design to be tested (specifically, it can be the storage controller in the design to be tested) can compare whether the data read by the read command is consistent with the data expected to be written by the WRP command to verify the correctness of the WRP command.

[0099] Based on this, in an optional implementation, Figure 5 Another optional flowchart of the command verification method provided in the embodiment of the present application is shown as an example. Figure 5 The method shown can be regarded as the process steps of the command verification method in the WRP command verification stage. Figure 5 The method shown can be implemented by a verification device. It should be noted that the steps performed by the various modules of the verification device involved in the command verification method provided in the embodiment of the present application can be regarded as the functional content of the various modules of the verification device; that is, the functional content of the various modules of the verification device and the content of the method can be referenced to each other.

[0100] Combination Figure 2 and Figure 5 As shown, the command verification method (WRP command verification stage) can be executed by a verification device, and the method can include the following steps.

[0101] In step S510, a WRP command is obtained.

[0102] After the design under test transmits a WRP verification configuration request to the verification device and completes configuration of the verification configuration information of the WRP command, the design under test can transmit a WRP command to the verification device to trigger the verification device to run the WRP command and the corresponding read command.

[0103] In an optional implementation, the WRP command may be issued by a storage controller of the design to be tested, so that the WRP command may be transmitted to a storage control interface (eg, a DFI interface) of the verification device.

[0104] In step S511, the read command corresponding to the WRP command is determined.

[0105] In an optional implementation, after obtaining the read command, the verification device can determine the read command corresponding to the WRP command. That is, in the process of verifying the WRP command, the WRP command transmitted by the design under test is used not only to trigger the verification device to execute the WRP command, but also to trigger the verification device to determine the read command corresponding to the WRP command, so that the verification device completes writing data to the memory by executing the WRP command, and completes reading and outputting the written data from the memory by executing the read command corresponding to the WRP command.

[0106] In an optional implementation, the verification device can decode the WRP command and generate a read command corresponding to the WRP command. Figure 2 As shown, the command decoder 224 can obtain the WRP command of the design to be tested, thereby decoding the WRP command to obtain a read command corresponding to the WRP command. For example, the command decoder 224 can identify the type of command transmitted by the storage control interface (such as the DFI interface) of the verification device, and if the command is a WRP command, decode the WRP command to obtain a read command corresponding to the WRP command.

[0107] In step S512, the check configuration information of the configured WRP command is read, and the check configuration information at least includes the data mode of the WRP command and the data width type of the memory.

[0108] In an optional implementation, step S511 and step S512 may be performed in parallel. The process of reading data by the read command involved in step S511 may refer to the description of the relevant part below.

[0109] In step S513, WRP data of the WRP command is generated according to the data mode of the WRP command and the data width type of the memory.

[0110] In step S514, the WRP data is written into the memory.

[0111] In a further optional implementation, after executing step S513 (i.e., generating the WRP data of the WRP command), the verification device may also cache the WRP data. Furthermore, the verification configuration information based on the configured WRP command may also include WRP timing information, and the verification device may write the cached WRP data into the memory after delaying the WRP timing information.

[0112] It should be noted that the above steps S512 to S514 can be regarded as the process of the verification device implementing the writing of WRP data during the verification process of the WRP command. Figure 2 As shown, a WRP writing module 225 may be provided in the verification device 220, and the WRP writing module may be used to execute the above steps S512 to S514, that is, to execute the process of writing WRP data.

[0113] It should be noted that the configuration process of verifying the configuration information can refer to the description of the corresponding part of the previous text, which will not be repeated here.

[0114] For ease of explanation, the process of writing WRP data provided by the embodiment of the present application is described below in conjunction with the optional structure of the WRP write module.

[0115] As an optional implementation, Figure 6 An optional block diagram of a WRP write module provided in an embodiment of the present application is shown as an example. Figure 6 As shown, the WRP write module may include: a WRP transmitter 610 , a WRP data slice generator 620 , a WRP data assembler 630 , a WRP data buffer 640 , a write delayer 650 , a WRP data loader 660 , and a memory 670 .

[0116] The WRP transmitter 610 can be used to obtain a WRP command and trigger the WRP data slice generator 620 to work according to the WRP command. For example, the WRP transmitter 610 can obtain the WRP command transmitted by the command decoder 224, that is, the WRP command recognized by the command decoder 224 can be transmitted to the WRP transmitter 610 of the WRP write module.

[0117] In an optional implementation, the WRP command may include an instruction and a write address of the WRP command; wherein the instruction of the WRP command may indicate writing data to the memory in a WRP manner, i.e., indicating a write operation of the WRP; the write address is the address where the data is written to the memory (e.g., the address where the data is written to the memory, etc.). It should be noted that, since the WRP command only transmits the command and does not transmit the data, the WRP command carries the write address of the data and does not contain the specific data to be written; the data written to the memory by the WRP command may be determined by the data mode of the WRP command configured in the configuration stage and the width type of the memory.

[0118] In an optional implementation, the write address (i.e., the write address of the WRP command) can support addressing according to multiples of the set data write granularity, so that the embodiment of the present application supports the storage space size corresponding to the write address (for example, the memory space size corresponding to the write address) being a multiple of the data write granularity.

[0119] In one example, the data write granularity may be 8 bytes, so that the write address of the WRP command may support the writing of 8×N bytes of data, where N is an integer greater than 0. Further, taking the data mode of the WRP command as 8 bits (8 bits) as an example, when the write address supports addressing in multiples of 8 bytes, the minimum data length that can be written by the WRP command at a single address is 64 bits (1 byte = 8 bits).

[0120] In a further optional implementation, the embodiment of the present application can refresh the data mode of the WRP command once (such as refreshing the value saved by MR48 once) when the data written by the WRP command reaches the minimum data length of the WRP command at a single address, so as to change the write data of the WRP command. Among them, the minimum data length of the WRP command at a single address can be determined by the data mode bit width and the data write granularity. For example, in the above example, the WRP command writes every 64 bits of data, then the data mode of the WRP command can be refreshed once (such as refreshing the value saved by MR48 once), thereby changing the write data of the WRP command. It should be noted that the specific value of the data mode bit width can be set according to the actual situation, and the specific value of the data write granularity can be set according to the actual situation, so that the minimum data length of the WRP command at a single address can be set and adjusted according to the specific situation, and the embodiment of the present application is not limited.

[0121] In an embodiment of the present application, the verification device can generate WRP data of the WRP command based on the data mode of the WRP command configured in the verification configuration information and the data width type of the memory. Optionally, the process of generating WRP data can be divided into: a process of forming a data slice and a process of assembling WRP data. Among them, the process of forming a data slice can be implemented by a WRP data slice generator, and the process of assembling WRP data can be implemented by a WRP data assembler.

[0122] In an optional implementation, the WRP data slice generator 620 may be configured to generate a data slice of a set data slice length according to a configured data mode of the WRP command and a data width type of the memory.

[0123] In an optional implementation, the WRP data slice generator 620 can read the data mode of the WRP command configured in the dedicated mode register (e.g., MR48), and read the data width type of the memory configured in the data width type register; thereby, according to the data mode of the WRP command and the data width type of the memory, a data slice is generated, and the length of the generated data slice is the set data slice length. It should be noted that the set data slice length can be determined according to the memory architecture (e.g., memory architecture), interface design, and application requirements, and the embodiments of the present application are not limited thereto; in a possible example, the set data slice length can be 32 bits (bits), and of course the embodiments of the present application can also support setting the data slice length to 16 bits, 64 bits, etc.

[0124] As an optional implementation method for generating data slices, an embodiment of the present application can define data pattern reading methods corresponding to multiple data width types, so that based on the configured data width type, the embodiment of the present application can select the data pattern reading method corresponding to the configured data width type from the data pattern reading methods corresponding to the multiple data width types; and then read the content of the data pattern based on the data pattern reading method corresponding to the configured data width type, and form a data slice of the set data slice length based on the content of the read data pattern.

[0125] Optionally, different data width types correspond to different data pattern reading methods. For example, the data pattern reading method may include the number of reads of a dedicated mode register (such as MR48) and the data read bits of the data pattern; thus, the number of reads of the dedicated mode register in the data pattern reading method corresponding to different data width types is different, and / or the data read bits of the data pattern are different.

[0126] Furthermore, in an optional implementation, the WRP data slice generator can read the content of the data pattern from the special mode register corresponding to the read quantity of the dedicated mode register corresponding to the configured data width type and the data read bit of the data pattern according to the data read bit; and based on the content of the read data pattern, form a data slice of a set data slice length.

[0127] As an optional implementation, Fig. 7A An optional block diagram of a WRP data slice generator provided in an embodiment of the present application is shown as an example. Fig. 7A As shown, the WRP data slice generator may include: a demultiplexer (Demultiplexer, DMUX) 710, a data selector 720 corresponding to a plurality of data width types, and a multiplexer (Multiplexer, MUX) 730.

[0128] It should be noted that the main function of the demultiplexer is to distribute an input signal to one of multiple outputs; the demultiplexer has an input line and multiple output lines, and at least one control line (selection line). The demultiplexer can determine the output to which the input signal is sent based on the state of the control line.

[0129] As an optional implementation, the demultiplexer 710 of the embodiment of the present application can be used to obtain a trigger signal of the WRP transmitter, and based on the data width type of the configured memory (such as the data width type configured in the data width type register), the trigger signal is passed to the data selector corresponding to the data width type to trigger the data selector corresponding to the data width type to work. For example, the input signal of the demultiplexer can be a trigger signal of the WRP transmitter, the state of the control line can be determined by the data width type of the configured memory, and the multiple outputs can be data selectors corresponding to various data width types; that is, the data width type of the configured memory (the state of the control line) determines the data selector to which the demultiplexer transmits the trigger signal (input signal). Optionally, the trigger signal of the WRP transmitter can be, for example, a WRP command.

[0130] The number of data selectors may correspond to the number of data width types of the memory, and one data width type of the memory corresponds to one data selector, so that for multiple data width types of the memory, the embodiment of the present application may set multiple data selectors, that is, data selectors corresponding to the multiple data width types of the memory. A data selector of a data width type may have a data pattern reading method that matches the corresponding data width type (such as the number of reads of the matching dedicated mode register, and the data read bits of the data pattern, etc.).

[0131] Thus, the data selector can be used to: when triggered to work, read the content of the data pattern in the data pattern reading method corresponding to the data width type corresponding to the data selector; and form a data slice of a set data slice length based on the content of the read data pattern.

[0132] For ease of example, Fig. 7A Taking data width types of x4, x8, and x16 as examples, a data selector 721 of x4, a data selector 722 of x8, and a data selector 723 of x16 are illustrated.

[0133] Among them, the x4 data selector 721 can be used to read the content of the data pattern in a data pattern reading method corresponding to the x4 data width type, and form a data slice of a set data slice length based on the content of the read data pattern.

[0134] For example, take the data width type of x4, MR48[7:0] (8-bit MR48), and the set data slice length of 32 bits as an example. Figure 7B The example diagram of generating a data slice provided by the embodiment of the present application is exemplarily shown. Figure 7B As shown, under the data width type of x4, since each data storage unit processes 4-bit data, the lower 4 bits or upper 4 bits in the 8-bit data mode of MR48 are reused, so that the lower 4 bits of data (or the upper 4 bits) of 8 MR48s (such as DRAM0_MR48 to DRAM7_MR48) can be read respectively, and the lower 4 bits or upper 4 bits of data of the 8 MR48s read respectively are combined into a 32-bit data slice. For example, taking the data pattern of 11001100 in MR48[7:0] as an example, the lower 4 bits of data (or the upper 4 bits) 1100 of 8 MR48s can be taken to assemble a 32-bit data slice. In this example, the data pattern reading method matched by the data width type of x4 indicates that 8 MR48s are read, and the data reading bit of the data pattern is the lower 4 bits. It should be noted that MR48 is only an optional example of a dedicated mode register, the data pattern bit width of 8 bits is only an optional example, and the content of the data pattern reading method of this example is also only an optional example.

[0135] The x8 data selector 722 can be used to read the content of the data pattern in a data pattern reading method corresponding to the x8 data width type, and form a data slice of a set data slice length based on the content of the read data pattern.

[0136] For example, take the data width type of x8, MR48[7:0], and the set data length of 32 bits as an example. Figure 7C Another example diagram of generating a data slice provided by an embodiment of the present application is exemplarily shown. Figure 7C As shown, under the data width type of x8, since each data storage unit processes 8-bit data, MR48 can use the entire 8-bit data pattern to express the data repetition form, so that the 8-bit data of 4 MR48s (such as DRAM0_MR48 to DRAM3_MR48) can be read separately, and the 8-bit data of the 4 MR48s read separately can be combined into a 32-bit data slice. For example, taking the data pattern of 10110110 in MR48[7:0] as an example, the 8-bit data 10110110 of 4 MR48s can be taken to assemble a 32-bit data slice. In this example, the data pattern reading method corresponding to the data width type of x8 indicates that 4 MR48s are read, and the data reading bit of the data pattern is 8 bits.

[0137] The x16 data selector 723 can be used to read the content of the data pattern in a data pattern reading method corresponding to the x16 data width type, and form a data slice of a set data slice length based on the content of the read data pattern. For example, taking the x16 data width type, MR48[7:0], and the set data slice length of 32 bits as an example, Fig.7D Another example diagram of generating a data slice provided by an embodiment of the present application is shown as an example. Fig.7D As shown, under the data width type of x16, since each data storage unit processes 16-bit data, MR48 can use the entire 8-bit data pattern to express the data repetition form, so that the 8-bit data of two MR48s (such as DRAM0_MR48 to DRAM1_MR48) can be read respectively, and the 8-bit data of the two MR48s read respectively are copied respectively, and the copied data and the read data form a 32-bit data slice. For example, taking the data pattern of 10110110 in MR48[7:0] as an example, the 8-bit data 10110110 of the two MR48s can be read respectively and copied respectively, so that the copied data and the read data can form a 32-bit data slice. In this example, the data pattern reading method corresponding to the data width type of x16 indicates that two MR48s are read and the data read by the two MR48s are copied, and the data reading bit of the data pattern is 8 bits.

[0138] The above example is only an optional way to read the content of the data pattern based on the data width type of the configured memory in a data pattern reading method corresponding to the data width type; the embodiment of the present application can also read data from a dedicated mode register (such as an MR48) according to the data reading bit of the data pattern (such as the data width type of x4 takes the lower 4 bits or the upper 4 bits of data, the data width type of x8 or x16 takes 8 bits of data, etc.), and copy it multiple times to obtain a data slice of a set data slice length (such as a 32-bit data slice); that is, the data obtained from a dedicated mode register (such as an MR48) is copied multiple times to form a data slice.

[0139] It can be seen that the embodiments of the present application can set data selectors corresponding to various data width types to define the data mode reading methods corresponding to various data width types, so that when the data width type of the memory supports arbitrary configuration under multiple data width types, the generation of corresponding data slices under various data width types can be realized, thereby supporting the verification scenarios of WRP commands in various data width types of the memory.

[0140] Back to Fig. 7AAs shown, the main function of the multiplexer is to select an output from multiple input signals; the multiplexer has multiple input lines and one output line, and may also have at least one selection line (control line), so that the multiplexer can decide the input signal connected to the output according to the state of the selection line.

[0141] As an optional implementation, the multiplexer 730 of the embodiment of the present application can be used to select a data selector corresponding to the configured data width type from the data selectors corresponding to the multiple data width types based on the data width type of the configured memory (such as the data width type configured in the data width type register), and output the data slice generated by the selected data selector. For example, the multiple input signals of the multiplexer can be the output results (i.e., data slices) of the data selectors corresponding to the various data width types, and the state of the control line can be determined by the data width type of the configured memory; that is, the data width type of the configured memory (the state of the control line) determines the data selector selected by the multiplexer.

[0142] Example, combined Fig. 7A As shown, if the configured data width type is x4, the demultiplexer can output the trigger signal to the data selector of x4, so that the data selector of x4 reads the content of the data pattern in the data pattern reading method matched by x4 and generates a 32-bit data slice; the data slice generated by the data selector of x4 can be transmitted to the multiplexer, and then the multiplexer can select the data slice generated by the data selector of x4 for output based on the configured data width type of x4. When the configured data width type is x8 or x16, the working process of the WRP data slice generator can be referred to in the same way, and will not be repeated here.

[0143] It can be seen that under the various data width types of the memory, the embodiment of the present application can configure data selectors corresponding to the various data width types, and the data selector supports the generation of data slices with a set data slice length (such as 32 bits). Therefore, the embodiment of the present application can achieve WRP command verification support for various data width types of the memory by setting data selectors corresponding to the various data width types, thereby increasing the coverage of the verification scenarios supported by the WRP command verification.

[0144] Back to Figure 6 As shown, the WRP data assembler 630 can be used to assemble the data slices with the set data slice length generated by the WRP data slice generator and the write address of the WRP command into WRP data with the set WRP data length.

[0145] In an optional implementation, the data slice of the set data slice length generated by the WRP data slice generator can be transmitted to the WRP data assembler, so that the WRP data assembler can assemble the data slice of the set data slice length and the write address of the WRP command into the effective data transmission length of the WRP data (i.e., the set WRP data length) to obtain the assembled WRP data. The WRP data assembled by the WRP data assembler can be the data written to the memory by the WRP command. In an optional implementation, in addition to transmitting the generated data slice to the WRP data assembler, the WRP data slice generator can also transmit the write address of the WRP command to the WRP data assembler; for example, the trigger signal (such as the WRP command) transmitted by the WRP transmitter to the WRP data slice generator can carry the write address, so that when the WRP data slice generator transmits the generated data slice to the WRP data assembler, it can also transmit the write address carried by the trigger signal (such as the WRP command) to the WRP data assembler, so that the WRP data assembler can assemble the received data slice and write address into WRP data.

[0146] In an optional implementation, the WRP data length may be set to be the effective data transmission length of the WRP data, which may be understood as the amount of data written by a WRP command. The WRP data length may be set to be greater than the data slice length, such as setting the WRP data length to 512 bits. It should be noted that the WRP data length may be set based on the memory type (such as the memory type), the physical configuration of the memory (such as the physical configuration of the memory), and the performance requirements of the system, and the embodiments of the present application are not limited thereto, and the above values ​​are only examples.

[0147] The WRP data buffer 640 can be used to cache WRP data and corresponding write addresses. For example, the WRP data assembled by the WRP data assembler can be cached in the WRP data buffer together with the write address. In an optional implementation, the WRP data buffer is, for example, a FIFO (First In First Out) buffer.

[0148] In an optional implementation, the WRP data buffer is introduced in the embodiment of the present application to solve the data processing problems that may be caused by the timing limitation of the write command. Specifically, the memory protocol (such as the DDR5 protocol) stipulates the minimum time between write commands (such as 1 / 2CWL), and the minimum time between the write command and the write data (such as CWL), and the minimum time between the write command and the write data is greater than the minimum time between the write commands; for continuous WRP commands (WRP commands are regarded as a write command for writing repeated data), since the minimum time between the write commands is less than the minimum time between the write command and the write data, without setting a buffer such as FIFO, continuous WRP commands may cause new write data to be processed while the previous write data has not been processed, resulting in data conflicts or data overwriting problems. Based on this, the embodiment of the present application uses a WRP data buffer to cache the WRP data assembled by the WRP data assembler to ensure that the WRP data can be processed at the right time to avoid data overwriting or data conflict problems caused by continuous WRP commands.

[0149] In an optional implementation, the cache depth of the WRP data buffer (such as a FIFO buffer) can be reasonably set according to actual conditions to prevent data overwriting or data conflict problems and to prevent cache resource waste. For example, the embodiment of the present application can design the cache depth of the WRP data buffer in combination with the historical quantity of WRP data and the timing constraints of the actual write command to achieve the effect of saving cache resources and meeting data performance requirements.

[0150] The write delayer 650 may be used to delay triggering of the WRP data loader 660 according to the configured WRP timing information. For example, the write delayer may read the WRP timing information stored in the timing register, and delay triggering of the WRP data loader according to the WRP timing information. In an optional implementation, the WRP timing information may be CWL, so that the write delayer may trigger the WRP data loader after delaying the CWL time.

[0151] In a possible implementation example, the embodiments of the present application can verify whether the WRP commands of different designs to be tested meet the timing requirements of the memory protocol (such as the DDR5 protocol) by changing the value of the WRP timing information (such as CWL).

[0152] The WRP data loader 660 may be configured to read the WRP data and the corresponding write address cached in the WRP data buffer based on the triggering of the write delayer, and write the WRP data into the memory 670 according to the write address corresponding to the WRP data.

[0153] In an optional implementation, when the WRP data loader writes the WRP data into the memory according to the write address corresponding to the WRP data, the WRP data can be written into the memory in an address linear writing manner or a random address writing manner. It should be noted that the linear address writing manner means that the data is sequentially written into the continuous address space of the memory, for example, the write address of the previous WRP data is continuous with the write address of the next WRP data; that is, in the address linear writing manner, the write addresses of consecutive WRP commands are continuous. The random address writing manner means that the address to which the data is written can be randomly specified and does not need to be continuous; that is, in the random address writing manner, the write addresses of consecutive WRP commands can be randomly distributed.

[0154] The memory 670 may be used to store WRP data according to the write address.

[0155] The embodiment of the present application adds WRP timing information during the execution of the WRP command, so that the WRP data is written into the memory after the WRP timing information is delayed, and timing control can be added during the execution of the WRP command to meet the timing verification requirements of the WRP command. At the same time, the combination of a WRP data buffer (such as a FIFO buffer) and a write delay device can ensure that the WRP data can be processed at the appropriate time, avoiding data overwriting or data conflict problems caused by continuous WRP commands.

[0156] It should be noted that in other possible implementations, the delay mechanism and the WRP data cache mechanism may not be set during the execution of the WRP command (for example, the write delay device and the WRP data cache may not be set), but after the WRP data assembler completes the assembly of the WRP data, the WRP data loader writes the WRP data into the memory according to the write address corresponding to the WRP data. For example, in some storage systems, if the operation rates of the storage controller (such as the memory controller) and the storage (such as the memory) are synchronized, or the data generation rate matches the write rate, the delay mechanism and the WRP data cache mechanism may not be set.

[0157] In a further optional implementation, the verification device may read the WRP data written into the memory by the WRP command based on the read command corresponding to the WRP command, and output the read data, so as to complete the verification of the WRP command by comparing whether the data read by the read command is consistent with the data expected to be written by the WRP command. Figure 5 As shown, after executing step S511, step S515 may be executed.

[0158] In step S515 , data is read based on the read address of the read command.

[0159] In step S516, the read data is output to verify whether the data read by the read command is consistent with the data expected to be written by the corresponding WRP command.

[0160] In a further optional implementation, after executing step S515 (ie, after reading the data), the verification device may also cache the read data, and then output the cached read data after a delay read delay time to output the read data.

[0161] It should be noted that the above steps S515 to S516 can be regarded as the process of the verification device implementing the data reading process during the verification process of the WRP command. Figure 2 As shown, a reading module 226 may be provided in the verification device 220, and the reading module may obtain a reading command corresponding to the WRP command, and execute the above-mentioned steps S515 to S516, that is, execute the process of reading data.

[0162] For ease of explanation, the process of reading data provided in the embodiment of the present application is described below in conjunction with the optional structure of the reading module.

[0163] As an optional implementation, Figure 8 An optional block diagram of a reading module provided in an embodiment of the present application is shown as an example. Figure 8 As shown, the read module may include: a read transmitter 810 and a read driver 820 .

[0164] In an optional implementation, the read transmitter 810 may be used to obtain a read command corresponding to the WRP command, and trigger the read driver 820 to work according to the read command. Optionally, the command decoder 224 may transmit the read command corresponding to the WRP command to the read transmitter 810 of the read module.

[0165] In an optional implementation, the read command corresponding to the WRP command may include an instruction of the read command and a read address; wherein the instruction of the read command may indicate an operation of performing a read data operation from the memory; and the read address may be an address for reading data from the memory. The write address of the WRP command may correspond to the read address of the read command corresponding to the WRP command.

[0166] The read driver 820 may be used to read data based on a read address of a read command under the triggering of the read transmitter 810 , and output the read data.

[0167] In an optional implementation, the embodiment of the present application can cache the read data after reading the data based on the read address of the read command; further, after a delayed read delay time, the cached read data can be output.

[0168] In an optional implementation, the read delay time can be set according to the WRP timing information in the verification configuration information of the WRP command, and the read delay time is greater than the WRP timing information; for example, the read delay time can be set to: WRP timing information plus a set number of minimum read data times, and the minimum read data time can be based on the requirements of the memory protocol (such as the DDR5 protocol). For example, taking the WRP timing information as CWL as an example, the read delay time can be set to be greater than CWL, such as the read delay time is CWL + a set number of minimum read data times. In a further example, the set number of minimum read data times can be 2 minimum read data times, so that the read delay time can be CWL + 2 minimum read data times; of course, 2 minimum read data times are only an example, and the set number of minimum read data times can be set according to actual conditions, and the implementation of this application is not limited.

[0169] In a further optional implementation, combining Figure 8 As shown, the read driver 820 may include a read data module 821 , a read buffer 822 , a read delay 823 , and a read output 824 .

[0170] The data reading module 821 can read data based on the read address of the read command under the triggering of the read transmitter 810 , and cache the read data in the read buffer.

[0171] The read buffer 822 may be used to buffer the read data. Optionally, the read buffer 822 may be in the form of a FIFO buffer.

[0172] The read delay device 823 can be used to save the read delay time, and under the triggering of the read transmitter 810, after delaying the read delay time, enable the read output device 824 to work.

[0173] The read output device 824 may be used to output the read data cached in the read buffer 822 when the read delay device 823 is enabled.

[0174] In an optional implementation, when the read data is output, the read data can be output through a storage control interface (e.g., a DFI interface); thus, the read data can be fed back to the design under test (e.g., a storage controller in the design under test). Furthermore, the design under test (e.g., a storage controller in the design under test) can compare whether the read data is consistent with the data expected to be written by the WRP command to verify the correctness of the WRP command; wherein, the data expected to be written by the WRP command can be the data expected to be written in the memory when the design under test outputs the WRP command.

[0175] In a further optional implementation, the embodiments of the present application may support a linear address readout method or a random address readout method when reading data. The linear address readout method means that data is sequentially read out from the continuous address space of the memory, for example, the read address of the last data read is continuous with the read address of the next data read; that is, in the address linear readout method, the read addresses of continuous read commands are continuous. The random address readout method means that the data readout address can be randomly specified and does not need to be continuous; that is, in the random address readout method, the read addresses of continuous read commands can be randomly distributed.

[0176] In a further optional implementation, when reading data, the read address of the read command of the embodiment of the present application can support addressing in multiples of the set data read granularity, so that the embodiment of the present application supports the storage space size corresponding to the read address (for example, the memory space size corresponding to the read address) is a multiple of the data read granularity.

[0177] In an optional implementation, the minimum configurable granularity of the data read granularity can be smaller than the minimum configurable granularity of the data write granularity; wherein the minimum configurable granularity of the data read granularity is the minimum configurable data read granularity, and the minimum configurable granularity of the data write granularity is the minimum configurable data write granularity. For example, the minimum configurable granularity of the data write granularity can be set to 8 bytes, and the minimum configurable granularity of the data read granularity can be set to 4 bytes; thus, the read address indicated by the opcode of the read command can support 4×N bytes of data reading, where N is an integer greater than 0; furthermore, the embodiment of the present application can support the read command to implement N×32bit (1byte=8bit) data reading, thereby realizing verification support in different data mode configuration scenarios.

[0178] The embodiment of the present application can verify the function and timing of the WRP command, and supports verification scenarios of memories with different data bit widths and arbitrary data modes, so that the verification flexibility and compatibility of the WRP command are improved, and the verification performance of the WRP command is improved. Furthermore, by changing the value of the WRP timing information (such as CWL), it is possible to verify whether the WRP commands of different designs to be tested meet the timing requirements of the memory protocol (such as the DDR5 protocol).

[0179] The solution provided in the embodiment of the present application can be applied to verifying WRP commands during pre-silicon simulation and verification; it can also be applied to verifying WRP commands using hardware such as FPGA (Field Programmable Gate Array); it can also be applied to verifying WRP commands during post-silicon verification.

[0180] Among them, pre-silicon simulation and verification refers to simulation and testing through a software environment before the actual chip (silicon chip) is manufactured; thus, the WRP command can be verified in the process of pre-silicon simulation and verification, which can be realized by software simulation. That is to say, the verification method and verification device provided in the embodiment of the present application can be implemented by software. Thus, the design to be tested and the verification device provided in the embodiment of the present application can be a software implementation, such as the design to be tested is a design code described by a hardware description language such as RTL (Register Transfer Level, register transfer level), and the verification device is a software device implemented by software program instructions. Optionally, the software implementation includes but is not limited to UVM (Universal Verification Methodology, Universal Verification Methodology), SystemVerilog (system level Verilog), Verilog, C language, C++ language, SystemC (system C) and other different forms of software implementation.

[0181] Using hardware such as FPGA to implement the verification WRP command means that the functions of the verification device can be programmed and loaded into the FPGA, so that the verification method and verification device provided in the embodiment of the present application can also be implemented by software programming.

[0182] Post-silicon verification refers to the verification test performed after the chip is manufactured. In this case, the design to be tested can be a manufactured hardware chip, so that the verification device provided in the embodiment of the present application can be implemented in hardware (for example, the verification device is implemented as a logic circuit that can execute the verification method, so that the device module inside the verification device can be regarded as a hardware device module), or it can be implemented in software (for example, the function of the verification device can be programmed and loaded into the FPGA, and the verification is performed by connecting the manufactured chip with the FPGA).

[0183] In a possible implementation, the verification method and verification device provided in the embodiment of the present application can be implemented by software. The embodiment of the present application also uses an electronic device, which can be a computer device that carries the software function of the verification device, including at least one processor and at least one memory, the memory stores one or more computer execution instructions, and the processor calls the computer execution instructions stored in the memory to execute the verification method performed by the verification device provided in the embodiment of the present application.

[0184] In a further optional implementation, an embodiment of the present application provides a storage medium, which stores one or more computer execution instructions. When the computer execution instructions are executed, the verification method performed by the verification device provided in the embodiment of the present application is implemented.

[0185] In a further optional implementation, an embodiment of the present application provides a computer program product, including one or more computer execution instructions, which, when executed, implement a verification method performed by a verification device as provided in an embodiment of the present application.

[0186] In a further optional implementation, the embodiment of the present application also provides a command verification system, including a design to be tested and a command verification device. Among them, the command verification device can be the command verification device provided in the embodiment of the present application, which can be implemented as a command verification device in hardware form, or a command verification device in software form; the relevant content of the command verification device can refer to the description of the corresponding part of the previous text. Further, the design to be tested can be used to transmit a WRP verification configuration request and a WRP command to the verification device; obtain the data read by the read command corresponding to the WRP command transmitted by the verification device; compare the data read by the read command to see if it is consistent with the data expected to be written by the WRP command, so as to verify the WRP command. The relevant content of the design to be tested can refer to the description of the corresponding part of the previous text.

[0187] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0188] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A command verification method, characterized in that: include: Get WRP verification configuration request; Based on the WRP check configuration request, configure the check configuration information of the WRP command; wherein the check configuration information at least includes a data mode of the WRP command and a data width type of the memory; the data mode supports arbitrary configuration under the data mode bit width, and the data width type supports configuration as any data width type among multiple data width types; The configured data mode and data width type are used to generate WRP data of the WRP command, and the WRP data is used as write data when verifying the WRP command.

2. The method according to claim 1, characterized in that The WRP verification configuration request includes a mode register write MRW command and value configuration information; The configuration of the verification configuration information of the WRP command based on the WRP verification configuration request includes: Based on the MRW command, a data mode of the WRP command is configured; and based on the value configuration information, at least a data width type of the memory is configured.

3. The method according to claim 2, characterized in that The verification configuration information also includes WRP timing information, and the WRP timing information is used to control the timing when the WRP data is written; The configuration of the verification configuration information of the WRP command based on the WRP verification configuration request further includes: Based on the value configuration information, WRP timing information is configured.

4. The method according to any one of claims 1 to 3, characterized in that: The data pattern expresses the data repetition form of the WRP command; the data width type of the memory determines whether to express the data repetition form as a whole using the data pattern, or to express the data repetition form using repeated data in the data pattern.

5. The method according to claim 4, characterized in that The data mode bit width of the data mode is 8 bits, and the multiple data width types include: a data width type of x4, a data width type of x8, and a data width type of x16; The data width type of the memory determines whether the data repetition form is expressed as a whole in the data pattern or the data repetition form is expressed as repeated data in the data pattern, including: For the data width type of x4, the lower 4 bits of data in the data pattern are repeated with the upper 4 bits of data to express the data repetition form; For the data width type of x8 or x16, the 8-bit data of the data pattern expresses the data repetition form as a whole, or the lower 4-bit data and the upper 4-bit data in the data pattern are repeated to express the data repetition form.

6. The method according to claim 2, characterized in that The obtaining of the WRP verification configuration request includes: Obtaining MRW commands through a storage control interface and obtaining value configuration information through a data communication interface; The method further comprises: Identify the type of command obtained through the storage control interface, and if the command is an MRW command, enter the step of configuring the data mode of the WRP command based on the MRW command.

7. A command verification method, characterized in that: include: Get WRP command; Read the verification configuration information of the configured WRP command, the verification configuration information at least including the data mode of the WRP command and the data width type of the memory; wherein the data mode supports arbitrary configuration under the data mode bit width, and the data width type supports configuration as any data width type among multiple data width types; Generate WRP data of the WRP command according to the data mode of the WRP command and the data width type of the memory; The WRP data is written to the memory in order to verify the WRP command.

8. The method according to claim 7, characterized in that Generating WRP data of the WRP command according to the data mode of the WRP command and the data width type of the memory includes: Generate a data slice of set data slice length according to the data mode of the WRP command and the data width type of the memory; The data piece of the set data piece length and the write address of the WRP command are assembled into WRP data of the set WRP data length.

9. The method according to claim 8, characterized in that The step of generating a data slice with a set data slice length according to the data mode of the WRP command and the data width type of the memory comprises: Selecting, from the data mode reading modes corresponding to the plurality of data width types, a data mode reading mode corresponding to the data width type configured in the verification configuration information; Read the content of the data pattern in the data pattern reading method corresponding to the configured data width type; Based on the content of the read data pattern, a data slice of a set data slice length is formed.

10. The method according to claim 9, characterized in that The data mode reading method includes: the reading quantity of the dedicated mode register and the data reading bit of the data mode; wherein the dedicated mode register is used to store the data mode of the configured WRP command, and the number of the dedicated mode registers is multiple; The data pattern reading method corresponding to the configured data width type includes: Based on the read quantity of the dedicated mode register corresponding to the configured data width type and the data read bit of the data mode, the content of the data mode is read from the dedicated mode register corresponding to the read quantity according to the data read bit.

11. The method according to claim 10, characterized in that The data mode bit width of the data mode is 8 bits, the number of the dedicated mode registers is 8, the set data slice length is 32 bits, and the multiple data width types include: a data width type of x4, a data width type of x8, and a data width type of x16; The reading quantity of the dedicated mode register corresponding to the configured data width type and the data reading bit of the data mode, reading the content of the data mode from the dedicated mode register corresponding to the reading quantity according to the data reading bit comprises: If the configured data width type is x4, read the lower 4 bits or upper 4 bits of the 8 dedicated mode registers respectively; If the configured data width type is x8, read 8-bit data of 4 dedicated mode registers respectively; If the configured data width type is x16, read 8-bit data of two dedicated mode registers respectively; The forming of a data slice of set data slice length based on the content of the read data pattern comprises: If the configured data width type is x4, the lower 4 bits or upper 4 bits of the 8 dedicated mode registers are read to form a 32-bit data slice; If the configured data width type is x8, the 8-bit data of the four dedicated mode registers will be read separately to form a 32-bit data slice; If the configured data width type is a data width type of x16, the 8-bit data of the two dedicated mode registers read respectively are copied respectively, and the copied data and the read data are combined into a 32-bit data slice.

12. The method according to any one of claims 7 to 11, characterized in that: The verification configuration information also includes: WRP timing information; The method further comprises: After generating the WRP data of the WRP command, the WRP data is cached; Writing the WRP data into a memory comprises: After delaying the WRP timing information, the buffered WRP data is written into the memory.

13. The method according to any one of claims 7 to 11, characterized in that: The WRP command includes an instruction and a write address of the WRP command; wherein the write address supports addressing according to a multiple of a set data write granularity; The method further comprises: When the data written by the WRP command reaches the minimum data length of the WRP command at a single address, the data mode of the WRP command is refreshed once; wherein the minimum data length of the WRP command at a single address is determined by the data mode bit width and the data write granularity.

14. The method according to any one of claims 7 to 11, characterized in that: Also includes: After obtaining the WRP command, determine the read command corresponding to the WRP command; Reading data based on a read address of a read command, wherein the read address of the read command corresponds to a write address of a corresponding WRP command; The read data is outputted to compare whether the data read by the read command is consistent with the data expected to be written by the corresponding WRP command.

15. The method according to claim 14, characterized in that Also includes: After reading the data, cache the read data; After the delay read delay time, the step of outputting the read data is entered; wherein the read delay time is set according to the WRP timing information in the verification configuration information, and the read delay time is set to: the WRP timing information plus a set number of minimum read data times.

16. The method according to claim 14, characterized in that The read address of the read command supports addressing at multiples of a set data read granularity, wherein the minimum configurable granularity of the data read granularity is smaller than the minimum configurable granularity of the data write granularity.

17. A command verification device, characterized in that: At least include: register configuration module and WRP writing module; The register configuration module is used to configure the verification configuration information of the WRP command based on the WRP verification configuration request when the command verification device obtains the WRP verification configuration request; the verification configuration information at least includes the data mode of the configured WRP command and the data width type of the memory, wherein the data mode supports arbitrary configuration under the data mode bit width, and the data width type supports configuration as any data width type among multiple data width types; The WRP write module is used to obtain a WRP command, read the verification configuration information of the configured WRP command; generate WRP data of the WRP command according to the data mode of the configured WRP command and the data width type of the memory; and write the WRP data into the memory to verify the WRP command.

18. The device according to claim 17, characterized in that The WRP verification configuration request includes a mode register write MRW command and value configuration information; the register configuration module includes: a MRW transmitter and a configuration register; The MRW transmitter is used to identify the data pattern carried by the MRW command and configure the identified data pattern to the configuration register; The configuration register is used to store the data mode of the MRW command configured by the MRW transmitter; and, based on the value configuration information, at least configure and store the data width type of the memory.

19. The device according to claim 18, characterized in that The configuration register includes: A dedicated mode register for a WRP command, used to store a data mode of the WRP command; wherein the data mode identified by the MRW transmitter is configured to the dedicated mode register; The data width type register is used to store the data width type of the memory configured based on the value configuration information.

20. The device according to claim 19, characterized in that The configuration register is further used to configure and save WRP timing information based on the value configuration information; The configuration register further includes: a timing register, which is used to store WRP timing information configured based on the value configuration information.

21. The device according to claim 19, characterized in that There are multiple dedicated mode registers, and the multiple dedicated mode registers include dedicated mode registers of multiple memory channels.

22. The device according to claim 17, characterized in that The WRP writing module at least includes: a WRP transmitter, a WRP data slice generator, a WRP data assembler, a WRP data loader and a memory; The WRP transmitter is used to obtain a WRP command and trigger the WRP data slice generator to work according to the WRP command; The WRP data slice generator is used to generate a data slice of a set data slice length according to the configured WRP command data mode and the data width type of the memory; The WRP data assembler is used to assemble the data slices of the set data slice length and the write address of the WRP command into WRP data of the set WRP data length; The WRP data loader is used to write the WRP data into the memory.

23. The device according to claim 22, characterized in that The WRP data slice generator is used to generate a data slice with a set data slice length according to the configured WRP command data mode and the data width type of the memory, including: Selecting, from the data mode reading modes corresponding to the plurality of data width types, a data mode reading mode corresponding to the data width type configured in the verification configuration information; Read the content of the data pattern in the data pattern reading method corresponding to the configured data width type; Based on the content of the read data pattern, a data slice of a set data slice length is formed.

24. The device according to claim 23, characterized in that The WRP data slice generator includes: a demultiplexer, data selectors corresponding to a plurality of data width types, and a multiplexer; The demultiplexer is used to obtain a trigger signal of the WRP transmitter, and based on the data width type of the configured memory, transmit the trigger signal to a data selector corresponding to the data width type to trigger the data selector corresponding to the data width type to work; The data selector is used to read the content of the data pattern in a data pattern reading mode corresponding to the data width type corresponding to the data selector when triggered to work; and form a data slice of a set data slice length based on the content of the read data pattern; The multiplexer is used to select a data selector corresponding to the configured data width type from data selectors corresponding to multiple data width types based on the data width type of the configured memory, and output a data slice generated by the selected data selector.

25. The device according to claim 24, characterized in that The data mode reading method includes: the reading quantity of the dedicated mode register and the data reading bit of the data mode; wherein the dedicated mode register is used to store the data mode of the configured WRP command, and the number of the dedicated mode registers is multiple.

26. The device according to claim 25, characterized in that The data mode bit width of the data mode is 8 bits, the number of the dedicated mode registers is 8, the set data slice length is 32 bits, and the multiple data width types include: a data width type of x4, a data width type of x8, and a data width type of x16; The data selectors corresponding to the multiple data width types include: The x4 data selector is used to read the lower 4 bits or higher 4 bits of data of the 8 special mode registers respectively when triggered, and form a 32-bit data slice with the lower 4 bits or higher 4 bits of data of the 8 special mode registers respectively read; The x8 data selector is used to read the 8-bit data of the four special mode registers respectively when triggered, and form a 32-bit data slice with the 8-bit data of the four special mode registers respectively read; The x16 data selector is used to read the 8-bit data of the two special mode registers respectively when triggered, copy the 8-bit data of the two special mode registers respectively, and form a 32-bit data slice with the copied data and the read data.

27. The device according to any one of claims 22 to 26, characterized in that The verification configuration information also includes: WRP timing information; the WRP write module also includes: a WRP data buffer and a write delay device; The WRP data buffer is used to cache the WRP data assembled by the WRP data assembler and the corresponding write address; The write delayer is used to delay triggering of the WRP data loader according to the configured WRP timing information; The WRP data loader, used to write the WRP data into the memory, comprises: Based on the triggering of the write delayer, the WRP data and the corresponding write address cached in the WRP data buffer are read, and the WRP data is written into the memory according to the write address corresponding to the WRP data.

28. The device according to claim 17, characterized in that Also includes: Read module; The reading module is used to obtain a read command corresponding to the WRP command; Read data based on the read address of the read command; The read data is output to verify whether the data read by the read command is consistent with the data expected to be written by the corresponding WRP command.

29. The device according to claim 28, characterized in that The read module includes: a read transmitter and a read driver; The read transmitter is used to obtain a read command corresponding to the WRP command, and trigger the read driver to work according to the read command; The read driver is used to read data based on the read address of the read command under the triggering of the read transmitter, and output the read data.

30. The device according to claim 29, characterized in that The read driver is further used to cache the read data; After the delayed read delay time, the cached read data is output; The read driver includes: a read data module, a read buffer, a read delay device, and a read output device; The data reading module is used to read data based on the read address of the read command under the triggering of the read transmitter; and cache the read data into the read buffer; The read buffer is used to cache the read data; The read delay device is used to store the read delay time, and under the triggering of the read transmitter, after delaying the read delay time, enable the read output device to work; wherein the read delay time is set according to the WRP timing information in the verification configuration information, and the read delay time is set to: the WRP timing information plus a set number of minimum read data time; The read output device is used to output the read data cached in the read buffer when the read delay device is enabled.

31. The device according to claim 28, characterized in that Also includes: command decoder, data communication interface, and storage control interface; The data communication interface is used to obtain the value configuration information in the WRP check configuration request, and transmit the value configuration information to the register configuration module to at least configure the data width type of the memory; The command decoder is used to identify the type of command transmitted by the storage control interface; if the command is an MRW command, it is transmitted to the register configuration module to configure the data mode of the WRP command; if the command is a WRP command, the read command corresponding to the WRP command is determined, the WRP command is transmitted to the WRP write module, and the read command corresponding to the WRP command is transmitted to the read module.

32. A command verification system, characterized in that: include: Design to be tested and calibration device; The verification device is a command verification device as described in any one of claims 17-31.

33. The system according to claim 32, characterized in that The design to be tested is used to transmit a WRP verification configuration request and a WRP command to the verification device; Obtaining data read by a read command corresponding to a WRP command transmitted by a verification device; The data read by the read command is compared to see whether it is consistent with the data expected to be written by the WRP command, so as to verify the WRP command.

34. An electronic device, characterized in that: It includes at least one memory and at least one processor, the memory stores one or more computer execution instructions, and the processor calls the computer execution instructions to execute the command verification method as described in any one of claims 1 to 6, and / or the command verification method as described in any one of claims 7 to 16.

35. A storage medium, characterized in that: The storage medium stores one or more computer-executable instructions, and when the computer-executable instructions are executed, the command verification method according to any one of claims 1 to 6 is implemented, and / or the command verification method according to any one of claims 7 to 16 is implemented.

36. A computer program product, characterized in that It comprises one or more computer-executable instructions, which, when executed, implement the command verification method as described in any one of claims 1 to 6, and / or the command verification method as described in any one of claims 7 to 16.

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