Data processing method and device for additive operation, electronic equipment and medium

Abstract

The invention provides a data processing method and device for additive operation, electronic equipment and a medium. The data processing method comprises the steps that the size relation between the bit width of an operation operand to be subjected to additive operation and a preset bit width is determined, the bit width of the operation operand is processed, and the operation operand subjected to bit width processing is used for additive operation. According to the invention, the problem that a large amount of resources are consumed during additive operation is solved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data processing method, device, electronic equipment and medium for addition operation. Background Art

[0002] Accumulation operations are often performed in fields such as image processing, speech coding, and artificial intelligence (AI) accelerators. In the hardware implementation process, it is common that the bit width of the operation operand is too large and the target bit width is insufficient to meet the bit width of the operation operand. In this case, the operation result is usually saturated and truncated. However, in this process, a large amount of resources will still be consumed when performing addition operations on the operation operands.

[0003] In view of the problem in the prior art that a large amount of resources are wasted when performing addition operations on operation operands, no effective solution has been proposed so far. Summary of the invention

[0004] The present invention provides a data processing method, device, electronic device and medium for addition operation, which are used to solve the problem in the prior art that a large amount of resources will be consumed when performing addition operation on operation operands, and the loss of resources during the addition operation is reduced by performing bit width processing on the operation operands in advance.

[0005] In a first aspect, the present invention provides a data processing method for addition operation, comprising: Determine the bit width of the operation operand to be added and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform addition operations using the bit-width processed operands.

[0006] Optionally, the processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: when the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0007] Optionally, the processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, n≤r and both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to r+1; when m>r, n≤r and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to r; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width.

[0008] Optionally, the processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, n>r, m and n are not equal, and both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to [min(m, n)+1], and the bit width of the second operation operand is reduced to min(m, n); when m>r, n>r, m and n are not equal, and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are both reduced to r; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0009] Optionally, the processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, m=n and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are reduced to r; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0010] Optionally, the method further comprises: The operation operands include a first operation operand and a second operation operand; When m≤r and n≤r, the bit widths of the first operation operand and the second operation operand remain unchanged; When m>r, m=n and both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0011] In a second aspect, the present invention provides a data processing device for addition operation, comprising: A determination module, used to determine the bit width of the operation operand to be added and the preset bit width; A first processing module, configured to process the bit width of the operation operand according to a size relationship between the bit width of the operation operand and the preset bit width; The second processing module is used to perform addition operation using the operation operands after bit width processing.

[0012] In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the processor implements any of the above-mentioned data processing methods for addition operations.

[0013] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-mentioned data processing methods for addition operations.

[0014] In a fifth aspect, the present invention further provides a computer program product, comprising a computer program, which, when executed by a processor, implements any of the above-mentioned data processing methods for addition operations.

[0015] The data processing method, device, electronic device and medium for addition operation provided by the present invention process the bit width of the operation operand to be added and the size relationship of the preset bit width, and perform addition operation using the operation operand after bit width processing. The problem that a large amount of resources will be consumed when performing addition operation on the operation operand in the prior art is solved, and the loss of resources in the addition operation process is reduced by performing bit width processing on the operation operand in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a flow chart of a data processing method for addition operation provided by the present invention.

[0018] Figure 2 It is a schematic diagram of the working principle of the adder provided by the present invention.

[0019] Figure 3 This is one of the flowcharts of bit width reduction provided by the present invention.

[0020] Figure 4 This is the second schematic diagram of the process of bit width reduction provided by the present invention.

[0021] Figure 5 This is the third schematic diagram of the process of bit width reduction provided by the present invention.

[0022] Figure 6 It is a structural schematic diagram of a data processing device for addition operation provided by the present invention.

[0023] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0024] In the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0025] In the present invention, the term "plurality" refers to two or more than two, and other quantifiers are similar to them.

[0026] In the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Figure 1 is a flow chart of a data processing method for addition operation provided by the present invention, such as Figure 1 As shown, the method includes the following steps S101-S103: Step S101: Determine the bit width of the operation operand to be added and the preset bit width.

[0029] It should be noted that the preset bit width can be the bit width of the adder, or the bit width of the addition function module in any image processing device, or the actual required bit width in the process of data operation and other processing (such as image data processing). The preset bit width here can also be understood as the bit width of the hardware device related to image processing when the result of the addition operation is the input of the hardware device related to image processing. Since the bit width of the hardware device related to image processing is limited (some hardware devices cannot handle too large a bit width), it is necessary to reduce the bit width of the operation operand before the addition operation to avoid the problem of operation failure due to exceeding the processing capacity of the hardware device related to image processing. The specific type of preset bit width is not further limited in the present invention. Based on this, the present invention can be used in an adder, and can also be used in a device with an addition function module in the field of image processing. The embodiment of the present invention does not further limit this.

[0030] It should be noted that, in combination with the characteristics of the addition operation, it can be known that the number of operation operands is at least two. In actual application, the present invention does not further limit the specific number of operation operands.

[0031] For ease of understanding, the present invention is further explained in an operation scenario of an adder with two operation operands.

[0032] As an optional embodiment, Figure 2 The schematic diagram of the working principle of the adder provided by the present invention is shown in the figure. As shown in the figure, the first operation operand is Input1, the second operation operand is Input2, the output is Output, the bit width of the first operation operand is m, the bit width of the second operation operand is n, and the preset bit width of the adder is r.

[0033] Optionally, when the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width, the bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0034] As an optional embodiment, the preset bit width can be the bit width of the adder. The preset bit width of the adder is 8-16 bits, the bit width of the first operation operand is 20 bits, and the bit width of the second operation operand is 4 bits. At this time, the bit width of the first operation operand is greater than the maximum boundary value of the preset bit width, and the bit width of the second operation operand is less than the minimum boundary value of the preset bit width, so it is necessary to process the bit width of the operation operand.

[0035] In the above embodiments, the bit width processing can be bit width reduction or bit width unchanged. Bit width reduction can reduce the storage requirements of data. A smaller bit width means that fewer bits are needed to represent a numerical value, thereby reducing the storage capacity required for storage. By determining the relationship between the bit width of the operation operand and the preset bit width, the problem of boundary relationship change caused by changing the bit width of the operation operand can be avoided.

[0036] Step S102: processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0037] It should be noted that, taking the simplest two operation operands as an example, the bit width processing of the operation operands includes the following three cases: (1) Only the first operation operand is reduced in bit width; (2) Only the second operation operand is reduced in bit width; (3) reducing the bit width of both the first operation operand and the second operation operand; It should be noted that when the bit width of the operation result is greater than the preset bit width of the adder, the operation result will be saturated and truncated. In other words, when the original operation result does not undergo saturation truncation, the bit width of the first operation operand and the second operation operand will not be reduced. Correspondingly, when the original operation result will undergo saturation truncation, the bit width of the first operation operand and / or the second operation operand needs to be reduced in advance.

[0038] It should be noted that when the calculation result does not undergo saturation truncation, the following equation holds true: Input1[m-1:0]+Input2[n-1:0]=Output[r-1:0] (1)

[0039] By transposing the above formula, we can get: Input1[m-1:0] = Output[r-1:0]- Input2[n-1:0] (2)

[0040] If both Input1 and Input2 are signed data, the bit width required on the right side of equation (2) is (max{n, r}+1) due to the presence of a sign bit. If both are unsigned data, the bit width required on the right side of equation (2) is r, because the value of Output-Input2 must be in the r-bit value range [0, 2r-1].

[0041] It should be further explained that as long as the bit width of Input1 can match the bit width required on the right side of formula (2), it can be ensured that when the original operation result does not undergo saturation truncation, the operation operand will not undergo saturation truncation. When the bit width of Input1 is less than or equal to the bit width on the right side of formula (2), it means that the bit width of Input1 cannot be optimized; when the bit width of Input1 is greater than the bit width on the right side of formula (2), the bit width of Input1 can be reduced to the bit width on the right side of formula (2).

[0042] It should be noted that since saturation truncation itself will cause data errors, the actual calculation results are not important when the bit width of Input1 and Input2 is reduced. The main discussion is whether Input1+Input2 is outside the minimum or maximum value boundary of Output.

[0043] Step S103: performing addition operation using the operation operands after bit width processing.

[0044] Specifically, since there are three different situations when performing bit width processing, correspondingly, step S103 also includes three situations: (1) Inputting the first operation operand after bit width reduction and the original second operation operand into the adder; (2) inputting the original first operation operand and the second operation operand with reduced bit width into the adder; (3) The first operation operand after the bit width reduction and the second operation operand after the bit width reduction are input to the adder.

[0045] It should be noted that since the operation operands after bit width reduction are input to the adder, the bit width of the operands is reduced regardless of the above situation. Based on the adaptive principle of the adder, the adder can call fewer resources than before the bit width reduction to perform the operation, thereby achieving the purpose of saving hardware resources.

[0046] In combination with the above, as an optional embodiment, the method of the present invention can also be: determining the bit width of the first operation operand to be input into the adder, the bit width of the second operation operand to be input into the adder, and the preset bit width of the adder; reducing the bit width of the first operation operand and / or the second operation operand according to the size relationship among the bit width of the first operation operand, the bit width of the second operation operand, and the preset bit width; and inputting the first operation operand after the bit width reduction and / or the second operation operand after the bit width reduction into the adder.

[0047] Through the above steps S101-S103, the bit width of the operation operand to be added is determined and the size relationship between the preset bit width, the bit width of the operation operand is processed, and the operation operand after the bit width processing is used to perform the addition operation. The problem that the operation operand in the prior art consumes a lot of resources when performing the operation is solved, and the bit width of the operation operand is processed in advance to reduce the loss of resources during the addition operation. Avoid the situation where the operation fails due to the bit width limitation of the image processing hardware device.

[0048] Optionally, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, n≤r and both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to r+1; It should be noted that, when m>r, n≤r and both the first operand and the second operand are signed data, only the bit width of the first operand is reduced to r+1, and the bit width of the second operand remains unchanged, that is, the bit width of the second operand is still n. At this time, the adder is optimized into an (r+1)+n adder.

[0049] When m>r, n≤r and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to r; It should be noted that, when m>r, n≤r and both the first operand and the second operand are unsigned data, only the bit width of the first operand is reduced to r, and the bit width of the second operand remains unchanged, that is, the bit width of the second operand is still n. At this time, the adder is optimized into an r+n adder.

[0050] Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0051] As an optional embodiment, the first operand of the adder is Input1, the second operand is Input2, the adder output is Output, and the preset bit width is r. When the bit width of Output remains unchanged, since the first operand and the second operand are both signed numbers, the signs will change when the terms are shifted, so the bit width needs to be reduced to r+1.

[0052] In the above embodiment, by reducing the bit width of the operation operand in advance, it is possible to save the operation resources of the adder and further improve the operation efficiency of the adder while ensuring that the adder will not be saturated and truncated.

[0053] Optionally, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, n>r and m and n are not equal and both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to [min(m, n)+1], and the bit width of the second operation operand is reduced to min(m, n); It should be noted that, when m>r, n>r and m and n are not equal and both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to [min(m, n)+1], and the bit width of the second operation operand is reduced to min(m, n), which is equivalent to optimizing the adder into an adder of [min(m, n)+1]+min(m, n); When m>r, n>r, m and n are not equal and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are reduced to r; It should be noted that, when m>r, n>r, m and n are not equal and the first operation operand and the second operation operand are both unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are both reduced to r, which is equivalent to optimizing the adder into an r+r adder; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0054] It should be noted that the original bit width relationship will not be changed after the bit width reduction is performed. That is, before the bit width reduction is performed, the bit width of the first operation operand is greater than the bit width of the second operation operand, then after the bit width reduction, the bit width of the first operation operand is still greater than the bit width of the second operation operand.

[0055] In the above embodiment, although the bit width reduction will bring about a certain loss of precision, the bit width reduction method in implementation can minimize the error while ensuring sufficient precision, thereby improving the overall calculation accuracy.

[0056] Optionally, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, m=n and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are both reduced to r; It should be noted that, when m>r, m=n and the first operation operand and the second operation operand are both unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are both reduced to r, which is equivalent to optimizing the adder into an r+r adder; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0057] As an optional embodiment, the preset bit width is 12 bits, the bit width of the first operation operand is 16 bits, and the bit width of the second operation operand is also 16 bits, which meets the above conditions. In this case, the bit widths of the first operation operand and the second operation operand are both reduced to 12 bits.

[0058] In the above embodiment, reducing the bit width in advance can effectively avoid data saturation and truncation in subsequent calculations, thereby avoiding calculation errors and system abnormalities caused by this. At the same time, since adders are commonly used in circuit design, the circuit components and wiring required after the bit width is reduced will also be simplified accordingly, which is beneficial to the design and manufacture of circuits.

[0059] Optionally, the method further comprises: The operation operands include a first operation operand and a second operation operand; When m≤r and n≤r, the bit widths of the first operation operand and the second operation operand remain unchanged, that is, the bit widths of the first operation operand and the second operation operand are not reduced; It should be noted that when reducing the bit width of Input1 and Input2, the actual operation result is not important. The main issue is whether Input1+Input2 is outside the minimum or maximum boundary of Output. When m≤r and n≤r, if the bit width is reduced, the boundary value between Input1+Input2 and Output may change. Therefore, the bit width is not reduced.

[0060] When m>r, m=n and both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0061] It should be noted that, since both the first operand and the second operand are signed numbers, after the shift, it is possible that one of the first operand and the second operand is signed data and the other is unsigned data, and therefore, the bit width of the operands is not reduced.

[0062] In the above embodiment, an advance judgment is made based on the size relationship between the bit width of the operation operand and the preset bit width, thereby avoiding the problem that the boundary situation may change after the operation operand with reduced bit width is input into the adder, thereby causing calculation errors. When the adder output data is used for data input for subsequent encoding and decoding or data noise reduction processing, the aforementioned early saturation truncation operation can also ensure the correctness of the subsequent encoding and decoding results or lay the foundation for good noise reduction performance.

[0063] The executor of each step in the method may be a data processing device for addition operations, which may be implemented through software and / or hardware. The device may be integrated into an electronic device, which may be a terminal device (such as a smart phone, a personal computer, etc.), a server (such as a local server or a cloud server, or a server cluster, etc.), a processor, or a chip, etc.

[0064] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. In order to better understand the above method, the above process is described below in conjunction with the embodiments, but the technical solutions of the embodiments of the present invention are not limited. Specifically: The above method provided by the present invention is illustrated below by using examples of specific application scenarios.

[0065] like Figure 2 As shown, it is a schematic diagram of the working principle of the adder provided by the present invention, wherein Input1 (corresponding to the first operation operand in the above embodiment), Input2 (corresponding to the second operation operand in the above embodiment) and Output are all integer types, and Input1, Input2 and Output must all be signed numbers at the same time, or unsigned numbers at the same time.

[0066] Since the saturation truncation operation itself will cause data errors, when the result of Input1+Input2 needs to be saturated and truncated, there is no need to care about the specific value of Input1+Input2. We only need to discuss whether Input1+Input2 is outside the minimum value boundary or the maximum value boundary of Output. Therefore, the bit width of Input1 or Input2 can be reduced as long as the position of the result of Input1+Input2 and the boundary value of Output remains unchanged.

[0067] The core principle of the present invention is that when the original operation result does not undergo saturation truncation, the operation operand will not undergo saturation truncation either. This can ensure that the calculation error introduced by reducing the bit width of the operation operand in advance will be masked by the error caused by the saturation truncation of the original operation result.

[0068] The principle is further explained based on the core principle as follows: When the original operation result does not undergo saturation truncation, the following equation holds true:

[0069] Input1[m-1:0]+Input2[n-1:0]=Output[r-1:0] (1)

[0070] Input1[m-1:0]=Output[r-1:0]-Input2[n-1:0] (2)

[0071] Analyze the required bit width on the right side of equation (2): (1) If both Input1 and Input2 are signed data, the required bit width on the right is (max{n, r}+1); (2) If both Input1 and Input2 are unsigned data, the required bit width on the right side is r, because the value of Output-Input2 must be in the r-bit value range [0, 2r-1].

[0072] In other words, as long as the bit width of Input1 can match the bit width required on the right side of formula (2), it can be ensured that when the original operation result does not undergo saturation truncation, the operation operand will not undergo saturation truncation. When the bit width of Input1 is less than or equal to the bit width on the right side of formula (2), it means that the bit width of Input1 cannot be optimized; when the bit width of Input1 is greater than the bit width on the right side of formula (2), the bit width of Input1 can be reduced to the bit width on the right side of formula (2).

[0073] Specifically: Assume Input1[m-1:0]+Input2[n-1:0]——Input[r-1:0].

[0074] Among them, the bit width of Input1 is m, the bit width of Input2 is n, and the bit width of Output is r (corresponding to the preset bit width in the above embodiment). The following only discusses the bit width reduction of Input1 and Input2, and the bit width of Output remains unchanged.

[0075] 1. When max{m,n}≤r, no bit width reduction is performed.

[0076] 2. When m>r and n≤r (m>r≥n), you can follow Figure 3 To process, Figure 3This is one of the flow charts of bit width reduction provided by the present invention. Figure 3 : (1) When the data type is unsigned, reduce the bit width of Input1 to r.

[0077] (2) When the data type is signed, reduce the bit width of Input1 to r+1.

[0078] 3. When m>r, n>r, and m When n, you can follow Figure 4 To process, Figure 4 This is the second schematic diagram of the process of reducing the bit width provided by the present invention. Figure 4 As shown: (1) When the data type is unsigned, reduce the bit width of both Input1 and Input2 to r.

[0079] (2) When the data type is signed, reduce the bit width of Input1 to (min{m, n}+1) and reduce the bit width of Input2 to min{m, n}.

[0080] 4. When m>r, m=n, you can follow Figure 5 To process, Figure 5 This is the third schematic diagram of the process of reducing the bit width provided by the present invention. Figure 5 As shown: (1) When the data type is unsigned, reduce the bit width of both Input1 and Input2 to r.

[0081] (2) When the data type is signed, no bit width reduction is performed.

[0082] It should be noted that the large bit width of Input1 and Input2 before optimization corresponds to the large bit width after optimization, and the small bit width before optimization corresponds to the small bit width after optimization.

[0083] Furthermore, the above principle is demonstrated in conjunction with specific embodiments.

[0084] For example: Input1[11:0]+Input2[9:0]——Output[7:0], where Input1, Input2 and Output are all unsigned numbers. When the original Output is not saturated and truncated, the following equation is obtained: Input1[11:0]+Input2[9:0]=Output[7:0] (3)

[0085] Input1[11:0]=Output[7:0]-Input2[9:0] (4)

[0086] Input2[9:0]=Output[7:0]-Input1[11:0] (5)

[0087] By using the bit width on the right side of equation (4), the bit width of Input1 can be reduced to 8 bits, that is, the original equation (3) becomes

[0088] Input1[7:0]+Input2[9:0]=Output[7:0]

[0089] If Input1[11:0]-Input1[7:0] is saturated and truncated, then equation (3) will also be saturated and truncated, and the boundary values ​​of the truncation are consistent.

[0090] By using the bit width on the right side of equation (5), the bit width of Input2 can be reduced to 8 bits, that is, the original equation (3) finally becomes: input1[7:0]+input2[7:0]=output[7:0].

[0091] The data processing device for addition operation provided by the present invention is described below. The data processing device for addition operation described below and the data processing method for addition operation described above can be referred to each other.

[0092] Figure 6 A schematic diagram of the structure of a data processing device for addition operation provided by the present invention, such as Figure 6 As shown, the device comprises: The determination module 601 is used to determine the bit width of the operation operand to be added and the preset bit width.

[0093] The first processing module 602 is used to process the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0094] The second processing module 603 is used to perform addition operation using the operation operands after bit width processing.

[0095] By using the data processing device for addition operation, the bit width of the operation operand to be added and the size relationship of the preset bit width are determined, the bit width of the operation operand is processed, and the operation operand after the bit width processing is used to perform the addition operation. The problem that a large amount of resources will be consumed when the operation operand is calculated by the adder in the prior art is solved, and the loss of resources in the addition operation process is reduced by performing bit width processing on the operation operand in advance.

[0096] Optionally, the first processing module 602 is further used to process the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width when the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width.

[0097] Optionally, the first processing module 602 is also used to reduce the bit width of the first operation operand to r+1 when m>r, n≤r and both the first operation operand and the second operation operand are signed data; and reduce the bit width of the first operation operand to r when m>r, n≤r and both the first operation operand and the second operation operand are unsigned data; wherein m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is a preset bit width.

[0098] Optionally, the first processing module 602 is further used to reduce the bit width of the first operation operand to [min(m, n)+1] and the bit width of the second operation operand to min(m, n) when m>r, n>r, m and n are not equal, and the first operation operand and the second operation operand are both signed data; and to reduce the bit width of the first operation operand and the bit width of the second operation operand to r when m>r, n>r, m and n are not equal, and the first operation operand and the second operation operand are both unsigned data; wherein m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0099] Optionally, the first processing module 602 is also used to reduce the bit width of the first operation operand and the bit width of the second operation operand to r when m>r, m=n and both the first operation operand and the second operation operand are unsigned data; wherein m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0100] Optionally, the device also includes a third processing module, which is used to not reduce the bit width of the first operation operand and the second operation operand when m>r, m=n and the first operation operand and the second operation operand are both signed data; wherein m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

[0101] It should be noted here that the above-mentioned device provided by the present invention can implement all the method steps implemented by the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects that are the same as the method embodiment in this embodiment will not be described in detail here.

[0102] Figure 7 A schematic diagram of the structure of an electronic device provided by the present invention, such as Figure 7As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute any of the data processing methods for addition operations provided in the above embodiments, and the method includes: Determine the bit width of the operation operand to be added and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform addition operations using the bit-width processed operands.

[0103] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0104] It should be noted here that the electronic device provided by the present invention can implement all the method steps implemented by the above-mentioned method embodiment, and can achieve the same technical effects. The parts and beneficial effects of this embodiment that are the same as the method embodiment will not be described in detail here.

[0105] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program can implement any of the data processing methods for addition operations provided in the above embodiments, the method comprising: Determine the bit width of the operation operand to be added and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform addition operations using the bit-width processed operands.

[0106] It should be noted here that the computer-readable storage medium provided by the present invention includes a non-transitory computer-readable storage medium and a transient computer-readable storage medium, which can implement all the method steps implemented by the above-mentioned method embodiment and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as the method embodiment will not be described in detail here.

[0107] In another aspect, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program may be stored in a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute any one of the data processing methods for addition operation provided in the above embodiments, the method comprising: Determine the bit width of the operation operand to be added and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform addition operations using the bit-width processed operands.

[0108] It should be noted here that the computer program product provided by the present invention can implement all the method steps implemented by the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those of the method embodiment will not be described in detail here.

[0109] The device embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, i.e., they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0110] Through the description of the above implementation modes, those skilled in the art can clearly understand that each implementation mode can be implemented by means of software plus a necessary general hardware platform, or of course by hardware. Based on such an understanding, the above technical solution can essentially or in other words be embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiment.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method for addition operation, characterized in that: include: Determine the bit width of the operation operand to be added and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform addition operations using the bit-width processed operands.

2. The data processing method for addition operation according to claim 1, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: When the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width, the bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

3. The data processing method for addition operation according to claim 1 or 2, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, n≤r and both the first operation operand and the second operation operand are signed data, reducing the bit width of the first operation operand to r+1; When m>r, n≤r and both the first operation operand and the second operation operand are unsigned data, reducing the bit width of the first operation operand to r; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width.

4. The data processing method for addition operation according to claim 1 or 2, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, n>r, m and n are not equal, and both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to [min(m, n)+1], and the bit width of the second operation operand is reduced to min(m, n); When m>r, n>r, m and n are not equal, and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are reduced to r; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

5. The data processing method for addition operation according to claim 1 or 2, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; When m>r, m=n and both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand and the bit width of the second operation operand are reduced to r; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

6. The data processing method for addition operation according to claim 2, characterized in that: The method further comprises: The operation operands include a first operation operand and a second operation operand; When m≤r and n≤r, the bit widths of the first operation operand and the second operation operand remain unchanged; When m>r, m=n and both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; Among them, m is the bit width of the first operation operand, n is the bit width of the second operation operand, and r is the preset bit width of the adder.

7. A data processing device for addition operation, characterized in that: include: A determination module, used to determine the bit width of the operation operand to be added and the preset bit width; A first processing module, configured to process the bit width of the operation operand according to a size relationship between the bit width of the operation operand and the preset bit width; The second processing module is used to perform addition operation using the operation operands after bit width processing.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the data processing method for addition operation according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method for addition operation according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the data processing method for addition operation according to any one of claims 1 to 6 is implemented.

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