Vector computing power distribution method, processor and equipment

Abstract

A vector computing power distribution method, processor and device belong to the technical field of vector computation.According to the method, after a system vector length is updated, an arithmetic unit is selected from a vector computing power pool according to the updated system vector length, and a vector execution unit is reconfigured, so that the newly configured vector execution unit can execute the vector computing on the premise that the newly configured vector execution unit can execute the vector computing; the included arithmetic unit is fully utilized, and the situation that the arithmetic unit does not participate in calculation, and consequently calculation power of the vector execution unit is wasted is avoided as much as possible.

Description

[0001] This disclosure claims priority to Chinese patent application No. 202310734151.9, filed on June 19, 2023, with invention name “A Scheduling Method”, the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of vector computing technology, and in particular to a method, processor and device for allocating vector computing power. Background Art

[0003] Vector computing is widely used in many fields such as high performance computing (HPC) and artificial intelligence (AI) computing.

[0004] Currently, in the instruction pipeline that performs vector calculations, a fixed number of vector execution units (VEUs) are configured. Each vector execution unit is composed of a fixed number of operators, and each vector execution unit can calculate vectors that are no greater than the system vector length.

[0005] When the user updates the system vector length to a value much smaller than the current system vector length, a large portion of operators will not participate in the calculation when each vector execution unit performs vector calculations. The vector execution unit cannot fully utilize its computing power, resulting in a waste of computing power. Summary of the invention

[0006] The present disclosure provides a method, processor and device for allocating vector computing power, which can improve the computing power utilization rate of vector execution units. The corresponding technical solutions are as follows:

[0007] In a first aspect, a method for allocating vector computing power is provided, the method comprising: an operator control circuit determines that a system vector length is updated from a first vector length to a second vector length, based on the second vector length, an operator is selected from a vector computing power pool, a first vector execution unit is configured, and the first vector execution unit executes a vector operation of the second vector length. The first vector execution unit is a vector execution unit that executes the second vector length, the first vector execution unit is composed of at least one operator, and the total data length that can be calculated by the at least one operator is greater than or equal to the second vector length.

[0008] In the technical solution provided in the present disclosure, the system vector length refers to the vector length in the vector calculation performed by the computing device. The system vector length can be set according to the actual computing requirements. Through this technical solution, after the system vector length is updated, the operator can be selected from the vector computing power pool according to the updated system vector length, and the vector execution unit can be reconfigured, so that the newly configured vector execution unit can make full use of the included operators while being able to perform vector calculations, and try to avoid the waste of computing power of the vector execution unit caused by the operator not participating in the calculation.

[0009] In one possible implementation, an operator is selected from a vector computing power pool, and the process of configuring a vector execution unit may be as follows: based on a multiple relationship between a second vector length and a data length that can be calculated by a single operator, a first number of operators included in a first vector execution unit is determined, an operator is selected from the vector computing power pool, and the selected first number of operators are configured as a first vector execution unit.

[0010] In the technical solution provided in the present disclosure, in order to ensure that the operators included in the configured vector execution unit can meet the vector calculation requirements and will not be idle when performing vector calculations, when determining the number of operators included in the vector execution unit, the multiple relationship between the second vector length and the data length that can be calculated by a single operator is first calculated, and then based on the multiple relationship, the number of operators included in the first vector execution unit is determined.

[0011] In a possible implementation, when the updated system vector length is smaller than the system vector length before the update, after determining the first number of operators included in the first vector execution unit to be configured, the second number of operators included in the second vector execution unit and the first number can be compared, wherein the second vector execution unit is a vector execution unit that executes the system vector length before the update. When it is determined that the second number is greater than the first number, it means that if the second vector execution unit is continued to be used to perform subsequent vector calculations, during the vector calculation process, operators in the second vector execution unit will be idle, wasting computing power. Therefore, in this case, operators can be selected from the vector computing power pool to reconfigure the vector execution unit.

[0012] In a possible implementation, when the updated system vector length is smaller than the system vector length before the update, after determining the first number of operators included in the first vector execution unit to be configured, the third number of operators included in the second vector execution unit and the first number may be compared, wherein the second vector execution unit is a vector execution unit that executes the system vector length before the update. When it is determined that the third number is smaller than the first number, it means that the vector length that can be executed by the second vector execution unit cannot support subsequent vector calculations. Therefore, in this case, an operator may be selected in the vector computing power pool to reconfigure the vector execution unit.

[0013] In one possible implementation, the process of selecting an operator in the vector computing power pool may be as follows: according to the identifier of each operator in the vector computing power pool, an operator is selected in the vector computing power pool, and each first number of selected operators is configured as a vector execution unit.

[0014] In a possible implementation, after the system vector length is updated, in order to be able to store the calculation results in cooperation with the reconfigured vector execution unit, the present disclosure may also group the vector physical registers, and the method is as follows: based on the second vector length, select the vector physical registers, configure at least one vector physical register group, each vector physical register group includes at least one vector physical register, and the total data length that can be stored by the at least one vector physical register is greater than or equal to the second vector length.

[0015] In the technical solution provided by the present disclosure, after the system vector length is updated, the vector physical registers can be grouped according to the updated system vector length, and the vector physical register group can be configured so that the configured vector physical register group can store the calculation data and calculation results of subsequent vector calculations.

[0016] In a possible implementation, the process of selecting vector physical registers and configuring at least one vector physical register group is as follows: determining a fourth number of vector physical registers included in each vector physical register group based on a multiple relationship between the second vector length and a data length that can be stored in a single vector physical register. Selecting vector physical registers, and configuring each fourth number of selected vector physical registers into a vector physical register group.

[0017] In the technical solution provided in the present disclosure, in order to ensure that the vector physical registers included in the configured single vector physical register group can meet the demand for storing the calculation result of a single vector calculation without too much remaining storage space when storing a single calculation result, when determining the number of vector physical registers included in the vector physical register group, the multiple relationship between the second vector length and the data length that can be stored in the single vector physical register is first calculated, and then based on the multiple relationship, the number of vector physical registers included in the single vector physical register group is determined.

[0018] In a possible implementation, when the updated system vector length is less than the system vector length before the update, after determining the fourth number of vector physical registers included in each vector physical register group to be configured, the fifth number of vector physical registers included in each current vector physical register group and the fourth number may be compared. When it is determined that the fifth number is greater than the fourth number, it means that if the currently configured vector physical register group continues to be used to store the calculation results of subsequent vector calculations, when a vector physical register group stores a calculation result, there may be more remaining storage space in the vector physical register group. Therefore, in this case, the vector physical register group may be reconfigured.

[0019] In a possible implementation, when the updated system vector length is greater than the system vector length before the update, after determining the fourth number of vector physical registers included in each vector physical register group to be configured, the sixth number of vector physical registers included in each current vector physical register group and the fourth number may be compared. When it is determined that the sixth number is greater than the fourth number, it means that the currently configured single vector physical register group may not be able to store the calculation result of a vector calculation, and therefore, in this case, the vector physical register group may be reconfigured.

[0020] In a possible implementation, the method for selecting vector physical registers to configure the vector physical registers may be as follows: according to the identifier of each vector physical register, the vector physical register is selected, and every fourth number of the selected vector physical registers is configured as a vector physical register group.

[0021] In a possible implementation, in order to allocate vector physical register groups for vector calculations, in the technical solution provided in the present disclosure, it is also possible to record whether each vector physical register group is idle, and the processing can be as follows: a group identifier is allocated to each vector physical register group, and a corresponding relationship between the group identifier of the vector physical register group and the status indication information of the vector physical register group is established, and the status indication information is used to indicate whether the vector physical register group is idle.

[0022] In a possible implementation, when a vector physical register group is used to store calculation results, the processing flow of vector calculation may be as follows: a vector calculation instruction is obtained, and a destination vector physical register group corresponding to the vector calculation instruction is determined in an idle vector physical register group according to a correspondence between a group identifier of the vector physical register group and state indication information of the vector physical register group. The vector calculation instruction is executed by a first vector execution unit, and a calculation result corresponding to the vector calculation instruction is written into the destination vector physical register group.

[0023] In a second aspect, the present disclosure provides a device for allocating vector computing power, which includes various modules for executing the method for allocating vector computing power in the first aspect or any possible implementation of the first aspect.

[0024] In a third aspect, the present disclosure provides a processor, the processor comprising a logic circuit and a power supply circuit, the logic circuit being used to execute the method for vector computing power allocation as described in the first aspect above.

[0025] In a fourth aspect, the present disclosure provides a computing device, comprising a processor and a memory, wherein the processor is used to execute the method for allocating vector computing power as described in the first aspect above.

[0026] In a fifth aspect, the present disclosure provides a computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is executed on a computing device, the computer executes the methods described in the above aspects.

[0027] In a sixth aspect, the present disclosure provides a computer program product comprising instructions, which, when executed on a computing device, enables the computing device to execute the methods described in the above aspects.

[0028] Based on the implementations provided in the above aspects, the present disclosure can be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the architecture of an instruction pipeline provided by the present disclosure;

[0030] Figure 2 It is a flowchart of a method for allocating vector computing power provided by the present disclosure;

[0031] Figure 3 It is a schematic diagram of the effect of vector computing power allocation provided by the present disclosure;

[0032] Figure 4 It is a schematic diagram of the effect of vector computing power allocation provided by the present disclosure;

[0033] Figure 5It is a flowchart of a method for allocating vector computing power provided by the present disclosure;

[0034] Figure 6 It is a schematic diagram of the effect of vector computing power allocation provided by the present disclosure;

[0035] Figure 7 It is a flow chart of a method for vector calculation provided by the present disclosure;

[0036] Figure 8 is a structural schematic diagram of a processor provided by the present disclosure;

[0037] Fig. 9 is a structural schematic diagram of a computing device provided by the present disclosure;

[0038] Fig.10 It is a schematic diagram of the structure of a device for allocating vector computing power provided by the present invention. DETAILED DESCRIPTION

[0039] In order to improve the utilization rate of vector execution units, the present disclosure provides a method for allocating vector computing power, in which the processor adjusts the data length that can be calculated by a single vector execution unit and the number of vector execution units according to the change of the system vector length. In this way, when the system vector length is small, more vector execution units can be configured to improve the parallelism of vector calculations, so that the operator can participate in the vector calculations as much as possible, thereby avoiding the waste of computing power of the vector execution unit.

[0040] The method for allocating vector computing power provided in the present disclosure can be applied to the instruction pipeline for performing vector calculations in the processor, wherein the processor can be deployed in various types of computing devices, and the processor can be implemented by at least one hardware form of application-specific integrated circuit (ASIC), digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). Of course, the processor can also have other hardware implementation methods, which are not limited by the present disclosure. Processor, such as central processing unit (CPU). In some examples, the processor can also be implemented by means of graphics processing unit (GPU) or data processing unit (DPU), system on chip (SoC), acceleration chip or acceleration card. In some examples, the processor can also be an artificial intelligence (AI) processor.

[0041] See also Figure 1 , the instruction pipeline 100 may include a decoding unit (Decode) 101, a renaming unit (Rename) 102, a reorder buffer (ReOrder Buffer) 103, an issue unit (Issue) 104, a vector physical register (VectorPhysical registers) 105, and an operator 106. Multiple operators form a vector execution unit (VectorExecution Unit) 1061. The operator can perform floating-point addition, floating-point multiplication, integer addition, integer multiplication and other operations. In addition, in Figure 1 Under the architecture shown, it may also include an operator control circuit 107 and a vector physical register control circuit 108. The operator control circuit 107 may execute the method for allocating vector computing power provided by the present disclosure, group the operators based on the system vector length, and serve as vector execution units. The vector register control circuit 108 may execute the method for allocating vector computing power provided by the present disclosure, group the vector physical registers based on the system vector length.

[0042] The method for allocating vector computing power provided by the present disclosure is described below in conjunction with the accompanying drawings. Figure 2 As shown, the processing flow of the method may include the following steps:

[0043] Step 201: The operator control circuit determines that the system vector length is updated from the first vector length to the second vector length.

[0044] The system vector length refers to the vector length in the vector calculation performed by the computing device, and the system vector length can be set by the user according to actual computing requirements.

[0045] In implementation, the user can update the system vector length according to actual computing requirements. When updating the system vector length, the user can input an update instruction for the system vector length to the computing device, and accordingly, the processor receives the update instruction, updates the system vector length from the first vector length to the second vector length indicated by the update, and the operator control circuit obtains the second vector length and determines that the system vector length is updated from the first vector length to the second vector length.

[0046] In a possible implementation, a Scalable Vector Extension Control Register (SVE Control Register) is provided in the processor, and when specifying the system vector length, the user can input a system register (Move (to) System Register, MSR) instruction to the computing device. The processor receives the MSR instruction, and updates the LEN field in the SVE Control Register from a first value to a second value indicated by the MSR instruction. The value of the LEN field is used to indicate the system vector length, the first value is used to indicate that the system vector length is a first vector length, and the second value is used to indicate that the system vector length is a second vector length. The operator control circuit reads the second value of the LEN field in the SVE Control Register, determines the second vector length indicated by the second value, and determines that the system vector length is updated from the first vector length to the second vector length.

[0047] Step 202: The operator control circuit selects an operator in the vector computing power pool based on the second vector length, and configures at least one vector execution unit, where the vector execution unit is composed of at least one operator, and the total data length that can be calculated by the at least one operator is greater than or equal to the second vector length.

[0048] The data types that can be calculated by the operator can be FP8 type, BF16, half-precision floating point number (FP16) type, single-precision floating point number (FP32) type, double-precision floating point number (FP64) type, INT8 type, short integer (INT16) type, basic integer (INT32) type, long integer (INT64) type, BF16, etc. When the data type that can be calculated by the operator is INT8 or FP8 type, the data length that can be calculated by a single operator is 8 bits; when the data type that can be calculated by the operator is BF16, half-precision floating point number type, or short integer type, the data length that can be calculated by a single operator is 16 bits; when the data type that can be calculated by the operator is single-precision floating point number type or basic integer type, the data length that can be calculated by a single operator is 32 bits; when the data type that can be calculated by the operator is double-precision floating point number type or long integer type, the data length that can be calculated by a single operator is 64 bits. Here, only the above data types are taken as examples to illustrate the data length that can be calculated by a single operator. The present disclosure does not limit the data type that can be calculated by the operator and the corresponding computable data length.

[0049] In implementation, a plurality of operators are included in the vector computing power pool. When the operator control circuit determines that the system vector length is updated from the first vector length to the second vector length, the number of operators included in a vector execution unit and the number of configured vector execution units can be determined based on the second vector length and the data length that can be calculated by a single operator. Then, the emission width of the emission unit in the instruction pipeline is updated to the number of vector execution units. The emission width refers to the maximum number of vector calculation instructions that the emission unit is allowed to emit to the vector execution unit within one clock cycle.

[0050] There are multiple calculation methods for how many vector execution units are configured and how many operators each vector execution unit includes, as long as the total data length that can be calculated by each vector execution unit is not less than the second vector length. Several methods are listed below for illustration.

[0051] Method 1:

[0052] Based on the multiple relationship between the total data length that can be calculated by the operators in the vector computing power pool and the second vector length, the number of configured vector execution units is determined. Then, based on the multiple relationship between the number of operators in the vector computing power pool and the number of configured vector execution units, the number of operators included in a vector execution unit is determined. Specifically, the following calculation formula can be used for implementation.

[0053] The number of operators in the vector computing power pool is multiplied by the data length that can be calculated by a single operator to obtain a first value. The first value is divided by the system vector length, and the division result is rounded up to obtain the number of configured vector execution units. The number of operators in the vector computing power pool is divided by the number of configured vector execution units, and the division result is rounded up to obtain the number of operators included in a vector execution unit. The calculation formula can be as follows: Formula (1):

[0054]

[0055] Wherein, E is the number of operators in the vector computing power pool, L is the length of data that can be calculated by a single operator, VL is the second vector length, E*L is the above-mentioned first value, N is the number of configured vector execution units, and n is the number of operators included in a vector execution unit. Indicates rounding up.

[0056] The following is an example to illustrate this method:

[0057] The number of operators is 32, the data length that can be calculated by a single operator is 64 bits, and the system vector length is 256 bits. The number of operators is multiplied by the data length that can be calculated by a single operator, and the first value is 2048. The first value is divided by the system vector length 256, and the second value is 8. The number of operators is divided by the second value, and the third value is 4. That is, the operators are divided into 8 groups, each group includes 4 operators, and each group of operators is configured as a vector execution unit, and a total of 8 vector execution units are configured.

[0058] Method 2:

[0059] Based on the multiple relationship between the second vector length and the data length that can be calculated by a single operator, the number of operators included in a vector execution unit is determined. Then, according to the multiple relationship between the number of operators in the vector computing power pool and the number of operators included in a vector execution unit, the number of configured vector execution units is determined. Specifically, it can be implemented using the following calculation formula.

[0060] Divide the second vector length by the data length that can be calculated by a single operator, and then round up the division result to get the number of operators included in a vector execution unit. Divide the number of operators in the vector computing power pool by the number of operators included in a vector execution unit, and then round up the division result to get the number of configured vector execution units. The calculation formula can be as follows (2):

[0061]

[0062] Wherein, E is the number of operators in the vector computing power pool, L is the length of data that can be calculated by a single operator, VL is the second vector length, E*L is the above-mentioned first value, N is the number of configured vector execution units, and n is the number of operators included in a vector execution unit. Indicates rounding up.

[0063] The following is an example to illustrate this method:

[0064] The number of operators is 32, the data length that can be calculated by a single operator is 64 bits, and the system vector length is 256 bits. The system vector length is divided by the data length that can be calculated by a single operator, and the third value is 4. The number of operators is divided by the third value, and the second value is 8. That is, the operators are divided into 8 groups, each group includes 4 operators, and each group of operators is configured as a vector execution unit, and a total of 8 vector execution units are configured.

[0065] After determining the number of configured vector execution units and the number of operators included in a vector execution unit, compare the number of operators included in the current vector execution unit with the number of operators included in the vector execution unit determined here. If the two numbers are different, select an operator in the vector computing power pool according to the identifier of the operator to configure the vector execution unit. Here, the current vector execution unit is the vector execution unit that executes the first vector length.

[0066] The number of operators is E, and the identifiers of the operators are: C1, C2, C3...C E , will be marked as C1, C2…C n The n operators are grouped into a vector execution unit and labeled as C n+1 , C n+2 …C 2n The n operators are divided into a group and configured as a vector execution unit. And so on, the E operators are divided into N groups and configured as N vector execution units.

[0067] For example, the number of operators is 32, and the identifiers of the operators are: C1, C2, C3...C 32 , the four operators marked as C1, C2, C3, and C4 are divided into a group and configured as a vector execution unit, the four operators marked as C5, C6, C7, and C8 are divided into a group and configured as a vector execution unit, and so on. The 32 operators are divided into 8 groups and configured as 8 vector execution units.

[0068] Through the above steps 201 and 202, when the system vector length changes from long to short, the operators can be reallocated and the vector execution units can be configured, so as to adapt to the adjustment of the number of vector execution units, increase the emission width, and improve the vector calculation parallelism.

[0069] The following is an example to illustrate the effect that can be achieved by using the method provided by the present disclosure when the system vector length changes from long to short:

[0070] like Figure 3 As shown, the number of operators is 32, the data length that can be calculated by a single operator is 64 bits (bit), the system vector length before the update is 512 bits, the number of vector execution units is 4, the transmission width of the transmission unit is 4, each vector execution unit includes 8 operators, and the data length that can be calculated by a single vector execution unit is 512 bits. The updated system vector length becomes 256 bits. If the configuration of the vector execution unit remains unchanged, the transmission width is still 4. When executing vector calculations, half of the operators will not perform calculations, wasting computing power. Through the above step 202, the operators can be reallocated, the number of operators in a single vector execution unit can be reduced, the number of vector execution units can be increased, and 8 vector execution units can be configured. Each vector execution unit includes 4 operators. Correspondingly, the transmission width of the transmission unit is updated to 8. In this way, after the system vector length becomes shorter, more vector calculation instructions can be executed at the same time, the vector calculation parallelism is further improved, the computing power is avoided, and the overall computing efficiency is improved.

[0071] When the system vector length changes from short to long, the operators can be reallocated and the vector execution units can be configured to adapt to the data length that can be calculated by the vector execution units, so that the vector execution units can perform calculations on longer vectors at a time.

[0072] The following is an example to illustrate the effect that can be achieved by using the method provided by the present disclosure when the system vector length changes from short to long:

[0073] like Figure 4As shown, the number of operators is 32, the data length that can be calculated by a single operator is 64 bits, the system vector length before the update is 128 bits, the number of vector execution units is 16, each vector execution unit includes 2 operators, the data length that can be calculated by a single vector execution unit is 128 bits, and the transmission width of the transmission unit is 16. After the update, the system vector length becomes 256 bits. If the configuration of the vector execution unit remains unchanged, and the data length that can be calculated by a single vector execution unit is still 128 bits, then the vector execution unit cannot perform one vector calculation instruction at a time, and needs to be divided into multiple executions, and the calculation efficiency is low. Through the above step 202, the operators can be reallocated, the number of operators in a single vector execution unit is increased, 8 vector execution units are configured, the transmission width of the transmission unit is updated to 8, each vector execution unit includes 4 operators, and the data length that can be calculated by a single vector execution unit is 256 bits. In this way, after the system vector length becomes longer, the data length that can be calculated by each vector execution unit will also adapt to the increase, so that the vector execution unit can execute a vector calculation instruction at a time without being divided into multiple executions, thereby improving the calculation efficiency.

[0074] After completing the grouping of the operators, the operator control circuit may send the configuration information of the vector execution unit to the transmitting unit. The configuration information of the vector execution unit may include the number of vector execution units, the identifier of the vector execution unit, and the identifier of the operator included in each vector execution unit. Exemplarily, the configuration information of the vector execution unit may be as shown in Table 1 below.

[0075] Table 1

[0076]

[0077] Of course, the above steps 201 and 202 may also be implemented by other hardware in the processor, such as a transmitting unit, and the present disclosure does not limit the specific execution subject.

[0078] After the vector execution unit is configured, the configured vector execution unit may perform the vector calculation of the second vector length.

[0079] In a possible implementation, vector physical registers can also be grouped according to the system vector length. After grouping, a vector physical register group can be used to store vectors. Compared with using a single vector physical memory to store vectors, using a vector physical register group to store vectors can store longer vectors. Figure 5 , the processing of vector physical register grouping may include the following steps:

[0080] Step 203: The vector physical register control circuit determines that the system vector length is updated from the first vector length to the second vector length.

[0081] The specific processing of the vector physical register control circuit in step 203 is the same as the specific processing of the operator control circuit in step 201 above, and will not be repeated here.

[0082] Step 204: The vector physical register control circuit selects a vector physical register based on the second vector length, and configures at least one vector physical register group, each of which includes at least one vector physical register, and the total data length that can be stored in the at least one vector physical register is greater than or equal to the second vector length.

[0083] The data length that can be stored in a single vector physical register refers to the maximum data length that can be stored in a vector physical register.

[0084] In an implementation, when determining that the system vector length is updated from the first vector length to the second vector length, the vector physical register control circuit can determine the number of vector physical registers included in a vector physical register group and the number of configured vector physical register groups based on the second vector length and the data length that can be stored in a single vector physical register.

[0085] There are multiple calculation methods for how many vector physical register groups are configured and how many vector physical registers each vector physical register group includes, as long as the total data length that can be stored in each vector physical register group is greater than or equal to the system vector length. Several methods are listed below for illustration:

[0086] Method 1:

[0087] Based on the multiple relationship between the total data length that can be stored by the available vector physical registers and the second vector length, the number of configured vector physical register groups is determined. Then, based on the multiple relationship between the number of available vector physical registers and the number of configured vector physical register groups, the number of vector physical registers included in a vector physical register group is determined. Specifically, the following calculation formula can be used for implementation.

[0088] The number of vector physical registers is multiplied by the length of data that can be stored in a single vector physical register to obtain a second value. The second value is divided by the second vector length, and the division result is rounded up to obtain the number of configured vector physical register groups. The number of available vector physical registers is divided by the number of configured vector physical register groups, and the division result is rounded up to obtain the number of vector physical registers included in a vector physical register group. The calculation formula can be as follows:

[0089]

[0090] Wherein, R is the number of available vector physical registers, l is the data length that can be stored in a single vector physical register, VL is the second vector length, R*L is the above-mentioned second value, M is the number of configured vector physical register groups, and m is the number of vector physical registers included in a vector physical register group.

[0091] The following is an example to illustrate this method:

[0092] The system vector length is 256 bits, the data length that can be stored in a single vector physical register is 128 bits, and the number of vector physical registers is 256. The number of vector physical registers is multiplied by the data length that can be stored in a single vector physical register, and a fourth value of 32768 is obtained. The fourth value is divided by the system vector length to obtain a fifth value of 128. The number of vector physical registers is divided by the fifth value to obtain a sixth value of 2. The vector physical registers are divided into 128 vector physical register groups. Each vector physical register group includes 2 vector physical registers.

[0093] Method 2:

[0094] Based on the multiple relationship between the second vector length and the data length that can be stored in a single vector physical register, the number of vector physical registers included in a vector physical register group is determined. Then, according to the multiple relationship between the number of available vector physical registers and the number of vector physical registers included in a vector physical register group, the number of configured vector physical register groups is determined. Specifically, the following calculation formula can be used for implementation.

[0095] The second vector length is divided by the data length that can be stored in a single vector physical register, and the division result is rounded up to obtain the number of vector physical registers included in a vector physical register group. The number of available vector physical registers is divided by the number of vector physical registers included in a vector physical register group, and the division result is rounded up to obtain the number of configured vector physical register groups. The calculation formula can be as follows:

[0096]

[0097] Wherein, R is the number of available vector physical registers, l is the data length that can be stored in a single vector physical register, VL is the second vector length, R*L is the above-mentioned second value, M is the number of configured vector physical register groups, and m is the number of vector physical registers included in a vector physical register group.

[0098] The following is an example to illustrate this method:

[0099] The number of vector physical registers is 256, the data length that can be stored in a single vector physical register is 128 bits, and the system vector length is 256 bits. The system vector length is divided by the data length that can be calculated by a single operator, and the sixth value is 2. The number of vector physical registers is divided by the sixth value, and the fifth value is 128. That is, the vector physical registers are divided into 128 groups, and each vector physical register group includes 2 vector physical registers.

[0100] After determining the number of configured vector physical register groups and the number of vector physical registers included in a vector physical register group, compare the number of vector physical registers included in a current vector physical register group with the number of vector physical registers included in a vector physical register group determined here. If the two numbers are different, the vector physical registers can be selected according to the identifier of the vector physical register group to configure the vector physical register group.

[0101] The number of vector physical registers is R, and the identifiers of vector physical registers are: V1, V2, V3...V R , will be marked as V1, V2…V m The m vector physical registers are grouped into a group, as a vector physical register group, and are identified as V m+1 、V m+2 …V 2m The m operators are divided into a group, as a vector physical register group, and so on, the R operators are divided into M groups.

[0102] For example, the number of vector physical registers is 256, and the identifiers of the vector physical registers are: V1, V2, V3...V 256 , the two operators identified as V1 and V2 are grouped together as a vector physical register group, the two vector physical registers identified as V3 and V4 are grouped together as a vector physical register group, and so on, the 256 vector physical registers are divided into 128 groups.

[0103] Through the above step 203, when the system vector length changes from short to long, if a single vector physical register cannot store a vector, multiple vector physical registers can be grouped together, and a vector physical register group can be used to store a vector, where the vector may refer to the calculation result of the vector calculation.

[0104] The following example illustrates the above effect:

[0105] like Figure 6As shown, the number of vector physical registers is 256, the amount of data that can be stored in a single vector physical register is 128 bits, the system vector length before the update is 128 bits, and one vector physical register can store one vector. The system vector length after the update is 256 bits, and one vector physical register cannot store one vector. Through the above step 203, two vector physical registers are combined into a vector physical register group, and 128 vector physical register groups can be formed. One vector physical register group is used to store one vector, and the data length that can be stored in each vector physical register group is 256 bits. In this way, the instruction pipeline can support vector calculations with longer vector lengths.

[0106] After completing the vector physical register grouping, the vector physical register control circuit may send the grouping information of the vector physical register to the renaming unit. The grouping information of the vector physical register may include the number of vector physical register groups, the identifiers of the vector physical registers included in each vector physical register group, and the group identifier of each vector physical register group. Exemplarily, the grouping information of the following vector physical registers may be shown in the following Table 2:

[0107] Table 2

[0108]

[0109] Of course, the above steps 203 and 204 may also be implemented by other hardware in the processor, such as a renaming unit, and the present disclosure does not limit the specific execution subject.

[0110] Based on the above vector computing power allocation, the present disclosure also provides a vector computing method, see Figure 7 , the method may include the following processing steps:

[0111] Step 301: A decoding unit decodes the code to obtain at least one set of vector operation information.

[0112] In implementation, the decoding unit obtains the code, decodes the code, and obtains at least one set of vector operation information, wherein each set of vector operation information includes a vector calculation instruction, an identifier of an architectural register (Architected Register Number, ARN) of each calculation data, and an identifier of an architectural register of a calculation result. The vector calculation instruction may be a micro operation code (Micro operation code, μop). The calculation data refers to the data involved in the vector calculation, for example, if the vector calculation is A+B, then vector A and vector B are the calculation data.

[0113] Step 302: The decoding unit sends the at least one set of vector operation information to the renaming unit.

[0114] Step 303: For each vector computing instruction, the renaming unit determines a destination vector physical register group corresponding to the vector computing instruction.

[0115] The destination vector physical register group is used to store the calculation results of the vector calculation instructions.

[0116] In implementation, a renaming list is recorded in the renaming unit or the reordering buffer, and the renaming list includes the correspondence between the identifier of the architecture register and the group identifier of the vector physical register group, and the correspondence can be changed dynamically. For each set of vector operation information received, the renaming unit obtains the identifier of the architecture register of each calculation data in the vector operation information, and inquires the group identifier of the original vector physical register group corresponding to the identifier of the architecture register of each calculation data in the above renaming list. Then, the calculation data is read in the original vector physical register group obtained by inquiry.

[0117] A status list of physical vector register groups is also recorded in the renaming unit or the reordering buffer, and the status list includes a correspondence between a group identifier of a vector physical register group and status indication information of the vector physical register group. For a vector calculation instruction in each set of vector operation information received, the renaming unit selects a physical vector register group with an idle status in the status list as a destination vector physical register group corresponding to the vector calculation instruction based on a correlation between the vector calculation instruction and other vector calculation instructions in the at least one vector operation information.

[0118] In addition, in order to return the calculation result according to the order of the vector calculation instructions in the code in the scenario where the vector calculation instructions are executed out of order, the renaming unit can send the vector calculation instructions in the at least one vector operation information to the reorder buffer according to the order of the vector calculation instructions in the code. The reorder buffer assigns a ROB id to each vector calculation instruction, and the ROB id is used to indicate the order of the corresponding vector calculation instructions in the code.

[0119] Step 304: The renaming unit sends the vector calculation instruction, the calculation data of the vector calculation instruction, and the group identifier of the destination vector physical register group corresponding to the vector calculation instruction to the issue unit.

[0120] In a possible implementation, when the reorder buffer assigns a ROB id to the vector calculation instruction, the renaming unit may also obtain the ROB id corresponding to each vector calculation instruction, and send the ROB id of the vector calculation instruction together with the vector calculation instruction to the emission unit.

[0121] Step 305: The issuing unit sends the vector computing instruction, the computing data of the vector computing instruction, and the group identifier of the destination vector physical register group corresponding to the vector computing instruction to the vector execution unit.

[0122] In implementation, the transmitting unit obtains the state of the vector execution unit and determines the vector execution unit that is in an idle state. Specifically, when receiving the vector calculation instruction, the transmitting unit can determine the operator included in each vector execution unit according to the configuration information of the vector execution unit, and then obtain the state of the operator included in the vector execution unit. If the operators included in the vector execution unit are all in an idle state, the vector execution unit is determined to be in an idle state.

[0123] For each vector calculation instruction, the issuing unit sends the vector calculation instruction, the calculation data of the vector calculation instruction and the group identifier of the destination vector physical register group corresponding to the vector calculation instruction to an idle vector execution unit. In the case of multiple idle vector execution units, the issuing unit can simultaneously send the vector calculation instructions to the multiple idle vector execution units respectively.

[0124] In a possible implementation, when the reorder buffer allocates a ROB id to the vector computing instruction, the renaming unit may also send the ROB id of the vector computing instruction together with the vector computing instruction to the vector execution unit.

[0125] Step 306: The vector execution unit calculates the calculation data according to the vector calculation instruction to obtain a calculation result, and writes the calculation result into the destination vector physical register group corresponding to the vector calculation instruction.

[0126] In implementation, the vector execution unit includes multiple operators, and the emission unit can divide the two calculation data of the vector calculation instruction into multiple groups of elements, and send a group of elements to an operator, which performs the operation of the group of elements to obtain the element calculation result. For example, the vector operation indicated by the vector calculation instruction is vector addition, and the calculation data includes A and B, where A is a vector: (A1, A2, A3, A4), and B is a vector: (B1, B2, B3, B4). The vector execution unit includes four operators, then A1 and B1 are a group of elements, A2 and B2 are a group of elements, A3 and B3 are a group of elements, and A4 and B4 are a group of elements. The four operators calculate A1+B1, A2+B2, A3+B3, and A4+B4 respectively.

[0127] The operator sends the element calculation results to the vector physical register control circuit in sequence. At the same time, the operator also sends the group identifier of the destination vector physical register group corresponding to the vector execution unit to the vector physical register control circuit. The vector physical register control circuit records the grouping information of the vector physical registers. The vector physical register control circuit queries the vector physical registers included in the destination vector physical register group and writes the calculation results into the vector physical registers included in the destination vector physical register group.

[0128] In a possible implementation, when the reorder buffer allocates a ROB id to the vector calculation instruction, the vector execution unit may also send the ROB id corresponding to the vector calculation instruction and the calculation result of the vector calculation instruction to the vector physical register control circuit. Accordingly, the vector physical register control circuit may write the calculation result of the vector calculation instruction into the corresponding physical vector register group in sequence according to the ROB id.

[0129] Figure 8 is a schematic diagram of the structure of a processor provided by the present disclosure, such as Figure 8 As shown, the processor 800 includes a logic circuit 801 and a power supply circuit 802. The logic circuit 801 may include at least one Figure 1 The power supply circuit 802 is used to supply power to the logic circuit 801 .

[0130] In a possible implementation, the processor 1801 may be a CPU or other general-purpose processor, and the processor 1801 may also be one or more integrated circuits for implementing the disclosed solution, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), a discrete gate or transistor logic device, a discrete hardware component, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0131] Fig. 9 is a schematic diagram of a computing device provided by the present disclosure, such as Fig. 9As shown, computing device 900 includes: bus 902, processor 904, memory 906 and communication interface 908. Processor 904, memory 906 and communication interface 908 communicate through bus 902. Bus 902 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one line is used to represent it, but it does not mean that there is only one bus or one type of bus. Bus 902 may include a path for transmitting information between various components of computing device 900 (e.g., memory 906, processor 904, communication interface 908). Processor 904 may include any one or more of processors such as CPU, graphics processing unit (GPU), microprocessor (MP) or digital signal processor (DSP). Memory 906 can be used as the memory or external memory of computing device 900. Memory 906 may include volatile memory, such as random access memory (RAM). Memory 906 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid state drive (SSD).

[0132] Fig.10 A vector computing power distribution device provided by the present disclosure is as follows: Fig.10 As shown, the device 1000 includes a determination module 1001, an operator allocation module 1002, and a vector calculation module 1003, wherein:

[0133] A determination module 1001, configured to determine whether the system vector length is updated from a first vector length to a second vector length;

[0134] An operator allocation module 1002 is used to select an operator in a vector computing power pool based on the second vector length, and configure a first vector execution unit, where the first vector execution unit is a vector execution unit that executes the second vector length, and the first vector execution unit is composed of at least one operator, and a total data length that can be calculated by the at least one operator is greater than or equal to the second vector length;

[0135] The vector calculation module 1003 is used to perform vector operations of the second vector length.

[0136] It should be understood that the device provided in the present application can be implemented by a central processing unit (CPU), or by an application-specific integrated circuit (ASIC), or a programmable logic device (PLD), and the above-mentioned PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or a data processing unit (DPU), a system on chip (SoC), an offload card or any combination thereof. It can also be implemented by the above-mentioned Figure 1 The control circuit of the operator in the implementation, or, Figure 8 The processor shown or Fig. 9 When the computing power allocation method described above can also be implemented by software, the apparatus 1000 and its various modules can also be software modules.

[0137] In a possible implementation, the operator allocation module 1002 is used to:

[0138] Determine a first number of operators included in the first vector execution unit based on a multiple relationship between the second vector length and a data length that can be calculated by a single operator;

[0139] An operator is selected from the vector computing power pool, and a first number of the selected operators are configured as a first vector execution unit.

[0140] In a possible implementation, when the second vector length is less than the first vector length, before selecting an operator from the vector computing power pool and configuring the selected first number of operators as the first vector execution unit, the operator allocation module 1002 is further used to:

[0141] Compare a second number of operators included in a second vector execution unit with the first number to determine that the second number is greater than the first number, wherein the second vector execution unit is a vector execution unit that executes the first vector length.

[0142] In a possible implementation, when the second vector length is greater than the first vector length, before selecting an operator from the vector computing power pool and configuring the selected first number of operators as the first vector execution unit, the operator allocation module 1002 is further used to:

[0143] Compare a third number of operators included in a second vector execution unit with the first number to determine that the third number is smaller than the first number, wherein the second vector execution unit is a vector execution unit that executes the first vector length.

[0144] In a possible implementation, the operator allocation module 1002 is used to:

[0145] According to the identifier of each operator in the vector computing power pool, an operator is selected in the vector computing power pool, and a first number of the selected operators are configured as a first vector execution unit.

[0146] In a possible implementation manner, the device further includes a vector physical register allocation module, configured to:

[0147] Based on the second vector length, a vector physical register is selected to configure at least one vector physical register group, each vector physical register group includes at least one vector physical register, and a total data length that can be stored by the at least one vector physical register is greater than or equal to the second vector length.

[0148] In a possible implementation, the vector physical register allocation module is used to:

[0149] determining a fourth number of vector physical registers included in each vector physical register group based on a multiple relationship between the second vector length and a length of data storable by a single vector physical register;

[0150] Vector physical registers are selected, and every fourth number of the selected vector physical registers are configured as a vector physical register group.

[0151] In a possible implementation manner, when the length of the second vector is less than the length of the first vector, the vector physical register allocation module is further configured to:

[0152] It is determined that a fifth number of vector physical registers included in each current vector physical register group is greater than the fourth number.

[0153] In a possible implementation, when the second vector length is greater than the first vector length, before selecting the vector physical registers and configuring every fourth number of selected vector physical registers as a vector physical register group, the method further includes:

[0154] It is determined that a sixth number of vector physical registers included in each current vector physical register group is smaller than the fourth number.

[0155] In a possible implementation, the vector physical register allocation module is used to:

[0156] According to the identifier of each vector physical register, a vector physical register is selected, and every fourth number of the selected vector physical registers is configured as a vector physical register group.

[0157] In a possible implementation, the vector physical register allocation module is further used to:

[0158] Assigning a group identifier to each vector physical register group;

[0159] A correspondence between a group identifier of a vector physical register group and state indication information of the vector physical register group is established, wherein the state indication information is used to indicate whether the vector physical register group is idle.

[0160] In a possible implementation manner, the first vector execution unit is further configured to:

[0161] Get vector calculation instructions;

[0162] According to the corresponding relationship, determining a destination vector physical register group corresponding to the vector calculation instruction in an idle vector physical register group;

[0163] The vector calculation instruction is executed by the first vector execution unit, and a calculation result corresponding to the vector calculation instruction is written into the destination vector physical register group.

[0164] The device 1000 for allocating vector computing power is applied to the above Figure 8 and 9In the processor, when the device 1000 performs vector computing power allocation, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functional allocation can be completed by different functional modules as needed, that is, the internal structure of the device 1000 for vector computing power allocation is divided into different functional modules to complete all or part of the functions described above. In addition, the device 1000 for vector computing power allocation and the above-mentioned method for vector computing power allocation belong to the same concept. The specific implementation process is detailed in the above-mentioned method flow of vector computing power allocation, which will not be repeated here.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for allocating vector computing power, characterized in that: The method comprises: Determine that the system vector length is updated from the first vector length to the second vector length; Based on the second vector length, selecting an operator in the vector computing power pool, configuring a first vector execution unit, the first vector execution unit being a vector execution unit that executes the second vector length, the first vector execution unit being composed of at least one operator, and a total data length that can be calculated by the at least one operator is greater than or equal to the second vector length; The first vector execution unit performs a vector operation of the second vector length.

2. The method according to claim 1, characterized in that: The selecting a computing unit in the vector computing power pool based on the second vector length and configuring at least one vector execution unit includes: Determine a first number of operators included in the first vector execution unit based on a multiple relationship between the second vector length and a data length that can be calculated by a single operator; An operator is selected from the vector computing power pool, and a first number of the selected operators are configured as a first vector execution unit.

3. The method according to claim 2, characterized in that When the second vector length is less than the first vector length, before selecting an operator from the vector computing power pool and configuring the selected first number of operators as the first vector execution unit, the method further includes: Compare a second number of operators included in a second vector execution unit with the first number to determine that the second number is greater than the first number, wherein the second vector execution unit is a vector execution unit that executes the first vector length.

4. The method according to claim 2, characterized in that: When the second vector length is greater than the first vector length, before selecting an operator from the vector computing power pool and configuring the selected first number of operators as the first vector execution unit, the method further includes: Compare a third number of operators included in a second vector execution unit with the first number to determine that the third number is smaller than the first number, wherein the second vector execution unit is a vector execution unit that executes the first vector length.

5. The method according to any one of claims 2 to 4, characterized in that: The selecting of operators from the vector computing power pool and configuring each of the first number of operators selected as a vector execution unit includes: According to the identifier of each operator in the vector computing power pool, an operator is selected in the vector computing power pool, and a first number of the selected operators are configured as a first vector execution unit.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Based on the second vector length, a vector physical register is selected to configure at least one vector physical register group, each vector physical register group includes at least one vector physical register, and a total data length that can be stored by the at least one vector physical register is greater than or equal to the second vector length.

7. The method according to claim 6, characterized in that The selecting a vector physical register based on the second vector length and configuring at least one vector physical register group includes: determining a fourth number of vector physical registers included in each vector physical register group based on a multiple relationship between the second vector length and a length of data storable by a single vector physical register; Vector physical registers are selected, and every fourth number of the selected vector physical registers are configured as a vector physical register group.

8. The method according to claim 7, characterized in that In a case where the second vector length is less than the first vector length, before selecting the vector physical registers and configuring every fourth number of selected vector physical registers as a vector physical register group, the method further includes: It is determined that a fifth number of vector physical registers included in each current vector physical register group is greater than the fourth number.

9. The method according to claim 7, characterized in that: In a case where the second vector length is greater than the first vector length, before selecting the vector physical registers and configuring every fourth number of selected vector physical registers as a vector physical register group, the method further includes: It is determined that a sixth number of vector physical registers included in each current vector physical register group is smaller than the fourth number.

10. The method according to any one of claims 7 to 9, characterized in that: The selecting of the vector physical registers configures each fourth number of the selected vector physical registers into a vector physical register group, including: According to the identifier of each vector physical register, a vector physical register is selected, and every fourth number of the selected vector physical registers is configured as a vector physical register group.

11. The method according to any one of claims 7 to 10, characterized in that: After configuring every fourth number of selected vector physical registers as a vector physical register group, the method further includes: Assigning a group identifier to each vector physical register group; A correspondence between a group identifier of a vector physical register group and state indication information of the vector physical register group is established, wherein the state indication information is used to indicate whether the vector physical register group is idle.

12. The method according to claim 11, characterized in that The first vector execution unit performs the vector operation of the second vector length, comprising: Get vector calculation instructions; According to the corresponding relationship, determining a destination vector physical register group corresponding to the vector calculation instruction in an idle vector physical register group; The vector calculation instruction is executed by the first vector execution unit, and a calculation result corresponding to the vector calculation instruction is written into the destination vector physical register group.

13. A device for allocating vector computing power, characterized in that: The device comprises: A determination module, used for determining that the system vector length is updated from the first vector length to the second vector length; a vector computing power allocation module, configured to select an operator in a vector computing power pool based on the second vector length, and configure a first vector execution unit, wherein the first vector execution unit is a vector execution unit that executes the second vector length, and the first vector execution unit is composed of at least one operator, and a total data length that can be calculated by the at least one operator is greater than or equal to the second vector length; A vector calculation module is used for executing vector operations of the second vector length by the first vector execution unit.

14. A processor, characterized in that: The processor includes a logic circuit and a power supply circuit, and the logic circuit is used to execute the method of vector computing power allocation as described in claims 1 to 12 above.

15. A computing device, characterized in that: The computing device includes a processor and a memory, and the processor is used to execute the method for allocating vector computing power as described in claims 1 to 12 above.

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