Memristor neural computing system fault detection method based on digital twinning technology

Abstract

The invention relates to a memristor neural computing system fault detection method based on a digital twinning technology, and the method comprises the steps: collecting and sensing voltage, current, related technological parameters and geometric parameters, and inputting the parameters into a digital twinning system; the digital twinning system comprises an RRAM physical model, an RRAM digital twinning model, an RRAM simulation detection model, a dynamic geometric model and a digital twinning database; and the digital twin system outputs a fault error position, downtime and a parameter adjustment strategy, and feeds back voltage, current, process parameters and geometric parameters to the RRAM physical model. Through the accurate digital twinborn model and real-time data analysis, the method can quickly and accurately identify the potential fault of the RRAM equipment, and has higher efficiency and accuracy compared with a traditional physical detection method.

Description

Technical Field

[0001] The present invention relates to a memristor neural computing system fault detection method based on digital twin technology, and belongs to the technical field of memristor neural computing system fault detection. Background Art

[0002] In the era of big data and advanced computing, the demand for computing power is growing. Currently, most computing devices are based on the von Neumann architecture, which inherently separates storage and computing, leading to data transmission bottlenecks and energy efficiency issues. To overcome these limitations, resistive random access memory (RRAM), as a new type of non-volatile memory technology, has attracted much attention due to its high density, low power consumption and fast response time. RRAM is particularly important in neural network computing systems because it can achieve efficient weight storage and neuron simulation.

[0003] However, RRAM devices are prone to failure during long-term use, such as the formation and destruction of conductive filaments, unstable redox reactions, etc. These failures can affect the reliability and performance of RRAM devices, especially in neural computing systems, where fault detection becomes a major challenge. Traditional fault detection methods rely on physical testing and analysis, which is not only time-consuming and labor-intensive, but may also bring physical risks.

[0004] In this context, the use of digital twin technology to solve the problem of RRAM fault detection is proposed. Digital twin technology can simulate and analyze RRAM devices without physical risks by creating accurate virtual models. This approach can improve the reliability of RRAM devices and reduce unexpected downtime through predictive maintenance and early fault detection, which is particularly suitable for demanding neural computing systems.

[0005] Although digital twin technology has been applied in other fields, its application in RRAM fault detection is an innovation that solves many problems and limitations in traditional methods. In addition, this method overcomes the difficulties encountered in traditional RRAM fault detection, such as insufficient understanding of fault mechanisms and lack of efficient fault prediction and analysis tools. Therefore, the method proposed in the present invention not only helps to improve the reliability of RRAM devices in neural computing systems, but also provides a new solution for the long-term stable use of RRAM.

[0006] Current RRAM fault detection methods mainly rely on physical testing, which is not only time-consuming and risky, but also unable to monitor and predict potential failures in real time. Secondary technical issues: Reduce the unexpected downtime and repair time of neural computing systems caused by RRAM failures. In traditional methods, once a failure occurs, time-consuming and costly physical inspection and repair are often required, which is particularly disadvantageous in applications with high reliability requirements.

[0007] The memristor neural computing system is a neural network computing system based on memristor devices. It combines the physical properties of memristors with the computing mechanism of neural networks, aiming to simulate the behavior of biological neural networks and improve computing efficiency. A memristor is a basic circuit element with a memory effect, and its resistance value can change as the charge passing through it changes. The resistance of a memristor depends not only on the current current, but also on the amount of charge that has passed through it in the past. This means that a memristor can "remember" past states, so it has important applications in the fields of storage and computing. In artificial neural networks, memristors are often used as weight memories. Weights are parameters that connect different neurons in a neural network and determine how inputs affect outputs. Using memristors, these weights can be stored directly in hardware, avoiding the bottleneck of separation of computing and storage in the traditional von Neumann architecture. Because memristors are non-volatile, they can save the weights in a neural network without losing data even when the power is turned off. Therefore, it is particularly suitable for long-term and stable neural computing. In a memristor neural computing system, the input signal of each neuron is weighted by a memristor and then the result is output. This weighted processing is achieved through the conductance (electrical conductivity) of the memristor, so the forward propagation and backpropagation processes in deep learning can be efficiently performed on hardware. Memristors can be used to simulate the behavior of neurons, making them exhibit the characteristics of brain-like computing in the computing process. Through the parallel and series structures of multiple memristors, the hierarchical structure in the neural network can be simulated to handle complex computing tasks such as pattern recognition, image processing and classification. Since memristor devices may fail during long-term use, such as unstable conductive filament formation and material degradation, fault detection is particularly important in such systems. The introduction of digital twin technology can help build virtual models, detect and predict memristor failures in real time, and ensure the reliability and stability of neural computing systems.

[0008] In summary, the memristor neural computing system combines the storage and computing functions of memristors to achieve efficient brain-like computing at the hardware level. It not only has energy efficiency advantages that are difficult to match with traditional computing systems, but also provides hardware acceleration support for complex computing tasks such as deep learning. Summary of the invention

[0009] In view of the deficiencies in the prior art, the present invention provides a fault detection method for a memristor neural computing system based on digital twin technology, which is used to improve the fault detection efficiency and accuracy of memristor (RRAM) devices in neural computing systems.

[0010] The technical solution of the present invention is:

[0011] A fault detection method for a memristor neural computing system based on digital twin technology includes:

[0012] Collect and sense voltage, current, related process parameters, and geometric parameters, and input them into the digital twin system;

[0013] The digital twin system includes RRAM physical model, RRAM digital twin model, RRAM simulation detection model, dynamic geometry model and digital twin database;

[0014] The digital twin system outputs fault error location, downtime and parameter adjustment strategy, and feeds back voltage, current, process parameters and geometric parameters to the RRAM physical model.

[0015] Preferably, according to the present invention, the RRAM physical model is used to simulate the performance and behavior of the RRAM device under actual working conditions, and is also used to verify the stability and reliability of the RRAM device.

[0016] Preferably according to the present invention, the RRAM digital twin model is a virtualized and digitized representation of the RRAM physical model, which is used to simulate and predict the operating status of the RRAM device; used for fault prediction and analysis, identifying and locating possible fault points, and evaluating the long-term performance of the RRAM device; used for optimization and adjustment, proposing parameter adjustment strategies, and improving the reliability of the RRAM device.

[0017] Preferably, according to the present invention, the RRAM simulation detection model simulates the calculation process of the RRAM neural network, including forward propagation and back propagation processes.

[0018] Preferably, according to the present invention, a dynamic geometry model is used to describe the geometric changes of the physical structure of the RRAM device.

[0019] Preferably, according to the present invention, in the RRAM simulation detection model, the simulation of the RRAM neural network calculation process is realized; comprising:

[0020] The first step is to understand the calculation process of RRAM. The forward propagation process in RRAM is expressed by formula (1):

[0021] i out =G·v in +g (1);

[0022] In RRAM neural network, i out represents the output current matrix, v in represents the input voltage matrix, G represents the weight matrix, and g represents the bias matrix;

[0023] In the second step, in the RRAM simulation detection model, the rules for updating weights and biases during the back-propagation process of the RRAM neural network are inferred; the output current of the RRAM neural network is converted into a probability distribution when using the cross-entropy loss function to handle multi-class problems; assuming that Ii represents the current of the output neuron of the i-th layer, and the conversion of probability using the Softmax function is expressed as formula (2):

[0024]

[0025] Among them, K represents the total number of output categories, P(y i ) represents the probability predicted by the RRAM neural network for the i-th class; therefore, the cross entropy loss L formula is expressed as formula (3):

[0026]

[0027] Among them, t i represents the one-hot encoding of the true label. If the i-th class is the correct class, then t i =1; otherwise, t i =0;

[0028] Therefore, the error δ of the output layer i The formula is formula (4):

[0029] δ i =P(y i )-t i . (4);

[0030] The error term of the ith neuron in the lth layer is expressed as The conductivity of the i-th neuron in the l-th layer and the j-th neuron in the 1st layer is recorded as The derivative of the activation function is denoted as f'; therefore, the formula for the error term is formula (5):

[0031]

[0032] Among them, δ i is the error, is the error of the jth neuron in the l+1th layer, V i (l) is the voltage of the ith neuron in the lth layer;

[0033] The change in conductivity between the ith neuron in layer l and the jth neuron in layer 1 is denoted by Used to update synaptic weights; the weight update formula is formula (6):

[0034]

[0035] in, is the old conductivity between the i-th and j-th neurons in layer l, That is, the updated conductivity; α represents the learning rate; the conductivity change of the bias of the i-th neuron in the first layer is expressed as Represents; the bias update formula is formula (7):

[0036]

[0037] is the old bias conductivity between the i-th and j-th neurons in layer l, That is, its updated bias conductivity.

[0038] Preferably, according to the present invention, the errors and failures of RRAM are simulated by using an RRAM error model; comprising:

[0039] RRAM errors and failures include soft errors and hard errors;

[0040] In the event of a soft error, the actual resistance of the RRAM cell differs from its expected value; for low resistance states, especially below 30 kOhm, the deviation during a soft error follows a log-normal distribution; in the log-normal distribution, the mean corresponds to the expected resistance setting of the RRAM, while the variance increases gradually with the number of write cycles; this log-normal distribution f(r; μ, σ) is described as equation (8):

[0041]

[0042] Where r is the resistance, μ is the mean, and σ is the standard deviation;

[0043] Convert equation (8) into the probability density distribution of conductivity f H (g), which is formula (9):

[0044]

[0045] Here, g refers to the electrical conductivity.

[0046] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of a fault detection method for a memristor neural computing system based on digital twin technology are implemented.

[0047] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a memristor neural computing system fault detection method based on digital twin technology.

[0048] The beneficial effects of the present invention are:

[0049] 1. Improve the accuracy and efficiency of fault detection: Through precise digital twin models and real-time data analysis, the invention can quickly and accurately identify potential faults of RRAM devices, with higher efficiency and accuracy than traditional physical detection methods.

[0050] 2. Reduce maintenance costs and risks: Since this method can predict and analyze failures without direct contact with physical equipment, it greatly reduces the physical risks and costs of the maintenance process, which is especially important in high-risk or difficult-to-access environments.

[0051] 3. Reduce system downtime: Through the predictive maintenance mechanism, failures can be predicted and measures can be taken before they occur, thereby reducing the unexpected downtime of the neural computing system and ensuring the stable operation and efficient performance of the system.

[0052] 4. Optimize fault diagnosis and processing: The present invention can not only accurately detect faults, but also provide specific processing suggestions based on the fault type, helping technicians solve problems more efficiently and accurately.

[0053] 5. Wide applicability: This approach is not limited to a specific type or size of RRAM devices and can be widely used in various neural computing systems to provide flexible fault detection and maintenance solutions.

[0054] 6. Enhanced system reliability and lifespan: By promptly identifying and resolving potential problems with RRAM devices, the invention helps improve overall system reliability and extend device lifespan. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is a block diagram of the implementation of a fault detection method for a memristor neural computing system based on digital twin technology;

[0056] Figure 2 A schematic diagram of the simulation of the RRAM neural network computing process; DETAILED DESCRIPTION

[0057] The present invention will be further defined below in conjunction with the accompanying drawings and embodiments, but is not limited thereto.

[0058] Example 1

[0059] Fault detection method of memristor neural computing system based on digital twin technology, such as Figure 1 As shown, including:

[0060] Collect and sense voltage, current, related process parameters, and geometric parameters, and input them into the digital twin system;

[0061] The digital twin system includes an RRAM physical model, an RRAM digital twin model, an RRAM simulation detection model, a dynamic geometry model, and a digital twin database; the digital twin system includes real-time mapping of the RRAM physical model and the RRAM digital twin model. In order to realize the detection and feedback optimization functions of the digital twin, the digital twin system also includes an RRAM simulation detection model and a dynamic geometry model driven by the digital twin. After the data of the RRAM physical model is collected, it is uniformly managed in the digital twin database and supports the operation of other digital twin parts;

[0062] The digital twin system outputs fault error location, downtime and parameter adjustment strategy, and feeds back voltage, current, process parameters and geometric parameters to the RRAM physical model.

[0063] Example 2

[0064] The difference between the memristor neural computing system fault detection method based on digital twin technology described in Example 1 is that:

[0065] The RRAM physical model is used to simulate the performance and behavior of RRAM devices under actual working conditions. It is also used to verify the stability and reliability of RRAM devices.

[0066] The RRAM physical model is built based on the physical properties of RRAM devices, including the basic structure, material properties, electrical properties, etc. of RRAM. It describes in detail the behavior of RRAM in actual operation, such as changes in conductivity, switching characteristics, and memory effects. An equivalent circuit model of RRAM is usually included to simulate its actual working state. The RRAM physical model is used to simulate the performance and behavior of RRAM devices under actual working conditions. By real-time monitoring of current, voltage, and resistance changes, the working state of RRAM can be understood, providing basic data for the digital twin model. At the same time, the RRAM physical model is used to verify the stability and reliability of RRAM devices and help identify potential hardware failures.

[0067] The RRAM digital twin model is a virtualized and digital representation of the RRAM physical model. It is used to simulate and predict the operating status of the RRAM device. It is used for fault prediction and analysis, identifying and locating possible fault points, and evaluating the long-term performance of the RRAM device. It is used for optimization and adjustment, proposing parameter adjustment strategies, and improving the reliability of the RRAM device.

[0068] The RRAM digital twin model is a virtualized and digitalized representation of the RRAM physical model. A virtual model similar to the actual RRAM device characteristics is constructed through digital twin technology. It contains key characteristic parameters of RRAM, such as conductivity, temperature change, and voltage response. The model can receive and process data from the physical model in real time, and update and adjust accordingly.

[0069] The RRAM simulation detection model reflects the application of RRAM in neural networks by simulating the calculation process of RRAM neural networks, including forward propagation and back propagation processes.

[0070] The RRAM simulation detection model integrates the error model of RRAM devices to simulate and detect possible soft errors and hard errors. It contains a detailed description of the cross entropy loss function and the weight update mechanism to simulate the calculation process in the deep neural network. It is used to simulate the calculation process and failure conditions of the RRAM neural network. It can help detect potential faults in the RRAM neural network, such as resistance value deviation, conductivity anomaly, etc. During the training process, the model can simulate the forward and backward propagation processes and adjust the weights of the neural network in real time to ensure the accuracy and stability of the model. At the same time, through the simulation detection model, the performance of the RRAM device can be optimized to improve its reliability in the neural computing system.

[0071] Dynamic geometry models are used to describe the geometric changes of the physical structure of RRAM devices.

[0072] Dynamic geometric models include size changes, shape changes, and structural stresses. Dynamic geometric models can dynamically adjust the geometry and size of RRAM devices according to their actual working environment and conditions to simulate their behavior under different conditions. It usually includes modules such as stress-strain analysis and thermal analysis. By dynamically simulating the geometric characteristics of RRAM devices, it is possible to predict structural changes that may occur during long-term use, such as material degradation and deformation. This is very important for evaluating the mechanical stability and durability of RRAM devices and helps to identify possible physical failures in advance. In addition, dynamic geometric models can be used to optimize the design of RRAM and provide a more stable physical structure to improve its long-term performance in neural computing systems.

[0073] In the RRAM simulation detection model, the simulation of the RRAM neural network calculation process is realized; Figure 2 As shown, including:

[0074] The core task of the RRAM simulation detection model is to simulate the calculation process of RRAM in the neural network, including forward propagation and back propagation. The purpose of this simulation is to accurately reproduce the operation mechanism of the RRAM neural network in a virtual environment for fault detection, performance evaluation and optimization.

[0075] In the construction process of memristor (RRAM), a comprehensive understanding of its calculation process is crucial to accurately establish its digital twin simulation. Since RRAM is generally used to replace traditional computing devices for deep learning process calculations, this paper mainly introduces the application process of RRAM in deep neural network calculations. Therefore, the first step is to understand the calculation process of RRAM. The forward propagation process in RRAM is expressed by formula (1):

[0076] i out =G·v in +g (1);

[0077] In RRAM neural network, i out represents the output current matrix, v in represents the input voltage matrix, G represents the weight matrix, and g represents the bias matrix; including G NOK It is composed of equal impedance units, G, g is their conductivity;

[0078] In the forward propagation process of the deep neural network, the input voltage of each layer is processed by impedance to generate the output current of the next layer of horizontal bars; the output current generates voltage on the horizontal bars of the next layer in turn, which serves as the input of the next neural network layer; through this layered calculation, the forward propagation in the deep neural network is realized;

[0079] The second step is to infer the rules for updating weights and biases during the back propagation of the RRAM neural network in the RRAM simulation detection model; usually, the back propagation of the RRAM neural network starts with calculating the loss. The present invention utilizes the commonly used cross entropy loss function. When using the cross entropy loss function to deal with multi-class problems, the output current of the RRAM neural network is converted into a probability distribution; assuming I i represents the current of the output neuron of the i-th layer, and the conversion of probability using the Softmax function is expressed as formula (2):

[0080]

[0081] Among them, K represents the total number of output categories, P(y i ) represents the probability predicted by the RRAM neural network for the i-th class; therefore, the cross entropy loss L formula is expressed as formula (3):

[0082]

[0083] Among them, t i represents the one-hot encoding of the true label. If the i-th class is the correct class, then t i =1; otherwise, t i= 0; this formula allows the actual classes to be accurately represented in the output of the model, enabling efficient computation of the cross entropy loss.

[0084] Therefore, the error δ of the output layer i The formula is formula (4):

[0085] δ i =P(y i )-t i . (4);

[0086] Once the error term formula for the output layer is established, the error term formula for the intermediate layer can be derived. The error term for the ith neuron in the lth layer is expressed as The conductivity of the i-th neuron in the l-th layer and the j-th neuron in the 1st layer is recorded as The derivative of the activation function is denoted as f'; therefore, the formula for the error term is formula (5):

[0087]

[0088] Among them, δ i is the error, is the error of the jth neuron in the l+1th layer, V i (l) is the voltage of the ith neuron in the lth layer;

[0089] The change in conductivity between the ith neuron in layer l and the jth neuron in layer 1 is denoted by Used to update synaptic weights; the weight update formula is formula (6):

[0090]

[0091] in, is the old conductivity between the i-th and j-th neurons in layer l, That is, the updated conductivity; α represents the learning rate; the conductivity change of the bias of the i-th neuron in the first layer is expressed as Represents; the bias update formula is formula (7):

[0092]

[0093] is the old bias conductivity between the i-th and j-th neurons in layer l, That is, its updated bias conductivity.

[0094] According to the above rules, the digital twin model of RRAM can be simulated and established in the virtual space to simulate its deep learning computing process.

[0095] The hardware architecture of the RRAM neural network mainly consists of the following parts:

[0096] 1) Neuron layer, including:

[0097] Input layer: The input layer receives external signals and processes them through the RRAM array.

[0098] Hidden layer: The hidden layer in the RRAM neural network simulates the intermediate output of the neural network. The neurons in each layer will process according to the weights passed from the previous layer to generate new outputs.

[0099] Output layer: The output layer in the RRAM neural network simulates the final output of the neural network.

[0100] 2) RRAM array

[0101] RRAM storage matrix: In the calculation of each layer of the neural network, the weights are stored in the resistance state of the RRAM cells. The RRAM array is arranged in a two-dimensional matrix, and each intersection represents a weight connection.

[0102] Multiplication and addition operation: The core operation in neural networks is the multiplication of input signals and weights, which can be achieved through the conductivity characteristics of RRAM. When the input signal is applied to the RRAM array, the conductivity of the RRAM memory cell is multiplied by the input signal, and the calculation result is the parallel weighted summation of multiple signals and weights.

[0103] 3) Control and feedback mechanisms

[0104] Read / write control: Each RRAM cell can have its resistance state controlled by a voltage pulse, thereby changing the weight. This read / write operation is the basis of the learning and updating process of the entire neural network.

[0105] Back propagation: During the training process, the back propagation algorithm is used to update the weights in the network. This process relies on the precise control of the resistance value of the RRAM cell. By controlling the voltage pulse, the resistance value in the RRAM can be updated, thereby achieving the update of the neural network weights.

[0106] 4) The operating mechanism of RRAM neural network:

[0107] Forward propagation: During forward propagation, input data is fed into the RRAM array, and the voltage signal passes through the RRAM storage unit to generate an output current. This process is similar to matrix multiplication, that is, the input signal matrix is ​​multiplied by the weight matrix, and the output result is used as the input of the next layer.

[0108] Back propagation and weight update: By calculating the gradient of the loss function, the neural network needs to adjust the weight of each connection, and the resistance value of the RRAM unit will be adjusted according to the calculation results to optimize the performance of the network.

[0109] RRAM error and failure simulation is performed through the RRAM error model; including:

[0110] In addition to simulating the computing process, it is also necessary to simulate the errors and failures of RRAM and establish an RRAM error model. The RRAM error model is used to simulate the errors and failures that may occur in RRAM devices during use, including soft errors (SoftErrors) and hard errors (Hard Errors). These errors will affect the performance and reliability of RRAM in neural computing systems, so they need to be simulated and analyzed in detail to achieve accurate fault detection and prediction. RRAM errors and failures include soft errors and hard errors; soft failures occur when the resistance of the RRAM cell remains in an adjustable state but deviates from the expected value. RRAM cells are the basic building blocks of RRAM (Resistive Random-Access Memory) devices and play a key role in the entire RRAM neural computing system. They are the basic elements for realizing data storage and neural network weight storage. This difference is usually caused by changes in manufacturing technology and write operations. For example, inconsistencies in the manufacturing process or insufficient control accuracy in the write phase may cause the resistance value to deviate from the target target. In the case of hard failures, the resistance of the RRAM cell becomes unchangeable, mainly including 0 (SA0) and 1 (SA1) failures. The origins of hard failures may include defects in the manufacturing process or the limited endurance of the RRAM cell. Certain manufacturing defects may cause the RRAM cell to be permanently fixed at a specific resistance value, while endurance issues may prevent the cell from changing its state after repeated write cycles.

[0111] Research has shown that both soft and hard faults are caused by the degradation of the endurance of the RRAM cell due to repeated writing. The endurance of low-endurance RRAM cells follows a Gaussian distribution, and the average endurance is defined as 5*10^6 with a variance of 1.5*10^6. The high-endurance model also follows a Gaussian distribution, with an average endurance of 10^8 cycles and a variance of 3*10^7. When the endurance threshold is reached, soft and hard faults occur randomly. Hard faults include SA0 faults and SA1 faults. SA0 faults mean that the weights of the neural network are fixed at zero and cannot be updated, while SA1 faults mean that the weights are fixed at 1 and are also not updateable.

[0112] In the event of a soft error, the actual resistance of the RRAM cell differs from its expected value; for the low resistance state (LRS), especially below 30 kOhm, the deviation during a soft error follows a log-normal distribution; in the log-normal distribution, the mean corresponds to the expected resistance setting of the RRAM, while the variance increases gradually with the number of write cycles; this log-normal distribution f(r; μ, σ) is described as equation (8):

[0113]

[0114] Where r is the resistance, μ is the mean, and σ is the standard deviation;

[0115] Convert equation (8) into the probability density distribution of conductivity f H (g), which is formula (9):

[0116]

[0117] Here, g refers to the electrical conductivity.

[0118] In the present invention, advanced digital twin technology is used to create an accurate virtual model of the RRAM device to achieve real-time simulation of its physical properties and performance. This simulation can be performed without affecting the real device, so as to safely and effectively predict and detect potential failures. The present invention realizes real-time data monitoring and analysis: the method collects the operating data of the RRAM device (such as current, voltage, temperature, etc.) and uses algorithms to analyze these data in order to detect abnormal patterns in time, thereby predicting and identifying failures. The present invention designs a predictive maintenance mechanism: using the data obtained from the digital twin model and real-time monitoring, the present invention can implement predictive maintenance, that is, predict and take measures before the failure occurs, thereby reducing downtime and maintenance costs.

[0119] Example 3

[0120] A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the memristor neural computing system fault detection method based on digital twin technology described in Example 1 or 2 are implemented.

[0121] Example 4

[0122] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the memristor neural computing system fault detection method based on digital twin technology described in Example 1 or 2.

Claims

1. A memristor neural computing system fault detection method based on digital twin technology, characterized in that: include: Collect and sense voltage, current, related process parameters, and geometric parameters, and input them into the digital twin system; The digital twin system includes RRAM physical model, RRAM digital twin model, RRAM simulation detection model, dynamic geometry model and digital twin database; The digital twin system outputs fault error location, downtime and parameter adjustment strategy, and feeds back voltage, current, process parameters and geometric parameters to the RRAM physical model.

2. The memristor neural computing system fault detection method based on digital twin technology according to claim 1 is characterized in that: The RRAM physical model is used to simulate the performance and behavior of RRAM devices under actual working conditions. It is also used to verify the stability and reliability of RRAM devices.

3. The memristor neural computing system fault detection method based on digital twin technology according to claim 1 is characterized in that: The RRAM digital twin model is a virtualized and digital representation of the RRAM physical model. It is used to simulate and predict the operating status of the RRAM device. It is used for fault prediction and analysis, identifying and locating possible fault points, and evaluating the long-term performance of the RRAM device. It is used for optimization and adjustment, proposing parameter adjustment strategies, and improving the reliability of the RRAM device.

4. The memristor neural computing system fault detection method based on digital twin technology according to claim 1 is characterized in that: The RRAM simulation detection model simulates the calculation process of the RRAM neural network, including forward propagation and back propagation processes.

5. The memristor neural computing system fault detection method based on digital twin technology according to claim 1 is characterized in that: Dynamic geometry models are used to describe the geometric changes of the physical structure of RRAM devices.

6. The memristor neural computing system fault detection method based on digital twin technology according to claim 1, characterized in that: In the RRAM simulation detection model, the simulation of the RRAM neural network calculation process is realized; including: The first step is to understand the calculation process of RRAM. The forward propagation process in RRAM is expressed by formula (1): i out =G·v in +g(1); In RRAM neural networks, i out represents the output current matrix, v in represents the input voltage matrix, G represents the weight matrix, and g represents the bias matrix; In the second step, in the RRAM simulation detection model, the rules for updating weights and biases during the back-propagation process of the RRAM neural network are inferred; the output current of the RRAM neural network is converted into a probability distribution when using the cross-entropy loss function to handle multi-class problems; assuming that I i represents the current of the output neuron of the i-th layer, and the conversion of probability using the Softmax function is expressed as formula (2): Among them, K represents the total number of output categories, P(y i ) represents the probability predicted by the RRAM neural network for the i-th class; therefore, the cross entropy loss L formula is expressed as formula (3): Among them, t i represents the one-hot encoding of the true label. If the i-th class is the correct class, then t i =1; otherwise, t i =0; Therefore, the error δ of the output layer i The formula is formula (4): δ i =P(y i )-t i . (4); The error term of the ith neuron in the lth layer is expressed as The conductivity of the i-th neuron in the l-th layer and the j-th neuron in the 1st layer is recorded as The derivative of the activation function is denoted as f'; therefore, the formula for the error term is formula (5): Among them, δ i is the error, is the error of the jth neuron in the l+1th layer, is the voltage of the ith neuron in the lth layer; The change in conductivity between the ith neuron in layer l and the jth neuron in layer 1 is denoted by Used to update synaptic weights; the weight update formula is formula (6): in, is the old conductivity between the i-th and j-th neurons in layer l, That is, the updated conductivity; α represents the learning rate; the conductivity change of the bias of the i-th neuron in the first layer is expressed as Represents; the bias update formula is formula (7): is the old bias conductivity between the i-th and j-th neurons in layer l, That is, its updated bias conductivity.

7. The memristor neural computing system fault detection method based on digital twin technology according to any one of claims 1 to 6, characterized in that: RRAM error and failure simulation is performed through the RRAM error model; including: RRAM errors and failures include soft errors and hard errors; In the event of a soft error, the actual resistance of the RRAM cell differs from its expected value; for low resistance states, especially below 30 kOhm, the deviation during a soft error follows a log-normal distribution; in the log-normal distribution, the mean corresponds to the expected resistance setting of the RRAM, while the variance increases gradually with the number of write cycles; this log-normal distribution f(r; μ, σ) is described as equation (8): Where r is the resistance, μ is the mean, and σ is the standard deviation; Convert equation (8) into the probability density distribution of conductivity f H (g), which is formula (9): Here, g refers to the electrical conductivity.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the memristor neural computing system fault detection method based on digital twin technology described in any one of claims 1-7 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the memristor neural computing system fault detection method based on digital twin technology described in any one of claims 1 to 7 are implemented.

Images