Chip performance debugging method, device, system, equipment, medium and product
By acquiring and decrypting the performance data of the GPU chip, and using multiple channels to realize chip performance debugging in a confidential virtual machine environment, the problem of lack of debugging solutions in the existing technology is solved, and safe and efficient GPU chip performance debugging is achieved.
Patent Information
- Application Number
- CN202411260419.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2024-12-20
AI Technical Summary
The existing technology lacks GPU chip performance debugging solutions in a confidential virtual machine environment, which increases the difficulty of confidential and secure design, making it difficult to effectively debug GPU chip performance.
By obtaining the security attribute configuration information of the performance data of the chip to be debugged, select the corresponding path based on the information to obtain the performance data, and perform performance debugging based on the decrypted performance data, including the performance counter sampling module, secure video memory, data encryption module and performance A channel composed of analyzer software buffer.
It realizes GPU chip performance debugging in a confidential virtual machine environment, ensures the security and efficiency of performance data, provides a visual interface to display debugging results, supports encrypted and non-encrypted data transmission paths, and improves security level and accuracy of performance debugging. sex.
Smart Images
Figure CN119166441A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer software technology, and in particular to a chip performance debugging method, device, system, equipment, medium and product. Background Art
[0002] Graphics Processing Unit (GPU) performance debugging is an important process that aims to optimize the performance of GPU chips to ensure that applications (especially graphics-intensive applications such as games and scientific computing) can run efficiently. In order to meet the needs of confidential computing (CC) in the big data era, corresponding confidentiality and security designs need to be added to the hardware design of GPU chips, which increases the difficulty of debugging GPU chip performance. Currently, there is no chip performance debugging solution in a confidential virtual machine (CVM) environment. Summary of the invention
[0003] The present invention provides a chip performance debugging method, device, system, equipment, medium and product, which are used to solve the defect that there is currently no chip performance debugging solution in a confidential virtual machine environment.
[0004] The present invention provides a chip performance debugging method applicable to a confidential virtual machine, the method comprising: Obtain security attribute configuration information of performance data of the chip to be debugged; Acquire the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; According to the performance data of the chip to be debugged, performance debugging is performed on the chip to be debugged.
[0005] As an embodiment, the channel includes a first channel consisting of a performance counter sampling module, a secure display memory, a data encryption module, a springboard buffer, and a performance analyzer software buffer, and a second channel consisting of a performance counter sampling module, a direct data transmission engine, and a performance analyzer software buffer. The performance data of the chip to be debugged is obtained based on a path corresponding to the value of the security attribute configuration information, including: If the value of the security attribute configuration information is characterized by encryption, selecting the first channel to obtain the performance data of the chip to be debugged; If the value of the security attribute configuration information is characterized as not being encrypted, the second channel is selected to obtain performance data of the chip to be debugged.
[0006] As an embodiment, the performance counter sampling module corresponding to the first channel is arranged in the stream processor, and the secure video memory and the data encryption module are arranged in the direct data transmission engine.
[0007] As an embodiment, if the first channel is selected to obtain the performance data of the chip to be debugged, the performance debugging of the chip to be debugged according to the performance data of the chip to be debugged includes: The performance data is decrypted based on a preset key, and performance debugging is performed on the chip to be debugged according to the decrypted performance data.
[0008] As an embodiment, after the performance debugging of the chip to be debugged according to the performance data of the chip to be debugged, the method further includes: The performance debugging results of the chip to be debugged are displayed based on a visual interface.
[0009] The present invention also provides a chip performance debugging device, comprising: A first acquisition module is used to acquire security attribute configuration information of performance data of the chip to be debugged; A second acquisition module, configured to acquire performance data of the chip to be debugged based on a path corresponding to a value of the security attribute configuration information; The debugging module is used to perform performance debugging on the chip to be debugged according to the performance data of the chip to be debugged.
[0010] The present invention also provides a chip performance debugging system, comprising a confidential virtual machine and at least one chip, wherein the confidential virtual machine is used to execute the chip performance debugging method.
[0011] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the processor implements any one of the above-mentioned chip performance debugging methods or the chip performance debugging method.
[0012] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements any of the above-mentioned chip performance debugging methods or the chip performance debugging method.
[0013] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any one of the above-mentioned chip performance debugging methods or the chip performance debugging method.
[0014] The chip performance debugging method, device, system, equipment, medium and product provided by the present invention obtain security attribute configuration information of performance data of the chip to be debugged; obtain performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; and perform performance debugging on the chip to be debugged according to the performance data of the chip to be debugged. The present invention is applicable to confidential virtual machines, and obtains performance data from the chip to be debugged through a path corresponding to the value of the security attribute configuration information so as to perform performance debugging on the chip to be debugged, thereby realizing chip performance debugging in a confidential virtual machine environment. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0016] Figure 1 It is a flow chart of the chip performance debugging method provided by the present invention.
[0017] Figure 2 This is one of the structural schematic diagrams of the chip performance debugging system provided by the present invention.
[0018] Figure 3 It is a flow chart of a method for debugging chip performance based on a first channel provided by the present invention.
[0019] Figure 4 This is the second structural schematic diagram of the chip performance debugging system provided by the present invention.
[0020] Figure 5 It is a flow chart of a method for debugging chip performance based on a first channel provided by the present invention.
[0021] Figure 6 It is a structural schematic diagram of the chip performance debugging device provided by the present invention.
[0022] Figure 7 This is the third structural schematic diagram of the chip performance debugging system provided by the present invention.
[0023] Figure 8 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION
[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0025] Figure 1 FIG. 1 is a flow chart of the chip performance debugging method provided by the present invention, such as Figure 1 As shown, the present invention provides a chip performance debugging method, which is applicable to confidential virtual machines. Confidential virtual machines are a technology that uses hardware security features to protect data and computing processes in virtual machines, and are mainly used to enhance data privacy and security in cloud computing environments; protect data in virtual machines through encryption technology to ensure that data will not be accessed without authorization even in the infrastructure of cloud service providers; provide stronger isolation to ensure that computing and data between different virtual machines will not interfere with each other, thereby enhancing the security of multi-tenant environments. Confidential virtual machines support secure boot, ensuring that only verified code can run in virtual machines, thereby preventing malware injection.
[0026] The present invention provides a chip performance debugging method, which at least includes steps S100 to S300.
[0027] Step S100, obtaining security attribute configuration information of performance data of the chip to be debugged; the chip to be debugged is a GPU chip, the performance data refers to the relevant data of the performance counter, and the security attribute configuration information is used to indicate whether the GPU chip encrypts the performance data.
[0028] Step S200, obtaining the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; specifically, determining whether the GPU chip encrypts the performance data according to the security attribute configuration information; if not encrypted, obtaining the performance data via the direct data transmission engine (DMA Engines) of the GPU; if encrypted, obtaining the performance data via the data encryption module of the direct data transmission engine.
[0029] Step S300, based on the performance data of the chip to be debugged, the performance of the chip to be debugged is debugged. Specifically, the performance debugging can be performed through CC-DevTool, which is a development / debugging tool usually used for programming and software development. It helps developers write, test and debug codes, provides compiling, running and error checking functions, and allows developers to execute codes step by step, check variable values, set breakpoints, etc., so as to find errors in the code.
[0030] It can be understood that the present invention is applicable to confidential virtual machines, and obtains performance data from a chip to be debugged through a path corresponding to the value of the security attribute configuration information so as to perform performance debugging on the chip to be debugged, thereby realizing chip performance debugging in a confidential virtual machine environment.
[0031] Figure 2 This is one of the structural schematic diagrams of the chip performance debugging system provided by the present invention. Figure 3 is a flow chart of a method for debugging chip performance based on the first channel provided by the present invention, Figure 4 This is the second structural diagram of the chip performance debugging system provided by the present invention. Figure 5 It is a flow chart of a method for debugging chip performance based on a first channel provided by the present invention.
[0032] like Figure 2-Figure 5 As shown, based on the above embodiment, as an optional embodiment, the channel includes a first channel consisting of a performance counter sampling module, a secure display memory, a data encryption module, a springboard buffer and a performance analyzer software buffer, and a second channel consisting of a performance counter sampling module, a direct data transmission engine and a performance analyzer software buffer. The performance data of the chip to be debugged is obtained based on a path corresponding to the value of the security attribute configuration information, including step S210 and step S220, and the order of step S210 and step S220 can be adjusted.
[0033] Step S210: If the value of the security attribute configuration information indicates encryption, the first channel is selected to obtain the performance data of the chip to be debugged. Specifically, the security attribute configuration information can be set to 1 to indicate that the performance data needs to be encrypted, for example, the Secure attribute bit on the S-AXI protocol is set to S=1, indicating that the performance counter has "security requirements".
[0034] Step S220: If the value of the security attribute configuration information indicates that it is not encrypted, the second channel is selected to obtain the performance data of the chip to be debugged. The security attribute configuration information can be set to 0 to indicate that the performance data needs to be encrypted. For example, setting the Secure attribute bit on the AXI protocol to S=0 indicates that the performance counter is at a normal security level and has no "security requirements".
[0035] Optionally, the performance counter sampling module corresponding to the first channel is arranged in the stream processor, and the secure display memory and the data encryption module are arranged in the direct data transmission engine. The performance counter is arranged in the stream processor, so that the performance data and the business data adopt the same encryption and decryption transmission path of confidential data, thereby ensuring the confidentiality of the performance data and improving the security level.
[0036] Optionally, if the first channel is selected to obtain the performance data of the chip to be debugged, the performance debugging of the chip to be debugged according to the performance data of the chip to be debugged includes: decrypting the performance data based on a preset key, and performing performance debugging on the chip to be debugged according to the decrypted performance data. The preset key is a key corresponding to the encryption process of the performance data by the data encryption module.
[0037] Optionally, after the performance debugging of the chip to be debugged according to the performance data of the chip to be debugged, the method further includes step S400.
[0038] Step S400, displaying the performance debugging result of the chip to be debugged based on a visual interface. In this step, displaying the performance debugging result to the user through a visual interface is conducive to the user to intuitively observe the performance debugging result and understand the relevant performance of the chip to be debugged.
[0039] like Figure 2 and Figure 4 As shown in the figure, the GPU chip includes the following functional modules: SM stream processor, performance counter (perf_Reg), high bandwidth memory (HBM), direct data transmission engine (DMA Engine) and data encryption module (Crypt) closely cascaded with DMA export. If the performance data does not need to be encrypted, the performance counter is separated from the stream processor.
[0040] The Performance Counter Sampling Module (PFC) is a tool for monitoring and analyzing the performance of the graphics processing unit (GPU). It provides performance data such as GPU usage, rendering performance, memory bandwidth, etc.
[0041] The data encryption module supports multiple encryption algorithms such as AES and DES. AES (Advanced Encryption Standard) and DES (Data Encryption Standard) are two common symmetric encryption algorithms. The data encryption module and the confidential virtual machine CVM have interactively confirmed the encryption and decryption keys in advance.
[0042] The performance counter perf_Reg is a storage interface implemented by hardware design and solidified inside the GPU, providing software with an operation interface such as reading or writing.
[0043] like Figure 3 As shown in the figure, the entire high bandwidth memory (HBM) of the GPU chip is divided into two different types of sub-areas – secure video memory (HBM-S) and normal video memory (HBM-NS). Secure video memory (HBM-S) is used to store confidential data, such as user code, user program input data, and program output results. Secure video memory usually uses encryption and access control mechanisms to ensure the security of data during storage and transmission to prevent unauthorized access. Data in normal video memory usually does not have additional security protection and is vulnerable to unauthorized access or malware attacks.
[0044] If the performance data needs to be encrypted, that is, the performance counter sampling module is set in the stream processor, then the data will pass through the secure video memory during the process of collecting performance data. The data in the secure video memory will later be encrypted into ciphertext by the data encryption module (Crypt) and transmitted to the bounce buffer (Bounce Buffer) in the memory on the confidential virtual machine side via the direct data transmission engine (DMA Engine). The performance debugging tool CC-DevTool running on the confidential virtual machine will read the ciphertext in the bounce buffer through the performance analyzer software buffer (Profiler Buffer) and decrypt it using the key. Finally, the performance counter data is obtained and processed and analyzed before being displayed to the user in the GUI interface.
[0045] Among them, Bounce Buffer is a memory management technology used to handle data transfer, especially in DMA (direct memory access) operations, the main purpose of which is to solve the data transfer problem caused by the mismatch between the address space of the device and the main memory. Profiler Buffer is a special memory area used to store performance data generated by the program at runtime, including the number of function calls, execution time, memory allocation and other information.
[0046] like Figure 5As shown, the performance counter sampling module PFC is separated from the SM stream processor, so the security attributes are no longer inherited from the SM stream processor. By fixing the security attributes of the performance counter sampling module PFC to Normal (S=0), the performance data can be directly written into the regular buffer of the confidential virtual machine (i.e., the performance analyzer software buffer) through the direct data transmission engine. Figure 5 The host side in is the confidential virtual machine.
[0047] It can be understood that the present invention provides two performance data collection schemes for different channels. In the first collection scheme, the performance data and business data use the same encryption and decryption transmission path of confidential data to ensure the confidentiality of the performance data and improve the security level. In the second collection scheme, the business data still uses the encryption and decryption transmission path of confidential data, and the security attribute of the performance counter sampling module PFC is separated from the stream processor and fixedly set to the normal (non-secure) attribute NS, so that the performance data has a normal and more relaxed access restriction, so that it can be directly stored in the Profiler buffer by the DMA engine with the help of traditional non-secure channels, without encryption and decryption, taking a shorter transmission path, and reducing the additional overhead caused by encryption and decryption.
[0048] The chip performance debugging device provided by the present invention is described below. The chip performance debugging device described below and the chip performance debugging method described above can be referred to each other.
[0049] Figure 6 FIG. 1 is a schematic diagram of the structure of the chip performance debugging device provided by the present invention. Figure 6 As shown, the present invention also provides a chip performance debugging device, including the following modules.
[0050] The first acquisition module 610 is used to acquire security attribute configuration information of performance data of the chip to be debugged.
[0051] The second acquisition module 620 is used to acquire the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information.
[0052] The debugging module 630 is used to perform performance debugging on the chip to be debugged according to the performance data of the chip to be debugged.
[0053] As an embodiment, the channel includes a first channel consisting of a performance counter sampling module, a secure display memory, a data encryption module, a springboard buffer and a performance analyzer software buffer, and a second channel consisting of a performance counter sampling module, a direct data transmission engine and a performance analyzer software buffer, and the second acquisition module 620 is further used to: If the value of the security attribute configuration information is characterized by encryption, selecting the first channel to obtain the performance data of the chip to be debugged; If the value of the security attribute configuration information is characterized as not being encrypted, the second channel is selected to obtain performance data of the chip to be debugged.
[0054] As an embodiment, the performance counter sampling module corresponding to the first channel is arranged in the stream processor, and the secure video memory and the data encryption module are arranged in the direct data transmission engine.
[0055] As an embodiment, if the first channel is selected to obtain the performance data of the chip to be debugged, the debugging module 630 is further used to: The performance data is decrypted based on a preset key, and performance debugging is performed on the chip to be debugged according to the decrypted performance data.
[0056] As an embodiment, it also includes: The display module is used to display the performance debugging result of the chip to be debugged based on a visual interface.
[0057] It should be noted that the chip performance debugging device provided by the present invention can execute the chip performance debugging method described in any of the above embodiments during specific operation, and has the technical effect corresponding to the method, which will not be elaborated in this embodiment.
[0058] The chip performance debugging system provided by the present invention is described below. The chip performance debugging system described below and the chip performance debugging method described above can be referred to each other.
[0059] Figure 2 This is one of the structural schematic diagrams of the chip performance debugging system provided by the present invention. Figure 4 This is the second structural diagram of the chip performance debugging system provided by the present invention. Figure 7 FIG. 3 is a schematic diagram of the structure of the chip performance debugging system provided by the present invention. Figure 2 , Figure 4 and Figure 7 As shown, the present invention also provides a chip performance debugging system, including a confidential virtual machine and at least one chip, wherein the chip is a GPU chip, and the confidential virtual machine is used to execute the chip performance debugging method, including: obtaining security attribute configuration information of performance data of the chip to be debugged; obtaining the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; and performing performance debugging on the chip to be debugged according to the performance data of the chip to be debugged.
[0060] Optionally, the confidential virtual machine exchanges data with the GPU chip through a PCIe interface. The PCIe interface can connect multiple GPU chips, and the specific number depends on the design of the motherboard, the number of PCIe slots, and the configuration of the GPU used.
[0061] As an embodiment, the channel includes a first channel consisting of a performance counter sampling module, a secure display memory, a data encryption module, a springboard buffer, and a performance analyzer software buffer, and a second channel consisting of a performance counter sampling module, a direct data transmission engine, and a performance analyzer software buffer. The performance data of the chip to be debugged is obtained based on a path corresponding to the value of the security attribute configuration information, including: If the value of the security attribute configuration information is characterized by encryption, selecting the first channel to obtain the performance data of the chip to be debugged; If the value of the security attribute configuration information is characterized as not being encrypted, the second channel is selected to obtain performance data of the chip to be debugged.
[0062] As an embodiment, the performance counter sampling module corresponding to the first channel is arranged in the stream processor, and the secure video memory and the data encryption module are arranged in the direct data transmission engine.
[0063] As an embodiment, if the first channel is selected to obtain the performance data of the chip to be debugged, the performance debugging of the chip to be debugged according to the performance data of the chip to be debugged includes: The performance data is decrypted based on a preset key, and performance debugging is performed on the chip to be debugged according to the decrypted performance data.
[0064] As an embodiment, after the performance debugging of the chip to be debugged according to the performance data of the chip to be debugged, the method further includes: The performance debugging results of the chip to be debugged are displayed based on a visual interface.
[0065] As an embodiment, after displaying the performance debugging result of the chip to be debugged based on the visual interface, the method further includes: In response to the operation instructions input by the user based on the visual interface, the performance of the chip to be debugged is optimized based on the preset optimization strategy, wherein the preset optimization strategy includes maximizing parallelism, optimizing memory access mode, reducing branch divergence, utilizing GPU memory hierarchy, overlapping calculation and memory access, hiding memory transmission delay, kernel startup parameter tuning, etc.
[0066] It should be noted that the chip performance debugging system provided by the present invention can implement the chip performance debugging method described in any of the above embodiments during specific operation, and has the technical effect corresponding to the method, which will not be elaborated in this embodiment.
[0067] Figure 8 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 8 As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication interface 820 and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute a chip performance debugging method, including: obtaining security attribute configuration information of performance data of the chip to be debugged; obtaining performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; and performing performance debugging on the chip to be debugged according to the performance data of the chip to be debugged.
[0068] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.
[0069] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the chip performance debugging methods provided by the above methods, including: obtaining security attribute configuration information of performance data of the chip to be debugged; obtaining the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; and performing performance debugging on the chip to be debugged according to the performance data of the chip to be debugged.
[0070] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the chip performance debugging method provided by the above methods, including: obtaining security attribute configuration information of performance data of the chip to be debugged; obtaining the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; and performing performance debugging on the chip to be debugged according to the performance data of the chip to be debugged.
[0071] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.
[0072] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.
[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A chip performance debugging method, characterized in that: Applicable to a confidential virtual machine, the method comprises: Obtain security attribute configuration information of performance data of the chip to be debugged; Acquire the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information; According to the performance data of the chip to be debugged, performance debugging is performed on the chip to be debugged.
2. The chip performance debugging method according to claim 1, characterized in that: The channel includes a first channel consisting of a performance counter sampling module, a secure display memory, a data encryption module, a springboard buffer, and a performance analyzer software buffer, and a second channel consisting of a performance counter sampling module, a direct data transmission engine, and a performance analyzer software buffer. The method of obtaining the performance data of the chip to be debugged based on a path corresponding to the value of the security attribute configuration information includes: If the value of the security attribute configuration information is characterized by encryption, selecting the first channel to obtain the performance data of the chip to be debugged; If the value of the security attribute configuration information is characterized as not being encrypted, the second channel is selected to obtain performance data of the chip to be debugged.
3. The chip performance debugging method according to claim 2, characterized in that: The performance counter sampling module corresponding to the first channel is arranged in the stream processor, and the secure video memory and the data encryption module are arranged in the direct data transmission engine.
4. The chip performance debugging method according to claim 2, characterized in that: If the first channel is selected to obtain the performance data of the chip to be debugged, the step of performing performance debugging on the chip to be debugged according to the performance data of the chip to be debugged includes: The performance data is decrypted based on a preset key, and performance debugging is performed on the chip to be debugged according to the decrypted performance data.
5. The chip performance debugging method according to any one of claims 1 to 4, characterized in that: After the performance debugging of the chip to be debugged is performed according to the performance data of the chip to be debugged, the method further includes: The performance debugging results of the chip to be debugged are displayed based on a visual interface.
6. A chip performance debugging device, characterized in that: include: A first acquisition module is used to acquire security attribute configuration information of performance data of the chip to be debugged; A second acquisition module, configured to acquire performance data of the chip to be debugged based on a path corresponding to a value of the security attribute configuration information; The debugging module is used to perform performance debugging on the chip to be debugged according to the performance data of the chip to be debugged.
7. A chip performance debugging system, characterized in that: It comprises a confidential virtual machine and at least one chip, wherein the confidential virtual machine is used to execute the chip performance debugging method described in any one of claims 1-5.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the chip performance debugging method according to any one of claims 1 to 5 is implemented.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip performance debugging method according to any one of claims 1 to 5 is implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the chip performance debugging method according to any one of claims 1 to 5 is implemented.