Method, computing device, medium and program product for controlling data access

Abstract

The present invention relates to a method, computing device, medium and program product for controlling data access. The method comprises: determining at least one GPU instance as a secure GPU instance among one or more GPU instances configured on the device side, wherein the one or more GPU instances are used to construct one or more physically isolated hardware access paths between a host and a device; using a security main control unit configured in the secure GPU instance to set a security bit, wherein the security bit is used to indicate the security attribute of an access request to a device memory; and at least using the security bit to check access to the device memory associated with the secure GPU instance. The present invention can prevent sensitive data on the device side from being leaked due to untrusted drivers or insecure command packet transmission, thereby significantly improving the security of sensitive data.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of artificial intelligence, and more specifically to a method, a computing device, a computer-readable storage medium, and a computer program product for controlling data access. Background Art

[0002] For confidential computing, access control to device memory of devices (e.g., graphics processing units, GPUs) is critical. Traditional methods for controlling data access are, for example, usually using security bits to block access from other virtual machines on the host (e.g., central processing unit, CPU) side or malicious access from the operating system / virtual machine hypervisor. Specifically, for example, by passing the security bit throughout the computing and data memory access channel (e.g., the security bit is passed from the CPU to the command processor, and the command processor is processed and passed to the computing core, network operation center, secondary cache (L2) and high-bandwidth memory) for security control. In the above-mentioned traditional methods for controlling data access, since the security bit is obtained from the command packet and written by the kernel driver of the host, if the driver is not trusted or the command packet transmission is not secure enough, data privacy cannot be guaranteed, which easily leads to the leakage of sensitive data.

[0003] In summary, the traditional method for controlling data access has the disadvantage that sensitive data is easily leaked due to untrustworthy drivers or insecure command packet transmission. Summary of the invention

[0004] The present invention provides a method, computing device, computer-readable storage medium and computer program product for controlling data access, which can prevent sensitive data on the device side from being leaked due to untrustworthy drivers or insecure command packet transmission, thereby significantly improving the security of sensitive data.

[0005] According to a first aspect of the present invention, a method for controlling data access is provided. The method comprises: determining at least one GPU instance as a secure GPU instance among one or more GPU instances configured on a device side, wherein the one or more GPU instances are used to construct one or more physically isolated hardware access paths between a host and a device; using a security master control unit configured in the secure GPU instance to set a security bit, wherein the security bit is used to indicate a security attribute of an access request to a device memory; and at least using the security bit to check access to the device memory associated with the secure GPU instance.

[0006] In some embodiments, the device memory associated with the secure GPU instance includes open memory and secure memory, and the secure main control unit is a kernel module used to consume or operate data stored in the secure memory in the GPU instance.

[0007] In some embodiments, the secure memory is used to store business data, and the open memory is used to store management data, and the management data includes: at least one of command packets, kernel functions, and page tables. The security master control unit can only perform "read operations" on the open memory in the secure GPU instance, and can perform "read operations and write operations" on the secure memory in the secure GPU instance.

[0008] In some embodiments, the method for controlling data access further includes: in a secure GPU instance, configuring a kernel module for consuming or operating data stored in a secure memory in the GPU instance as a secure master control unit; and configuring a kernel module for consuming or operating data stored in an open memory in the secure GPU instance as a non-secure master control unit.

[0009] In some embodiments, the method for controlling data access also includes: using at least the security bit, checking access to the device memory associated with the secure GPU instance includes: comparing the address of the access request with the security area via a security check unit, and the security check unit is configured at the entry of the device memory; and receiving or discarding the access request based on the comparison result and the request type of the access request.

[0010] In some embodiments, based on the comparison result and the request type of the access request, receiving or discarding the access request includes: in response to determining that the comparison result indicates that the address of the access request is within the range of the security area, receiving the access request; in response to determining that the comparison result indicates that the address of the access request is not within the range of the security area and the request type is a "read operation", the security check unit triggers a software interrupt and returns a predetermined value; and in response to determining that the comparison result indicates that the address of the access request is not within the range of the security area and the request type includes a "write operation", the security check unit triggers a software interrupt and discards the access request.

[0011] In some embodiments, the method for controlling data access further includes: upon initialization, the host operating system or hypervisor sends a request for a security configuration, the request for the security configuration indicating a confidential computing mode; and the secure microprocessor obtains the security configuration.

[0012] In some embodiments, the method for controlling data access further includes: based on the security configuration, the security microprocessor notifies each security main control unit of the identification of the security GPU instance; and configuring the security area to the security check unit.

[0013] According to a second aspect of the present invention, a computing device is also provided. The computing device comprises: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the method of the first aspect of the present invention.

[0014] According to a third aspect of the present invention, a computer-readable storage medium is further provided, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a machine, the method of the first aspect of the present invention is executed.

[0015] According to a fourth aspect of the present invention, there is further provided a computer program product, comprising a computer program, wherein when the computer program is executed by a machine, the method of the first aspect of the present invention is performed.

[0016] The beneficial effects of the present invention are as follows: the present invention sets a security bit through a security main control unit configured in a secure GPU instance determined on the device side, and uses the security bit to check access to device memory associated with the secure GPU instance. Therefore, sensitive data on the device side will not be leaked due to unreliable driver programs or insecure command packet transmission, thereby significantly improving the security of sensitive data.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features, advantages and aspects of the embodiments of the present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements.

[0019] Figure 1 The diagram schematically shows a computing device implementing a method for controlling data access according to an embodiment of the present invention.

[0020] Figure 2 A flow chart of a method for controlling data access according to an embodiment of the present invention is shown.

[0021] Figure 3 A schematic diagram of a system for controlling data access according to some embodiments of the present invention is shown.

[0022] Figure 4A flow chart of a method for checking secure access to a memory using a security bit according to an embodiment of the present invention is shown.

[0023] Figure 5 A schematic diagram of a system for checking access to device memory associated with the secure GPU instance according to an embodiment of the present invention is shown.

[0024] Figure 6 A flow chart of a method for security configuration according to an embodiment of the present invention is shown.

[0025] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0026] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0027] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0028] As described above, in the traditional method for controlling data access, since the security bit is obtained from the command packet and written by the kernel driver of the host, if the driver is not trustworthy or the command packet transmission is not secure enough, data privacy cannot be guaranteed, which easily leads to the leakage of sensitive data. Therefore, the disadvantage of the traditional method for controlling data access is that sensitive data is easily leaked due to untrustworthy drivers or insecure command packet transmission.

[0029] In order to at least partially solve one or more of the above problems and other potential problems, an exemplary embodiment of the present invention proposes a method for controlling data access. In this method, a security bit is set by a security main control unit configured in a secure GPU instance determined on the device side, rather than by the kernel driver of the host writing the security bit into the command packet. Therefore, the security attribute of the access request of the present invention will not be affected by the untrusted host driver or the insecurity of the command packet transmission between the host and the device; in addition, the present invention uses the security bit to check the access to the device memory associated with the secure GPU instance, so that all accesses to the device memory associated with the secure GPU instance can be controlled based on the security bit set by the security main control unit, so that the security of the core or sensitive data in the GPU device memory can be improved. Therefore, the present invention can prevent the sensitive data on the device side from being leaked due to the untrusted driver or the insecurity of the command packet transmission, thereby significantly improving the security of sensitive data.

[0030] Figure 1 A schematic diagram of a computing device 100 for implementing a method for controlling data access according to an embodiment of the present invention is shown schematically. Figure 1 As shown, the computing device 100 may have one or more processing units, including special processing units such as a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a general-purpose graphics processing unit (GPGPU), and a general-purpose processing unit such as a CPU. In some embodiments, the computing device 100 is also configured with at least: a secure GPU instance determination unit 102, a security bit configuration unit 104, and a device memory access check unit 106. In some embodiments, the secure GPU instance determination unit 102, the security bit configuration unit 104, and the device memory access check unit 106. For example, it is a program module running on the computing device 100.

[0031] Regarding the secure GPU instance determination unit 102, it is used to determine at least one GPU instance as a secure GPU instance among one or more GPU instances configured on the device side, and the one or more GPU instances are used to build one or more physically isolated hardware access paths between the host and the device.

[0032] The security bit configuration unit 104 is used to set a security bit using a security master control unit configured in the secure GPU instance, where the security bit is used to indicate a security attribute of an access request to a device memory.

[0033] The device memory access checking unit 106 is configured to check access to the device memory associated with the secure GPU instance by at least utilizing the security bit.

[0034] The following will be combined Figure 2 and Figure 3 A method 200 for controlling data access according to an embodiment of the present invention is described. Figure 2 A flow chart of a method 200 for controlling data access according to an embodiment of the present invention is shown. Figure 3 2 shows a schematic diagram of a system for controlling data access according to some embodiments of the present invention. It should be understood that the method 200 can be used, for example, in Figure 1 The method 200 is executed at the described computing device 100. The method 200 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0035] The system 300 includes, for example, a host (eg, a CPU), a device (eg, a GPU), and a peripheral component interconnect express (PCIe). Figure 3 The host, device and PCIe are not shown in the figure, only some components in the device are shown. It should be understood that the device side is configured with one or more physically isolated GPU instances. The host is configured with one or more virtual machines. The one or more GPU instances configured on the device side and the corresponding virtual machines configured on the host constitute one or more physically isolated hardware access paths between the host and the device.

[0036] like Figure 3 As shown, in some embodiments, the device of system 300 further includes: a secure microprocessor 320, a command processor 310, a low-speed bus 330, a high-speed bus 340, a program address generator 336, and a device memory. The device memory includes, for example, a secondary cache (e.g., L2), a high bandwidth memory (High Bandwidth Memory, HBM), that is, HBM 350. In some embodiments, the device side of system 300 further includes a device portal ( Figure 3 Not shown, such as Figure 5 Indicated by the mark 516 in the figure), the safety inspection unit ( Figure 3 Not shown, such as Figure 5 542 in the reference numeral 542), a physical address generator ( Figure 3 Not shown, such as Figure 5 as shown).

[0037] Regarding the device portal, it is configured to obtain interaction data transmitted between the host and the device, for example.

[0038] Regarding the security check unit, it is configured at the entry of the device memory and is used to use at least the security bit to check the access to the device memory associated with the secure GPU instance, such as receiving or discarding the access request to the device memory.

[0039] The security microprocessor 320 is used to obtain the security configuration and, based on the security configuration, notify each security main control unit of the identification of the security GPU instance.

[0040] At step 202, the computing device 100 determines at least one GPU instance as a secure GPU instance among one or more GPU instances configured on the device side, and the one or more GPU instances are used to build one or more physically isolated hardware access paths between the host and the device.

[0041] The host is, for example, a CPU. A plurality of virtual machines are configured on the host side.

[0042] Regarding the device, it is, for example, a GPU. One or more hardware-isolated GPU instances are configured on the device side to form an independent hardware access path with at least one of the multiple virtual machines configured by the host, so as to build a trusted execution environment that supports confidential computing. For example, the computing device 100 configures 4 GPU instances that are hardware-isolated from each other on the GPU (for example, a first GPU instance, a second GPU instance, a third GPU instance, and a fourth GPU instance, that is, VF0, VF1, VF2, and VF3). And 4 corresponding virtual machines are configured on the CPU, thereby building 4 independent hardware access paths between the host and the device.

[0043] Regarding the GPU instance, it is configured, for example, in the following manner: the computing device 100 isolates the address space of the hardware on the device side; and isolates the device memory, command processor, and computing core associated with the configured GPU instance from each other. Figure 3As shown, the command processor 310 includes VF0 channel, VF1 channel, VF2 channel, and VF3 channel isolated from each other. The VF0 channel, VF1 channel, VF2 channel, and VF3 channel are associated with the first GPU instance, the second GPU instance, the third GPU instance, and the fourth GPU instance, respectively. For another example, for each of the multiple GPU instances configured on the device side, a corresponding computing core is allocated. For each of the multiple GPU instances configured on the device side, a corresponding device memory is allocated. For example, the associated device memory of the second GPU instance is Figure 3 358 of VF1 device memory.

[0044] Regarding the secure GPU instance, its associated device memory includes open memory and secure memory. Secure memory is used to store business data (business data, for example, involves direct memory access (DMA) data). Open memory is used to store management data (management data, for example, includes: command packets, kernel functions, at least one type of data in the page table). For open memory, the non-secure master control unit can perform "read operations and write operations". The secure master control unit can only perform "read operations" on the open memory in the secure GPU instance. It should be understood that open memory can be used for the interaction of command information and management information.

[0045] For example, the computing device 100 determines that the first GPU instance (e.g., VF0) is a secure GPU instance (the secure GPU instance is, for example, referred to as "CVF") among the four GPU instances configured by the GPU and whose hardware is isolated from each other. It should be understood that the hardware access path composed of the first GPU instance (e.g., VF0) and the corresponding virtual machine is a confidential hardware access path, which can be used to construct the trusted execution environment for supporting confidential computing. The second GPU instance to the fourth GPU instance are, for example, determined to be ordinary GPU instances, and the hardware access paths constructed by them and the corresponding virtual machines are, for example, used to run ordinary, non-encrypted applications.

[0046] At step 204, the computing device 100 uses the security master control unit configured in the secure GPU instance to set a security bit, where the security bit is used to indicate the security attribute of the access request to the device memory.

[0047] Regarding the secure master control unit (Secure Master), it is configured in the secure GPU instance and is a kernel module used to consume or operate data stored in the secure memory in the secure GPU instance.

[0048] For example, in some embodiments, the computing device 100 configures the kernel module used to consume or operate the data stored in the secure memory in the GPU instance as a secure main control unit in the secure GPU instance; and configures the kernel module used to consume or operate the data stored in the open memory in the secure GPU instance as a non-secure main control unit. By adopting the above means, the present invention can save the implementation cost of the confidential computing environment while ensuring the security of the core data.

[0049] As mentioned above, the secure master control unit can perform "read operations and write operations" on the secure memory in the secure GPU instance, such as Figure 3 As indicated by the bidirectional dashed arrow 372 in FIG. 1 , the security master control unit, for example, SDMA 332, can perform “read operations and write operations” on the VF0 secure memory 356 in HBM 350. In addition, as Figure 3 As indicated by the bidirectional dashed arrow 374 in FIG. 3 , the security master control unit, for example, SPC 334, can perform “read operations and write operations” on the VF0 secure memory 356 in HBM 350. It should be understood that the security master control unit can only perform “read operations” on the open memory in the secure GPU instance, and cannot perform “write operations” on the open memory in the secure GPU instance. Figure 3 As indicated by the unidirectional dotted arrow 376, SPC 334 can only perform a "read operation" on the VF0 open memory 352 in HBM 350. By adopting the above means, the present invention can avoid leakage of sensitive data when the security master control unit accesses the open memory.

[0050] It should be understood that if business data is stored in the secure memory in the secure GPU instance, and other data (e.g., management data, which includes at least one of command packets, kernels, page tables, etc.) is stored in the open memory (i.e., non-secure memory) in the secure GPU instance, then the kernel module (or "IP module") used to consume or operate the business data stored in the secure memory in the secure GPU instance will be defined as a secure master in the secure GPU instance. For example, kernel modules that directly operate on direct memory access (DMA) data and video core data are configured as secure masters. Kernel modules that only consume or operate command packets, descriptors, and page tables are defined as non-secure masters, which only perform ordinary management and do not access confidential business data.

[0051] Regarding the security bit (or "Secure Bit"), it is set by the security master control unit, for example. For example, the security master control unit configures the security bit "securebit == SECURE" for all memory access requests. For example, if the GPU instance is determined by the host as a secure GPU instance (for example, the secure GPU instance is handed over to a confidential user), the security master control unit configured in the secure GPU instance configures the security bit to "enabled" for memory access from the computing core, DMA execution unit (ie, Execution Unit, EU) or video core, then the security bit will not be passed through the entire hardware path, but is only used for memory access to the device memory (e.g., L2 and / or HBM) in the secure GPU instance.

[0052] For example, Figure 3 As shown, the GSP firmware 322 in the secure microprocessor 320 (the secure microprocessor is, for example, a secure MPU) notifies the kernel module in each GPU instance of the identifier of the current secure GPU instance (the identifier of the secure GPU instance is, for example, referred to as "CFV ID") during initialization. The identifier of the secure GPU instance indicates, for example, VF0. For example, if the system direct content access module (System Direct memory access, referred to as SDMA) 332 determines that the identifier of the GPU instance in which it is located is equal to the identifier of the secure GPU instance, then SDMA 332 will configure a security bit (for example, a security bit indicating that the security attribute is enabled, that is, "AxPROT[1] = secure") in the access request for the VF0 secure memory indicated by the tag 356 in the High Bandwidth Memory (HBM). For another example, if SPC 334 determines that the identifier of the GPU instance in which it is located is equal to the identifier of the secure GPU instance, such as VF0, SPC 334 configures the security bit (ie, AxPROT[1] = secure) in the read / write request for the VF0 secure memory indicated by the tag 356 in HBM 350.

[0053] In some embodiments, in order to simplify the process and improve efficiency while maintaining acceptable security, the command packet does not always carry the security bit indicating the security attribute to the downstream kernel module.

[0054] At step 206, the computing device 100 checks access to device memory associated with the secure GPU instance using at least the security bit.

[0055] For example, the computing device 100 compares the address of the access request with the security area via a security check unit, and the security check unit is configured at the entrance of the device memory; and based on the comparison result and the request type of the access request, receives or discards the access request. Specifically, for example, if the computing device 100 determines that the comparison result indicates that the address of the access request is within the range of the security area, the access request is received; if it is determined that the comparison result indicates that the address of the access request is not within the range of the security area and the request type is a "read operation", the security check unit triggers a software interrupt and returns a predetermined value; and if it is determined that the comparison result indicates that the address of the access request is not within the range of the security area and the request type includes a "write operation", the security check unit triggers a software interrupt and discards the access request. The following will be combined with Figure 4 The method 400 for checking access to the device memory associated with the secure GPU instance is described and will not be described in detail here.

[0056] In the above scheme, at least one GPU instance physically isolated from each other configured on the device side is determined as a secure GPU instance; and a security bit for indicating the security attribute of an access request is set by using a security main control unit configured in the secure GPU instance; because the security bit is set by the security main control unit configured in the secure GPU instance determined on the device side, rather than being written into the command packet by the kernel driver of the host, the security attribute of the access request of the present invention will not be affected by the untrusted host driver or the insecurity of the command packet transmission between the host and the device; in addition, the present invention uses the security bit to check the access to the device memory associated with the secure GPU instance, so that all accesses to the device memory associated with the secure GPU instance can be controlled based on the security bit set by the security main control unit, so that the security of the core or sensitive data in the GPU device memory can be improved. Therefore, the present invention can prevent the sensitive data on the device side from being leaked due to the untrusted driver or the insecurity of the command packet transmission, thereby significantly improving the security of sensitive data.

[0057] The following will be combined Figure 3 , Figure 4 and Figure 5 A method 400 for checking secure access to a memory using a security bit according to an embodiment of the present invention is described. Figure 4 A flow chart of a method 400 for checking secure access to a memory using a security bit according to an embodiment of the present invention is shown. Figure 5 Schematic diagram of a system 500 for checking access to device memory associated with the secure GPU instance according to an embodiment of the present invention is shown. It should be understood that the method 400 can be used, for example, in Figure 1The method 400 is executed at the described computing device 100. The method 400 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0058] At step 402, the computing device 100 compares the address of the access request with the security area via a security check unit, where the security check unit is configured at the entry of the device memory.

[0059] Regarding the security check unit 542, it is configured at the entry of the device memory, for example. In some embodiments, the security check unit 542 includes: a security register, a security detection module and an interrupt module, such as Figure 5 As shown. The security detection module is used, for example, to compare the address of the access request to the device memory with the security area. The interrupt module is used, for example, to generate a software interrupt when the access is illegal. In some embodiments, the security check strategy of the security check unit 542 can directly follow the AXI-Bridge interface standard.

[0060] like Figure 5 As shown, if the main control unit 510 of the device is a security main control unit, the security bit of the access request (e.g., "read / write request") issued by it indicates that the security attribute is enabled. The access request with the security bit is passed through the system memory management unit 512, the physical address generator, and the high-speed bus and then transmitted to the security check unit 542 configured at the entrance of the device memory (e.g., HBM). The security check unit 542 compares the address of the access request with the security area.

[0061] Regarding the security area, it is configured into the security check unit 542 by the security microprocessor during initialization, for example.

[0062] At step 404, if the computing device 100 determines that the comparison result indicates that the address of the access request is within the range of the secure area, the access request is received.

[0063] For example, if the security check unit 542 of the computing device 100 determines that the comparison result indicates that the address of the access request is within the range of the security area, then the read / write request is received, as indicated by the dotted line 520, and the main control unit 510 of the device can perform read and write operations on the data stored in the HBM secure memory 550.

[0064] At step 406, if the computing device 100 determines that the comparison result indicates that the address of the access request is not within the range of the security area and the request type is a "read operation", the security check unit triggers a software interrupt and returns a predetermined value.

[0065] Regarding the predetermined value, in some embodiments, it is, for example, "0".

[0066] For example, an access request for data stored in the HBM secure memory 550 is initiated from the host 514. Since the access request does not come from the security master control unit, the access request does not include a security bit for indicating that the security attribute is enabled. The access request passes through the device portal 516, the physical address generator, and the high-speed bus and is passed to the security check unit 542 configured at the entrance of the device memory (e.g., HBM), as indicated by the dotted line 530. The security check unit 542 determines that the comparison result indicates that the address of the access request is not within the range of the security area, and if the security check unit 542 determines that the request type of the access request is only a "read operation", the interrupt module of the security check unit 542 triggers a software interrupt and returns "0".

[0067] At step 408, if the computing device 100 determines that the comparison result indicates that the address of the access request is not within the range of the security area and the request type includes a "write operation", the security check unit triggers a software interrupt and discards the access request.

[0068] If the security check unit 542 determines that the comparison result indicates that the address of the access request is not within the scope of the security area, and determines that the request type of the access request (for example, a "read and write request") includes a "write operation", the interrupt module of the security check unit 542 triggers a software interrupt and discards the access request.

[0069] In some embodiments, if the security check unit detects an access request from a main control unit of the device (e.g., a security main control unit) for data stored in the HBM open memory 552, and determines that the type of the access request is only a "read operation", the access request is accepted, such as Figure 5 Indicated by the dashed line 522.

[0070] If the security check unit detects an access request from the host for data stored in the HBM open memory 552 and determines that the type of the access request is a "read / write operation", the access request will also be accepted, such as Figure 5 Indicated by the dashed line 532.

[0071] By adopting the above-mentioned means, the present invention can achieve effective security control over the accessibility of data stored in the device's secure memory without affecting the processing efficiency of data stored in the device's open memory.

[0072] The following will be combined Figure 3 , Figure 6 A method 600 for security configuration according to an embodiment of the present invention is described. Figure 6 FIG. 6 is a flowchart of a method 600 for security configuration according to an embodiment of the present invention. It should be understood that the method 600 can be implemented in Figure 1 The method 600 is executed at the described computing device 100. The method 600 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0073] At step 602, when the computing device 100 is initialized, the host operating system or hypervisor sends a request for security configuration, and the request for security configuration indicates a confidential computing mode.

[0074] For example, during initial authentication, the host operating system or hypervisor sends a security configuration request with a confidential computing mode and writes it to the flash memory.

[0075] At step 604, the security microprocessor of the computing device 100 obtains the security configuration.

[0076] Regarding the secure microprocessor, it is, for example, referred to as a "secure MPU". In some embodiments, the secure microprocessor includes, for example, GSP firmware, such as Figure 3 shown.

[0077] Regarding the security configuration, it indicates at least the identification of the secure GPU instance, for example. In some embodiments, the security configuration also indicates the range size of the secure memory and the open memory of the secure GPU instance, for example.

[0078] At step 606, the computing device 100 notifies each security master control unit of the identification of the secure GPU instance based on the security configuration by the secure microprocessor.

[0079] For example, during initialization, the GSP firmware 322 of the secure microprocessor 320 notifies the kernel module in each GPU instance of the identifier of the current secure GPU instance (i.e., CVF ID). If the identifier of the current GPU instance (i.e., VFID) is equal to the identifier of the notified secure GPU instance, i.e., VFID == CVF ID, the kernel module (i.e., the security master control unit) of the current GPU instance sets the security register and configures the security bit so that all access requests to the secure memory of the secure GPU instance include the security bit (e.g., AxPROT[1] = secure).

[0080] Regarding the distribution method of the security bit, for example, it includes: after the command packet is processed, the command will be further passed to the downstream kernel module without the security bit, and the security master control unit (for example, the computing core, DMA execution unit, or video core) will attach its security bit (for example, AxPROT[1] = secure) to any access request to the secure memory. Figure 3As shown, the GSP firmware 322 in the secure microprocessor 320 notifies the SPC 334 and SDMA 332 of the identifier of the secure GPU instance (the identifier indicates VF0, for example). If the SPC 334 and SDMA 332 determine that the identifier of the current GPU instance is VF0, the read / write requests initiated by the SPC 334 and SDMA 332 for the VF0 secure memory in the HBM 350 will include a security bit (for example, AxPROT[1] = secure).

[0081] At step 608 , the computing device 100 configures the security area to the security check unit.

[0082] It should be understood that by configuring the security area to the security checking unit, the security checking unit can check or control access requests to the device memory based on the security area.

[0083] The security check unit is configured, for example, at the entry of the device memory. The security check unit is configured, for example, to: compare the address of the access request with the security area; and based on the comparison result and the request type of the access request, accept or discard the access request.

[0084] By adopting the above means, the present invention can realize the security configuration required for data access control.

[0085] The various processes and processing described above, such as methods 200, 400, and 600, may be performed at a computing device. The computing device, for example, includes: at least one processor (at least one graphics processor and at least one central processing unit); and a memory connected to the at least one processor in communication; wherein the memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor. In some embodiments, methods 200, 400, and 600 may be implemented as a computer software program or program product, which is tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program may be loaded and / or installed on a computing device via a read-only memory (ROM) and / or a communication unit. When the computer program is loaded into a random-access memory (RAM) and executed by a GPU and a CPU, one or more actions of methods 200, 400, and 600 described above may be performed.

[0086] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions for executing various aspects of the present invention. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof.

[0087] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram, and the combination of boxes in the flowchart and / or block diagram, can be implemented by computer-readable program instructions.

[0088] These computer-readable program instructions can be provided to a central processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the central processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0089] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the function involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0090] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0091] The above specific implementations do not constitute a limitation on the protection scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made according to design requirements and other factors.

Claims

1. A method for controlling data access, characterized in that: The method comprises: Determine at least one GPU instance as a secure GPU instance among the one or more GPU instances configured on the device side, wherein the one or more GPU instances are used to construct one or more physically isolated hardware access paths between the host and the device; Using a security master control unit configured in a secure GPU instance to set a security bit, the security bit being used to indicate a security attribute of an access request to a device memory, the security master control unit being a kernel module for consuming or operating data stored in a secure memory in the GPU instance; and Access to device memory associated with the secure GPU instance is checked using at least the security bit.

2. The method according to claim 1, characterized in that The device memory associated with a secure GPU instance includes open memory and secure memory.

3. The method according to claim 2, characterized in that The secure memory is used to store business data, and the open memory is used to store management data. The management data includes: at least one of command packets, kernel functions, and page tables. The secure main control unit can only perform "read operations" on the open memory in the secure GPU instance, and can perform "read operations and write operations" on the secure memory in the secure GPU instance.

4. The method according to claim 1, characterized in that Also includes: In a secure GPU instance, configuring a kernel module for consuming or operating data stored in a secure memory in the GPU instance as a secure master control unit; as well as A kernel module used to consume or operate data stored in an open memory in a secure GPU instance is configured as a non-secure master.

5. The method according to claim 1, characterized in that Using at least the security bit, checking access to device memory associated with the secure GPU instance includes: Comparing the address of the access request with the security area via a security check unit, wherein the security check unit is configured at the entry of the device memory; and Based on the comparison result and the request type of the access request, the access request is accepted or discarded.

6. The method according to claim 5, characterized in that Based on the comparison result and the request type of the access request, receiving or discarding the access request includes: In response to determining that the comparison result indicates that the address of the access request is within the range of the security area, receiving the access request; In response to determining that the comparison result indicates that the address of the access request is not within the range of the security area and the request type is a "read operation", the security check unit triggers a software interrupt and returns a predetermined value; and In response to determining that the comparison result indicates that the address of the access request is not within the range of the security area and the request type includes “write operation”, the security check unit triggers a software interrupt and discards the access request.

7. The method according to claim 1, characterized in that Also includes: Upon initialization, the host operating system or hypervisor sends a request for a security configuration, the request for a security configuration indicating a confidential computing mode; as well as The secure microprocessor obtains the secure configuration.

8. The method according to claim 7, characterized in that Also includes: Based on the security configuration, the security microprocessor notifies each security master control unit of the identity of the security GPU instance; as well as Configure the security zone to the security check unit.

9. A computing device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a machine, the method according to any one of claims 1 to 8 is performed.

11. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a machine, performs the method according to any one of claims 1 to 8.

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