Memory page processing method, equipment and device and storage medium

Abstract

The invention discloses a memory page processing method, equipment and device and a storage medium, and belongs to the technical field of communication. According to the method, after the memory page is allocated to the virtual address causing the missing page interruption, the allocated memory page is filled with the first data in advance, then the memory page filled with the first data is accessed, and if the data in the memory page is migrated to the cache subsequently, the first data filled in the memory page can also be migrated to the cache, so that the data in the memory page cannot be migrated to the cache. If the data of the memory page in the cache is eliminated to the memory, the eliminated cache data may also include the first data, and because the first data is the data in the data sequence corresponding to the cache compression mode, when the cache data including the first data is eliminated back to the memory, the probability that the cache data is matched with the cache compression mode can be increased, and the cache compression mode is matched with the cache data. And thus, the compression rate of the cached data can be improved.

Description

[0001] This application claims priority to Chinese patent application No. 202310740304.0, filed on June 20, 2023, with invention name “A memory setting method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a method, device, apparatus and storage medium for processing a memory page. Background Art

[0003] In order to alleviate the performance bottleneck caused by the memory wall, in related technologies, attempts are made to make up for the performance gap between the central processing unit (CPU) and the memory from the optimization of the micro-architecture level. For example, the design of the chip micro-architecture attempts to reduce the amount of data for off-chip communication through cache compression technologies such as frequent pattern compression (FPC). Specifically, when data in the CPU cache is eliminated from a cache line to the memory, the memory management unit (MMU) compresses the data in the cache line according to the cache compression mode matched by the data in the cache line to obtain compressed data, and stores the compressed data in the memory to eliminate the cache line data from the memory.

[0004] However, in addition to the data written by the application, there may be some random values ​​in the cache line, which causes the data in the cache line to not match the data compression pattern well. When the data that does not match the data compression pattern is eliminated from the cache line, it cannot be stored in the memory in a compressed manner, which reduces the compression rate of the cache data when the cache eliminates data from the memory. Summary of the invention

[0005] The embodiment of the present application provides a memory page processing method, device, apparatus and storage medium, which can improve the compression rate of cache data. The technical solution is as follows:

[0006] In a first aspect, a method for processing a memory page is provided, the method comprising the following steps: when a virtual address (called a first address virtual) accessed by an application causes a page fault interrupt, a memory page (called a first memory page) is allocated for the first virtual address; then, the first memory page is filled with: data in a data sequence corresponding to a cache compression mode (called the first data), wherein the cache compression mode is a data compression mode used when migrating data written by an application in a cache to a memory page; then, based on the first virtual address, the filled first memory page is accessed.

[0007] This method pre-fills the first data in the allocated memory page after allocating the memory page for the virtual address that caused the page fault interrupt, and then accesses the memory page filled with the first data. If the data in the memory page is subsequently migrated to the cache, the first data filled in the memory page will also be migrated to the cache. If the data of the memory page in the cache is eliminated to the memory, the eliminated cache data may also include the first data. Since the first data is data in the data sequence corresponding to the cache compression mode, when the cache data including the first data is eliminated back to the memory, the probability of the cache data matching the cache compression mode can be increased, thereby improving the compression rate of the cache data.

[0008] In one possible implementation, the above process of filling the first memory page with the first data may be: when the application turns on the memory pre-filling function, filling the first data in the first memory page, wherein the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

[0009] Based on the above possible implementation methods, the first data will be pre-filled for the memory pages allocated to the application only when the memory pre-filling function is turned on by the application. There is no need to pre-fill the first data for the memory pages allocated to each running application, thereby reducing the workload of filling the first data.

[0010] In a possible implementation, when the application enables the memory pre-filling function, before the first memory page is filled with the first data, the method further includes the following steps: based on the running status of the application, periodically enabling the memory pre-filling function for the application.

[0011] In one possible implementation, when the application turns on the memory pre-filling function, before filling the first memory page with the first data, the method also includes the following steps: when the type of the application is a target type, turning on the memory pre-filling function for the application, and the target type application is applicable to the cache compression mode.

[0012] Based on the above possible implementation methods, the memory pre-filling function will be enabled for the application only when the cache compression mode is applicable to the application, so that during the running of the application, the compression efficiency of the application data when migrating from the cache to the memory can be improved by pre-filling the first data for the memory pages of the application. It can also avoid filling the first data for the memory pages of the application that is not applicable to the cache compression mode, thereby reducing the workload of filling the first data.

[0013] In one possible implementation, the access to the filled first memory page based on the first virtual address includes the following steps: first receiving a first write request from an application, the first write request indicating writing second data to the first virtual address, and then updating the first data at a position corresponding to the first virtual address in the first memory page to the second data.

[0014] Based on the above possible implementation methods, the first data is the data previously filled by the application to the memory page. When the application subsequently writes data to the memory page, it only needs to update the first data to the data to be written. In this way, the cache compression rate can be improved by pre-filling the first data without affecting the normal writing of data by the application.

[0015] In one possible implementation, multiple second memory pages are used to store task data of the same computing task of an application, and multiple second memory pages are filled with first data. The method also includes the following steps: receiving a second write request from the application, the second write request indicating writing task data to a second virtual address; updating the first data at a position corresponding to the second virtual address in the multiple second memory pages to task data.

[0016] Based on the above possible implementation methods, multiple memory pages corresponding to the same computing task have been filled with the first data. When writing task data to any memory page, the first data in any memory page can be updated to the task data. Even if any memory page among the multiple memory pages has not written task data, due to the existence of the first data, no random value will be written to the memory page, thereby avoiding the random value from affecting the compression of the cache data of the memory page, thereby improving the cache compression rate.

[0017] In a possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest occurrence frequency in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0018] Based on the above possible implementation methods, the first data in the data sequence is filled in the first memory page. If the data of the first memory page is subsequently migrated to the cache, when the cache data of the first memory page is migrated from the cache, part of the first data in the cache data may still be retained in the cache, so that the cache data can be more easily matched with the data compression pattern, so as to further improve the compression rate of the cache data.

[0019] In a possible implementation, the first data is S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0020] Based on the above possible implementation methods, the first data in multiple data sequences is filled in the first memory page. If the data of the first memory page is subsequently migrated to the cache, when the cache data of the first memory page is migrated from the cache, part of the first data in the cache data may still be retained in the cache, so that the cache data can be more easily matched with the multiple data compression patterns, thereby increasing the probability that the cache data matches the data compression pattern, so as to further improve the compression rate of the cache data.

[0021] In a second aspect, a method for processing a memory page is provided, the method comprising the following steps: after obtaining an allocation notification message, filling a first memory page with first data, wherein the allocation notification message is used to notify a page fault interrupt caused by an application accessing a first virtual address, and a first memory page has been allocated for the first virtual address, and the first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by an application in a cache to a memory page.

[0022] In a possible implementation, filling the first data in the first memory page includes the following steps: filling the first data in the first memory page when the application turns on a memory pre-filling function, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

[0023] In a possible implementation, when the application enables the memory pre-filling function, before the first memory page is filled with the first data, the method further includes the following steps: based on the running status of the application, periodically enabling the memory pre-filling function for the application.

[0024] In one possible implementation, when the application turns on the memory pre-filling function, before filling the first memory page with the first data, the method also includes the following steps: when the type of the application is a target type, turning on the memory pre-filling function for the application, and the target type application is applicable to the cache compression mode.

[0025] In a possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest occurrence frequency in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0026] In a possible implementation, the first data is S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0027] According to a third aspect, a memory page processing device is provided, the memory page processing device comprising a functional module for executing the memory page processing method provided by the first aspect or any optional method of the first aspect.

[0028] In a fourth aspect, a memory filling device is provided, which includes a functional module for executing the memory page processing method provided by the second aspect or any optional method of the second aspect.

[0029] In a fifth aspect, an electronic device is provided, comprising a processor, wherein the processor is used to execute program code so that the electronic device performs operations performed by a memory page processing method provided in the first aspect or any optional method of the first aspect.

[0030] In a sixth aspect, a memory filling device is provided, which includes a processor, and the processor is used to execute program code so that the memory filling device performs operations performed by a memory page processing method provided in the second aspect or any optional method of the second aspect.

[0031] In a seventh aspect, a computer-readable storage medium is provided, in which at least one program code is stored. The program code is read by a processor to enable an electronic device to execute the operations performed by the memory page processing method provided in the first aspect or any optional method of the first aspect.

[0032] In an eighth aspect, a computer-readable storage medium is provided, in which at least one program code is stored. The program code is read by a processor to enable a memory filling device to perform the operations performed by a memory page processing method provided in the second aspect or any optional method of the second aspect.

[0033] In the ninth aspect, a computer program product or a computer program is provided, which includes a program code, and the program code is stored in a computer-readable storage medium. A processor of an electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the electronic device executes the method provided in the above-mentioned first aspect or various optional implementations of the first aspect.

[0034] In the tenth aspect, a computer program product or a computer program is provided, which includes a program code, and the program code is stored in a computer-readable storage medium. The processor of a memory filling device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the memory filling device executes the method provided in the above-mentioned second aspect or various optional implementations of the second aspect.

[0035] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is an electronic device architecture diagram of an application memory page processing method provided in an embodiment of the present application;

[0037] Figure 2 It is a flow chart of a method for processing a memory page provided in an embodiment of the present application;

[0038] Figure 3 It is an architecture diagram of an electronic device that uses another method for processing an application memory page provided in an embodiment of the present application;

[0039] Figure 4 is a flow chart of another method for processing a memory page provided in an embodiment of the present application;

[0040] Figure 5 It is a schematic diagram of an application accessing memory provided by an embodiment of the present application;

[0041] Figure 6 It is a structural schematic diagram of a memory page processing device provided in an embodiment of the present application;

[0042] Figure 7 It is a structural schematic diagram of a memory filling device provided in an embodiment of the present application;

[0043] Figure 8 It is a structural schematic diagram of another memory filling device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the specific implementation of the present application, some of the nouns involved in the specific implementation are introduced as follows.

[0045] Memory page: Divide the memory space into partitions of equal size. Each partition is a memory page. Each memory page is referred to by a physical page number. Different memory pages have different physical page numbers. Memory pages are also called physical blocks or page frames.

[0046] Virtual page: Divide the virtual address space of an application into regions of equal size. The size of each region is equal to the size of a memory page. Each region is a virtual page. Each virtual page is referred to by a virtual page number. Different virtual pages have different virtual page numbers. Virtual pages are also called pages or pages.

[0047] Page table: includes multiple page table entries (PTE), each PPE includes a virtual page number of a virtual page, a physical page number of a physical page, and a valid flag to indicate that the virtual page is mapped to the memory page (i.e., whether the virtual page is loaded into the memory page). The value of the valid flag is used to indicate whether the mapping relationship between the virtual page and the physical page is valid (i.e., whether the PTE is valid). Exemplarily, the valid flag has a value of 1, indicating that the mapping relationship is valid and the virtual page has been loaded into the memory page. The valid flag has a value of 0, indicating that the mapping relationship is invalid and the virtual page has not been loaded into the memory page.

[0048] Page fault interrupt: When an application accesses a virtual page, the memory management unit (MMU) queries the page table to determine whether the virtual page to be accessed has been loaded into the memory page. Whenever the virtual page is not loaded into the memory page, a page fault interrupt will be generated. The operating system will allocate a memory page for the virtual page from the memory requested by the application, and load the virtual page into the allocated memory page to resolve the page fault interrupt.

[0049] Virtual address (VA): an address in a virtual address space. The virtual address space includes multiple virtual addresses. A virtual address includes a virtual page number of a virtual page and an offset within the page. The offset within the page indicates the address offset of the virtual address in the virtual page.

[0050] Physical address (PA): It is an address in the physical address space. The physical address space is the space provided by the memory. The physical address space includes multiple physical addresses. The physical address includes a physical page number of a physical page and an offset within the page. The offset within the page indicates the address offset of the physical address in the memory page.

[0051] Cache compression algorithm: a data compression algorithm used when migrating data in a cache (called cache data) to a memory page. The cache compression algorithm defines at least one cache compression mode, a data compression method for each cache compression mode, and a data sequence required by each cache compression mode. Different cache compression modes require different data sequences. The cache compression mode is a data compression mode used when migrating cache data to a memory page. When the cache data to be compressed is the same (i.e., matches) as the data sequence required by any cache compression mode, the cache compression scheme used for any cache compression mode can be used to compress the cache data to be compressed. If the cache data to be compressed is not the same as the data sequence required by at least one cache compression mode, the cache data to be compressed cannot be compressed. The data sequence required by any cache compression mode includes N (N>1) data, and the N data are N values ​​in the same N-base. Therefore, the data sequence can also be called a value sequence. Taking hexadecimal as an example, each of the N data is a value from 0 to F in hexadecimal. Taking decimal as an example, each data is a value from 0 to 9 in decimal. The N data may be the same value or different values. Each data in the N data is stored in binary data form. When stored, each data is represented by a binary value (0 / 1) of M (M>0) bits. Taking N=16 and M=4 as an example, a hexadecimal data is represented by a 4-bit binary value. When stored, the length of the data sequence is M*N bits.

[0052] FPC: A cache compression algorithm based on cache line compression / decompression. Each cache line is divided into 32-bit words. For example, a 64-byte cache line is 16 words. Each 32-bit word is encoded as a 3-bit prefix plus data. Specifically, FPC defines seven cache compression modes: zero run mode, 4-bit sign-extended mode, 1-byte sign extended mode, halfword sign-extended mode, halfword padded with a zero halfword mode, two halfwords, each a byte sign-extended mode, and word consisting of repeated bytes mode. Each cache compression mode corresponds to a 3-bit prefix (pre-fix), and the pre-fix is ​​the corresponding data compression method. Taking the zero running mode as an example, the pre-fix corresponding to the zero running is 000, and the data sequence required by the zero running mode is a 32-bit word represented by the value 0. If the cache data to be compressed is a 32-bit word, and the cache data is 0x0000000000000000, then the cache data matches the zero running mode, and the zero running mode is used to compress the cache data to obtain compressed data 0x0, that is, the compressed data is 0-bit data + 3-bit pre-fix.

[0053] First data: data pre-filled in an empty memory page by a memory filling device before an application reads or writes data to the empty memory page. An empty memory page refers to a memory page to which no data is written.

[0054] Memory pre-fill function: indicates to fill the first data in the empty memory page before the application accesses the empty memory page.

[0055] Next, the application environment of the memory page processing method provided by the present application is introduced in conjunction with the accompanying drawings.

[0056] Figure 1 is an electronic device architecture diagram of an application memory page processing method provided in an embodiment of the present application, Figure 1 The electronic device 100 shown may be a terminal, a server or a network device. Here, the embodiment of the present application does not limit the device type of the electronic device 100.

[0057] like Figure 1As shown, the electronic device 100 includes a processor core 101, a performance monitoring unit (PMU) 102, an address translation lookaside buffer (TLB) 103, an MMU 104, a memory filling device 105, a memory 106, and a bus 107. Among them, the processor core 101, the PMU 102, the MMU 104, and the TLB 103 are all integrated in a central processing unit (CPU). The CPU includes one or more processor cores 101. The CPU may also include a cache, which is used to cache data stored in the memory 106. The cache in the CPU may also be a multi-level cache, such as a first-level cache to a third-level cache, or a first-level cache and a second-level cache. Here, the embodiment of the present application does not limit the number of caches in the CPU and the level of the cache. The MMU 104 communicates with the memory 106 through the bus 107. The memory 106 is also called the main memory.

[0058] The processor core 101 is used to run applications. One processor core 101 can run one or more applications. During the running of the application on the processor core 101, the application performs read and write access (i.e., read access or write access) to the virtual page. The processor core 101 performs read and write access to the memory page corresponding to the virtual page in the memory 106 through the MMU 104 to complete the read and write access to the virtual page, where read access refers to reading data on the page, and write access refers to writing data on the page.

[0059] PMU102 is a performance monitoring component embedded in the CPU, which is used to count specific hardware events (called PMU events) occurring in the CPU, such as events related to the processor core, events related to the cache, and events related to the TLB, etc. Among them, events related to the processor core include the number of instructions executed, captured exceptions, clock cycles, branch prediction errors, etc., events related to the cache include the number of accesses to each level of cache, cache misses, etc., and events related to TLB103 include TLB misses.

[0060] TLB103 is used to cache page table entries in a page table, and the page table is stored in memory 106. MMU104 is a component for managing memory 106, and MMU104 is also called a memory management device. MMU104 can translate the virtual address accessed by the application into a physical address in memory 106 and access the physical address. For example, when the processor core 101 is running an application, it sends the virtual address to be accessed by the application to MMU104, and MMU104 queries the virtual page number in the virtual address in the page table entry cached by TLB103. If a PTE including the virtual page number is found, a TLB hit occurs. If the PTE including the virtual page number is not found in TLB103, a TLB miss occurs, and MMU104 queries the PTE including the virtual page number from the page table in memory 106, and composes the physical address with the physical page number in the queried PTE and the address offset in the virtual address, so as to realize the conversion from the virtual address to the physical address, and perform read and write access to the location indicated by the physical address in memory 106, so as to realize the read and write access to the virtual address. During the running of the application, MMU104 migrates the data frequently accessed by the application in memory 106 to the last level cache (LLC) in the CPU. When the space in LLC is insufficient, MMU104 can eliminate the cached data in at least one cache line in LLC back to memory 106. In the process of eliminating cached data from memory 106, a cache compression algorithm can be used to migrate the cached data to memory 106.

[0061] When the virtual page accessed by the application is not loaded into the memory page, a page fault interrupt is triggered. In response to the page fault interrupt, the operating system loads the virtual page into a certain memory page of the memory 106. The loaded memory page is an empty memory page without data filled in. For this empty memory page, the memory filling device 105 is used to pre-fill the first data in the memory page before the application accesses the loaded virtual page, so that when the subsequent application writes data to the virtual page, the first data at the to-be-written position in the memory page can be updated to the to-be-written data. Optionally, before filling the first data into the memory page, the memory filling device 105 can also first determine whether the application to which the memory page belongs has enabled the memory pre-filling function. If the memory pre-filling function is enabled, the first data is filled in the memory page, otherwise, the first data is not filled in the memory page. Exemplarily, the memory filling device 105 can enable the memory pre-filling function for the application based on the PMU events monitored by the PMU 102 during the running of the application. This process will be described in detail later in conjunction with the method embodiment.

[0062] The memory filling device 105 can be implemented by software, hardware or a combination of software and hardware. As an example of a software functional unit, the memory filling device 105 includes program code, and the processor core 101 implements the function of the memory filling device 105 by running the program code.

[0063] The memory filling device 105 is an example of a hardware functional unit. The memory filling device 105 may be a device implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0064] When the memory filling device 105 is used as a hardware functional unit, the memory filling device 105 is integrated in the MMU 104 or is independent of the MMU 104. For example, the memory filling device 105 is located outside the MMU 104 in the CPU or is located outside the CPU in the electronic device where the electronic device 100 is located. Here, the embodiment of the present application does not limit the location of the memory filling device 105.

[0065] Alternatively, if Figure 1 As shown, the memory filling device 105 includes a judgment unit 51 and a filling unit 52. The judgment unit 51 is preset to judge whether the application to which the memory page belongs has enabled the memory pre-filling function, and is also used to enable the memory pre-filling function for the application according to the PMU events monitored by the PMU 102 during the running of the application. The filling unit 52 is used to pre-fill the first data into the memory page according to the judgment result of the judgment unit 51, or not to pre-fill the first data into the memory page. For any sub-unit in the judgment unit 51 and the filling unit 52, the any sub-unit can be implemented by software, hardware, or a combination of software and hardware. For example, if both the judgment unit and the filling unit 52 are implemented by hardware, as shown in FIG. Figure 1 As shown, the filling unit 52 is integrated in the MMU 104 , and the judgment unit 51 is independent of the MMU 104 . In other embodiments, the filling unit 52 and the judgment unit 51 are both integrated in the MMU 104 or are independent of the MMU 104 .

[0066] Next, combine Figure 2 , a process of pre-filling the first data in the memory page by the memory filling device is introduced in detail.

[0067] Figure 2 This is a flow chart of a method for processing a memory page provided in an embodiment of the present application. The method is applied to an electronic device, such as electronic device 100. The method is implemented by an operating system, a memory filling device and an MMU in the electronic device through interaction. The method includes the following steps.

[0068] 201. When a first virtual address accessed by an application causes a page fault interrupt, the operating system allocates a first memory page to the first virtual address.

[0069] Among them, the application is any application running on any processor core in any CPU of the electronic device, the application corresponds to a virtual address space, the first virtual address is any virtual address in the virtual address space, for the convenience of description, the virtual page number in the first virtual address is called the first virtual page number, the virtual page indicated by the first virtual page number is called the first virtual page, the first virtual page is the virtual page accessed by the application, and the memory page is allocated to the first virtual address, that is, the memory page is allocated to the first virtual page. This step 201 means that when the first virtual page accessed by the application causes a page fault interrupt, the operating system allocates a memory page to the first virtual page, and the first memory page is the memory page allocated to the first virtual page by the operating system.

[0070] In a possible implementation, when the processing core in the electronic device is running the application, if a page fault interrupt is caused by accessing the first virtual address, the processing core notifies the operating system of the page fault interrupt, and the operating system allocates a memory page for the first virtual page and loads the first virtual page into the memory page to end the page fault interrupt. Figure 3 The electronic device architecture diagram shown and Figure 4 Another method for processing a memory page is shown in the flowchart, and the triggering process and processing flow of the page fault interrupt are introduced as follows:

[0071] Step A1: When running an application program, the processor core sends a first read / write request to the MMU. The first read / write request includes a first virtual address to instruct to read / write data to the first virtual address.

[0072] Among them, reading and writing data to the first virtual address means performing read and write access to the first virtual address, and the first read and write request is a write request or a read request. When the first read and write request is a write request, the first read and write request also includes data to be written (referred to as second data), and the first read and write request indicates writing the second data to the first virtual address. When the first read and write request is a read request, the first read and write request indicates reading the data stored at the first virtual address.

[0073] Exemplarily, when the processor core executes any instruction (referred to as a first instruction) in an application program, if there is a need to access a first virtual address, the processor core sends a first read / write request to the MMU.

[0074] Step A2: The MMU receives the first read / write request, and based on the first read / write request, queries the PTE (referred to as the first PTE) corresponding to the first virtual address, where the first PTE is the PTE in the page table that includes the first virtual page number.

[0075] like Figure 3 As shown, the MMU first requests the TLB to query the first PTE. If the TLB finds the first PTE in the locally cached PTE, the TLB returns the first PTE to the MMU. If the first PTE is not found in the TLB, the MMU requests the memory to query the first PTE in the page table. If the memory finds the first PTE in the page table, the memory returns the first PTE to the MMU, so that the MMU can query the first PTE from the TLB or the memory.

[0076] like Figure 3 As shown, if the TLB does not cache the first PTE and the page table includes the first PTE, as the application runs, the MMU can also cache the first PTE in the page table to the TLB, so that when the application subsequently accesses the first virtual page again, the first PTE can be queried in the TLB. After the first PTE is cached in the TLB, as the application runs, the TLB may also eliminate the first PTE back to the page table.

[0077] After obtaining the first PTE, when the valid flag in the first PTE is not 0, for example, the valid flag in the first PTE is 1, the MMU is triggered to execute the following steps A3 and A4. When the valid flag in the first PTE is 0, the MMU jumps to execute the following step A5.

[0078] Step A3: When the valid flag in the first PTE is not 0, the MMU constructs a first physical address to be accessed based on the first PTE and the first virtual address, and accesses the first physical address in the memory.

[0079] The first physical address is a physical address corresponding to the first virtual address, that is, a physical address converted from the first virtual address. The first virtual address is accessed by accessing the first physical address.

[0080] For example, the MMU combines the memory page number in the first PTE (referred to as the first memory page number) with the page offset in the first virtual address to obtain a first physical address. When the first read / write request is a read request, the MMU reads the data stored at the first physical address in the first memory page (referred to as the fourth data) to access the first physical address. When the memory access request is a write request, the MMU writes the second data to the first physical address in the first memory page to access the first physical address.

[0081] Step A4: The MMU sends a read / write completion response to the processor core, where the read / write completion response indicates that the reading and writing of data to the first virtual address is completed. At this time, the process of accessing the first virtual address ends.

[0082] Among them, when the first read-write request is a read request, the read-write completion response is a read completion response, indicating that the data has been read at the first virtual address. At this time, the read-write completion response also includes the fourth data read from the first physical address. When the first read-write request is a write request, the read-write completion response is a write completion response, indicating that the second data has been written to the first virtual address.

[0083] Step A5: When the valid flag in the first PTE is 0, the MMU sends a read / write failure response to the processor core, where the read / write failure response indicates that the read / write of the first virtual address fails due to the lack of a corresponding memory page.

[0084] Step A6: Based on the read / write failure response, the processor core suspends the first instruction, triggers a page fault interrupt, and sends a page fault interrupt notification message to the operating system, where the page fault interrupt notification message indicates that a page fault interrupt occurs on the first virtual page.

[0085] The page fault interrupt notification message includes the first virtual page number.

[0086] Step A7: The operating system receives the page fault interrupt notification message and allocates a first memory page to the first virtual page based on the page fault interrupt notification message to perform page fault exception processing.

[0087] like Figure 4As shown, after receiving the page fault interrupt notification message, the operating system queries whether there are unoccupied memory pages from the memory pages allocated to the application, wherein the memory pages allocated to the application are memory pages in the memory space allocated to the application by the operating system when the application applies for memory. There are multiple memory pages allocated to the application, and the unoccupied memory pages refer to memory pages that are not called into the virtual pages, that is, memory pages that do not have a valid mapping relationship with the virtual pages in the page table.

[0088] If there are unoccupied memory pages among the memory pages allocated to the application, the operating system allocates any unoccupied memory page to the first virtual page. Figure 3 As shown, the operating system sends a first memory allocation request to the MMU, wherein the first memory allocation request includes a first virtual page number and a physical page number of the memory page, to indicate that the memory page is allocated to the first virtual page. After receiving the first memory allocation request, the MMU queries whether there is a valid PTE including the physical page number in the page table. Since the memory page has not been occupied, the MMU cannot query the valid PTE including the physical page number. The MMU continues to query the first PTE in the page table, such as Figure 4 As shown, the MMU fills the physical page number of the memory page into the first PTE, sets the valid flag in the first PTE to 1, and makes the first PTE valid, to indicate that the memory page is allocated to the first virtual page, that is, the first virtual page is called into any memory page. At this time, the memory page is the first memory page.

[0089] If there are no unoccupied memory pages in the memory pages allocated to the application, at this time, the memory pages allocated to the application are all occupied, and the operating system determines a victim page from the memory pages occupied by the application according to the swap-in and swap-out mechanism of the memory pages, and allocates the victim page to the first virtual page, wherein the victim page is the memory page to be allocated to the first virtual page. Figure 3 As shown, the operating system sends a second memory allocation request to the MMU, and the second memory allocation request includes the first virtual page number and the physical page number of the victim page to indicate that the victim page is allocated to the first virtual page. After receiving the second memory allocation request, the MMU queries whether there is a valid PTE including the physical page number in the page table. The valid PTE found is called the second PTE. The second PTE found indicates that the victim page has been allocated to other virtual pages except the first virtual page. In order to avoid data loss of the other virtual pages, as shown in FIG. Figure 3 and Figure 4As shown, the MMU queries whether data is stored in the sacrifice page. If data is stored in the sacrifice page, the data in the sacrifice page is written to the disk of the electronic device, so that the sacrifice page becomes an empty memory page. If no data is stored in the sacrifice page, the sacrifice page is an empty memory page. In the case where the sacrifice page is an empty memory page, the MMU sets the valid flag in the second PTE to 0 to invalidate the second PTE, queries the first PTE in the page table, fills the physical page number of the sacrifice page into the first PTE, and sets the valid flag in the first PTE to 1, so that the first PTE is valid, to indicate that the sacrifice page is assigned to the first virtual page, that is, the first virtual page is transferred to the sacrifice page. At this time, the sacrifice page is the first memory page.

[0090] The above is explained using an example in which the page table includes an invalid first PTE when the application accesses the first virtual page. In other embodiments, when the application accesses the first virtual page, the MMU may not be able to query the first PTE in the page table. In this case, the MMU still sends a read / write failure response to the processor core, triggering a page fault interrupt, thereby triggering the operating system to allocate a first memory page to the first virtual page. In this case, after the MMU determines the first memory page to be allocated to the first virtual page (such as a sacrifice page or any unoccupied memory page), the MMU creates a valid first PTE in the page table based on the first virtual page number and the physical page number of the first memory page (referred to as the first physical page number).

[0091] like Figure 3 As shown, after the first PTE is valid, the MMU sends an allocation notification message to the memory filling device, and the allocation notification message is used to notify that the first memory page has been allocated to the first virtual page, that is, to notify that the first memory page has been allocated to the first virtual address for the page fault interrupt caused by the application accessing the first virtual address. After receiving the allocation notification message, the memory allocation unit performs the following step 202 based on the allocation notification message. The allocation notification message includes the first virtual page number and the first physical page number.

[0092] 202. A memory filling device fills a first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, where the cache compression mode is a data compression mode used when migrating data written by an application in a cache to a memory page.

[0093] The cache compression mode is a cache compression mode defined in a cache compression algorithm used by the MMU, for example, the cache compression algorithm is FPC or other cache compression technology that relies on the cache compression mode. The cache compression algorithm defines at least one cache compression mode, a data sequence corresponding to each cache compression mode, and a data compression method, and the data sequence corresponding to each cache compression mode is the data sequence required by each cache compression mode for compressed data.

[0094] The first data is data in a data sequence corresponding to any cache compression mode in the at least one cache compression mode. Exemplarily, the first data is all the data in the data sequence (i.e., each data in the data sequence), or the first data is part of the data in the data sequence. Taking the case where the first data is part of the data in the data sequence as an example, assuming that the data sequence includes N data, the first data is the S data with the highest frequency of occurrence in the data sequence, wherein N is greater than 1, and S is greater than 0 and less than N. For example, S=1, taking the zero operation mode in the cache compression mode FPC as an example, the hexadecimal value 0 is the data with the highest frequency of occurrence in the data sequence corresponding to the zero operation mode, and taking the 1-byte sign extension mode in the cache compression mode FPC as an example, the data with the highest frequency of occurrence in the 1-byte sign extension mode is the hexadecimal value F. For another example, S=2, the data sequence is 0000FFFF, and the first data is 0 and F. Alternatively, the first data is R consecutive data in the data sequence, for example, the first R data in the data sequence are the first data, or the middle R data are the first data, or the last R data are the first data, where R is greater than 0 and less than N, and R and S may be the same or different. Here, the embodiments of the present application do not limit the values ​​of R and S.

[0095] In other embodiments, the first data is data in multiple data sequences required by multiple data compression modes defined by the cache compression algorithm. For example, the first data is S data with the highest occurrence frequency in the multiple data sequences, or the first data is data common to multiple data sequences.

[0096] like Figure 3 As shown, after receiving the allocation notification message from the MMU, the memory filling device learns that the MMU has allocated the first memory page to the first virtual page based on the first virtual page number and the first physical page number in the allocation notification message. At this time, the first memory page is an empty memory page, and the memory filling device fills the first memory page with the first data. For example, the first memory page is filled with the first data, or part of the memory space of the first memory page is filled with the first data, and the remaining space is not filled with the first data (that is, the first memory page is not filled with the first data).

[0097] Taking the case of filling the first memory page with the first data as an example, assuming that the size of the first memory page is 64 bytes (byte), 64byte=16*8*4bit, if the size of the first data is 4bit when stored, as shown in Table 1, the memory filling device fills 8 first data every 4byte (i.e. 8*4bit) in the first memory page to fill the first memory page with the first data. In this way, when the subsequent application writes data to the first virtual page again, the MMU updates the first data at the to-be-written position in the first memory page to the to-be-written data.

[0098] Table 1

[0099]

[0100] like Figure 3 As shown, after the first memory page is filled with the first data, the memory filling device sends a filling completion response to the MMU, and the filling completion response is used to indicate that the first data has been filled in the first memory page. After receiving the filling completion response, the MMU sends an allocation completion response to the operating system, and the allocation completion response indicates that the first memory page has been allocated to the first virtual page. After the operating system receives the allocation completion response, it sends a page fault interrupt processing completion response to the processor core to indicate that the page fault interrupt caused by the first virtual page has been processed. After the processor core receives the interrupt processing completion response, it ends the page fault interrupt processing flow, releases the suspended first instruction, and executes the first instruction again. Therefore, for the application, it can only perceive the occurrence of a page fault interrupt, and cannot perceive the action of pre-filling the first memory page with the first data.

[0101] When the processor core executes the first instruction again, it sends a first read / write request to the MMU. After receiving the first read / write request again, the MMU accesses the first memory page based on the first virtual address in the first read / write request (ie, step 203 below).

[0102] 203. The memory management unit accesses the filled first memory page based on the first virtual address.

[0103] Exemplarily, if the first read / write request received again is a write request, in order to distinguish it from other write requests described later, the first read / write request is referred to as a first write request. The MMU executes step A2 again, queries the first PTE corresponding to the first virtual address. At this time, the valid flag in the first PTE is 1, that is, the first PTE is a valid PTE. The MMU constructs a first physical address based on the first PTE and the first virtual address, and writes the second data to the position indicated by the first physical address in the first memory page (referred to as the first position) to achieve writing data to the corresponding position of the first virtual address in the first memory page. At this time, the first position may have been filled with the first data or may not have been filled with the first data. If the first position is not filled with the first data, the MMU writes the second data to the first position to complete the access to the first physical address and the first virtual address. If the first position has been pre-filled with the first data, when writing the second data to the first position, the first data at the first position is updated to the second data, wherein the storage space occupied by the second data is greater than or equal to the storage space occupied by the first data. Exemplarily, the MMU writes the second data to the first location indicated by the first physical address in the first memory page in the form of an overwrite, so that the first data at the first location is updated to the second data to complete the access to the first physical address and the first virtual address.

[0104] Among them, writing data to the first position means writing data starting from the first position. Still taking the above Table 1 as an example, assuming that the page offset in the first physical address is 0, the first position indicated by the first physical address is the starting position of the first memory page, and if the size of the second data is 4 bytes, as shown in Table 2, the MMU updates the first data stored in the first 4 bytes in the first memory page to the second data.

[0105] Table 2

[0106]

[0107] Assume that the first read / write request is a read request. At this time, the first memory page is pre-filled with the first data, not the data to be read by the application program. The data to be read by the application program has not yet been loaded into the first memory page. Figure 3 As shown, in order for the application to read the required fourth data, the MMU first writes the fourth data stored in the disk to the first physical address of the first memory page to update the first data at the first physical address to the fourth data. Thereafter, the application reads the fourth data from the first physical address to complete the access to the first physical address and the first virtual address.

[0108] After completing the access to the first physical address, the access to the first memory page is completed, and the MMU returns a read / write completion response to the processor core (ie, the above step A4).

[0109] After the processing core receives the read / write completion response, the processor core continues to execute the first instruction or executes other instructions of the application program (referred to as the second instruction) other than the first instruction. In the process of continuing to execute the first instruction or the second instruction, the application program will access the first virtual page or other virtual pages other than the first virtual page. In the case of accessing the first virtual page, the application program may access other virtual addresses of the first virtual page other than the first virtual address, or access the first virtual address again. The process of accessing other virtual addresses of the first virtual page can refer to the process of accessing the first virtual address, which will not be repeated here. The process of accessing other virtual pages can refer to the process of accessing the first virtual page, which will not be repeated here.

[0110] During the process of the processor core running the application, the application may access the first virtual page multiple times. For the application's write access to any virtual address of the first virtual page, the MMU updates the first data at the corresponding position of the any virtual address in the first memory page to the data to be written. If the application frequently accesses at least one virtual address of the first virtual page during operation, the MMU migrates the data in the target memory space where the at least one virtual address of the first memory page is located to a cache line (referred to as the first cache line) in the cache (such as LLC), wherein the at least one virtual address may include the first virtual address or may not include the first virtual address, the size of the target memory space is the same as the size of the cache line, the size of the target memory space may be the same as the size of the memory page or may be different from the size of the memory page, and when the size of the target memory space is the same as the size of the memory page, the target memory space is the first memory page, and all data stored in the first memory page must be migrated to the first cache line.

[0111] For ease of description, the data in the target memory space (i.e., the data migrated to the cache) is referred to as the first migration data. As the application accesses the target memory space, the first migration data includes the first data and / or the data written by the application. Taking Table 2 as an example, assuming that the size of the cache line is the same as the size of the memory page, both are 64 bytes, and the application frequently accesses the first memory page shown in Table 2, then the first memory page is the target memory space, the second data stored in the first memory page and each first data constitute the first migration data, and the MMU migrates the first migration data to the first cache line in the cache, and caches the first PTE in the page table to the TLB.

[0112] After migrating the first migration data to the first cache line, when the application reads the first virtual page, the MMU returns the data to be read in the first cache line to the application to achieve read access to the first memory page and the first virtual page. When the application writes to the first virtual page, the MMU writes the data in the first cache line to achieve write access to the first memory page and the first virtual page. At this time, the first migration data is updated, and the updated first migration data is called second migration data.

[0113] Still taking the application accessing the first virtual address as an example, the processor core sends an instruction to the MMU for the first read / write request. Based on the first virtual address in the first read / write request, the MMU can query the first PTE from the TLB, construct the first physical address according to the first PTE and the first virtual address, and perform read access or write access to the position corresponding to the first physical address in the first cache line. Taking write access as an example, the data to be written is called the fifth data. The MMU writes the fifth data to the position corresponding to the first physical address in the first cache line (called the second position) in the form of overwrite, so that the data at the second position is updated to the fifth data, and then the first migration data in the first cache line is updated to the second migration data. The data at the second position may be the first data or may not be the first data. Still taking the first migration data as the data shown in Table 2 as an example, assuming that the second position is the first bite of the 9th byte of the first memory page, if the fifth data is 4 bytes, as shown in Table 3, after writing the fifth data to the first cache line, the fifth data can overwrite the 8 first data from the 9th byte to the 12th byte of the first memory page in the first cache line. Assuming that the second position is the first bite of the 13th byte of the first memory page, if the fifth data is 2 bytes, as shown in Table 3, after writing the fifth data into the first cache line, the fifth data can overwrite the four first data of the 9th byte and the 10th byte of the first memory page in the first cache line.

[0114] Table 3

[0115]

[0116] Subsequently, when the cache data (first migration data or second migration data) in the first cache line meets the elimination condition, the MMU migrates the cache data to the first memory page. The elimination condition is a condition for eliminating the cache data in the cache line to the memory. Assuming that the data sequence length required by the cache compression mode is M*Nbit, the storage space size of the first cache line is Kbit, where K is greater than M*N, then K / (M*N) data to be migrated are stored in the first cache line. Still taking Table 3 as an example, K=64 bytes, M*N=4 bytes, then 16 data to be migrated are stored in the first cache line, such as the second data is one data to be migrated, 8 first data are one data to be migrated, 4 bytes of the fifth data are one data to be migrated, and 2 bytes of the fifth data and 4 first data are one data to be migrated.

[0117] When migrating cache data in the first cache row to the first memory page, for each data to be migrated, the MMU matches the data to be migrated with the data sequence required by at least one cache compression mode. If the data to be migrated is the same as the data sequence required by any cache compression mode, the data to be migrated matches the data sequence and matches any cache compression mode. Otherwise, the data to be migrated does not match any cache compression mode. If the data to be migrated matches any cache compression mode, the MMU compresses the data to be migrated using the data compression method corresponding to any cache compression mode to obtain compressed data, and writes the compressed data to the first memory page to achieve migration of the data to be migrated to the first memory page. If the data to be migrated does not match any cache compression mode, the MMU writes the data to be migrated to the first memory page to achieve migration of the data to be migrated to the first memory page.

[0118] As shown in Table 3, the data to be migrated may be the first data, or a combination of the fifth data and part of the first data (called combined data), or the fifth data. If the first data is data in a cache compression mode in the cache compression algorithm, when the data to be migrated is the first data or the combined data, relative to random data, the data to be migrated is more likely to match the cache compression mode, thereby increasing the probability of the data to be migrated being compressed, and further increasing the compression rate of the cache data when the cache is eliminated from the memory. For example, when the first data is a hexadecimal value of 0, the data to be migrated is 8 values ​​of 0, and the cache compression mode is the zero operation mode in FPC, relative to random data, the data to be migrated can definitely match the zero operation mode. If the first data is data in multiple data sequences of multiple cache compression modes defined by the cache compression algorithm, such as the S data with the highest frequency in multiple data sequences or the data common in multiple data sequences, when the data to be migrated is the first data or the combined data, the data to be migrated is more likely to match the cache compression mode in the multiple cache compression modes relative to the random data, thereby further increasing the probability that the data to be migrated matches the cache compression mode, further increasing the probability that the data to be migrated is compressed, and further increasing the compression rate of the cache data when the cache is eliminated from the memory. Taking the first data as the hexadecimal value 0, the data sequences corresponding to the zero operation mode, the 4-bit sign extension mode, the half-word sign extension mode, and the half-word mode filled with 0 half-words in the FPC all have the value 0. If the data to be migrated is 8 values ​​0, the data to be migrated can be matched to the zero operation mode. If the data to be migrated is a combination of multiple values ​​0 and other values, the data to be migrated may match the 4-bit sign extension mode, the half-word sign extension mode, or the half-word mode filled with 0 half-words.

[0119] The method provided by the embodiment of the present application pre-fills the first data in the allocated memory page after allocating the memory page for the virtual address that causes the page fault interrupt, and then accesses the memory page filled with the first data. If the data in the memory page is subsequently migrated to the cache, the first data filled in the memory page will also be migrated to the cache. If the data of the memory page in the cache is eliminated to the memory, the eliminated cache data may also include the first data. Since the first data is the data in the data sequence corresponding to the cache compression mode, when the cache data including the first data is eliminated back to the memory, the probability that the cache data matches the cache compression mode can be increased, and then the compression rate of the cache data can be increased, thereby reducing the overhead of transmitting the cache data from the cache to the memory.

[0120] Figure 2The embodiment shown is described by taking the example that the memory filling device fills the first data in the first memory page after the operating system allocates the first memory page for the first virtual page. In another possible implementation, Figure 4 As shown, before filling the first data into the first memory page, the memory filling device will first determine whether the application accessing the first virtual page has enabled the memory pre-filling function. If the application has not enabled the memory pre-filling function unit, the memory filling device does not perform the step of filling the first data into the first memory page, and returns a filling failure response to the MMU to indicate that the first data has not been filled into the first memory page. Figure 4 In step A8, when the application turns on the memory pre-filling function, the memory filling device fills the first data in the first memory page allocated to the virtual address, and returns a filling completion response to the MMU. In this way, after the MMU sends the allocation notification message to the memory filling device, it receives the filling failure response or the filling completion response from the memory filling device, and then returns the allocation completion response to the operating system, so that the operating system sends a page fault interrupt processing completion response to the processor core, so that the processor core executes step A1 again. In other embodiments, when the first data is not filled into the first memory page, the memory filling device may not return a filling failure response to the MMU, and when the first data is filled into the first memory page, it may not return a filling completion response to the MMU. In this case, after the MMU sends the allocation notification message to the memory filling device, after a certain period of time, it returns an interrupt processing completion response to the operating system to reserve time for the memory filling device to fill the first data.

[0121] against Figure 4 In the implementation method described, when the application turns on the memory pre-filling function, the memory filling device will pre-fill the first data for the memory page allocated to the application. There is no need to pre-fill the first data for the memory pages allocated to each application running in the electronic device, thereby reducing the workload of the memory filling device.

[0122] Next, a method of enabling the memory pre-filling function for an application program to determine whether the memory pre-filling function is enabled for the application program is introduced as follows.

[0123] In one possible manner, the memory filling device enables the memory pre-filling function for the application through the following enabling method 1 or enabling method 2.

[0124] Enabling method 1: When the type of the application is the target type, the memory filling device enables the memory pre-filling function for the application.

[0125] Among them, the cache compression mode is applicable to target type applications, such as compilers, applications for simulating discrete events, applications for processing big data, etc. The cache compression mode is not applicable to non-target type applications, such as compression applications for compressing data, applications for scientific computing, etc.

[0126] Before the application is run or during the application is run, the memory filling device queries the program type of the application from the configuration information of the application in the operating system. If the program type of the application is the target type, the memory filling device turns on the memory pre-filling function for the application. If the program type of the application is not the target type, the memory filling device does not turn on the memory pre-filling function for the application. The way to turn it on is, for example, to add a preset function turn-on flag in the configuration information, and the preset function turn-on flag is used to indicate that the application has turned on the memory pre-filling function.

[0127] In another possible implementation, the memory filling device is not responsible for enabling the memory pre-filling function for the application, and the operating system enables the memory pre-filling function for the target type of application in a similar manner. Alternatively, neither the memory filling device nor the operating system actively enables the memory pre-filling function for the application. Only when the user issues an instruction to enable the memory pre-filling function for the application, the operating system will add a preset function enable flag to the configuration information of the application in accordance with the user's instruction to enable the memory pre-filling function for the application.

[0128] For the above-mentioned enabling method 1, before filling the first data into any memory page, the memory filling device determines whether the application has enabled the memory pre-filling function by querying whether the configuration information of the application accessing the memory page includes a preset function enabling flag. Figure 5Taking the schematic diagram of application accessing memory as an example, it is assumed that the processing core runs process 1 and process 2, and the process identifiers (PID) of process 1 and process 2 are 11111 and 22222 respectively. Process 1 and process 2 correspond to application 1 and application 2 respectively. Application 1 is a big data application, suitable for cache compression mode, and the memory pre-filling function is enabled. Application 2 is a compression application, not suitable for cache compression mode, and the memory pre-filling function is not enabled. The processor core runs process 1 and process 2 to realize the operation of application 1 and application 2. It is assumed that virtual page 1 accessed by process 1 and virtual page 2 accessed by process 2 both trigger page fault interrupts. After the MMU creates valid PTEs for virtual page 1 and virtual page 2, it notifies the filling unit in the memory filling device that memory pages have been allocated for virtual pages 1 and 2. Based on the notification of the MMU, the memory filling device sends a judgment request to the judgment unit to request whether the applications corresponding to process 1 and process 2 have enabled the memory pre-filling function. After receiving the judgment request, the judgment unit queries the configuration information of application 1 and the configuration information of application 1, and queries the preset function activation flag from the configuration information of application 2, and queries the preset function activation flag from the configuration information of application 1 and corresponds to PID1 of process 1, and then returns a judgment response to the filling unit to indicate that application 2 corresponding to process 2 does not have the memory pre-filling function enabled, and application 1 corresponding to process 1 has the memory pre-filling function enabled. After receiving the judgment response, the memory preset module fills the first data in the memory page allocated for virtual page 1 according to the indication of the judgment response, and does not fill the first data in the memory page allocated for virtual page 2.

[0129] Considering that even if the memory pages allocated to an application that is not applicable to the cache compression mode are pre-filled with the first data, the data of the application cannot be well matched with the cache compression mode when it is migrated from the cache to the memory, through the above-mentioned activation method 1, when the application is applicable to the cache compression mode, the memory filling device will enable the memory pre-filling function for the application, so that during the running of the application, the memory pages of the application are pre-filled with the first data, thereby improving the compression efficiency of the application data when it is migrated from the cache to the memory, and avoiding filling the memory pages of the application that is not applicable to the cache compression mode with the first data, thereby reducing the workload of the memory filling device.

[0130] Enabling method 2: During the running of the application, the memory filling device periodically enables the memory pre-filling function for the application based on the running status of the application.

[0131] The running status of the application is reflected by the first PMU event and / or the second PMU event triggered during the running of the application. The first PMU event is the running of a floating-point operation instruction when the application is running. The floating-point operation instruction refers to an instruction used for floating-point operation.

[0132] The second PMU event refers to a PMU event related to data exchange between the cache and the memory. The second PMU event can reflect the data exchange between the cache and the memory during the running of the application. There is at least one second PMU event, such as a cache miss event, a TLB miss event, and a pipeline stall (core_pipeline_stall_due_to_cache_miss) event caused by the number of first / second cache misses.

[0133] In a possible implementation, during the running of the application, after each time period, the memory filling device predicts whether the cache compression mode is applicable to the application when it runs in the next time period based on the running status of the application in the time period, and if applicable, the memory pre-filling function of the next time period is enabled for the application, otherwise, the step of enabling the memory pre-filling function of the next time period for the application is not performed. The duration of the time period is the same as the duration of the next time period, and the duration of the time period is the unit duration of enabling the memory pre-filling function.

[0134] by Figure 5 For example, when the processor core is running an application, the PMU records and counts the first PMU event and / or the second PMU event triggered by the application. The judgment unit in the memory filling device obtains the statistical information of the first PMU event and / or the second PMU event in the time period from the PMU every time period, and predicts whether the cache compression mode is applicable when the application runs in the next time period based on the statistical information.

[0135] Exemplarily, taking the acquisition of the statistical information of the first PMU event in the time period as an example, the statistical information of the first PMU event in the time period is the number of floating-point operation instructions running in the time period, the judgment unit also obtains the total number of instructions of the application running in the time period from the PMU, and based on the number of floating-point operation instructions and the total number of instructions, obtains the proportion of floating-point operation instructions in the application instructions running in the time period, the proportion is the ratio between the number of floating-point operation instructions and the total number of instructions, the cache compression mode is applicable to non-floating-point data (such as integer data), not to floating-point data, if the proportion is less than or equal to the proportion threshold, it means that the application is applicable to the cache compression mode, then the judgment unit turns on the memory pre-filling function for the next time period for the application. If the proportion is greater than the proportion threshold, it means that the application is not applicable to the cache compression mode, then the judgment unit does not temporarily turn on the memory pre-filling function for the application.

[0136] Taking the statistical information of the second PMU event as an example, assuming that at least one of the cache miss event, the TLB miss event, and the pipeline pause event caused by the first / second cache miss number is a second PMU event, the statistical information of the cache miss event in the time period is the number of occurrences of the cache miss event in the time period (referred to as the first occurrence number), if the first occurrence number is greater than or equal to the first number threshold, it means that the cache and the memory frequently exchange data in the time period, if the first occurrence number is less than the first number threshold, it means that the cache and the memory do not frequently exchange data in the time period. The statistical information of the TLB miss event in the time period is the number of occurrences of the TLB miss event in the time period (referred to as the second occurrence number), if the second occurrence number is greater than or equal to the second number threshold, it means that the cache and the memory frequently exchange data in the time period, if the second occurrence number is less than the first number threshold, it means that the cache and the memory do not frequently exchange data in the time period. The statistical information of the pipeline pause event in the time period is: the total pipeline pause duration (pipeline stall) caused by the pipeline pause event in the time period. If the pipeline stall is greater than or equal to the duration threshold, it means that the cache and the memory frequently exchange data in the time period. If the pipeline stall is less than the duration threshold, it means that the cache and the memory do not frequently exchange data in the time period. If the cache and the memory frequently exchange data in the time period, it means that the cache compression mode is applicable to the application when it is running in the time period, and the application may also apply the cache compression mode when it is running in the next time period. If the cache and the memory do not frequently exchange data in the time period, it means that the cache compression mode is not applicable to the application when it is running in the time period, and the application may also not apply the cache compression mode when it is running in the next time period. Based on this, if the first occurrence number is less than the first number threshold, the second occurrence number is less than the second number threshold, and the pipeline stall is less than the duration threshold, the cache compression mode is not applicable to the application when it runs in the next time period, and the judgment unit does not temporarily enable the memory pre-filling function for the application; if the first sending number, the second occurrence number, and the pipeline stall satisfy at least one of the following: the first occurrence number is greater than or equal to the first number threshold, the second occurrence number is greater than or equal to the second number threshold, and the pipeline stall is greater than or equal to the duration threshold, the cache compression mode is applicable to the application when it runs in the next time period, and the judgment unit enables the memory pre-filling function for the next time period for the application.

[0137] In other embodiments, the preset submodule does not obtain the statistical information of the first PMU event in the time period, obtains the statistical information of the second PMU event, and determines whether it is necessary to enable the memory pre-fill function for the next time period for the application based only on the statistical information of the second PMU event.

[0138] In some other embodiments, the judgment unit may also input the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period into an artificial intelligence (AI) model, and the AI ​​model outputs a judgment result based on the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period, the judgment result indicating whether it is necessary to enable the memory pre-filling function for the next time period for the application, and the threshold judgment submodule enables the memory pre-filling function for the next time period for the application based on the indication of the judgment result, or temporarily does not enable the memory pre-filling function for the next time period for the application. The AI ​​model is trained based on a plurality of first training data and a plurality of second training data statistical information, the first training data is the statistical information of the first PMU event and / or the second PMU event triggered during the operation of the target type application, and the second training data is the statistical information of the first PMU event and / or the second PMU event triggered during the operation of the non-target type application, so that the AI ​​model can learn the mapping relationship between the statistical information of the first PMU event and / or the second PMU event and whether it is necessary to enable the memory pre-filling function for the next time period for the application during the training process. The AI ​​model may be a decision tree model or other types of AI models.

[0139] Taking the acquisition of the statistical information of the first PMU event and the second PMU event in the time period as an example, if it is determined based on the statistical information of the first PMU event that the cache compression mode is not applicable when the application is running in the next time period, the judgment unit determines whether to enable the memory pre-filling function for the application in the next time period based on the statistical information of the second PMU event. If it is determined based on the statistical information of the first PMU event that the application is applicable to the cache compression mode when it is running in the next time period, the judgment unit does not need the statistical information of the second PMU event to make further judgments. In other embodiments, the judgment logic is implemented using a decision tree. When in use, the judgment unit can input the statistical information of the first PMU event and the second PMU event in the time period into the decision tree, and the decision tree outputs a judgment result according to the above judgment logic, and the judgment result indicates whether to enable the memory pre-filling function for the next time period for the application.

[0140] In other embodiments, the judgment unit may also input the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period into an artificial intelligence (AI) model, and the AI ​​model outputs the judgment result based on the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period. The AI ​​model is trained based on a plurality of first training data and a plurality of second training data statistical information, the first training data is the statistical information of the first PMU event and / or the second PMU event triggered during the operation of the target type application, and the second training data is the statistical information of the first PMU event and / or the second PMU event triggered during the operation of the non-target type application, and the training enables the AI ​​model to learn the mapping relationship between the statistical information of the first PMU event and / or the second PMU event and the judgment result. The AI ​​model is, for example, a neural network model.

[0141] If the judgment unit determines to enable the memory pre-filling function for the application in the next time period, it queries whether the configuration information of the application in the operating system includes a preset function enabling flag. If the preset function enabling flag is not included, the preset function enabling flag is added to the configuration information. If the preset function enabling flag is included, there is no need to add the preset function enabling flag. In this way, in the next time period, the judgment unit can determine that the memory pre-filling function of the application is enabled in the next time period through the preset function enabling flag in the configuration information.

[0142] If the judgment unit determines that the memory pre-filling function is not enabled for the application in the next time period, the configuration information of the application in the operating system is queried to see whether it includes a preset function enabling flag, and if it includes the preset function enabling flag, the preset function enabling flag in the configuration information is deleted. In this way, in the next time period, the judgment unit cannot find the preset function enabling flag in the configuration information, and thus can determine that the memory pre-filling function is not enabled for the application in the next time period.

[0143] Figure 5 The illustrated embodiment is described by taking the memory filling device including a judgment unit and a filling unit as an example. In other embodiments, the memory filling device is not divided into sub-units. In this case, the steps performed by the judgment unit and the filling unit are all implemented by the memory filling device.

[0144] Based on the above-mentioned activation method 2, during the running of the application, the memory pre-filling function can be periodically enabled for the application, so that more detailed control can be performed on whether the application enables the memory filling function. During the time period when the memory pre-filling function is not enabled, there is no need to fill the empty memory page called into the virtual page with the first data, which further reduces the workload of the memory filling device.

[0145] In other embodiments, the memory pre-filling unit does not have the ability to enable the memory pre-filling function for the application. In this case, the operating system or other units can enable the memory pre-filling function for the application according to the above-mentioned enabling method 1 or enabling method 2.

[0146] Figure 2-Figure 5 The described embodiments are all explained by taking an application accessing a virtual page as an example. In other embodiments, a computing task of the application may correspond to multiple virtual pages, and the multiple virtual pages are continuous. The multiple memory pages corresponding to the multiple virtual pages are used to store task data of the computing task, and the task data is the data generated by the application in the process of executing the computing task.

[0147] When the application writes the task data, the task data may be written to all virtual pages of the multiple virtual pages, or may be written to some virtual pages of the multiple virtual pages. When writing data to some virtual pages, the virtual pages where the task data is written may be adjacent or non-adjacent. For example, the computing task corresponds to virtual pages 1-3, and virtual pages 1-3 are continuous. It is assumed that when the computing task meets condition 1, the application writes the task data of the computing task to virtual page 1, when the computing task meets condition 2, the task data of the computing task is written to virtual page 2, and when the computing task meets condition 3, the task data of the computing task is written to virtual page 3. When the application is executing the computing task, the computing task may not meet one of the conditions 1-3, resulting in the application not filling task data into some virtual pages in virtual pages 1-3. For example, during the execution of the computing task, only conditions 1 and 3 are met, but condition 2 is not met, then the application will write task data into virtual pages 1 and 3, but will not write task data into virtual page 2. In the related art, the MMU writes task data into memory pages 1 and 3 corresponding to virtual pages 1 and 3 to write task data into virtual pages 1 and 3. Since the application does not write task data into virtual page 2, the MMU will fill random values ​​into inner page 2 corresponding to virtual page 2. Once the data in memory pages 1-3 are migrated to the cache, the random values ​​filled into memory page 2 will also be migrated to the cache. When the cached data in memory pages 1-3 in the cache are eliminated back into the memory page, the random values ​​in the cached data of memory page 2 make it difficult for the cached data to match the cache compression mode, resulting in a low cache compression rate.

[0148] The present application fills the first data in each empty memory page of the application through a memory filling unit. If the task data of the computing task executed by the application is not filled into the corresponding memory page, since the memory page has been filled with the first data, the MMU will not continue to fill the random value in the memory page, thereby avoiding the problem of low cache compression rate caused by filling random value.

[0149] For example, a computing task of an application corresponds to multiple virtual pages (called second virtual pages), and the memory page corresponding to the second virtual page is called a second memory page. The multiple second memory pages are all used to store the task data of the computing task of the application. Figure 2 or Figure 4 ), when each second memory page is transferred into the corresponding second virtual page, the memory filling unit will fill the first data in the second memory page, so that the application can pre-fill the first data for each second memory page before writing the task data to each second memory page.

[0150] During the process of the processor core executing the computing task of the application, when the application writes task data to any virtual address (referred to as the second virtual address) in the plurality of second virtual pages, the processor core is triggered to send a second write request of the application to the memory management device, and the second write request indicates to write the task data to the second virtual address. After receiving the second write request, the memory management device converts the second virtual address in the second write request into a physical address (referred to as the second physical address), wherein the process of converting the address can refer to the process of converting the first virtual address into the first physical address. The memory management device updates the task data to be written with the first data at the second physical address in the plurality of second memory pages, so as to update the first data at the corresponding position of the second virtual address in the plurality of second memory pages to the task data. The second memory page where the second physical address is located is called the third memory page. When writing task data to the second physical address in the third memory page, if the data in the third memory page has not been migrated to the cache line in the cache (called the second cache line), the memory management device writes the task data to the second physical address in the third memory page. If the data in the third memory page has been migrated to the second cache line, the memory management device writes the task data to the position corresponding to the second physical address in the second cache line to overwrite the first data at the position. If the cache data of the third memory page in the second cache line is subsequently eliminated back to the third memory page, since the cache data includes the first data, the cache data is easier to match the cache compression mode, thereby improving the cache compression rate.

[0151] After the data in the multiple second memory pages are migrated to the cache, the first data filled in the multiple second memory pages and / or the task data written by the application program will be migrated to the cache together. For any memory page (referred to as the fourth memory page) other than the third memory page in the multiple second memory pages, before writing the task data to the fourth memory page, the data in the fourth memory page is the first data, and the cache data of the fourth memory page in the cache is the second data. If the application program has not written the task data to the fourth memory page during the execution of the computing task, the cache data of the fourth memory page in the cache is always the first data, and will not be a random value. When the cache data of the fourth memory page is subsequently eliminated back to the fourth memory page, the cache data is easier to match the cache compression mode, thereby improving the cache compression rate. If the application program subsequently writes the task data to the fourth memory page, the task data will be written to the cache data of the fourth memory page in the cache to overwrite part or all of the first data in the cache data. When the cache data of the fourth memory page is subsequently eliminated back to the fourth memory page, if the cache data of the fourth memory page still has the first data, the cache data is easier to match the cache compression mode, thereby improving the cache compression rate.

[0152] The above describes the method of the embodiment of the present application, and the following describes the device and equipment of the embodiment of the present application. It should be understood that the device and equipment described below have the same inventive concept as the above method embodiment, and can achieve the beneficial effects that can be achieved by the above method embodiment. Figures 6 to 8 Describe the apparatus and device of the embodiments of the present application. It should be understood that the technical features described in the method embodiment are also applicable to the following apparatus embodiment and device embodiment.

[0153] Figure 6 is a structural diagram of a memory page processing device provided in an embodiment of the present application, Figure 6 The device 600 shown may be an electronic device, such as a terminal, a server, or a network device, etc., and the device type of the device 600 is not limited here. Figure 6 As shown, the device 600 includes:

[0154] The running device 601 is used to allocate a first memory page to the first virtual address accessed by the application by running the operating system when a page fault interrupt is caused by the first virtual address accessed by the application. The running device 601 is a module in the device 600 that runs the operating system.

[0155] A memory filling device 602 is used to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, where the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page;

[0156] The memory management device 603 is used to access the filled first memory page based on the first virtual address.

[0157] In a possible implementation, the memory filling device 602 is further used to:

[0158] In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

[0159] In a possible implementation, the memory filling device 602 is further used to:

[0160] The memory filling device periodically enables the memory pre-filling function for the application based on the running status of the application, otherwise, the step of enabling the memory pre-filling function for the application is not performed.

[0161] In a possible implementation, the memory filling device 602 is further used to:

[0162] In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

[0163] In a possible implementation, the memory management device 603 is used to:

[0164] receiving a first write request from the application, wherein the first write request indicates writing second data to the first virtual address;

[0165] The first data at a position corresponding to the first virtual address in the first memory page is updated to the second data.

[0166] In a possible implementation, the plurality of second memory pages are all used to store task data of a same computing task of the application, the plurality of second memory pages are all filled with the first data, and the memory management device 603 is further used to:

[0167] receiving a second write request from the application, wherein the second write request indicates writing the task data to a second virtual address;

[0168] The first data at the position corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

[0169] In a possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest occurrence frequency in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0170] In a possible implementation, the first data is S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0171] When the device 600 processes a memory page, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device 600 is divided into different functional modules to complete all or part of the functions described above. In addition, the device 600 provided in the above embodiment and the above method embodiment belong to the same concept, and the specific implementation process is detailed in the above method embodiment, which will not be repeated here.

[0172] Figure 7 is a schematic diagram of the structure of a memory filling device provided in an embodiment of the present application, such as Figure 7 As shown, the apparatus 700 includes:

[0173] An acquisition unit 701 is used to acquire an allocation notification message, where the allocation notification message is used to notify that a first memory page has been allocated to a first virtual address for a page fault interrupt caused by an application accessing a first virtual address;

[0174] The filling unit 702 is used to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page.

[0175] In a possible implementation, the filling unit 702 is further configured to:

[0176] In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

[0177] In a possible implementation manner, the apparatus 700 further includes:

[0178] An enabling unit is used to periodically enable the memory pre-filling function for the application based on the running status of the application.

[0179] In a possible implementation manner, the apparatus 700 further includes:

[0180] An enabling unit is used to enable the memory pre-filling function for the application when the type of the application is a target type, and the target type of application is suitable for the cache compression mode.

[0181] The opening unit involved in the above two implementations may be a judgment unit in the memory filling device introduced in the above embodiments.

[0182] In a possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest occurrence frequency in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0183] In a possible implementation, the first data is S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0184] It should be understood that when the device 700 processes memory pages, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device 700 is divided into different functional modules to complete all or part of the functions described above. In addition, the device 700 provided in the above embodiment and the above method embodiment belong to the same concept, and the specific implementation process is detailed in the above method embodiment, which will not be repeated here.

[0185] Figure 8 is a schematic diagram of the structure of another memory filling device provided in an embodiment of the present application, such as Figure 8 As shown, the memory filling device 800 includes: a bus 802, a processor 804, a memory 806 and a communication interface 808. The processor 804, the memory 806 and the communication interface 808 communicate with each other through the bus 802. The memory filling device 800 can be a server or a client. It should be understood that the present application does not limit the number of processors and memories in the memory filling device 800. The bus 802 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8Only one line is used to represent it, but it does not mean that there is only one bus or one type of bus. Bus 802 may include a path for transmitting information between various components of memory filling device 800 (for example, memory 806, processor 804, communication interface 808). Processor 804 may include any one or more of processors such as central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP) or digital signal processor (DSP). Memory 806 may include volatile memory (volatile memory), such as random access memory (RAM). Memory 806 may also include non-volatile memory (non-volatile memory), such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid state drive (SSD). Executable program code is stored in memory 806, and processor 804 executes the executable program code so that memory filling device 800 implements the method for processing memory pages. In a possible implementation, the memory filling device 800 is a chip.

[0186] In an exemplary embodiment, an electronic device is also provided, which includes a processor, and the processor is used to execute program code so that the electronic device executes operations performed by a method for processing memory pages applied to the electronic device. Exemplarily, the hardware structure of the electronic device can refer to the memory filling device 800. The difference from the memory filling device 800 is that the program code stored in the memory in the electronic device is used to implement the method for processing memory pages applied to the electronic device.

[0187] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including a program code, and the program code can be executed by a processor of the memory filling device 800 to complete the memory page processing method in the above embodiment. Alternatively, the program code is executed by a processor of an electronic device to complete the memory page processing method applied to the electronic device in the above embodiment. For example, the computer-readable storage medium is a non-temporary computer-readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0188] The embodiment of the present application also provides a computer program product or computer program, which includes a program code, the computer instruction is stored in a computer-readable storage medium, the processor of the memory filling device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the memory filling device executes the memory page processing method in the above embodiment. Alternatively, the processor of the electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the electronic device executes the memory page processing method in the above embodiment.

[0189] Among them, the device, equipment, computer-readable storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0190] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0191] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0192] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0193] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0194] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" means one or more, and "plurality" means two or more. The words "first", "second", etc. do not limit the quantity and execution order, and the words "first", "second", etc. do not limit them to be different.

[0195] In this application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the related concepts in a concrete way.

[0196] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the data written to the memory page involved in this application is obtained with full authorization.

[0197] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0198] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for processing a memory page, characterized in that: The method comprises: In the case where a first virtual address accessed by the application causes a page fault interrupt, allocating a first memory page to the first virtual address; Filling the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, where the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page; Based on the first virtual address, the filled first memory page is accessed.

2. The method according to claim 1, characterized in that: Filling the first data in the first memory page includes: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

3. The method according to claim 2, characterized in that In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: Based on the running status of the application, the memory pre-filling function is periodically enabled for the application.

4. The method according to claim 2, characterized in that: In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

5. The method according to any one of claims 1 to 4, characterized in that The accessing the filled first memory page based on the first virtual address includes: receiving a first write request from the application, wherein the first write request indicates writing second data to the first virtual address; The first data at a position corresponding to the first virtual address in the first memory page is updated to the second data.

6. The method according to claims 1-5, characterized in that: The plurality of second memory pages are all used to store task data of a same computing task of the application program, the plurality of second memory pages are all filled with the first data, and the method further includes: receiving a second write request from the application, wherein the second write request indicates writing the task data to a second virtual address; The first data at the position corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

7. The method according to any one of claims 1 to 6, characterized in that The first data are each data in the data sequence; Alternatively, the first data is S data with the highest occurrence frequency in the data sequence, and S is greater than 0; Alternatively, the first data is R consecutive data in the data sequence, where R is greater than 0.

8. The method according to any one of claims 1 to 6, characterized in that The first data is S data with the highest occurrence frequency in a plurality of data sequences, the plurality of data sequences correspond to different cache compression modes, and S is greater than 0; Alternatively, the first data is data common to the multiple data sequences.

9. A method for processing a memory page, characterized in that: The method comprises: Acquire an allocation notification message, where the allocation notification message is used to notify a page fault interrupt caused by an application accessing a first virtual address, and a first memory page has been allocated to the first virtual address; The first memory page is filled with first data, where the first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page.

10. The method according to claim 9, characterized in that Filling the first data in the first memory page includes: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

11. The method according to claim 10, characterized in that In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: Based on the running status of the application, the memory pre-filling function is periodically enabled for the application.

12. The method according to claim 10, characterized in that In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

13. A memory page processing device, characterized in that: The device comprises: An operating device, configured to allocate a first memory page to a first virtual address accessed by an application program by running an operating system when a page fault interrupt is induced by the first virtual address accessed by the application program; A memory filling device, used to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, where the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page; A memory management device is used to access the filled first memory page based on the first virtual address.

14. The device according to claim 13, characterized in that The memory filling device is also used for: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

15. The device according to claim 14, characterized in that The memory filling device is also used for: Based on the running status of the application, the memory pre-filling function is periodically enabled for the application.

16. The device according to claim 14, characterized in that The memory filling device is also used for: In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

17. The device according to any one of claims 13 to 16, characterized in that The memory management device is used for: receiving a first write request from the application, wherein the first write request indicates writing second data to the first virtual address; The first data at a position corresponding to the first virtual address in the first memory page is updated to the second data.

18. The device according to claims 13-17, characterized in that The plurality of second memory pages are all used to store task data of a same computing task of the application program, the plurality of second memory pages are all filled with the first data, and the memory management device is further used to: receiving a second write request from the application, wherein the second write request indicates writing the task data to a second virtual address; The first data at the position corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

19. The device according to any one of claims 13 to 18, characterized in that The first data are each data in the data sequence; Alternatively, the first data is S data with the highest occurrence frequency in the data sequence, and S is greater than 0; Alternatively, the first data is R consecutive data in the data sequence, R is greater than 0, and the first data is a hexadecimal value 0 or a value F.

20. The device according to any one of claims 13 to 18, characterized in that The first data is S data with the highest occurrence frequency in a plurality of data sequences, the plurality of data sequences correspond to different cache compression modes, and S is greater than 0; Alternatively, the first data is data common to the multiple data sequences.

21. A memory filling device, characterized in that: The device comprises: an acquisition unit, configured to acquire an allocation notification message, wherein the allocation notification message is used to notify that a first memory page has been allocated to a first virtual address for a page fault interrupt caused by an application accessing a first virtual address; A filling unit is used to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page.

22. The device according to claim 21, characterized in that The filling unit is also used for: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

23. An electronic device, characterized in that: The electronic device comprises a processor, and the processor is used to execute program code, so that the electronic device performs the method according to any one of claims 1 to 8.

24. A memory filling device, characterized in that: The memory filling device comprises a processor, and the processor is used to execute program code, so that the memory filling device performs the method according to any one of claims 9 to claim 12.

25. A computer-readable storage medium, characterized in that: At least one program code is stored in the storage medium, and the at least one program code is read by a processor to execute the method according to any one of claims 1 to 12.

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