Bus circuit, chip and control method

Abstract

The embodiment of the invention provides a bus circuit, a chip and a control method, and relates to the technical field of integrated circuits. A data transmitting unit in the bus circuit is used for transmitting test data to a data receiving unit at a first sampling edge of a first clock signal. And the data receiving unit is used for sampling the data transmitted by the data transmitting unit at the second sampling edge of the second clock signal and transmitting the received data to the receiving end control unit. The receiving end control unit is used for shortening the interval duration between the second sampling edge and the first sampling edge under the condition that the data received from the data receiving unit is the same as the test data, and controlling the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal; and the receiving end control unit is also used for determining the target sampling duration under the condition that the data received from the data receiving unit is different from the test data. According to the invention, the stability of data transmission on the bus is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a bus circuit, a chip and a control method. Background Art

[0002] With the development of integrated circuits, the functional integration of chips has gradually increased, and the scale of chips has become larger and larger. The bus is the main communication trunk for transmitting data between various functional components in the chip. For example, the bus is a common channel for the processor, memory, input / output devices and other components in the chip to transmit data. The bus is generally implemented in the form of a synchronous circuit. The access end, output end, and relay end of the bus all send / receive data under the same clock signal.

[0003] However, as the requirements for bus transmission frequency increase and the bus transmission distance increases, it is often difficult for buses with longer distances to maintain a higher bus transmission frequency. The bus needs to be segmented between the access end and the output end by adding pipeline stages to ensure that each segment of the bus can meet the bus transmission frequency requirements. However, the latches introduced by adding pipeline stages will introduce additional delays to the bus. For example, the device transmission delay of the latch, the delay introduced by the control deviation of the clock signal on the latch, etc.

[0004] Moreover, in order to ensure the bus transmission performance, the bus also needs to be split into multiple bus segments by the buffer. That is, a buffer is inserted at every interval on the bus to use the buffer to adjust the performance of the signal transmitted by the bus. Therefore, the bus delay also comes from the device transmission delay introduced by the buffer. In addition, the bus delay also includes the interconnection delay. There will be parasitic resistance and parasitic capacitance between the interconnections between the buffers. Parasitic resistance and parasitic capacitance will cause transmission delay for the signal propagating on the interconnection. In particular, with the improvement of integrated circuit manufacturing technology, the size of integrated circuits has gradually decreased, resulting in a decrease in the physical size of the interconnection and the physical distance between the interconnections, an increase in the coupling effect between the interconnections, and an increase in the parasitic capacitance generated by the coupling, which aggravates the crosstalk between the interconnections and increases the interconnection delay. Of course, the bus delay also comes from other factors such as the bus manufacturing process deviation.

[0005] Thus, since the causes of bus delay are complex, when using static timing analysis to predict bus delay during the chip design phase, it is necessary to introduce conservative amounts under various delay causes, which reduces the prediction accuracy and increases the error probability of data transmission based on the predicted delay. Summary of the invention

[0006] In view of the above problems, embodiments of the present invention are proposed to provide a bus circuit, chip and control method that overcome the above problems or at least partially solve the above problems, so as to solve the problem of low accuracy of current bus delay prediction.

[0007] In order to solve the above problems, an embodiment of the present invention discloses a bus circuit, which includes: a data sending unit, a data receiving unit, and a receiving end control unit;

[0008] The data sending unit is connected to the data receiving unit, and the data sending unit is used to transmit the test data to the data receiving unit at a first sampling edge of the first clock signal;

[0009] The data receiving unit is also connected to the receiving end control unit, and the data receiving unit is used to sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit, the first clock signal and the second clock signal are synchronous clock signals, and there is an interval time between the second sampling edge and the first sampling edge;

[0010] The receiving end control unit is used for shortening the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, and controlling the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal;

[0011] The receiving end control unit is also used to determine a target sampling duration when the data received from the data receiving unit is different from the test data. The target sampling duration is used for the data receiving unit to delay the data sampling start time of the data sending unit by at least the target sampling duration to sample the data transmitted by the data sending unit. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

[0012] An embodiment of the present invention further discloses a chip, which includes: any of the above-mentioned bus circuits.

[0013] An embodiment of the present invention further discloses a method for controlling a bus circuit, which is applied to any of the above bus circuits or any of the above chips, and the method includes:

[0014] transmitting the test data to the data receiving unit through the data sending unit at the first sampling edge of the first clock signal;

[0015] The data receiving unit samples the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit.

[0016] When the data received from the data receiving unit is the same as the test data, the receiving end control unit shortens the interval between the second sampling edge and the first sampling edge, and controls the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal;

[0017] The receiving end control unit determines a target sampling duration when the data received from the data receiving unit is different from the test data. The target sampling duration is used for the data receiving unit to delay the data sampling start time of the data sending unit by at least the target sampling duration to sample the data transmitted by the data sending unit. The target sampling duration is the shortest interval duration between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

[0018] The embodiments of the present invention include the following advantages:

[0019] In an embodiment of the present invention, the bus circuit includes: a data sending unit, a data receiving unit, and a receiving end control unit. The data sending unit is used to transmit test data to the data receiving unit at the first sampling edge of the first clock signal. The data receiving unit is used to sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit. The receiving end control unit is used to shorten the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, and control the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal; and is also used to determine the target sampling duration when the data received from the data receiving unit is different from the test data, so that the data receiving unit samples the data transmitted by the data sending unit at least after the data sampling start time of the data sending unit. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

[0020] In this technical solution, by adjusting the relative sampling duration between the data sending unit and the data receiving unit (i.e., the interval duration between the second sampling edge and the first sampling edge), and comparing whether the data sampled by the data receiving unit is the same as the test data sent by the data sending unit, the shortest duration (i.e., the target sampling duration) for the data receiving unit to sample the test data correctly is determined according to the comparison result, thereby realizing adaptive delay detection of the bus connecting the data sending unit and the data receiving unit. Compared with the bus delay prediction solution in the chip design stage in the related art, the technical solution of this application directly performs bus delay detection on the bus circuit in actual use, which can guarantee the accuracy of the detected bus delay to a certain extent, thereby improving the stability of data transmission on the bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A structural diagram of a bus circuit in the related art is shown;

[0022] Figure 2 A circuit timing diagram of a bus circuit in the related art is shown;

[0023] Figure 3 A circuit timing diagram of another bus circuit in the related art is shown;

[0024] Figure 4 A structural diagram of a bus circuit in an embodiment of the present invention is shown;

[0025] Figure 5 A structural diagram of another bus circuit in an embodiment of the present invention is shown;

[0026] Figure 6 A flow chart showing a method for controlling a bus circuit in an embodiment of the present invention is shown;

[0027] Figure 7 A flow chart showing another method for controlling a bus circuit in an embodiment of the present invention is shown;

[0028] Figure 8 A structural block diagram of an electronic device in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] In order to facilitate understanding of the technical solution provided by the present application, the following gives priority to explaining the improvement principle of the bus circuit provided in the embodiment of the present application.

[0031] Please refer to Figure 1, which shows a transmission structure diagram of a bus circuit provided by the related art. Figure 1 As shown, the bus circuit 100 includes: a data sending unit 101 , a relay transmission unit 102 and a data receiving unit 103 .

[0032] Among them, the data sending unit is also called the data sending end, the relay transmission unit is also called the data relay end, and the data receiving unit is also called the data receiving end. The data sending unit 101 and the data receiving unit 103 are connected through a bus. The bus includes a plurality of bus segments connected through the relay transmission unit 102. It should be noted that, when the number of the relay transmission unit 102 is 1, the bus connecting the data sending unit 101 and the data receiving unit 103 includes two bus segments. One of the two bus segments is connected to the data sending unit 101 and the relay transmission unit 102 respectively; the other bus segment is connected to the relay transmission unit 102 and the data receiving unit 103 respectively.

[0033] Of course, under normal circumstances, the number of relay transmission units corresponding to one bus is multiple, so that the data sending unit 101 and the data receiving unit 103 are connected through multi-stage relay transmission units. Obviously, the more relay transmission units corresponding to one bus, the greater the delay of the bus. In the case where the data of the relay transmission unit 102 is n, the bus connecting the data sending unit 101 and the data receiving unit 103 includes n+1 bus segments. Among them, n is a positive integer greater than 1. The data sending unit 101 and the relay transmission unit 102, the two relay transmission units 102, and the relay transmission unit 102 and the data receiving unit 103 are all connected through bus segments.

[0034] In the bus circuit, the data sending unit 101, the relay transmission unit 102 and the data receiving unit 103 sample data under the control of the same clock signal CLK. In this way, the data transmitted in the bus circuit is transmitted to the next level beat by beat under the unified control of the clock signal.

[0035] For example, it is taken that the data sending unit 101 and the data receiving unit 103 are connected via a relay transmission unit 102. Figure 2 , which shows a circuit timing diagram of a bus circuit in the related art. Among them, FF1 represents the data sending unit 101, FF2 represents the relay transmission unit 102, and FF3 represents the data receiving unit 103. Figure 2As shown, the data sending unit FF1, the relay transmission unit FF2, and the data receiving unit FF3 sample data D0, data D1, data D2...data Dn in turn under the control of the clock signal CLK. Among them, the data sampling edges of the data sending unit FF1, the relay transmission unit FF2, and the data receiving unit FF3 are all the rising edges of the clock signal CLK. The data sending unit FF1 samples data D0, data D1, data D2...data Dn at the second rising edge of the clock signal CLK. The relay transmission unit FF2 samples data D0, data D1, data D2...data Dn at the third rising edge of the clock signal CLK. The data receiving unit FF3 samples data D0, data D1, data D2...data Dn at the fourth rising edge of the clock signal CLK. It is not difficult to see that the data receiving unit FF3 samples data with a delay of two clock cycles compared to the data sending unit FF1. That is, there is a delay of two clock cycles in the data from the data sending unit FF1 to the data receiving unit FF3.

[0036] It can be seen from this that the valid sampling edge of the receiving end of the data receiving unit is: the data sampling edge on the clock signal that is two clock cycles later than the starting data sampling edge of the data sending unit 101. In this way, if the data receiving unit is set to perform data sampling only at the valid sampling edge of the receiving end, the validity of the sampled data can be effectively guaranteed.

[0037] Continue with Figure 2 Taking the example shown as an example, the effective sampling edge of the receiving end of the data receiving unit is the fourth clock rising edge of the clock signal CLK. The data receiving unit 103 is set to perform data sampling only on the fourth clock rising edge of the clock signal CLK. Please refer to Figure 3 , which shows a circuit timing diagram of a bus circuit provided with a valid sampling edge of the receiving end of the data receiving unit 103. Figure 3 As shown, the data sending unit FF1 samples data D0, data D1, data D2...data Dn at the second clock rising edge of the clock signal CLK1. The data receiving unit FF3 samples data D0, data D1, data D2...data Dn at the first clock rising edge of the clock signal CLK3 (i.e., the effective sampling edge at the receiving end). Among them, the clock signal CLK1 and the clock signal CLK3 are synchronous clock signals, and the first clock rising edge of the clock signal CLK3 is two clock cycles later than the second clock rising edge of the clock signal CLK1.

[0038] Furthermore, after the bus circuit design is completed, that is, after the physical distance from the data sending unit to the data receiving unit in the bus circuit, the insertion design of the relay transmission unit (such as a relay buffer) and the physical connection are completed, the signal delay from the data sending unit to the data receiving unit on the bus circuit is usually a fixed value. In this way, by testing the delay of the data from the data sending unit to the data receiving unit during actual use of the bus circuit, the effective sampling edge of the receiving end of the data receiving unit is set, so that the data receiving unit samples the data transmitted from the data sending unit at the effective sampling edge of the receiving end, thereby ensuring the validity of the data sampled by the data receiving unit and the correctness of the bus function. The bus circuit provided in the embodiment of the present application works on this principle.

[0039] Please refer to Figure 4 , which shows a schematic diagram of the structure of a bus circuit provided by an embodiment of the present application. Figure 4 As shown, the bus circuit 400 includes: a data sending unit 401, a data receiving unit 402, and a receiving end control unit 403.

[0040] The data sending unit 401 is connected to the data receiving unit 402 via a bus. The data sending unit 401 is used to transmit the test data to the data receiving unit 402 at the first sampling edge of the first clock signal.

[0041] The data receiving unit 402 is also connected to the receiving end control unit 403. The data receiving unit 402 is used to sample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit 403.

[0042] Among them, the first clock signal and the second clock signal are synchronous clock signals, and there is an interval time between the second sampling edge and the first sampling edge. In an optional implementation, the first clock signal and the second clock signal can be the same clock signal. The data sending unit 401 and the data receiving unit 402 can receive the same clock signal transmitted by the same clock source. In another optional implementation, the first clock signal and the second clock signal can be clock signals from different sources but with the same frequency and phase. The data sending unit 401 and the data receiving unit 402 can receive clock signals from different clock sources. Further optionally, the initial interval time between the second sampling edge and the first sampling edge can be the maximum preset delay between the data sending unit and the data receiving unit to avoid the data receiving unit failing to sample the test data and ensure the accuracy of the subsequent target sampling time.

[0043] The receiving end control unit 403 is used to shorten the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit 402 is the same as the test data, and control the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge of the first clock signal.

[0044] The receiving end control unit 403 is also used to determine the target sampling duration when the data received from the data receiving unit 402 is different from the test data. The target sampling duration is used for the data receiving unit 402 to delay the data sampling start time of the data sending unit 401 by at least the target sampling duration to sample the data transmitted by the data sending unit 401. The target sampling duration is the shortest interval duration between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit 402 is the same as the test data.

[0045] In the embodiment of the present application, the receiving end control unit 403 is used to receive the data sampled by the data receiving unit 402, and compare the received data with the test data. In the case where the data received from the data receiving unit 402 is the same as the test data, it means that the receiving end control unit 403 has sampled the test data, and the interval between the current first sampling edge and the second sampling edge is at least equal to (i.e., greater than or equal to) the actual signal delay between the data sending unit 401 and the data receiving unit 402. In this case, the receiving end control unit 403 shortens the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402, and controls the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge of the first clock signal, so that the data receiving unit 402 restarts to sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal.

[0046] In the case where the data received from the data receiving unit 402 is different from the test data, it means that the receiving end control unit 403 may not sample the test data, and the interval between the current first sampling edge and the second sampling edge is less than the actual signal delay between the data sending unit 401 and the data receiving unit 402. The receiving end control unit 403 can determine a target sampling duration, so that the data receiving unit 402 subsequently delays the data sampling start time of the data sending unit 401 by at least the target sampling duration, and samples the data transmitted by the data sending unit 401.

[0047] In an optional implementation, the bus circuit may have an adaptive training mode and a normal working mode. When the bus circuit is in the adaptive training mode, the training process may be performed m times until the target sampling time length of the data receiving unit 402 is determined, where m is a positive integer. The yth training process includes:

[0048] The data sending unit 401 transmits the test data to the data receiving unit 402 at the first sampling edge of the first clock signal for the yth time. The data receiving unit 402 samples the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal for the ith time, and transmits the received data to the receiving end control unit 403.

[0049] When the receiving end control unit 403 determines that the data received from the data receiving unit 402 for the yth time is the same as the test data, it shortens the interval between the second sampling edge and the first sampling edge, and controls the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge of the first clock signal, so that the bus circuit enters the y+1th training process.

[0050] When determining that the data received from the data receiving unit 402 for the yth time is different from the test data, the receiving end control unit 403 determines the interval between the second sampling edge and the first sampling edge in the y-1th training process as the target sampling duration, where y is a positive integer less than or equal to m.

[0051] When the bus circuit is in normal working mode, the data sending unit 401 transmits data to the data receiving unit 402 under the control of the third clock signal. The data receiving unit samples the data transmitted by the data sending unit 401 after delaying the target sampling time under the control of the third clock signal. The third clock signal is a synchronous clock signal with the first clock signal and the second clock signal.

[0052] In another optional implementation, when the bus circuit 400 is in a normal working mode, as an example, the bus circuit 400 may send an enable signal to the data receiving unit 402 when the data sending unit 401 sends actual data to the data receiving unit 402. When the data receiving unit 402 receives the enable signal, it starts timing and starts sampling the actual data transmitted from the data sending unit 401 after the target sampling time.

[0053] In another example, the bus circuit 400 may send the data sampling start time of the data sending unit to the data receiving unit 402 when the data sending unit 401 sends actual data to the data receiving unit 402. The data receiving unit 402 calculates the data sampling time of the data receiving unit 402 according to the data sampling start time and the target sampling duration. The data receiving unit 402 samples the data transmitted from the data sending unit 401 at the data sampling time.

[0054] In summary, the bus circuit provided by the embodiment of the present application includes: a data sending unit, a data receiving unit, and a receiving end control unit. The data sending unit is used to transmit test data to the data receiving unit at the first sampling edge of the first clock signal. The data receiving unit is used to sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit. The receiving end control unit is used to shorten the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, and control the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal; and is also used to determine the target sampling duration when the data received from the data receiving unit is different from the test data, so that the data receiving unit delays the data transmitted by the data sending unit by at least the target sampling duration compared to the data sampling start time of the data sending unit. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

[0055] In this technical solution, by adjusting the relative sampling duration between the data sending unit and the data receiving unit (i.e., the interval duration between the second sampling edge and the first sampling edge), and comparing whether the data sampled by the data receiving unit is the same as the test data sent by the data sending unit, the shortest duration (i.e., the target sampling duration) for the data receiving unit to sample the test data correctly is determined according to the comparison result, thereby realizing adaptive delay detection of the bus connecting the data sending unit and the data receiving unit. Compared with the bus delay prediction solution in the chip design stage in the related art, the technical solution of this application directly performs bus delay detection on the bus circuit in actual use, which can guarantee the accuracy of the detected bus delay to a certain extent, thereby improving the stability of data transmission on the bus.

[0056] In the embodiment of the present application, the data sending unit 401 is used to transmit the test data to the data receiving unit 402 at the first sampling edge of the first clock signal.

[0057] Optionally, the data sending unit 401 is used to transmit the test data to the data receiving unit at the first sampling edge of the first clock signal according to the acquired first indication data. The first indication data is used to indicate the first sampling edge of the first clock signal. Optionally, the first indication data indicates the order of the first sampling edge in the first clock signal. In one example, the first indication data indicates that the first sampling edge is the jth sampling edge of the first clock signal. In another example, the first indication data indicates that the first sampling edge is the x×jth sampling edge of the first clock signal. Both j and x are positive integers greater than 1.

[0058] In an optional case, the data sending unit 401 stores the first indication data. After the bus circuit 400 enters the adaptive training mode, the data sending unit 401 obtains the first indication data stored therein, determines the first sampling edge, and transmits the test data to the data receiving unit at the first sampling edge of the first clock.

[0059] In another alternative case, if Figure 5 As shown, the bus circuit 400 further includes: a transmitting end control unit 404. The transmitting end control unit 404 is connected to the data transmitting unit 401. The transmitting end control unit 404 is used to transmit the first indication data to the data transmitting unit 401, so that the data transmitting unit 401 transmits the test data to the data receiving unit at the first sampling edge of the first clock.

[0060] Further optionally, the data sending unit 401 includes: a data sending module and a second counting module.

[0061] The data sending module and the second counting module synchronously receive the first clock signal. The second counting module is used to count the second number of sampling edges of the first clock signal and transmit the second number to the data sending module.

[0062] The data sending module is used for determining that the first sampling edge is reached when the second quantity indicates the order indicated by the first indication data, and transmitting the test data to the data receiving unit 402 .

[0063] In one example, the first indication information indicates that the first sampling edge is the third sampling edge of the first clock signal. The second counting module counts the second number of sampling edges of the first clock signal it receives, and transmits the second number to the data sending module. When the second number is 3, the data sending module determines that the first sampling edge is reached, and transmits the test data to the data receiving unit 402.

[0064] In another example, the first indication information indicates that the first sampling edge is the 3jth sampling edge of the first clock signal. The second counting module counts the second number of sampling edges of the first clock signal it receives, and transmits the second number to the data sending module. When the second number is an integer multiple of 3, the data sending module determines that the first sampling edge is reached, and transmits the test data to the data receiving unit 402.

[0065] It should be noted that the first clock signal received by the data sending unit 401 may be received after the bus circuit 400 is powered on. Alternatively, the first clock signal received by the data sending unit 401 may also be transmitted by the transmitting end control unit 404 to the data sending unit 401 after the bus circuit 400 performs the adaptive training mode.

[0066] In the embodiment of the present application, the data receiving unit 402 is used to sample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit 403.

[0067] The receiving end control unit 403 is used to shorten the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit 402 is the same as the test data, and control the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge of the first clock signal.

[0068] Optionally, the receiving end control unit 403 is used to determine the second indication data according to the initial interval duration and the first indication data before receiving the data transmitted from the data receiving unit 402, and transmit the second indication data to the data receiving unit 402.

[0069] The second indication data indicates the second sampling edge. Optionally, the initial interval duration can be the maximum preset delay of data from the data sending unit to the data receiving unit to avoid the data receiving unit failing to sample the training data, thereby ensuring the accuracy of the subsequent target sampling duration. Further optionally, the second indication data indicates the order of the second sampling edge in the second clock signal. For example, the second indication data indicates that the second sampling edge is the p-th sampling edge of the second clock signal, where p is a positive integer greater than 1.

[0070] The receiving end control unit 403 is also used to shorten the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402 when the data received from the data receiving unit 402 is the same as the test data, obtain updated second indication data, transmit the updated second indication data to the data receiving unit 402, and control the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal.

[0071] The data receiving unit 402 is further configured to determine, based on the second indication data, when the second sampling edge of the second clock signal arrives, to start sampling the data transmitted by the data sending unit 401 .

[0072] In an optional case, the receiving end control unit 403 is used to obtain the first indication data and the initial interval duration, calculate the second indication data, and transmit the second indication data to the data receiving unit 402 after the bus circuit 400 enters the adaptive training mode.

[0073] The first indication data may be the data stored therein. Alternatively, the receiving end control unit 403 is also connected to the sending end control unit 404. The first indication data may also be transmitted from the sending end control unit 404 to the receiving end control unit 403.

[0074] For example, the first indication data indicates that the first sampling edge is the jth sampling edge of the first clock signal. The first clock signal and the second clock signal are synchronous clock signals, and the first indication data also indicates that the synchronous sampling edge of the first sampling edge on the second clock signal is the kth sampling edge of the second clock signal.

[0075] Wherein, if the first clock signal and the second clock signal are the same clock signal, then k=j. If the starting time of the first clock signal being transmitted to the data sending unit is different from the starting time of the second clock signal being transmitted to the data receiving unit, then k=j+a, where a is the number of sampling cycles corresponding to the transmission time difference between the first clock signal and the second clock signal. For example, if the second clock signal is generated two sampling cycles later than the first clock signal, then a is -2.

[0076] If the sampling period is a clock period, and the initial interval duration is 3 sampling periods, the second sampling edge of the second clock signal indicated by the second indication data is the k+3th sampling edge. In this case, the data sending unit 401 transmits the test data to the data receiving unit 402 at the jth sampling edge of the first clock signal. The data receiving unit 402 starts sampling the data transmitted by the data sending unit 401 at the k+3th sampling edge of the second clock signal.

[0077] Further optionally, the data receiving unit 402 includes: a data receiving module and a first counting module.

[0078] The data receiving module and the first counting module synchronously receive the second clock signal. The first counting module is used to count the first number of sampling edges of the second clock signal and transmit the first number to the data receiving module.

[0079] The data receiving module is used for determining that the second sampling edge has arrived when the first quantity indicates the order of the second quantity indication data indication, and starting to sample the data transmitted by the data sending unit 401 .

[0080] For example, assuming that the initial interval duration is 3 clock cycles, the second indication information indicates that the second sampling edge is the 3+3rd sampling edge of the second clock signal. The first counting module counts the first number of sampling edges of the second clock signal it receives, and transmits the first number to the data receiving module. When the first number is 6, the data receiving module determines that the second sampling edge is reached, and samples the data transmitted by the data sending unit 401.

[0081] As mentioned above, the receiving end control unit 403 can also be used to shorten the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402 when the data received from the data receiving unit 402 is the same as the test data, obtain updated second indication data, transmit the updated second indication data to the data receiving unit 402, and control the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal.

[0082] In an optional case, the receiving end control unit 403 is also used to shorten the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402 when the data received from the data receiving unit 402 is the same as the test data, and determine the shortened interval duration. According to the first indication data and the shortened interval duration, the second indication data is updated to obtain the updated second indication data. It should be noted that the implementation process of updating the second indication data according to the first indication data and the shortened interval duration can refer to the aforementioned implementation process of determining the second indication data according to the initial interval duration and the first indication data, which will not be described in detail.

[0083] Optionally, the receiving end control unit 403 can shorten the interval duration by a target value each time. The target value can be a fixed value, or the target value is inversely proportional to the number of shortenings. In this way, since the data received from the data receiving unit 402 is the same as the test data, it can be shown that the interval duration between the current first sampling edge and the second sampling edge is at least equal to the actual signal delay between the data sending unit 401 and the data receiving unit 402. Therefore, as the number of times the receiving end control unit 403 needs to shorten the interval duration increases, the shortening amount of the interval duration each time gradually decreases, and the interval duration between the first sampling edge and the second sampling edge can be accurately made closer to the actual signal delay. Obviously, the closer the interval duration between the first sampling edge and the second sampling edge is to the actual signal delay, the higher the accuracy of the determined target sampling duration.

[0084] Correspondingly, the data receiving unit 402 is further configured to determine, according to the updated second indication data, when the second sampling edge of the second clock signal arrives, to start sampling the data transmitted by the data sending unit 401 .

[0085] It should be noted that the second clock signal received by the data receiving unit 402 may be received after the bus circuit 400 is powered on. Alternatively, the second clock signal received by the data receiving unit 402 may also be transmitted by the receiving end control unit 403 to the data receiving unit 402 after the bus circuit 400 performs the adaptive training mode.

[0086] In some embodiments of the present application, the bus circuit 400 further includes: a general control unit and a transmitting end control unit 404. The general control unit is connected to the transmitting end control unit 404 and the receiving end control unit 403 respectively.

[0087] The general control unit is used to synchronously transmit a first test signal to the transmitting end control unit 404 and the receiving end control unit 403. The first test signal is generated at least after each startup of the chip where the bus circuit 400 is located and / or after the operating frequency of the chip is changed. Optionally, the first test signal indicates that the bus circuit enters an adaptive training mode.

[0088] The transmitting end control unit 404 is used to transmit test data and a first clock signal to the data transmitting unit 401 when receiving the first test signal, and control the data transmitting unit 401 to transmit the test data to the data receiving unit 402 at the first sampling edge.

[0089] The receiving end control unit 403 is further configured to transmit a second clock signal to the data receiving unit 402 when receiving the first test signal, and control the data receiving unit 402 to sample the data transmitted by the data sending unit 401 at the second sampling edge.

[0090] Optionally, the data receiving unit 402 includes a data receiving module and a first counting module. The receiving end control unit 403 is further configured to synchronously transmit a second clock signal to the data receiving module and the first counting module when receiving the first test signal, so that the first counting module starts to count the first number of sampling edges of the second clock signal, thereby controlling the data receiving unit 402 to sample data at the second sampling edge of the second clock signal.

[0091] It is easy to understand that the receiving end control unit 403 can control the data receiving unit 402 to start sampling data at the second sampling edge of the second clock signal by controlling the first counting module to start counting the sampling edge of the second clock signal.

[0092] In addition, the receiving end control unit 403 is also used to shorten the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402 when the data received from the data receiving unit 402 is the same as the test data, and control the data sending unit 401 through the sending end control unit 404 to transmit the test data to the data receiving unit 402 again at the first sampling edge of the first clock signal. Accordingly, the receiving end control unit 403 controls the data receiving unit 402 to sample the data transmitted by the data sending unit 401 at the second sampling edge again. Optionally, the receiving end control unit 403 can control the first counting module to reset the count, and restart counting the first number of sampling edges of the second clock signal, so as to control the data receiving unit 402 to start sampling data at the second sampling edge again.

[0093] Similarly, optionally, the data sending unit 401 includes a data sending module and a second counting module. The sending end control unit 404 is also used to transmit test data to the data sending module when receiving the first test signal, and synchronously transmit the first clock signal to the data sending module and the second counting module, so that the second counting module starts to count the second number of sampling edges of the first clock signal, so as to achieve the purpose of controlling the data sending unit 401 to transmit test data to the data receiving unit 402.

[0094] It is not difficult to understand that the transmitting end control unit 404 can control the start time of the data transmitting unit 401 transmitting the test data by controlling the second counting module to start counting the sampling edge of the first clock signal. For example, the transmitting end control unit 404 can control the second counting module to reset the count and restart counting the second number of the sampling edges of the first clock signal to control the data transmitting unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge of the first clock signal.

[0095] Further optionally, the general control unit is further configured to synchronously transmit a second test signal to the transmitting end control unit 404 and the receiving end control unit 403 after transmitting the first test signal to the transmitting end control unit 404. In this case, the first test signal is used to instruct the bus circuit to enter the adaptive training mode. The second test signal is used to trigger the transmitting end control unit 404 to control the data transmitting unit 401 to start sending test data, and the receiving end control unit 403 to control the data receiving unit 402 to start sampling data at the second sampling edge of the second clock signal.

[0096] The transmitting end control unit 404 is also used to control the data sending unit 401 to transmit the test data to the data receiving unit 402 at the first sampling edge when the second test signal is received. In this way, through the two independent signals of the first test signal and the second test signal, the data sending unit 401 performs the operation of collecting test data from the transmitting end control unit 404 and the operation of sending test data to the data receiving unit 402 at intervals, that is, the data sending unit 401 first saves the test data and then sends the test data. In this way, it can be avoided that when the collection operation and the sending operation are performed synchronously, the delay introduced by the collection operation can be avoided, resulting in the target sampling duration determined by the receiving end control unit 403 including the delay introduced by the collection operation, thereby reducing the accuracy of the target sampling duration.

[0097] The receiving end control unit 403 is further used to control the data receiving unit 402 to sample the data transmitted by the data transmitting unit at the second sampling edge when the second test signal is received. That is, when the receiving end control unit 403 receives the first test signal, it transmits the second clock signal to the data receiving unit 402. When the second test signal is received, it controls the data receiving unit 402 to sample the data transmitted by the data transmitting unit at the second sampling edge.

[0098] The receiving end control unit 403 is also used to shorten the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402 when the data received from the data receiving unit 402 is the same as the test data, generate and transmit a second test signal to the transmitting end control unit 404, and control the data receiving unit 402 to sample the data transmitted by the data transmitting unit 401 at the shortened second sampling edge. It is easy to understand that the receiving end control unit 403 transmits the second test signal to the transmitting end control unit 404, so as to control the data transmitting unit 401 to transmit the test data to the data receiving unit 402 at the first sampling edge again through the transmitting end control unit 404.

[0099] It should be noted that, when the transmitting end control unit 404 receives the second test signal, the control process of controlling the data sending unit 401 to transmit the test data to the data receiving unit 402 at the first sampling edge can refer to the aforementioned process of controlling the data sending unit 401 to send data. For example, when the transmitting end control unit 404 receives the second test signal, the second counting module of the control data sending unit 401 starts counting the sampling edges, or resets the count to zero and restarts counting the sampling edges.

[0100] When the receiving end control unit 403 receives the second test signal, the control process of controlling the data receiving unit 402 to sample the data transmitted by the data sending unit 401 at the second sampling edge can refer to the aforementioned process of controlling the data receiving unit 402 to start sampling data. For example, when the receiving end control unit 403 receives the second test signal, the first counting module of the control data receiving unit 402 starts counting the sampling edges, or resets the count to zero and retries to start counting the sampling edges.

[0101] In some embodiments of the present application, the bus circuit may include multiple buses. In one case, each bus may be connected to a data receiving unit and a data sending unit.

[0102] The bus may be a unidirectional transmission line. The bus is connected to a data receiving unit and a data sending unit in the data transmission direction. The bus may also be a bidirectional transmission line. The bus is connected to a data receiving unit and a data sending unit in two data transmission directions. It is not difficult to understand that, assuming that the bus is connected to device A and device B. When device A sends data to device B, device A is the data sending unit and device B is the data receiving unit; when device B sends data to device A, device B is the data sending unit and device A is the data receiving unit.

[0103] When the bus is a bidirectional transmission line, the bus circuit can determine the target sampling duration of the data receiving unit in the two data transmission directions respectively. Alternatively, after the bus circuit determines the target sampling duration of the data receiving unit in one data transmission direction, the data receiving unit in the other data transmission direction can reuse the target sampling duration.

[0104] In another case, each bus can be connected to a data sending unit and n data receiving units. That is, the data on the bus will be transmitted in multiple stages. Of course, it can also be understood that the bus is divided into n bus segments by the data sending unit and n data receiving units. For each bus segment, one data receiving unit and one data sending unit are connected in the data transmission direction. The following is a further introduction to the bus circuit in different cases.

[0105] For the former case, the bus circuit 400 includes: a plurality of buses. Each bus is connected to a data receiving unit 402 and a data sending unit 401. The receiving end control unit 403 is connected to the data receiving unit 402 of each bus.

[0106] For each bus, the receiving end control unit 403 is used to shorten the interval between the second sampling edge and the first sampling edge of the data receiving unit 402 when the data received from the data receiving unit 402 through the bus is the same as the test data corresponding to the bus, and control the data sending unit 401 to transmit the corresponding test data to the data receiving unit 402 again at the first sampling edge.

[0107] The receiving end control unit 403 is also used to determine the target sampling duration of the bus when the data received from the data receiving unit 402 through the bus is different from the test data corresponding to the bus. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit 402 is the same as the test data. The target sampling duration is used for the data receiving unit 402 of the bus to delay the data sampling start time of the data sending unit 401 by at least the target sampling duration to sample the data transmitted by the data sending unit 401.

[0108] Optionally, when the bus circuit 400 includes a transmitting end control unit 404, each data transmitting unit 401 is connected to the transmitting end control unit 404. It should be noted that the receiving end control unit 403 and the transmitting end control unit 404 control the data receiving unit 402 and the data transmitting unit 401 of each bus in the same manner, and thus the method for determining the target acquisition duration of each bus is the same, and the foregoing description may be referred to, and the embodiments of the present application will not be described in detail herein.

[0109] In another case, the number of data receiving units 402 in one bus is n. The n data receiving units 402 are serially connected to the data sending unit 401. The receiving end control unit 403 is connected to each data receiving unit 402, and n is a positive integer greater than 2.

[0110] Each data receiving unit 402 is used to sample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit 403. The longer the connection distance to the data sending unit 401, the longer the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402.

[0111] The receiving end control unit 403 is used to set the second sampling edge corresponding to each data receiving unit 402 according to the initial interval duration and the first sampling edge; when the data received from the first data receiving unit 402 is the same as the test data, shorten the interval duration between the second sampling edge and the first sampling edge corresponding to the first data receiving unit 402, and control the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge; when the data received from the first data receiving unit 402 is different from the test data, determine the target sampling duration corresponding to the first data receiving unit 402.

[0112] The receiving end control unit 403 is further configured to perform a sampling duration test process on the second data receiving unit to the nth data receiving unit in sequence until the data received by the nth data receiving unit 402 is different from the test data. The sampling duration test process includes:

[0113] The second sampling edge of the i-1th data receiving unit 402 is set according to the target sampling duration and the first sampling edge of the i-1th data receiving unit 402. The second sampling edges of the i-th data receiving unit 402 to the n-th data receiving unit 402 are set according to the initial interval duration and the first sampling edge. i is a positive integer greater than 1.

[0114] In the case where the data received from the i-th data receiving unit 402 is the same as the test data, the interval between the second sampling edge and the first sampling edge corresponding to the i-th data receiving unit 402 is shortened, and the data sending unit 401 is controlled to transmit the test data to the data receiving unit 402 at the first sampling edge again; in the case where the data received from the i-th data receiving unit 402 is different from the test data, the target sampling duration corresponding to the i-th data receiving unit 402 is determined. It should be noted that, in the case where a bus has n data receiving units 402, the determination process of the target sampling duration of each data receiving unit 402 can follow the principle of sequential determination. That is, the target sampling duration of each data receiving unit can be determined sequentially according to the connection sequence of the n data receiving units 402 and the data sending unit 401.

[0115] In some embodiments of the present application, the data sending unit 401 transmits the test data to the data receiving unit 402 at the first sampling edge of the first clock signal. The receiving end control unit 403 sets the second sampling edge corresponding to each data receiving unit 402 according to the initial interval duration and the first sampling edge, controls each data receiving unit 402 to sample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit 403.

[0116] When the data received from the first data receiving unit 402 is the same as the test data, the receiving end control unit 403 shortens the interval between the second sampling edge and the first sampling edge corresponding to the first data receiving unit 402, does not change the second sampling edges corresponding to the second data receiving unit 402 to the nth data receiving unit 402, controls the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge, controls each data receiving unit 402 to resample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit 403.

[0117] When the data received from the first data receiving unit 402 is different from the test data, the receiving end control unit 403 determines the target sampling duration corresponding to the first data receiving unit 402. The receiving end control unit 403 sets the second sampling edge of the first data receiving unit 402 according to the target sampling duration corresponding to the first data receiving unit 402 and the first sampling edge. And according to the initial interval duration and the first sampling edge, the second sampling edges of the second data receiving unit 402 to the nth data receiving unit 402 are set. The receiving end control unit 403 controls the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge, and controls each data receiving unit 402 to resample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit 403.

[0118] When the data received from the second data receiving unit 402 is the same as the test data, the receiving end control unit 403 shortens the interval between the second sampling edge and the first sampling edge corresponding to the second data receiving unit 402, does not change the second sampling edges corresponding to the first data receiving unit 402, the third data receiving unit 402 to the nth data receiving unit 402, controls the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge, controls each data receiving unit 402 to resample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit 403.

[0119] When the data received from the second data receiving unit 402 is different from the test data, the receiving end control unit 403 determines the target sampling duration corresponding to the second data receiving unit 402. The receiving end control unit 403 sets the second sampling edge of the first data receiving unit 402 according to the target sampling duration and the first sampling edge corresponding to the first data receiving unit 402, sets the second sampling edge of the second data receiving unit 402 according to the target sampling duration and the first sampling edge corresponding to the second data receiving unit 402, and sets the second sampling edges of the third data receiving unit 402 to the nth data receiving unit 402 according to the initial interval duration and the first sampling edge. The receiving end control unit 403 controls the data sending unit 401 to transmit the test data to the data receiving unit 402 again at the first sampling edge, controls each data receiving unit 402 to resample the data transmitted by the data sending unit 401 at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit 403. ...until the receiving end control unit 403 determines the target sampling duration corresponding to the nth data receiving unit 402 when the data received from the nth data receiving unit 402 is different from the test data.

[0120] In the embodiment of the present application, the longer the connection distance to the data sending unit 401, the longer the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit 402. Optionally, in the case where the bus has n data receiving units 402, the initial interval duration may be the maximum preset delay corresponding to the bus segment of the bus. That is, the initial interval duration corresponding to the data receiving unit is: the maximum preset delay corresponding to the bus segment in the bus that uses the data receiving unit to receive data. On the bus, the initial interval duration corresponding to each data receiving unit may be different.

[0121] The process in which the receiving end control unit 403 sets the second sampling edge corresponding to each data receiving unit 402 according to the initial interval duration and the first sampling edge may include: the receiving end control unit 403 may determine the second sampling edge of the first data receiving unit 402 according to the initial interval duration and the first sampling edge. For the i-th data receiving unit 402, the receiving end control unit 403 may determine the second sampling edge of the i-th data receiving unit 402 according to the second sampling edges of the first data receiving unit 402 to the i-1-th data receiving unit 402 and the initial interval duration of the i-th data receiving unit 402.

[0122] For example, it is assumed that the bus has one data sending unit 401 and three data receiving units 402. The initial interval durations of the first data receiving unit 402 to the third data receiving unit 402 are T1 to T3 respectively. The initial sampling durations T1 to T3 are 2, 3, and 3 sampling cycles respectively.

[0123] The receiving end control unit 403 determines the second sampling edge of the first data receiving unit 402 as the o1th rising sampling edge of the second clock signal according to the initial interval duration T1 and the first sampling edge. The receiving end control unit 403 determines the second sampling edge of the second data receiving unit 402 as the o1+3th rising sampling edge of the second clock signal, and the second sampling edge of the third data receiving unit 402 as the o1+6th rising sampling edge of the second clock signal.

[0124] In the embodiment of the present application, by adjusting the relative sampling duration between the data sending unit and the data receiving unit (i.e., the interval duration between the second sampling edge and the first sampling edge), and comparing whether the data sampled by the data receiving unit is the same as the test data sent by the data sending unit, the shortest duration (i.e., the target sampling duration) for the data receiving unit to sample the test data correctly is determined according to the comparison result, so as to realize adaptive delay detection of the bus connecting the data sending unit and the data receiving unit. Compared with the bus delay prediction scheme in the chip design stage in the related art, the technical scheme of the present application directly performs bus delay detection on the bus circuit in the actual use process, which can guarantee the accuracy of the detected bus delay to a certain extent, thereby improving the stability of data transmission on the bus.

[0125] For ease of understanding, the bus circuit provided by the embodiment of the present application is schematically described again by way of example below. Figure 5 As shown, it may have an adaptive training mode and a normal working mode. After the bus circuit 400 determines the target sampling duration of the data receiving unit 402 through the adaptive training mode, it may perform the normal working mode to perform data transmission.

[0126] The bus circuit 400 enters the adaptive training mode after the chip is started, or when the operating frequency of the chip needs to be adjusted. For a bus included in the bus circuit 400, when the bus circuit 400 is in the adaptive training module, the transmitting end control unit 404 sets the data sending unit 401 of the bus to an invalid state. The data sending unit 401 in the invalid state samples test data from the transmitting end control unit 404. The bus circuit starts to execute the training process.

[0127] In the first training process, the transmitting end control unit 404 controls the data transmitting unit 401 to transmit the test data to the data receiving unit 402 along the bus at the first sampling edge of the first clock signal for the first time.

[0128] The data receiving unit 402 samples the data transmitted by the data transmitting unit 401 for the first time at the second sampling edge of the second clock signal, and transmits the sampled data to the receiving end control unit 403. The receiving end control unit 403 compares whether the data received from the data receiving unit 402 is the same as the test data transmitted by the transmitting end control unit 404.

[0129] When the data received from the data receiving unit 402 is the same as the test data transmitted by the transmitting control unit 404, the sampling interval of the data receiving unit 402 is reduced, that is, the interval between the second sampling edge and the first sampling edge is shortened, and a retest signal (that is, the second test signal) is sent to the transmitting control unit 404 to enable the bus circuit to perform a second training process.

[0130] When receiving the retest signal, the transmitting end control unit 404 controls the data transmitting unit 401 to transmit the test data to the data receiving unit 402 along the bus at the first sampling edge of the first clock signal for the second time. The data receiving unit 402 samples the data transmitted by the data transmitting unit 401 for the second time at the second sampling edge of the second clock signal, and transmits the sampled data to the receiving end control unit 403. The receiving end control unit 403 compares whether the data received from the data receiving unit 402 is the same as the test data transmitted by the transmitting end control unit 404. ....... The bus circuit performs the yth training process.

[0131] When receiving the retest signal, the transmitting end control unit 404 controls the data transmitting unit 401 to transmit the test data to the data receiving unit 402 along the bus at the first sampling edge of the first clock signal for the yth time. The data receiving unit 402 samples the data transmitted by the data transmitting unit 401 at the second sampling edge of the second clock signal for the yth time, and transmits the sampled data to the receiving end control unit 403. The receiving end control unit 403 compares whether the data received from the data receiving unit 402 is the same as the test data transmitted by the transmitting end control unit 404.

[0132] When the data received from the data receiving unit 402 is different from the test data transmitted by the transmitting control unit 404, the target sampling duration of the data receiving unit 402 is determined to be the sampling interval of the data receiving unit 402 during the y-1th training process, that is, the interval duration between the second sampling edge and the first sampling edge.

[0133] In this way, the bus circuit 400 saves the target sampling duration of the data receiving unit 402, exits the adaptive training mode, and enters the normal working mode. In the normal working mode, the transmitting end control unit 404 and the receiving end control unit 403 may not work. When the data transmitting unit 401 starts to transmit actual data to the data receiving unit 402, the general control unit transmits an enable signal to the data receiving unit 402. After receiving the enable signal, the data receiving unit 402 starts sampling the data transmitted by the transmitting end control unit 404 after the target sampling duration.

[0134] In some embodiments of the present application, the receiving end control unit 403 and / or the transmitting end control unit 404 may be a digital circuit. And the receiving end control unit 403 and / or the transmitting end control unit 404 may operate at a lower operating frequency. The receiving end control unit 403 and / or the transmitting end control unit 404 may use the same clock signal as the latch of the data receiving unit / data sending unit to save the clock wiring resources of the bus circuit. Furthermore, the receiving end control unit 403 and / or the transmitting end control unit 404 may reduce its operating frequency by controlling the effective sampling edge of the clock, and turn off its operating clock in the normal operating mode, so that both stop working, saving the power consumption of the bus circuit.

[0135] It should be noted that the selection of test data (i.e., test vector) in the embodiment of the present application needs to at least consider the factor of the maximum transmission delay of the data on the bus, so as to reasonably set the test data and ensure that the effective target sampling duration of the data receiving unit can be tested using the test data. The effective target sampling duration can be the minimum sampling interval of the data receiving unit when receiving data with the maximum transmission delay.

[0136] Among them, the factors that may cause the maximum transmission delay of data on the bus may include: 1) the maximum delay of each bit of data on the bus when it is at a high level / low level. 2) the combined delay of multi-bit data (i.e., multi-bit vector) on the bus. 3) the effect of the inversion of the transmission signal on the transmission line arranged around the bus in the bus circuit on the delay of the bus transmission data.

[0137] Among them, for factor 1), the bus circuit can use multiple test data to respectively determine the target sampling duration of the data receiving unit, and then determine the maximum target sampling duration as the final target sampling duration of the data receiving unit, so as to ensure that the data receiving unit can effectively sample the data when the data transmitted on the bus has the maximum transmission delay. Among them, each test data has an outlier that is different from other bits of data. The number of bits of the outliers of multiple test data is different. For example, the bit width of the data transmitted on the bus is 4. Multiple test data include: 1000, 0100, 0010, 0001, 0111, 1011, 1101, 1110. Among them, the outliers in the first 4 test data are 1; the outliers in the last 4 test data are 0.

[0138] Regarding factor 2), in the data transmitted by the bus, there is a delay effect between different bits of data. For example, if a certain bit of data on the bus is high, that is, the data line transmitting a certain bit of data transmits high-level data, but the data lines arranged adjacent to the data line all transmit low-level data, then the delay on the data line is the largest. Factor 3) is similar to factor 2), and the data transmitted on the transmission lines arranged around the bus may also cause the delay on the bus to increase.

[0139] In this way, the selection of test data needs to consider the physical layout of the data lines that transmit each bit of data in the bus and the transmission lines arranged around the bus. However, the delay caused by these two factors can be avoided by the routing design of the bus circuit. For example, the distribution area and wiring space where the bus is located are isolated and arranged from other transmission lines on the bus circuit. Multiple transmission lines in the same bus can also be designed for intra-bus spacing. For example, each of the multiple transmission lines included in the bus is distributed on multiple metal layers to increase the spacing between the transmission lines.

[0140] In some embodiments of the present application, the amount of test data can be reduced by the arrangement of the transmission lines on the bus. For example, the multiple transmission lines included in the bus can be divided into multiple sub-bus groups. Each sub-bus group is set at intervals, that is, a physical isolation setting is performed. In this way, the coupling effect between the sub-bus groups can be reduced or even eliminated. The delay between each sub-bus group is the same. Based on this, the test data can be the test data of a group of sub-bus groups. Compared with the test data of the bus, the test data of the sub-bus group has a smaller number of bits and a smaller amount of test data.

[0141] In an optional implementation, after the structural design of the bus circuit is completed, the test data can be designed according to the structure of the bus circuit. In an example, the test data can be combined and set to obtain multiple test data. Each of the multiple test data has a different number from other bits of data, and the number of bits of the different numbers of the multiple test data is different. In another example, the buses in the bus circuit are arranged at intervals according to the sub-bus groups. The test data can be a group structure. That is, the test data can be a plurality of test data obtained after the test data corresponding to each sub-bus group is arranged and combined. It should be noted that the test data can be pre-written into the data sending unit 401 / transmitting end control unit 404. Alternatively, the test data can also be input to the data sending unit 401 / transmitting end control unit 404 using a data writing unit. That is, the bus circuit 400 can support external input test data, so as to facilitate the modification and improvement of the test data, and enhance the flexibility of test data setting. For example, the data writing unit can be a test scan structure for shifting the test data to the data sending unit 401 / transmitting end control unit 404.

[0142] In summary, the bus circuit provided by the embodiment of the present application includes: a data sending unit, a data receiving unit, and a receiving end control unit. The data sending unit is used to transmit test data to the data receiving unit at the first sampling edge of the first clock signal. The data receiving unit is used to sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit. The receiving end control unit is used to shorten the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, and control the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal; and is also used to determine the target sampling duration when the data received from the data receiving unit is different from the test data, so that the data receiving unit delays the data transmitted by the data sending unit by at least the target sampling duration compared to the data sampling start time of the data sending unit. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

[0143] In this technical solution, by adjusting the relative sampling duration between the data sending unit and the data receiving unit (i.e., the interval duration between the second sampling edge and the first sampling edge), and comparing whether the data sampled by the data receiving unit is the same as the test data sent by the data sending unit, the shortest duration (i.e., the target sampling duration) for the data receiving unit to sample the test data correctly is determined according to the comparison result, thereby realizing adaptive delay detection of the bus connecting the data sending unit and the data receiving unit. Compared with the bus delay prediction solution in the chip design stage in the related art, the technical solution of this application directly performs bus delay detection on the bus circuit in actual use, which can guarantee the accuracy of the detected bus delay to a certain extent, thereby improving the stability of data transmission on the bus.

[0144] The present application also provides a chip, which may include the bus circuit provided by the present application. Figure 4 or Figure 5 The bus circuit is shown.

[0145] The present application also provides a method for controlling a bus circuit, which can be applied to the bus circuit provided by the present application, or the chip provided by the present application. Figure 6 As shown, the control method of the bus circuit may include:

[0146] Step 601: Transmit test data to a data receiving unit through a data sending unit at a first sampling edge of a first clock signal.

[0147] The specific execution process of this step can refer to the above description, and the embodiments of the present application will not be repeated here. It should be noted that, optionally, the process in which the data sending unit transmits the test data to the data receiving unit at the first sampling edge of the first clock signal may include: the data sending unit may transmit the test data to the data receiving unit at the first sampling edge of the first clock signal according to the acquired first indication data.

[0148] Further optionally, the first indication data indicates the order of the first sampling edges in the first clock signal. In the case where the data sending unit includes a data sending module and a second counting module, the data sending module and the second counting module synchronously receive the first clock signal.

[0149] The process of the data sending unit transmitting the test data to the data receiving unit at the first sampling edge of the first clock signal may include: the data sending unit is used to count the second number of the sampling edges of the first clock signal through the second counting module, and transmit the second number to the data sending module. The data sending unit is used to determine that the first sampling edge is reached when the second number indicates the order indicated by the first indication data through the data sending module, and transmit the test data to the data receiving unit.

[0150] Step 602: The data receiving unit samples the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit.

[0151] The specific execution process of this step can refer to the above description, and the embodiment of the present application will not be repeated here.

[0152] Step 603, when the data received from the data receiving unit is the same as the test data, the receiving end control unit shortens the interval between the second sampling edge and the first sampling edge, and controls the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal.

[0153] The specific execution process of this step can refer to the above description, and the embodiment of the present application will not be repeated here.

[0154] Step 604: The receiving end control unit determines a target sampling duration when the data received from the data receiving unit is different from the test data.

[0155] The specific execution process of this step can refer to the above description, and the embodiments of the present application will not be described in detail here. Among them, the target sampling duration is used for the data receiving unit to delay the data sampling start time of the data sending unit by at least the target sampling duration, and sample the data transmitted by the data sending unit. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

[0156] It should be noted that, optionally, before receiving the data transmitted from the data receiving unit, the receiving end control unit may also determine the second indication data according to the initial interval duration and the first indication data, and transmit the second indication data to the data receiving unit, so that the data receiving unit determines, according to the second indication data, that the second sampling edge of the second clock signal has arrived, and starts sampling the data transmitted by the data sending unit. The first indication data indicates the first sampling edge, and the second indication data indicates the second sampling.

[0157] The process of shortening the interval between the second sampling edge and the first sampling edge by the receiving end control unit when the data received from the data receiving unit is the same as the test data may include: shortening the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, obtaining updated second indication data, and transmitting the updated second indication data to the data receiving unit, so that the data receiving unit determines, based on the updated second indication data, that when the second sampling edge of the second clock signal is reached, it starts sampling the data transmitted by the data sending unit.

[0158] Further optionally, the second indication data indicates the order of the second sampling edge in the second clock signal. In the case where the data receiving unit includes a data receiving module and a first counting module, the data receiving module and the first counting module synchronously receive the second clock signal. The process of the data receiving unit sampling the data transmitted by the data sending unit at the second sampling edge of the second clock signal may include: the data receiving unit counts the first number of sampling edges of the second clock signal through the first counting module, and transmits the first number to the data receiving module; the data receiving unit determines that the second sampling edge has arrived when the first number indicates the order indicated by the second indication data through the data receiving module, and starts sampling the data transmitted by the data sending unit.

[0159] In an optional implementation, when the bus circuit further includes a general control unit and a transmitting end control unit, the control method of the bus circuit further includes:

[0160] The first test signal is synchronously transmitted to the transmitting end control unit and the receiving end control unit through the general control unit. When the transmitting end control unit receives the first test signal, the test data and the first clock signal are transmitted to the data transmitting unit, and the data transmitting unit is controlled to transmit the test data to the data receiving unit at the first sampling edge.

[0161] When receiving the first test signal, the receiving end control unit transmits a second clock signal to the data receiving unit, and controls the data receiving unit to sample the data transmitted by the data sending unit at the second sampling edge. The first test signal is generated at least after the chip where the bus circuit is located is started each time, and / or after the operating frequency of the chip is changed.

[0162] Further optionally, the bus circuit control method further includes: after the main control unit transmits the first test signal to the transmitting-end control unit, the main control unit synchronously transmits the second test signal to the transmitting-end control unit and the receiving-end control unit.

[0163] Accordingly, the process in which the transmitting end control unit controls the data sending unit to transmit the test data to the data receiving unit at the first sampling edge may include: when the transmitting end control unit receives the second test signal, the data sending unit is controlled to transmit the test data to the data receiving unit at the first sampling edge.

[0164] The process in which the receiving end control unit controls the data receiving unit to sample the data transmitted by the data sending unit at the second sampling edge may include: when the receiving end control unit receives the second test signal, controlling the data receiving unit to sample the data transmitted by the data sending unit at the second sampling edge.

[0165] The process in which the receiving-end control unit shortens the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, and controls the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal may include: when the data received from the data receiving unit is the same as the test data, the receiving-end control unit shortens the interval between the second sampling edge and the first sampling edge, generates and transmits a second test signal to the sending-end control unit, and controls the data receiving unit to sample the data transmitted by the data sending unit at the shortened second sampling edge.

[0166] In an optional implementation, when the bus circuit includes multiple buses, each bus is connected to a data receiving unit and a data sending unit, and the receiving end control unit is connected to the data receiving unit of each bus, the control method of the bus circuit further includes:

[0167] For each bus, the receiving end control unit can shorten the interval between the second sampling edge and the first sampling edge of the data receiving unit when the data received from the data receiving unit through the bus is the same as the test data corresponding to the bus, and control the data sending unit to transmit the corresponding test data to the data receiving unit again at the first sampling edge;

[0168] The receiving end control unit may determine the target sampling duration of the bus when the data received from the data receiving unit through the bus is different from the test data corresponding to the bus.

[0169] In another optional implementation, when the number of data receiving units is n, and the n data receiving units are serially connected to the data sending unit, and the receiving end control unit is connected to each data receiving unit, the control method of the bus circuit further includes:

[0170] Each data receiving unit can sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit.

[0171] The receiving end control unit can set the second sampling edge corresponding to each data receiving unit according to the initial interval duration and the first sampling edge; when the data received from the first data receiving unit is the same as the test data, shorten the interval duration between the second sampling edge and the first sampling edge corresponding to the first data receiving unit, and control the data sending unit to transmit the test data to the data receiving unit at the first sampling edge again; when the data received from the first data receiving unit is different from the test data, determine the target sampling duration corresponding to the first data receiving unit;

[0172] The receiving end control unit may also perform sampling duration test processing on the second data receiving unit to the nth data receiving unit in sequence until the data received by the nth data receiving unit is different from the test data, and the sampling duration test processing includes:

[0173] According to the target sampling duration and the first sampling edge of the i-1th data receiving unit, the second sampling edge of the i-1th data receiving unit is set, and according to the initial interval duration and the first sampling edge, the second sampling edges of the i-th data receiving unit to the n-th data receiving unit are set, where i is a positive integer greater than 1;

[0174] When the data received from the i-th data receiving unit is the same as the test data, the interval between the second sampling edge and the first sampling edge corresponding to the i-th data receiving unit is shortened, and the data sending unit is controlled to transmit the test data to the data receiving unit again at the first sampling edge; when the data received from the i-th data receiving unit is different from the test data, the target sampling duration corresponding to the i-th data receiving unit is determined. The longer the connection distance to the data sending unit is, the longer the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit is.

[0175] In the embodiment of the present application, by adjusting the relative sampling duration between the data sending unit and the data receiving unit (i.e., the interval duration between the second sampling edge and the first sampling edge), and comparing whether the data sampled by the data receiving unit is the same as the test data sent by the data sending unit, the shortest duration (i.e., the target sampling duration) for the data receiving unit to sample the test data correctly is determined according to the comparison result, so as to realize adaptive delay detection of the bus connecting the data sending unit and the data receiving unit. Compared with the bus delay prediction scheme in the chip design stage in the related art, the technical scheme of the present application directly performs bus delay detection on the bus circuit in the actual use process, which can guarantee the accuracy of the detected bus delay to a certain extent, thereby improving the stability of data transmission on the bus.

[0176] It should be noted that, as shown above, in some embodiments, the number of test data can be multiple. The bus circuit / chip can sequentially use multiple test data (ie, test vectors) to determine the target sampling duration of the data receiving unit. For example, Figure 7 As shown, the control method of the bus circuit includes:

[0177] The transmitting end control unit performs test vector selection, specifically including: the transmitting end control unit selects a test vector from a plurality of candidate test vectors. The candidate test vector is a test vector that is not selected from the plurality of test vectors.

[0178] The transmitting end control unit performs initialization data and sampling clock configuration, specifically including: the transmitting end control unit sends the selected test vector to the data sending unit and the receiving end control unit, and configures the data sending unit to transmit test data to the data receiving unit at the first sampling edge of the first clock signal. The receiving end control unit configures the data receiving unit to sample the data transmitted by the data receiving unit at the second sampling edge of the second clock signal.

[0179] The data sending unit sends data, specifically including: the data sending unit transmits test data to the data receiving unit at the first sampling edge of the first clock signal, so that the data receiving unit samples the data transmitted by the data receiving unit at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit.

[0180] The receiving end control unit performs sampling data comparison, specifically including: the receiving end control unit compares whether the data received from the data receiving unit is the same as the test data to determine whether the data received from the data receiving unit is correct. Wherein, if the data received from the data receiving unit is the same as the test data, it is determined that the data received from the data receiving unit is correct test data. If the data received from the data receiving unit is different from the test data, it is determined that the data received from the data receiving unit is wrong test data.

[0181] When the sampling data comparison result determines that the data received from the data receiving unit is correct test data, the receiving end control unit reduces the sampling interval and controls the sending end control unit to configure the sampling clock. Specifically, the receiving end control unit shortens the interval between the second sampling edge and the first sampling edge, and controls the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal.

[0182] The receiving end control unit determines the sampling interval (i.e., target sampling duration) when the sampled data comparison result determines that the data received from the data receiving unit is erroneous test data. Specifically, it includes: determining the target sampling duration corresponding to the test vector, the target sampling duration being the shortest interval duration between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

[0183] The transmitting end control unit determines whether there is an unselected test vector among all the test vectors. If so, it returns to execute test vector selection to select a test vector from multiple candidate test vectors until there is no unselected test vector.

[0184] The receiving end control unit selects a target sampling duration with the longest duration from the target sampling durations corresponding to the multiple test vectors, and determines the target sampling duration as the final target sampling duration of the data receiving unit.

[0185] In summary, the control method of the bus circuit provided by the embodiment of the present application transmits the test data to the data receiving unit through the data sending unit at the first sampling edge of the first clock signal, and the data receiving unit samples the data transmitted by the data sending unit at the second sampling edge of the second clock signal to transmit the received data to the receiving end control unit. Thus, when the data received from the data receiving unit is the same as the test data, the receiving end control unit shortens the interval between the second sampling edge and the first sampling edge, and controls the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal; and when the data received from the data receiving unit is different from the test data, the receiving end control unit determines the target sampling duration. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data. The target sampling duration is used for the data receiving unit to delay the data sampling start time of the data sending unit by at least the target sampling duration, and to sample the data transmitted by the data sending unit.

[0186] In this technical solution, by adjusting the relative sampling duration between the data sending unit and the data receiving unit (i.e., the interval duration between the second sampling edge and the first sampling edge), and comparing whether the data sampled by the data receiving unit is the same as the test data sent by the data sending unit, the shortest duration (i.e., the target sampling duration) for the data receiving unit to sample the test data correctly is determined according to the comparison result, thereby realizing adaptive delay detection of the bus connecting the data sending unit and the data receiving unit. Compared with the bus delay prediction solution in the chip design stage in the related art, the technical solution of this application directly performs bus delay detection on the bus circuit in actual use, which can guarantee the accuracy of the detected bus delay to a certain extent, thereby improving the stability of data transmission on the bus.

[0187] Figure 8 8 is a block diagram of an electronic device according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0188] Reference Figure 8 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0189] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0190] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0191] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0192] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0193] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0194] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0195] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of the components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0196] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0197] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processing circuits (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0198] In this embodiment, the electronic device further includes the bus circuit or chip as described above.

[0199] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0200] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0201] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0202] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0203] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0204] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0205] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0206] The current source module and device, an electronic device and a storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A bus circuit, characterized in that: The bus circuit includes: a data sending unit, a data receiving unit, and a receiving end control unit; The data sending unit is connected to the data receiving unit, and the data sending unit is used to transmit the test data to the data receiving unit at the first sampling edge of the first clock signal; The data receiving unit is also connected to the receiving end control unit, and the data receiving unit is used to sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit, the first clock signal and the second clock signal are synchronous clock signals, and there is an interval time between the second sampling edge and the first sampling edge; The receiving end control unit is used for shortening the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, and controlling the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal; The receiving end control unit is also used to determine a target sampling duration when the data received from the data receiving unit is different from the test data. The target sampling duration is used for the data receiving unit to delay the data sampling start time of the data sending unit by at least the target sampling duration to sample the data transmitted by the data sending unit. The target sampling duration is the shortest interval between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

2. The bus circuit according to claim 1, characterized in that: The receiving end control unit is used to determine second indication data according to the initial interval duration and the first indication data before receiving the data transmitted from the data receiving unit, and transmit the second indication data to the data receiving unit, wherein the first indication data indicates the first sampling edge, and the second indication data indicates the second sampling edge; The receiving end control unit is further used to shorten the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, obtain the updated second indication data, and transmit the updated second indication data to the data receiving unit; The data receiving unit is further configured to determine, based on the second indication data, when a second sampling edge of the second clock signal arrives, to start sampling the data transmitted by the data sending unit.

3. The bus circuit according to claim 2, characterized in that: The second indication data indicates the order of the second sampling edges in the second clock signal; the data receiving unit comprises: a data receiving module and a first counting module; The data receiving module and the first counting module synchronously receive the second clock signal, and the first counting module is used to count a first number of sampling edges of the second clock signal and transmit the first number to the data receiving module; The data receiving module is used for determining that the second sampling edge has arrived when the first quantity indicates the order indicated by the second indication data, and starting to sample the data transmitted by the data sending unit.

4. The bus circuit according to claim 2 or 3, characterized in that: The data sending unit is used to transmit the test data to the data receiving unit at a first sampling edge of the first clock signal according to the acquired first indication data.

5. The bus circuit according to claim 4, characterized in that: The first indication data indicates the order of the first sampling edges in the first clock signal; the data sending unit comprises: a data sending module and a second counting module; The data sending module and the second counting module synchronously receive the first clock signal, and the second counting module is used to count the second number of sampling edges of the first clock signal and transmit the second number to the data sending module; The data sending module is used for determining that the first sampling edge is reached when the second number indicates the order indicated by the first indication data, and transmitting the test data to the data receiving unit.

6. The bus circuit according to claim 1, characterized in that: The bus circuit also includes: a general control unit and a sending end control unit; The general control unit is connected to the sending end control unit and the receiving end control unit respectively, and the general control unit is used to synchronously transmit a first test signal to the sending end control unit and the receiving end control unit; The transmitting end control unit is used for transmitting the test data and the first clock signal to the data transmitting unit when receiving the first test signal, and controlling the data transmitting unit to transmit the test data to the data receiving unit at the first sampling edge; The receiving end control unit is further used to transmit the second clock signal to the data receiving unit when the first test signal is received, and control the data receiving unit to sample the data transmitted by the data sending unit at the second sampling edge; The first test signal is generated at least after the chip where the bus circuit is located is started each time and / or after the operating frequency of the chip is changed.

7. The bus circuit according to claim 6, characterized in that: The general control unit is further configured to synchronously transmit a second test signal to the transmitting end control unit and the receiving end control unit after transmitting the first test signal to the transmitting end control unit; The transmitting end control unit is further used to control the data transmitting unit to transmit the test data to the data receiving unit at the first sampling edge when the second test signal is received; The receiving end control unit is further used to control the data receiving unit to sample the data transmitted by the data sending unit at the second sampling edge when the second test signal is received; The receiving end control unit is also used to shorten the interval between the second sampling edge and the first sampling edge when the data received from the data receiving unit is the same as the test data, generate and transmit the second test signal to the sending end control unit, and control the data receiving unit to sample the data transmitted by the data sending unit on the shortened second sampling edge.

8. The bus circuit according to claim 1, characterized in that: The bus circuit comprises: a plurality of buses, each of which is connected to a data receiving unit and a data sending unit correspondingly, and the receiving end control unit is connected to the data receiving unit of each bus; For each of the buses, the receiving end control unit is used to shorten the interval between the second sampling edge and the first sampling edge of the data receiving unit when the data received from the data receiving unit through the bus is the same as the test data corresponding to the bus, and control the data sending unit to transmit the corresponding test data to the data receiving unit again at the first sampling edge; The receiving end control unit is further used to determine the target sampling duration of the bus when the data received from the data receiving unit through the bus is different from the test data corresponding to the bus.

9. The bus circuit according to claim 1, characterized in that: The number of the data receiving units is n, the n data receiving units are connected in series with the data sending unit, the receiving end control unit is connected with each of the data receiving units, and n is a positive integer greater than 2; Each of the data receiving units is used to sample the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmit the received data to the receiving end control unit, wherein the longer the connection distance to the data sending unit is, the longer the interval between the second sampling edge and the first sampling edge corresponding to the data receiving unit is; The receiving end control unit is used to set the second sampling edge corresponding to each of the data receiving units according to the initial interval duration and the first sampling edge; when the data received from the first data receiving unit is the same as the test data, shorten the interval duration between the second sampling edge corresponding to the first data receiving unit and the first sampling edge, and control the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge; when the data received from the first data receiving unit is different from the test data, determine the target sampling duration corresponding to the first data receiving unit; The receiving end control unit is further used to perform sampling duration test processing on the second data receiving unit to the nth data receiving unit in sequence until the data received by the nth data receiving unit is different from the test data, and the sampling duration test processing includes: According to the target sampling duration of the i-1th data receiving unit and the first sampling edge, the second sampling edge of the i-1th data receiving unit is set, and according to the initial interval duration and the first sampling edge, the second sampling edges of the i-th data receiving unit to the n-th data receiving unit are set, where i is a positive integer greater than 1; When the data received from the i-th data receiving unit is the same as the test data, the interval between the second sampling edge and the first sampling edge corresponding to the i-th data receiving unit is shortened, and the data sending unit is controlled to transmit the test data to the data receiving unit again at the first sampling edge; when the data received from the i-th data receiving unit is different from the test data, the target sampling duration corresponding to the i-th data receiving unit is determined.

10. A chip, characterized in that: The chip comprises: the bus circuit according to any one of claims 1 to 9.

11. A method for controlling a bus circuit, characterized in that: Applied to the bus circuit according to any one of claims 1 to 9, or the chip according to claim 10, the method comprising: transmitting the test data to the data receiving unit through the data sending unit at the first sampling edge of the first clock signal; The data receiving unit samples the data transmitted by the data sending unit at the second sampling edge of the second clock signal, and transmits the received data to the receiving end control unit. When the data received from the data receiving unit is the same as the test data, the receiving end control unit shortens the interval between the second sampling edge and the first sampling edge, and controls the data sending unit to transmit the test data to the data receiving unit again at the first sampling edge of the first clock signal; The receiving end control unit determines a target sampling duration when the data received from the data receiving unit is different from the test data. The target sampling duration is used for the data receiving unit to delay the data sampling start time of the data sending unit by at least the target sampling duration to sample the data transmitted by the data sending unit. The target sampling duration is the shortest interval duration between the second sampling edge and the first sampling edge when the data sampled by the data receiving unit is the same as the test data.

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