A storage controller and an electronic system

Abstract

The present invention discloses a storage controller and an electronic system. The storage controller includes: a first interface, a data management module, and a second interface group, where the second interface group includes N second interfaces, and N is a natural number; the first interface is used to communicate with a main control component, the second interface is used to externally connect to a memory, and the data management module is connected between the first interface and the second interface to obtain a control instruction of the main control component and manage data storage of the memory based on the control instruction. By means of the present invention, a solution for reducing the cost of memory capacity upgrade is provided.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular, to a storage controller and an electronic system. Background Art

[0002] With the development of electronic technology, the demand for memory capacity in various electronic products is increasing day by day.

[0003] The upper limit of the memory capacity of existing electronic products is often determined by the capacity supported by the main control components such as the motherboard chipset or the CPU. When the demand reaches the maximum memory capacity supported by the main control components, it will be impossible to continue expanding, and only products with higher configurations can be replaced, which results in huge hardware upgrade costs and resource waste. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a storage controller and an electronic system that overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, a storage controller is provided, including:

[0006] A first interface, a data management module, and a second interface group, where the second interface group includes N second interfaces, and N is a natural number;

[0007] The first interface is used to communicate with the main control component, the second interface is used to externally connect a memory, and the data management module is connected between the first interface and the second interface to obtain a control instruction of the main control component and manage the data storage of the memory based on the control instruction.

[0008] Optionally, the second interface includes a plurality of dedicated circuits, and each dedicated circuit is used to support different types of memories.

[0009] Optionally, the second interface further includes: a general circuit and an interface circuit. The plurality of dedicated circuits are all connected to the general circuit to share the functions of the general circuit, and the plurality of dedicated circuits are all connected to the interface circuit to share the interface circuit to realize the connection with the memory.

[0010] Optionally, the storage controller further includes: an on-chip cache module, connected to the first interface, for caching communication data with the main control component.

[0011] Optionally, the on-chip cache module is connected to the data management module and stores cached data, so as to be able to query the cached data according to a read instruction of the main control component.

[0012] Optionally, the storage controller further includes: a cache interface module group, the cache interface module group includes M cache interface modules, M is a natural number; the cache interface module is used for externally connecting to a cache unit.

[0013] Optionally, the cache unit and the storage controller are integrated through chip stacking technology.

[0014] Optionally, the storage controller also includes an on-chip cache module connected to the first interface; wherein the on-chip cache module and the cache interface module group are both connected to the data management module, and the on-chip cache module and the cache unit both store cache data; wherein, when the storage controller receives a read instruction from the main control component, it first queries the cache data in the on-chip cache module, and if there is no hit, it then queries the cache data in the cache unit, and if there is still no hit, it then queries the data in the memory.

[0015] Optionally, the storage controller further includes: a data protection module connected to the second interface group and used for data encryption, decryption and / or error correction.

[0016] Optionally, the storage controller further includes: a control module connected to the data management module and used to configure parameters of each module in the storage controller.

[0017] In a second aspect, an electronic system is provided, comprising:

[0018] A main control component, a memory, and a storage controller as described in any one of the first aspects;

[0019] The storage controller communicates with the main control component through the first interface and is connected to the memory through the second interface to expand the memory capacity of the electronic system.

[0020] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0021] The storage controller and electronic system provided by the embodiment of the present invention are provided with a storage controller including a first interface, a data management module and a second interface group. Communication with the main control component is achieved through the first interface, an external memory is connected through the second interface, and data storage in the memory is managed through the data management module. This enables the main control component to remove the restrictions on memory capacity by means of an external memory, and the memory bandwidth and capacity can be expanded without replacing the main control device, greatly reducing the cost of upgrading the memory capacity. In addition, in addition to being used for expanding the memory capacity, the external memory can also be used for the functions that other memories such as hard disks and near-memory computing acceleration cards can provide, thereby improving computer performance in all aspects.

[0022] The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are hereinafter specifically exemplified. Description of the Drawings

[0023] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0024] Figure 1 is a schematic structural diagram of the storage controller in an embodiment of the present invention Figure 1 ;

[0025] Figure 2 is a schematic structural diagram of the second interface in an embodiment of the present invention;

[0026] Figure 3 is a schematic structural diagram of the storage controller in an embodiment of the present invention Figure 2 ;

[0027] Figure 4 is a schematic structural diagram of the storage controller in an embodiment of the present invention Figure 3 ;

[0028] Figure 5 is a schematic structural diagram of the electronic system in an embodiment of the present invention. Detailed Embodiments

[0029] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0030] Various schematic structural diagrams according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, where for the purpose of clear illustration, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary, and may actually deviate due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0031] Please refer to Figure 1 Figure 1 , an embodiment of the present application provides a storage controller 101, including: a first interface 1, a data management module 2, and a second interface group. The second interface group includes N second interfaces 3, where N is a natural number. The first interface 1 is used to communicate with a main control component 102, the second interface 3 is used to externally connect to a memory 103, and the data management module 2 is connected between the first interface 1 and the second interface 3 to obtain a control instruction of the main control component 102 and manage the data storage of the memory 103 based on the control instruction.

[0032] It should be noted that although a part of the capacity of a computer hard disk can be divided into virtual memory for use through an operating system to expand the memory capacity, its bandwidth and latency cannot meet the performance requirements of the memory. Therefore, even if the memory capacity is increased through virtual memory, it cannot respond to read and write requests as quickly as the original memory, reducing the performance of the system. However, through the storage controller 101 of the present application, the coupling relationship between the main control component and the memory capacity can be eliminated, and the memory bandwidth and capacity can be expanded without replacing the main control component, greatly reducing the cost of memory capacity upgrade. Moreover, through the setting of the second interface group, the present application can support the flexible use of various new storage media to expand the memory, get rid of the dependence on dynamic random access memory (DRAM), and can further reduce the cost of the memory.

[0033] Next, the structure and operation mode of the storage controller 101 will be introduced in detail.

[0034] Among them, the first interface 1 is used to communicate with a main control component 102 such as a CPU. In an optional embodiment, the first interface 1 can be a cache coherent bus interface or an Open Industry Standard Interconnect (Compute Express Link, CXL) interface module, which can be used to connect processors, accelerators, memory buffers, intelligent network interfaces, and storage devices, etc.

[0035] Among them, the data management module 2 can obtain the control instruction of the main control component 102 and manage the data storage of the memory 103 based on the control instruction. Specifically, the data management module 2 can also perform operations such as wear leveling on the memory 103 (that is, control the storage amount and read / write quantity of data in each memory to be uniform to avoid damage to memories with excessive storage amount or overly frequent read / write), bad block management (that is, be able to isolate faulty memories or faulty storage units in the memory to avoid the impact of the faulty part on the overall storage), and data backup (can also perform backup management on the data stored in the memory to avoid the loss of important data), etc., to improve the stability, reliability, and lifespan of the memory.

[0036] Among them, the second interface group may include multiple second interfaces 3 to be able to access multiple memories 103 to expand the memory capacity.

[0037] Please refer to Figure 2 , in an alternative embodiment, the second interface 3 includes multiple dedicated circuits 201, and each dedicated circuit 201 is used to support different types of memories 103. Specifically, each dedicated circuit 201 is adapted to the communication protocols of different memories. In this way, each second interface 3 can be compatible with one or more types of memories 103 at the same time. The types of memories it is compatible with may include volatile memories (such as dynamic memory DRAM) and non-volatile memories (such as phase change memory PCM, flash memory Flash, resistive random access memory RRAM, etc.), so as to increase the applicable range of the memory controller 101, improve the flexibility of memory expansion, get rid of the dependence on dynamic memory DRAM, and further reduce the cost of memory.

[0038] In an alternative embodiment, as Figure 2 shown, it can be set that the second interface 3 includes: multiple dedicated circuits 201, a general circuit 202, and an interface circuit 203. The multiple dedicated circuits 201 are all connected to the general circuit 202 to share the functions of the general circuit 202. Moreover, the multiple dedicated circuits 201 are also all connected to the interface circuit 203 to share the interface circuit 203 to realize the connection with the memory 103. Specifically, the dedicated circuit 201 is respectively used to support different types of memories, and it is mainly the circuit part related to the communication protocol of the memory. The general circuit 202 is a reusable circuit, and it is mainly the circuit part related to the signal transmission line, such as a general high-speed bus, etc. The interface circuit 203 is a reusable connection interface circuit with the memory. These three parts of the circuit cooperate through software and / or hardware configuration to realize the data transmission of different types of memories. Moreover, through the sharing of the general circuit 202 and the interface circuit 203, the chip area and cost can also be saved.

[0039] Of course, it is also possible to adopt another way to realize the access of multiple types of memories. For example, among the multiple second interfaces in the second interface group, interface modules that support different types of memories are included. For example, the second interface group includes 6 second interfaces 3, among which, 2 support dynamic memory DRAM, 2 support phase change memory PCM, and 2 support flash memory Flash. There are no restrictions here.

[0040] Of course, in the specific implementation process, in addition to being used to expand and increase the memory capacity, the memory 103 externally connected to the memory controller 101 can also be used for other purposes other than the memory according to the type of the memory 103, such as a hard disk, a near-memory computing acceleration card, etc., to improve the performance of the computer.

[0041] Please refer toFigure 3 In an alternative embodiment, the storage controller 101 may further include an on-chip cache module 4, which is connected to the first interface 1 and is used to cache communication data with the host component 102. The data cached in the on-chip cache module 4 may include any one or a combination of the following: data to be written sent by the host component 102 to the storage controller 101, data to be read by the host component 102, and instruction data of the host component 102.

[0042] Taking the caching of data to be written as an example, the write data received by the storage controller 101 from the first interface 1 will be first cached in the on-chip cache module 4. When the trigger condition is met, the data management module 2 will move the write data to the memory 103 through the second interface 3 for storage. The trigger condition includes any one or a combination of the following: the time interval for accessing the memory 103 reaches a threshold, the number of accesses to the memory 103 within a certain period of time is less than the threshold, new data needs to be written to the on-chip cache module 4 after the on-chip cache module 4 is full, the data management module 2 actively triggers the transfer operation, or the write to the memory 103 is triggered simultaneously when data is written to the on-chip cache module 4.

[0043] In an alternative embodiment, it may also be set that part of the cached data is stored in the on-chip cache module 4. When the storage controller 101 receives a read instruction for data sent by the host component 102 from the first interface 1, it will first query in the on-chip cache module 4. If the target data to be read can be found, the target data will be directly returned to the host component 102. If the query fails to hit, the memory 103 will be accessed to read the target data, and the target data will be returned to the host component 102 through the first interface 1. This can improve the data reading speed and efficiency, and also avoid high-frequency access to the memory 103, ensuring the service life of the memory 103.

[0044] Specifically, the cached data pre-stored in the on-chip cache module 4 can be data pre-obtained from the memory 103 through the data management module 2 connected thereto, or data pre-obtained from the memory 103 through software control (external device software control or other internal module software control), or data written and cached in the on-chip cache module 4 received through the first interface 1, without limitation here. Taking the cached data as the data pre-obtained by the data management module 2 as an example, it can be set that the data management module 2 is preset with prefetch algorithms. The number of the prefetch algorithms can be one or more. Any number of prefetch algorithms can be selected by software configuration to take effect simultaneously, or multiple prefetch algorithms that take effect can be combined by the three logics of AND, OR, and NOT, without limitation here, so as to improve the flexibility and scalability of the prefetch algorithms. For example, based on the prefetch algorithm, according to the characteristics of the previously received read instructions, prefetch can be performed from the memory 103, and the data is stored in the on-chip cache module 4 to improve the data reading efficiency.

[0045] Please refer to Figure 4 In an alternative embodiment, it can be set that the memory controller 101 further includes: a cache interface module group, and the cache interface module group includes M cache interface modules 5, where M is a natural number. The cache interface module 5 is used to externally connect a cache unit 104. Among them, the cache interface module 5 can adopt the same structural design as the second interface 3, and can be provided with multiple dedicated circuits to adapt to different memory types, or only a circuit for adapting to a single memory type, without limitation here.

[0046] Specifically, setting the cache interface module 5 to externally connect the cache unit 104 can alleviate the problem of insufficient on-chip cache capacity. Since the on-chip cache module 4 of the memory controller 101 is often implemented by a static random access memory (SRAM), limited by the chip area, its capacity cannot be very large and the cost is very high. However, the on-chip cache module 4 can significantly improve the data reading efficiency. Therefore, by setting a cache interface module group in the memory controller 101 to connect a group of external cache units 104 as off-chip caches, the capacity of the on-chip cache module 4 can be expanded.

[0047] Among them, the cache unit 104 is an external memory. The connection method between it and the cache interface module 5 can be achieved by plugging, soldering, wire connection, etc. between independent devices, or can be integrally connected through chip stacking technology, which is not limited here. Integrating the cache unit 104 and the storage controller 101 together through chip stacking technology (2D interconnection technology, 2.5D interconnection technology or 3D interconnection technology) can significantly shorten the data communication duration between the cache unit 104 and the storage controller 101 and improve the access efficiency. And the stacking technology can increase the number of connection channels to realize the parallel access of the cache unit 104, further improving the bandwidth, so as to achieve a transmission rate not lower than the GB / s level and a transmission delay of the ns level to meet the requirements of realizing the cache function.

[0048] In an alternative embodiment, an on-chip cache module 4 and the cache unit 104 can be combined to form a multi-level cache. Specifically, it can be set that both the on-chip cache module 4 and the cache interface module group are connected to the data management module 2, and both the on-chip cache module 4 and the cache unit 104 store cache data (the acquisition method of the cache data here can be the same as the method of saving the cache data to the on-chip cache module 4). When the storage controller 101 receives a read instruction from the main control component 102, it first queries the cache data in the on-chip cache module 4. If the target data to be read is not hit, it then queries the cache data in the cache unit 104. If the target data to be read is still not hit, it then queries the data in the memory 103. In this way, on the one hand, by setting the transmission distance (for example, setting the cache unit 104 and the storage controller 101 to be integrated through chip stacking technology and the memory 103 to be connected in an external manner), or by setting the type of storage medium (for example, setting the cache unit 104 to use a storage medium type with a faster read speed than the memory 103), the access speed of the main control component 102 to the data is sorted from fast to slow as the on-chip cache module 4, the cache unit 104, and the memory 103. Therefore, multi-level query from fast to slow can effectively improve the data reading speed. On the other hand, querying in the cache first can effectively reduce the number of times of accessing the memory 103 and improve the lifespan of the memory 103.

[0049] In an alternative embodiment, such as Figure 3As shown, the storage controller 101 may further include a data protection module 6, which is connected to the second interface group and is used for data encryption / decryption and / or error correction. Specifically, the data protection module 6 may include any one or a combination of the following: encryption / decryption circuits, error detection and correction circuits, and encoding / decoding circuits. In this way, the data protection module 6 can perform encryption / decryption processing, error detection and correction processing, and encoding / decoding processing on the data, thereby ensuring the security and correctness of the written and read data. The operation speed of the data protection module 6 can be preset to meet the bandwidth requirements when the data link is fully loaded, and its error correction ability covers the error rate of the memory 103, thereby ensuring that the uncorrectable bit error rate (UBER) value of the memory 103 after error correction is better than 10 -15 .

[0050] In an alternative embodiment, as Figure 3 shown, the storage controller 101 may further include a control module 7, which is connected to the data management module 2 and is used for configuring the parameters of each module in the storage controller 101. Specifically, the control module 7 is a control and computing module integrated in the storage controller 101, which is used to execute software code and can perform data operation processing. Through it, the control and configuration of each module inside the storage controller 101 can be realized. For example, after the storage controller 101 receives the configuration instruction from the main control component 102, the configuration instruction is transmitted to the control module 7 through the first interface 1. After the control module 7 analyzes the configuration instruction, it obtains information such as the configuration object and configuration parameters, and configures the parameters of the configuration object according to the obtained information. The configuration content may be the data access frequency and trigger access conditions of the data management module 2, the update of the prefetch algorithm, or the limitation conditions of the cached data content and cache frequency in the on-chip cache module 4, etc. There is no limitation here and no further enumeration will be made.

[0051] Based on the same inventive concept, an embodiment of the present application further provides an electronic system, as Figure 5 shown, including:

[0052] The main control component 102, the memory 103, and the storage controller 101 provided in the foregoing embodiment. The storage controller 101 communicates with the main control component 102 through the first interface and is connected to the memory 103 through the second interface to expand the memory capacity of the electronic system.

[0053] Since the storage controller 101 included in the electronic system introduced in the embodiments of the present application is exactly the storage controller 101 introduced in the embodiments of the present application, the principle and structure of the storage controller 101 and its connection manner with the main control component 102 and the memory 103 have been described in detail above, so they will not be elaborated here. Any electronic system including the storage controller 101 of the embodiments of the present application falls within the scope of protection of the present invention.

[0054] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0055] The storage controller and the electronic system provided in the embodiments of the present invention are configured such that the storage controller includes a first interface, a data management module, and a second interface group. Communication with the main control component is achieved through the first interface, a memory is externally connected through the second interface, and data storage in the memory is managed through the data management module. This enables the memory capacity limitation of the main control component to be lifted by using an externally connected memory, and the memory bandwidth and capacity can be expanded without replacing the main control device, significantly reducing the cost of upgrading the memory capacity. Moreover, the externally connected memory can be used not only for expanding the memory but also for functions provided by other memories such as hard disks and near-memory computing acceleration cards, thereby comprehensively improving the performance of the computer.

[0056] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings provided herein. The structure required to construct such systems will be apparent from the above description. In addition, the present invention is not directed to any particular programming language. It should be understood that the content of the present invention described herein can be implemented using various programming languages, and the description of the specific language above is for disclosing the best mode of the present invention.

[0057] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0058] Similarly, it should be understood that, for the purpose of streamlining this disclosure and aiding in the understanding of one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0059] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and arranged in one or more devices different from those embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted to combine all the features disclosed in this specification (including the abstract and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the accompanying abstract and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0060] In addition, those skilled in the art can understand that although some of the embodiments herein include certain features included in other embodiments rather than other features, the combination of the features of different embodiments means that it is within the scope of the present invention and forms different embodiments.

[0061] It should be noted that the above embodiments illustrate the present invention rather than limit the present invention. Any reference signs between parentheses should not be construed as limiting the present invention. The word "comprising" does not exclude the presence of components or steps not listed in the present invention. The word "a" or "an" before a component does not exclude the presence of a plurality of such components. The present invention can be implemented by means of hardware including several different components and by means of a suitably programmed computer. In an embodiment listing several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

Claims

1. A storage controller, characterized in that: include: A first interface, a data management module, a second interface group, an on-chip cache module and a cache interface module group, wherein the second interface group includes N second interfaces, where N is a natural number; The first interface is used to communicate with the main control component, the second interface is used to connect to an external memory, and the data management module is connected between the first interface and the second interface to obtain control instructions of the main control component and manage data storage in the memory based on the control instructions; The first interface is an open industry standard interconnection interface, the second interface includes a plurality of dedicated circuits, a general circuit and an interface circuit, each of the dedicated circuits is used to support different types of memories, the plurality of dedicated circuits are connected to the general circuit to share the function of the general circuit, and the plurality of dedicated circuits are connected to the interface circuit to share the interface circuit to achieve connection with the memory; The on-chip cache module is connected to the first interface; the cache interface module group is used for externally connecting a cache unit, and the cache unit is integrated with the storage controller through chip stacking technology, so that the speed of the main control component accessing data is arranged from fast to slow in the order of the on-chip cache module, the cache unit, and the memory; Among them, when the storage controller receives the read instruction from the main control component, it first queries the cache data in the on-chip cache module. If there is no hit, it queries the cache data in the cache unit. If there is still no hit, it queries the data in the memory.

2. The storage controller according to claim 1, wherein: The on-chip cache module is also used to cache communication data with the main control component; The on-chip cache module is connected to the data management module and stores cache data, so as to query the cache data according to the read instruction of the main control component.

3. The storage controller according to claim 1, wherein: The cache interface module group includes M cache interface modules, where M is a natural number; the cache interface module is used to externally connect to the cache unit.

4. The storage controller according to claim 1, wherein: Also includes: A data protection module is connected to the second interface group and is used for data encryption, decryption and / or error correction.

5. The storage controller according to claim 1, wherein: Also includes: A control module is connected to the data management module and is used to configure parameters of each module in the storage controller.

6. An electronic system, characterized in that: include: A main control component, a memory and a storage controller as claimed in any one of claims 1 to 5; The storage controller communicates with the main control component through the first interface and is connected to the memory through the second interface to expand the memory capacity of the electronic system.

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