Signal transmission method and device and electronic equipment

Abstract

The invention relates to a signal transmission method and device and electronic equipment, and the method comprises the steps that the electronic equipment comprises a first FPGA module and a second FPGA module, and the first FPGA module and the second FPGA module are electrically connected through a flexible circuit board. The first FPGA module is used for carrying out compression coding on multiple paths of signals to be transmitted to obtain target signals; the flexible circuit board is used for transmitting the target signal to the second FPGA module; and the second FPGA module is used for decoding the target signal to obtain multiple paths of signals. The multi-channel signals to be transmitted can be compressed and coded through the first FPGA module to obtain the target signals, that is, signal aggregation is realized in a compressed and coded manner, and the multi-channel signals are aggregated into one or a few of signals, so that the target signals can be transmitted to the second FPGA module by adopting fewer physical channels on the flexible circuit board. Therefore, the size of the flexible circuit board can be greatly reduced, and the size of the electronic equipment is further reduced.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a signal transmission method, device and electronic equipment. Background Art

[0002] With the rapid development of electronic device-related technologies, more and more electronic devices are equipped with foldable screens. Foldable screens are a branch of flexible screens, which are screens that can be bent or even twisted. When the foldable screen is in the unfolded state, it can provide users with a larger screen; and when the foldable screen is in the folded state, it can reduce the size of the electronic device, making it easier to operate with one hand or carry.

[0003] Flexible printed circuits (FPC) are foldable, bendable, and can be wired in three dimensions, so they are widely used in folding devices. Adding FPC to folding devices can transmit multiple signals between the two sides of the folding screen electronic device through the FPC. However, traditional folding devices can no longer meet the current user demand for thinner and lighter electronic devices. Summary of the invention

[0004] The embodiments of the present application provide a signal transmission method, device and electronic device, which can greatly reduce the size of the electronic device and meet the current user's demand for thinner and lighter electronic devices.

[0005] In one aspect, an electronic device is provided, the electronic device comprising a first FPGA module and a second FPGA module, the first FPGA module and the second FPGA module being electrically connected via a flexible circuit board;

[0006] The first FPGA module is used to compress and encode the multi-channel signals to be transmitted to obtain the target signal;

[0007] The flexible circuit board is used to transmit the target signal to the second FPGA module;

[0008] The second FPGA module is used to decode the target signal to obtain the multi-channel signal.

[0009] On the other hand, a signal transmission method is provided, which is applied to an electronic device, wherein the electronic device includes a first FPGA module and a second FPGA module, and the first FPGA module and the second FPGA module are electrically connected via a flexible circuit board; the method includes:

[0010] The first FPGA module compresses and encodes the multi-channel signals to be transmitted to obtain a target signal;

[0011] Transmitting the target signal to the second FPGA module through the flexible circuit board;

[0012] The target signal is decoded by the second FPGA module to obtain the multi-channel signal.

[0013] On the other hand, a signal transmission device is provided, characterized in that it is applied to an electronic device, the electronic device includes a first FPGA module and a second FPGA module, and the first FPGA module and the second FPGA module are electrically connected through a flexible circuit board; the device includes:

[0014] A signal encoding module, used for compressing and encoding the multi-channel signals to be transmitted through the first FPGA module to obtain a target signal;

[0015] A signal transmission module, used for transmitting the target signal to the second FPGA module through the flexible circuit board;

[0016] A signal decoding module is used to decode the target signal through the second FPGA module to obtain the multi-channel signal.

[0017] The electronic device of the present application includes a first FPGA module and a second FPGA module, and the first FPGA module and the second FPGA module are electrically connected through a flexible circuit board. The first FPGA module is used to compress and encode the multi-channel signals to be transmitted to obtain the target signal; the flexible circuit board is used to transmit the target signal to the second FPGA module; the second FPGA module is used to decode the target signal to obtain the multi-channel signal. Since the multi-channel signals to be transmitted can be compressed and encoded by the first FPGA module to obtain the target signal, that is, the signal aggregation is realized by compression encoding, and the multi-channel signals are aggregated into one or a few channels. Therefore, the target signal can be transmitted to the second FPGA module using fewer physical channels on the flexible circuit board. Then, the size of the flexible circuit board can be greatly reduced, and then the volume of the folding structure can be reduced, thereby greatly reducing the size of the electronic device, meeting the current user's demand for thin and light electronic devices. Finally, the target signal is decoded by the second FPGA module, and the target signal is restored to the multi-channel signal sent by the signal sending end, and distributed to the signal receiving end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations. Therefore, the electronic device can compress and encode the multi-channel signals to be transmitted through the first FPGA module, and then transmit them to the second FPGA module through the flexible circuit board, and the second FPGA module decodes them. This ensures the accuracy of signal transmission while greatly reducing the size of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a schematic diagram of the internal structure of an electronic device in one embodiment;

[0020] Figure 2 for Figure 1 A schematic diagram of the structure of the first FPGA module and the second FPGA module;

[0021] Figure 3 for Figure 2 A schematic diagram of the structure of a first encoding path in the first FPGA module and a first decoding path in the second FPGA module;

[0022] Figure 4 for Figure 2 A schematic diagram of the structure of a second encoding path in the first FPGA module and a second decoding path in the second FPGA module;

[0023] Figure 5 A schematic diagram of an application processor of an electronic device sending multiple signals to a first FPGA module in one embodiment;

[0024] Figure 6 A schematic diagram of a structure in which firmware is burned into a first flash memory chip and a second flash memory chip by an application processor in one embodiment;

[0025] Figure 7 A schematic diagram of a load circuit sending multiple signals to a first FPGA module in one embodiment;

[0026] Figure 8 is a schematic structural diagram of a signal transmission path in an exemplary embodiment;

[0027] Fig. 9 is a schematic diagram of the structure of a signal transmission path in an embodiment;

[0028] Fig.10 is a flow chart of a signal transmission method in one embodiment;

[0029] Fig.11 A schematic diagram of a packet structure for transmitting data between a first FPGA module and a second FPGA module;

[0030] Fig.12 is a structural block diagram of a signal transmission device in one embodiment;

[0031] Fig.13 FIG. 1 is a schematic diagram of the internal structure of an electronic device in an embodiment. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] It is understood that the terms "first", "second", etc. used in this application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of this application, the first FPGA module can be called the second FPGA module, and similarly, the second FPGA module can be called the first FPGA module. Both the first FPGA module and the second FPGA module are FPGA modules, but they are not the same FPGA module. Among them, the full name of FPGA in English is Field Progammable Gate Array, that is, field programmable gate array.

[0034] With the rapid development of technologies related to electronic devices, more and more electronic devices are equipped with folding screens, which are screens that can be bent or even twisted. When the folding screen is in the unfolded state, it can provide users with a larger screen; and when the folding screen is in the folded state, it can reduce the size of the electronic device, making it easier to operate with one hand or carry. FPC flexible circuit boards have the characteristics of being foldable, bendable, and three-dimensionally wired, so FPC flexible circuit boards are widely used in folding devices. Adding FPC flexible circuit boards to folding devices can realize the transmission of multiple signals through the FPC flexible circuit boards. However, FPC flexible circuit boards are wider and larger in size, resulting in traditional folding devices being unable to meet the current user demand for thinner and lighter electronic devices.

[0035] Traditionally, the FPC on the folding device can be made thinner by transmitting multiple signals through the FPC by switching and time-division multiplexing, but this method has the problem that multiple signals cannot be transmitted simultaneously. The FPC on the folding device can also be made thinner by reducing the width of the traces on the FPC, but this method has the problem that the FPC may break due to long-term folding use. The FPC on the folding device can also be made thinner by increasing the number of layers of the FPC, but this method has the problem of not meeting the thinning requirements.

[0036] In order to solve the problem that traditional folding devices can no longer meet the current user's demand for thin and light electronic devices, in one embodiment, the present application proposes an electronic device 10, such as Figure 1 As shown, the electronic device 10 includes a first FPGA module 122 and a second FPGA module 142, and the first FPGA module 122 and the second FPGA module 142 are electrically connected via a flexible circuit board 160. The first FPGA module 122 is used to compress and encode the multi-channel signals to be transmitted to obtain the target signal; the flexible circuit board 160 is used to transmit the target signal to the second FPGA module 142; and the second FPGA module 142 is used to decode the target signal to obtain the multi-channel signal.

[0037] Optionally, the electronic device 10 includes a first housing 12, a folding mechanism 16 and a second housing 14. The folding mechanism 16 can be deformed so that the first housing 12 and the second housing 14 can be relatively unfolded or relatively folded, wherein the folding mechanism 16 can be at least one of a shaft structure, a gear structure, a hinge structure, a slider structure, a slide groove structure, a pin structure, a connecting rod structure, a swing rod structure, a slide rod structure, an elastic material, and a memory alloy material, which is not limited in the present application. For example, Figure 1 The middle folding mechanism 16 includes a rotating shaft structure 162 and a hinge structure 164 .

[0038] The electronic device 10 further includes a flexible circuit board 160, a first circuit board 120, and a second circuit board 140. The first circuit board 120 is disposed in the first housing 12, the second circuit board 140 is disposed in the second housing 14, the first circuit board 120 includes a first FPGA module 122, and the second circuit board 140 includes a second FPGA module 142. The flexible circuit board 160 runs through the folding mechanism 16 to connect the first FPGA module 122 and the second FPGA module 142, thereby achieving signal conduction between the first FPGA module 122 and the second FPGA module 142. For example, the first FPGA module 122 can send multiple signals to the second FPGA module 142 through the flexible circuit board 160, or the second FPGA module 142 can send multiple signals to the first FPGA module 122 through the flexible circuit board 160. Optionally, the flexible circuit board 160 can be a single-sided board, a double-sided board, or a multi-layer board, which is not limited in this application.

[0039] Here, the multi-channel signal transmitted by the flexible circuit board 160 may be a multi-channel digital signal, but is not limited thereto, and may also be a multi-channel analog signal, and of course, this application does not limit this. The following description is made by taking the transmission of a multi-channel digital signal by the flexible circuit board 160 as an example. When the flexible circuit board 160 is used to transmit a multi-channel digital signal, the multi-channel digital signal may include a digital signal generated by a processor and / or a functional circuit, and sent to a corresponding functional circuit or processor to realize signal transmission between the processor and the functional circuit.

[0040] First, the multi-channel signal to be transmitted is compressed and encoded by the first FPGA module 122 to obtain a target signal. Since the target signal is a signal obtained by compressing and encoding the multi-channel signal to be transmitted, it is obvious that the number of physical channels required to transmit the target signal is less than the number of physical channels required to transmit the multi-channel signal. For example, under normal circumstances, the number of multi-channel signals to be transmitted can reach 40 channels, and the first FPGA module 122 is used to compress and encode the multi-channel signal to be transmitted. The obtained target signal includes one signal or a preset number of signals, and the preset number is less than 40 channels. Among them, under normal circumstances, when transmitting signals through the flexible circuit board 160, for each signal, it is necessary to use a physical channel on the flexible circuit board 160 for transmission. At this time, fewer physical channels on the flexible circuit board 160 can be used to transmit the target signal.

[0041] The physical channels are arranged on the flexible circuit board 160, and the number of the physical channels is positively correlated with the size of the flexible circuit board 160, so the reduction of the physical channels also reduces the size (e.g., width and / or thickness) of the flexible circuit board 160. Therefore, the target signal can be transmitted to the second FPGA module 142 based on the flexible circuit board 160 with a smaller size (thinner and / or narrower).

[0042] Finally, the target signal is decoded by the second FPGA module 142 and restored to the multi-channel signal sent by the signal sending end. Optionally, the target signal (including one channel of signal or a preset number of signals) can be decoded by the second FPGA module 142 and restored to 40 channels of signals sent by the signal sending end.

[0043] In the embodiment of the present application, the first FPGA module 122 can compress and encode the multi-channel signals to be transmitted to obtain the target signal, that is, the signal aggregation is realized by compression encoding, and the multi-channel signals are aggregated into one or a few channels of signals. Therefore, the target signal can be transmitted to the second FPGA module 142 using fewer physical channels on the flexible circuit board 160. Then, the size of the flexible circuit board 160 can be greatly reduced, and the volume of the folding structure can be reduced, thereby greatly reducing the size of the electronic device 10, meeting the current user's demand for thinness of the electronic device 10. Finally, the target signal is decoded by the second FPGA module 142, and the target signal is restored to the multi-channel signal sent by the signal sending end, and distributed to the signal receiving end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations. Therefore, the electronic device 10 can compress and encode the multi-channel signal to be transmitted through the first FPGA module 122, and then transmit it to the second FPGA module 142 through the flexible circuit board 160, and the second FPGA module 142 decodes it, thereby ensuring the accuracy of signal transmission while greatly reducing the size of the electronic device 10.

[0044] In one embodiment, Figure 2 As shown, the first FPGA module 122 includes a first encoding path 122a and a second encoding path 122b; the first encoding path 122a is used to compress and encode multiple non-protocol signals in the multiple signals to be transmitted to obtain target non-protocol signals; the second encoding path 122b is used to compress and encode multiple protocol signals in the multiple signals to be transmitted to obtain target protocol signals.

[0045] Optionally, the multi-channel signal to be transmitted may include multiple non-protocol signals and / or multiple protocol signals. Among them, the non-protocol signal includes a GPIO (general porpose input output) signal. Of course, the present application does not limit this. Therefore, if the multi-channel signal to be transmitted includes multiple non-protocol signals, the multiple non-protocol signals in the multi-channel signal to be transmitted can be compressed and encoded through the first encoding path 122a to obtain the target non-protocol signal. For example, if the multiple non-protocol signals include multiple GPIO signals, the multiple GPIO signals can be compressed and encoded through the first encoding path 122a to obtain the target non-protocol signal. Here, the target non-protocol signal includes one non-protocol signal or a preset number of non-protocol signals. Of course, the number of physical channels required to transmit the target non-protocol signal is less than the number of physical channels required to transmit the multiple non-protocol signals.

[0046] The protocol class signal includes at least one of an I2C signal, an SPI signal, an I2S signal, an RFEE signal, and an I3C signal. Of course, the present application does not limit this. Therefore, if the multi-channel signal to be transmitted includes a multi-channel protocol class signal, the multi-channel protocol class signal in the multi-channel signal to be transmitted can be compressed and encoded through the second encoding path 122b to obtain a target protocol signal. For example, if the multi-channel protocol class signal includes a multi-channel I2C signal, the multi-channel I2C signal can be compressed and encoded through the second encoding path 122b to obtain a target protocol signal. For example, if the multi-channel protocol class signal includes a multi-channel I2C signal and a multi-channel SPI signal, the second encoding path 122b includes a second encoding path corresponding to the I2C signal and a second encoding path corresponding to the SPI signal. Then, the multi-channel I2C signal can be compressed and encoded through the second encoding path corresponding to the I2C signal to obtain the target protocol signal; the multi-channel SPI signal can be compressed and encoded through the second encoding path corresponding to the SPI signal to obtain the target protocol signal. Here, the target protocol signal includes one protocol signal or a preset number of protocol signals. Of course, the number of physical channels required to transmit the target protocol signal is less than the number of physical channels required to transmit multiple protocol signals.

[0047] In the embodiment of the present application, for the multi-channel non-protocol signals in the multi-channel signals to be transmitted, compression encoding can be performed through the first encoding path 122a to obtain the target non-protocol signal, and the number of physical channels required for transmitting the target non-protocol signal is less than the number of physical channels required for transmitting the multi-channel non-protocol signal; for the multi-channel protocol signals in the multi-channel signals to be transmitted, compression encoding can be performed through the second encoding path 122b to obtain the target protocol signal, and the number of physical channels required for transmitting the target protocol signal is less than the number of physical channels required for transmitting the multi-channel protocol signal. In this way, the target non-protocol signal and the target protocol signal can be transmitted to the second FPGA module 142 using fewer physical channels on the flexible circuit board 160. Then, the size of the flexible circuit board 160 can be greatly reduced, and then the volume of the folding structure can be reduced, thereby greatly reducing the size of the electronic device 10, meeting the current user's demand for thin and light electronic devices 10.

[0048] In one embodiment, Figure 3 As shown, the first encoding path 122a includes a first register and a first controller; the first register is connected to the first controller, and the first controller is connected to the second FPGA module 142; the first register is used to receive and store multiple non-protocol signals; the first controller is used to read multiple non-protocol signals from the first register, and compress and encode the multiple non-protocol signals to obtain target non-protocol signals, and transmit the target non-protocol signals to the second FPGA module 142.

[0049] Combination Figure 3 As shown, the first FPGA module 122 includes a first receiving end RX (receive) and a first transmitting end TX (transport) for transmitting non-protocol signals, one end of the first register is connected to the upstream end of the first FPGA module 122 (the first receiving end RX of the first FPGA module 122), and the other end of the first register is connected to the first controller. One end of the first controller is connected to the downstream end of the first FPGA module 122 (the first transmitting end TX of the first FPGA module 122), and the first transmitting end TX is connected to the first receiving end RX of the second FPGA module 142.

[0050] When compressing and encoding the multiple non-protocol signals in the multiple signals to be transmitted through the first encoding path 122a, firstly, the multiple non-protocol signals are received and stored from the first receiving end RX of the first FPGA module 122 through the first register. Secondly, the multiple non-protocol signals are read from the first register through the first controller, and the multiple non-protocol signals are compressed and encoded to obtain the target non-protocol signal, and the target non-protocol signal is transmitted to the first receiving end RX of the second FPGA module 142 through the first transmitting end TX of the first FPGA module 122.

[0051] Here, the target non-protocol signal includes TX_CLK and TX_data, of course, this application does not limit this. Among them, TX_CLK is a continuous clock signal (that is, the signal always exists when the system is started), TX_CLK is the reference clock signal from RS (Reconciliation sublayer) to PHY (physical layer interface); TX_data represents the transmitted data.

[0052] The above embodiment can use fewer physical channels on the flexible circuit board 160 to transmit the target non-protocol signal to the second FPGA module 142. Then, the size of the flexible circuit board 160 can be greatly reduced, thereby reducing the volume of the folding structure, thereby greatly reducing the size of the electronic device 10, and meeting the current user's demand for thin and light electronic devices 10.

[0053] In one embodiment, Figure 4As shown, the second encoding path 122b includes a first protocol parsing unit, a second register and a second controller; the first protocol parsing unit is connected to the second register, the second register is connected to the second controller, and the second controller is connected to the second FPGA module 142; the first protocol parsing unit is used to receive multiple protocol signals, and perform protocol parsing on the multiple protocol signals to obtain multiple signals after protocol parsing, and transmit the multiple signals after protocol parsing to the second register; the second register is used to receive and store the multiple signals after protocol parsing; the second controller is used to read the multiple signals after protocol parsing from the second register, and compress and encode the multiple signals after protocol parsing to obtain the target protocol signal, and transmit the target protocol signal to the second FPGA module 142.

[0054] Combination Figure 4 As shown, the first FPGA module 122 includes a second receiving end RX and a second transmitting end TX for transmitting protocol class signals. One end of the first protocol parsing unit is connected to the upstream end of the first FPGA module 122 (the second receiving end RX or the second transmitting end TX of the first FPGA module 122), the other end of the first protocol parsing unit is connected to the second register, the second register is connected to the second controller, the second controller is connected to the downstream end of the first FPGA module 122 (the second transmitting end TX or the second receiving end RX of the first FPGA module 122), and the downstream end is further connected to the upstream end of the second FPGA module 142 (the first receiving end RX or the first transmitting end TX of the second FPGA module 142).

[0055] When compressing and encoding the multi-channel protocol signals in the multi-channel signals to be transmitted through the second encoding path 122b, first, the multi-channel protocol signals are received from the upstream end of the first FPGA module 122 through the first protocol parsing unit, and the multi-channel protocol signals are parsed to obtain the multi-channel signals after the protocol parsing, and the multi-channel signals after the protocol parsing are transmitted to the second register. Secondly, the multi-channel signals after the protocol parsing are received and stored through the second register. Finally, the multi-channel signals after the protocol parsing are read from the second register through the second controller, and the multi-channel signals after the protocol parsing are compressed and encoded to obtain the target protocol signal, and the target protocol signal is transmitted to the upstream end of the second FPGA module 142 through the downstream end of the first FPGA module 122.

[0056] Here, the target protocol signal includes TX_CLK and TX_data, and of course, this application does not limit this. Among them, TX_CLK is a continuous clock signal (that is, the signal always exists when the system is started), TX_CLK is the reference clock signal from RS (Reconciliation sublayer) to PHY (physical layer interface); TX_data represents the transmitted data.

[0057] The above embodiment can use fewer physical channels on the flexible circuit board 160 to transmit the target protocol signal to the second FPGA module 142. Then, the size of the flexible circuit board 160 can be greatly reduced, thereby reducing the volume of the folding structure, thereby greatly reducing the size of the electronic device 10, and meeting the current user's demand for thin and light electronic devices 10.

[0058] In one embodiment, in combination Figure 2 As shown, the second FPGA module 142 includes a first decoding path 142a and a second decoding path 142b; the first encoding path 122a is connected to the first decoding path 142a through the flexible circuit board 160, and the second encoding path 122b is connected to the second decoding path 142b through the flexible circuit board 160; the first decoding path 142a is used to decode the target non-protocol signal to obtain multiple non-protocol signals; the second decoding path 142b is used to decode the target protocol signal to obtain multiple protocol signals.

[0059] Combination Figure 2 As shown, the first FPGA module 122 includes a first encoding path 122a and a second encoding path 122b, and also includes a first decoding path 142a and a second decoding path 142b. The first encoding path 122a is connected to the first decoding path 142a through a flexible circuit board 160, and the second encoding path 122b is connected to the second decoding path 142b through a flexible circuit board 160.

[0060] If the multi-channel signals to be transmitted may include multi-channel non-protocol signals, the multi-channel non-protocol signals in the multi-channel signals to be transmitted may be compressed and encoded through the first encoding path 122a to obtain the target non-protocol signals. Then, the first encoding path 122a sends the target non-protocol signals to the first decoding path 142a through the flexible circuit board 160, and the target non-protocol signals may be decoded through the first decoding path 142a to obtain the multi-channel non-protocol signals.

[0061] Among them, non-protocol signals include GPIO signals, and of course, this application does not limit this. For example, if multiple non-protocol signals include multiple GPIO signals, the multiple GPIO signals can be compressed and encoded through the first encoding path 122a to obtain the target non-protocol signal. Then, the first encoding path 122a sends the target non-protocol signal to the first decoding path 142a through the flexible circuit board 160, and the target non-protocol signal can be decoded through the first decoding path 142a to obtain multiple GPIO signals.

[0062] If the multi-channel signal to be transmitted may include a multi-channel protocol signal, the multi-channel protocol signal in the multi-channel signal to be transmitted may be compressed and encoded through the second encoding path 122b to obtain a target protocol signal. Then, the second encoding path 122b sends the target protocol signal to the second decoding path 142b through the flexible circuit board 160, and the target protocol signal may be decoded through the second decoding path 142b to obtain a multi-channel protocol signal.

[0063] Among them, the protocol signal includes at least one of an I2C signal, an SPI signal, an I2S signal, an RFEE signal, and an I3C signal. Of course, this application does not limit this. For example, if the multi-channel protocol signal includes multiple I2C signals or multiple SPI signals, the second encoding path 122b includes a second encoding path 122b corresponding to the I2C signal or a second encoding path 122b corresponding to the SPI signal. Then, the multiple I2C signals can be compressed and encoded by the second encoding path 122b corresponding to the I2C signal to obtain the target protocol signal; or, the multiple SPI signals can be compressed and encoded by the second encoding path 122b corresponding to the SPI signal to obtain the target protocol signal. Then, the second encoding path 122b sends the target protocol signal to the second decoding path 142b through the flexible circuit board 160, and the target protocol signal can be decoded by the second decoding path 142b to obtain multiple I2C signals or multiple SPI signals.

[0064] In the embodiment of the present application, the first decoding path 142a is used to restore the target non-protocol signal to the multi-channel non-protocol signal sent by the signal sending end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations. Similarly, for the multi-channel protocol signal in the multi-channel signal to be transmitted, the second encoding path 122b can be used for compression encoding to obtain the target non-protocol signal. Then, the target protocol signal is decoded by the second decoding path 142b to obtain the multi-channel protocol signal. In this way, the target protocol signal is restored to the multi-channel protocol signal sent by the signal sending end through the second decoding path 142b, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations.

[0065] In one embodiment, Figure 3 As shown, the first decoding path 142a includes a third register and a third controller; the third register is connected to the first FPGA module and the third controller respectively; the third register is used to receive and store the target non-protocol signal from the first FPGA module 122; the third controller is used to read the target non-protocol signal from the third register, and decode the target non-protocol signal to obtain multiple non-protocol signals.

[0066] Combination Figure 3As shown, the second FPGA module 142 includes a first receiving terminal RX and a first transmitting terminal TX for transmitting non-protocol signals. One end of the third register is connected to the first receiving terminal RX of the second FPGA module 142, and the other end of the third register is connected to the third controller; one end of the third controller is connected to the first transmitting terminal TX of the second FPGA module 142.

[0067] When decoding the target non-protocol signal through the first decoding path 142a, first, the target non-protocol signal is received and stored from the first FPGA module 122 through the third register. Secondly, the third controller is used to read the target non-protocol signal from the first register and decode the target non-protocol signal to obtain multiple non-protocol signals.

[0068] The above embodiment can use fewer physical channels on the flexible circuit board 160 to transmit the target non-protocol signal to the second FPGA module 142. Then, the target non-protocol signal is decoded through the first decoding path 142a in the second FPGA module 142, and the target non-protocol signal is restored to the multi-channel non-protocol signal sent by the signal sending end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations.

[0069] In one embodiment, Figure 4 As shown, the second decoding path 142b includes a second protocol parsing unit, a fourth register and a fourth controller; the fourth controller is respectively connected to the first FPGA module 122 and the fourth register, and the fourth register is connected to the second protocol parsing unit; the fourth controller is used to receive the target protocol signal from the first FPGA module 122, and decode the target protocol signal to obtain multiple protocol signals; the fourth register is used to receive and store multiple protocol signals; the second protocol parsing unit is used to read multiple protocol signals from the fourth register, and perform protocol parsing on the multiple protocol signals to obtain multiple signals after protocol parsing.

[0070] Combination Figure 4 As shown, the second FPGA module 142 includes a second receiving end RX and a second transmitting end TX for transmitting protocol signals. One end of the fourth controller is connected to the upstream end of the second FPGA module 142 (the second receiving end RX or the second transmitting end TX of the second FPGA module 142), and the upstream end of the second FPGA module 142 is connected to the downstream end of the first FPGA module 122 (the second transmitting end TX or the second receiving end RX of the first FPGA module 122). The other end of the fourth controller is connected to the fourth register, and the fourth register is connected to the second protocol parsing unit, and the second protocol parsing unit is connected to the signal receiving end through the downstream end of the second FPGA module 142 (the second receiving end RX or the second transmitting end TX of the second FPGA module 142).

[0071] When decoding the target protocol signal through the second decoding path 142b, first, the fourth controller is used to receive the target protocol signal from the first FPGA module 122, and decode the target protocol signal to obtain a multi-channel protocol signal. Secondly, the fourth register is used to receive and store the multi-channel protocol signal. Finally, the second protocol parsing unit is used to read the multi-channel protocol signal from the fourth register, and perform protocol parsing on the multi-channel protocol signal to obtain the multi-channel signal after protocol parsing.

[0072] In the embodiment of the present application, for the multi-channel protocol signals in the multi-channel signals to be transmitted, the second protocol parsing unit, the fourth register and the fourth controller in the second decoding path 142b can be compressed and decoded to obtain the target protocol signal. And the number of physical channels required to transmit the target protocol signal is less than the number of physical channels required to transmit the multi-channel protocol signals. In this way, the target protocol signal can be transmitted to the second FPGA module 142 using fewer physical channels on the flexible circuit board 160.

[0073] Then, the target protocol signal is decoded through the second decoding path 142b in the second FPGA module 142, and the target protocol signal is restored to the multi-channel protocol type signal sent by the signal sending end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations.

[0074] In one embodiment, the electronic device also includes an application processor or a load circuit, which is electrically connected to the first FPGA module; the multiple signals to be transmitted include multiple non-protocol signals and / or multiple protocol signals; the application processor or the load circuit is used to send multiple non-protocol signals and / or multiple protocol signals to the first FPGA module; the multiple protocol signals include preset format data and empty packet format data after the preset format data.

[0075] Combination Figure 5As shown, it is a schematic diagram of an application processor (Application Processor) 124 in an electronic device 10 sending multiple signals to a first FPGA module 122. The electronic device 10 includes a first FPGA module 122, a second FPGA module 142, and an application processor 124. The application processor 124 is electrically connected to the upstream end of the first FPGA module 122, and sends multiple signals to be transmitted to the upstream end of the first FPGA module 122 through the application processor 124, and the multiple signals to be transmitted include multiple non-protocol signals and / or multiple protocol signals. The application processor 124 controls the GPIO load through the GPIO host driver, or the application processor 124 controls the I2C / SPI load through the I2C / SPI host driver. Among them, the multiple protocol signals include preset format data and empty packet format data after the preset format data. That is, multiple non-protocol signals and multiple protocol signals can be sent to the upstream end of the first FPGA module 122 through the application processor 124.

[0076] Since in the process of compressing and encoding the multi-channel protocol class signal to be transmitted by the first FPGA module 122 to obtain the target signal, there is a delay problem compared to the process in which the signal sending end (for example, the application processor 124) directly sends the multi-channel protocol class signal to the signal receiving end (for example, the load circuit 126), and then receives the data returned by the signal receiving end, therefore, the preset format data of the multi-channel protocol class signal can be processed with empty packets, that is, the empty packet format data is added after the preset format data. For example, a dummy bit (pseudo bit) of a preset duration is sent after the preset format data. Among them, the preset format data includes the signal content of the multi-channel protocol class signal. In this way, in the case of delay in compressing and encoding the multi-channel protocol class signal to be transmitted by the first FPGA module 122, because the multi-channel protocol class signal includes the empty packet format data, the signal sending end can wait for the multi-channel protocol class signal returned by the signal receiving end based on the gap of the empty packet format data, that is, delay decoding is realized, so the signal sending end is guaranteed to receive the complete data returned by the signal receiving end through delay decoding.

[0077] Optionally, the application processor 124 may be connected to the upstream end of the first FPGA module 122, and send multiple non-protocol signals and / or multiple protocol signals to the upstream end of the first FPGA module 122. If the application processor 124 sends multiple non-protocol signals to the upstream end of the first FPGA module 122, then the upstream end of the first FPGA module 122 includes the first receiving end RX of the first FPGA module 122. If the application processor 124 sends multiple protocol signals to the upstream end of the first FPGA module 122, then the upstream end of the first FPGA module 122 includes the second receiving end RX or the second transmitting end TX of the first FPGA module 122.

[0078] Combination Figure 7 As shown, it is a schematic diagram of a load circuit 126 of an electronic device 10 sending multiple signals to a first FPGA module 122 in an embodiment. The electronic device 10 includes a first FPGA module 122, a second FPGA module 142, and a load circuit 126. The load circuit 126 is electrically connected to the upstream end of the first FPGA module 122, and multiple signals to be transmitted are sent to the upstream end of the first FPGA module 122 through the load circuit 126, and the multiple signals to be transmitted include multiple non-protocol signals and / or multiple protocol signals. Among them, the multiple protocol signals include preset format data and empty packet format data after the preset format data. That is, multiple non-protocol signals and multiple protocol signals can be sent to the upstream end of the first FPGA module 122 through the load circuit 126.

[0079] In the embodiment of the present application, because the multi-channel protocol signal includes empty packet format data, the signal sending end can wait for the multi-channel protocol signal returned by the signal receiving end based on the gaps in the empty packet format data, that is, delayed decoding is realized. Therefore, delayed decoding ensures that the signal sending end can receive the complete data returned by the signal receiving end.

[0080] In one embodiment, the first FPGA module 122 includes a first flash memory chip, the second FPGA module 142 includes a second flash memory chip, and the application processor 124 is further used to burn firmware into the first flash memory chip and the second flash memory chip.

[0081] Combination Figure 6As shown, it is a structural schematic diagram of burning firmware into the first flash memory chip and the second flash memory chip through the application processor 124 in one embodiment. The electronic device 10 includes a first FPGA module 122, a second FPGA module 142, and an application processor 124, and the application processor 124 is electrically connected to the first FPGA module 122 and the second FPGA module 142 respectively. The first FPGA module 122 includes a first flash memory chip (flash), and the second FPGA module 142 includes a second flash memory chip (flash). Among them, the first FPGA module 122 can be a first FPGA chip (FPGA#1), and the second FPGA module 142 can be a second FPGA chip (FPGA#2).

[0082] When the application processor 124 is in AP mode, it can output a high level, so that the first FPGA chip (FPGA#1) and the second FPGA chip (FPGA#2) are powered on. Then, the AP can burn the firmware to the first flash chip (flash). Secondly, the AP burns the SRAM (static random access memory) of the first FPGA chip, so that the first FPGA chip enters the transparent transmission mode. Here, the first FPGA chip (FPGA#1) enters the transparent transmission mode, which means that the first FPGA chip (FPGA#1) is in a pass-through state, which is equivalent to connecting the AP and the second FPGA chip (FPGA#2) through the first FPGA chip (FPGA#1). Finally, the AP can burn the firmware to the second flash chip of the second FPGA chip through the first FPGA chip.

[0083] In the embodiment of the present application, the first FPGA module 122 includes a first flash memory chip, the second FPGA module 142 includes a second flash memory chip, and the application processor 124 is also used to burn firmware into the first flash memory chip and the second flash memory chip. Here, the firmware is used to instruct the electronic device 10 to compress and encode the multi-channel signals to be transmitted through the first FPGA module 122 to obtain the target signal; transmit the target signal to the second FPGA module 142 through the flexible circuit board 160; and decode the target signal through the second FPGA module 142 to obtain the multi-channel signal. In this way, by burning the firmware into the first flash memory chip and the second flash memory chip, new functions are added to the first flash memory chip and the second flash memory chip, so that the first FPGA module 122 and the second FPGA module 142 can realize the compression encoding and decoding functions of the multi-channel signals to be transmitted.

[0084] In one embodiment, the electronic device 10 also includes a load circuit 126, which is electrically connected to the first FPGA module 122; the multiple signals to be transmitted include multiple non-protocol signals and / or multiple protocol signals; the load circuit 126 is used to send multiple non-protocol signals and / or multiple protocol signals to the first FPGA module 122; the multiple protocol signals include preset format data and empty packet format data after the preset format data.

[0085] Combination Figure 7 As shown, it is a schematic diagram of a load circuit 126 of an electronic device 10 sending multiple signals to a first FPGA module 122 in an embodiment. The electronic device 10 includes a first FPGA module 122, a second FPGA module 142, and a load circuit 126. The load circuit 126 is electrically connected to the upstream end of the first FPGA module 122, and multiple signals to be transmitted are sent to the upstream end of the first FPGA module 122 through the load circuit 126, and the multiple signals to be transmitted include multiple non-protocol signals and / or multiple protocol signals. Among them, the multiple protocol signals include preset format data and empty packet format data after the preset format data. That is, multiple non-protocol signals and multiple protocol signals can be sent to the upstream end of the first FPGA module 122 through the load circuit 126.

[0086] Since there is a delay in the process of compressing and encoding the multi-channel protocol signals to be transmitted by the first FPGA module 122 to obtain the target signal, compared with the process in which the signal transmitting end directly sends the multi-channel protocol signals to the signal receiving end and then receives the data returned by the signal receiving end, the preset format data of the multi-channel protocol signals can be processed with empty packets, that is, the empty packet format data is added after the preset format data. Among them, the preset format data includes the signal content of the multi-channel protocol signals. In this way, in the case where there is a delay in compressing and encoding the multi-channel protocol signals to be transmitted by the first FPGA module 122, because the multi-channel protocol signals include the empty packet format data, the signal transmitting end can wait for the multi-channel protocol signals returned by the signal receiving end based on the gap of the empty packet format data, that is, delayed decoding is realized. Therefore, the signal transmitting end is guaranteed to receive the complete data returned by the signal receiving end through delayed decoding.

[0087] Optionally, the load circuit 126 may be connected to the upstream end of the first FPGA module 122, and send multiple non-protocol signals and / or multiple protocol signals to the upstream end of the first FPGA module 122. If the load circuit 126 sends multiple non-protocol signals to the upstream end of the first FPGA module 122, then the upstream end of the first FPGA module 122 includes the first receiving end RX of the first FPGA module 122. If the load circuit 126 sends multiple protocol signals to the upstream end of the first FPGA module 122, then the upstream end of the first FPGA module 122 includes the second receiving end RX or the second transmitting end TX of the first FPGA module 122.

[0088] In the embodiment of the present application, because the multi-channel protocol signal includes empty packet format data, the signal sending end can wait for the multi-channel protocol signal returned by the signal receiving end based on the gaps in the empty packet format data, that is, delayed decoding is realized. Therefore, delayed decoding ensures that the signal sending end can receive the complete data returned by the signal receiving end.

[0089] In one embodiment, Figure 8 , which is a schematic diagram of the structure of a signal transmission path in an exemplary embodiment. The second FPGA module 142 also includes a third encoding path 142c; the third encoding path 142c is used to compress and encode multiple non-protocol signals in the multiple signals to be transmitted by the GPIO load circuit to obtain a second target non-protocol signal; the second target non-protocol signal is a second target signal corresponding to the multiple non-protocol signals.

[0090] The third encoding path 142c includes a fifth controller and a fifth register; the fifth register is connected to the fifth controller, and the fifth controller is connected to the first FPGA module 122. The fifth register is used to receive and store multiple non-protocol signals. The fifth controller is used to read multiple non-protocol signals from the fifth register, compress and encode the multiple non-protocol signals, obtain a second target non-protocol signal, and transmit the second target non-protocol signal to the first FPGA module 122.

[0091] The electronic device 10 further includes an application processor 124 or a load circuit 126, and the application processor 124 or the load circuit 126 is electrically connected to the second FPGA module 142, and is used to send the multi-channel signal to be transmitted to the second FPGA module 142. Figure 8As shown, it is a schematic diagram that the load circuit 126 is electrically connected to the second FPGA module 142, and the load circuit 126 is used to send the multi-channel signals to be transmitted to the second FPGA module 142. On the other hand, the application processor 124 can also be electrically connected to the second FPGA module 142, and the application processor 124 is used to send the multi-channel signals to be transmitted to the second FPGA module 142. For this case, no corresponding schematic diagram is provided.

[0092] The first FPGA module 122 also includes a third decoding path 122c; the third decoding path 122c is used to decode the second target non-protocol signal to obtain multiple non-protocol signals. Among them, the third decoding path 122c includes a sixth register and a sixth controller; the sixth register is connected to the sixth controller, and the sixth register is connected to the second FPGA module. The sixth register is used to receive and store the second target non-protocol signal. The sixth controller is used to read the second target non-protocol signal from the sixth register, and decode the second target non-protocol signal to obtain multiple non-protocol signals, and transmit the multiple non-protocol signals to the application processor 124.

[0093] In the embodiment of the present application, since the second FPGA module 142 can compress and encode the multi-channel signals to be transmitted to obtain the target signal, the target signal can be transmitted to the first FPGA module 122 using fewer physical channels on the flexible circuit board 160. Then, the size of the flexible circuit board 160 can be greatly reduced, and the volume of the folding structure can be reduced, thereby greatly reducing the size of the electronic device 10, meeting the current user's demand for thinness of the electronic device 10. Finally, the target signal is decoded by the first FPGA module 122, and the target signal is restored to the multi-channel signal sent by the signal sending end, and distributed to the signal receiving end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations. Therefore, the electronic device 10 can compress and encode the multi-channel signal to be transmitted through the second FPGA module 142, and then transmit it to the first FPGA module 122 through the flexible circuit board 160, and the first FPGA module 122 decodes it, thereby ensuring the accuracy of signal transmission while greatly reducing the size of the electronic device 10.

[0094] On the contrary, the first FPGA module 122 can also compress and encode the multi-channel signals to be transmitted to obtain the target signal, and then use fewer physical channels on the flexible circuit board 160 to transmit the target signal to the second FPGA module 142. Finally, the second FPGA module 142 decodes the target signal, restores the target signal to the multi-channel signal sent by the signal sending end, and distributes it to the signal receiving end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations.

[0095] Fig. 9 FIG. 1 is a schematic diagram of the structure of a signal transmission path in an embodiment. Fig. 9 As shown, the electronic device includes a first FPGA module 122 and a second FPGA module 142, and the first FPGA module 122 and the second FPGA module 142 are electrically connected through a flexible circuit board (not shown). The electronic device compresses and encodes the multi-channel signals to be transmitted through the first FPGA module 122 to obtain a target signal; transmits the target signal to the second FPGA module 142 through the flexible circuit board 160; and decodes the target signal through the second FPGA module 142 to obtain a multi-channel signal. Conversely, the electronic device can compress and encode the multi-channel signals to be transmitted through the second FPGA module 142 to obtain a target signal, and transmit the target signal to the first FPGA module 122 using fewer physical channels on the flexible circuit board 160. Finally, the target signal is decoded through the first FPGA module 122 to restore the target signal to a multi-channel signal sent by the signal transmitting end. Among them, the electronic device can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices, and the Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart vehicle-mounted devices, smart cars, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0096] Fig.10 FIG. 1 is a flow chart of a signal transmission method in one embodiment. Fig. 9 As shown, the electronic device includes a first FPGA module 122 and a second FPGA module 142, an application processor 124 and a load circuit 126, the application processor 124 is connected to the first FPGA module 122, the first FPGA module 122 and the second FPGA module 142 are electrically connected via a flexible circuit board (not shown), and the second FPGA module 142 is connected to the load circuit 126. Fig.10 As shown, the signal transmission method includes steps 1020 to 1060, wherein:

[0097] Step 1020: compress and encode the multi-channel signals to be transmitted through the first FPGA module to obtain a target signal.

[0098] First, the first FPGA module 122 is used to compress and encode the multi-channel signals to be transmitted sent by the application processor 124 to obtain a target signal. Since the target signal is a signal obtained by compressing and encoding the multi-channel signals to be transmitted, it is obvious that the number of physical channels required to transmit the target signal is less than the number of physical channels required to transmit the multi-channel signals. For example, under normal circumstances, the number of multi-channel signals to be transmitted can reach 40 channels. The first FPGA module 122 is used to compress and encode the multi-channel signals to be transmitted. The obtained target signal includes one signal or a preset number of signals, and the preset number is less than 40 channels. Under normal circumstances, when transmitting signals through the flexible circuit board 160, each signal needs to be transmitted using a physical channel on the flexible circuit board 160. At this time, fewer physical channels on the flexible circuit board 160 can be used to transmit the target signal.

[0099] Step 1040: Transmit the target signal to the second FPGA module via the flexible printed circuit board.

[0100] The physical channels are arranged on the flexible circuit board 160, and the number of the physical channels is positively correlated with the size of the flexible circuit board 160, so the reduction of the physical channels also reduces the size (e.g., width and / or thickness) of the flexible circuit board 160. Therefore, the target signal can be transmitted to the second FPGA module 142 based on the smaller (thinner and / or narrower) flexible circuit board 160.

[0101] Step 1060: decode the target signal through the second FPGA module to obtain a multi-channel signal.

[0102] Finally, the target signal is decoded by the second FPGA module 142 to be restored to the multi-channel signal sent by the signal sending end, and the multi-channel signal is sent to the load circuit 126. Optionally, the target signal (including one signal or a preset number of signals) can be decoded by the second FPGA module 142 to be restored to 40 channels of signals sent by the signal sending end.

[0103] The application processor 124 can be used to add corresponding power supply signals and clock signals to the first FPGA module 122 and the second FPGA module 142. The application processor 124 can communicate with the first FPGA module 122 and the second FPGA module 142 through the I2C protocol, so that the status of the first FPGA module 122 and the second FPGA module 142 can be monitored through the application processor 124. The first FPGA module 122 and the second FPGA module 142 also communicate with each other through the I2C protocol.

[0104] Manchester encoding can be used for transmission between the first FPGA module 122 and the second FPGA module 142. Here, Manchester encoding is also called phase encoding. Manchester encoding is a self-synchronous encoding method, that is, the clock synchronization signal is hidden in the data waveform. In Manchester encoding, there is a jump in the middle of each bit, and the jump can be used as both a clock signal and a data signal. Therefore, there is no need to send a synchronization signal when sending a Manchester encoded signal. In other words, the Manchester encoded signal contains self-synchronization information, that is, the Manchester encoded code type includes both data and clock information. Manchester defines 1->10, 0->01, and 100110 is encoded in Manchester as: 100101101001.

[0105] The packet structure of data transmitted between the first FPGA module 122 and the second FPGA module 142 is as follows: Fig.11 As shown in the figure, the packet structure of the data sent by the sender is: Sync Request+Sync End+Data (Data Type, Address, Length, Data). After the receiver receives the data sent by the sender, the packet structure of the data to be fed back is: SyncReply+Sync End+ACK. If the receiver needs to send back the data axis, it can add the data to be replied after the ACK.

[0106] The CLK signal between the first FPGA module 122 and the second FPGA module 142 is responsible for clock synchronization between the first FPGA module 122 and the second FPGA module 142. Among them, TX_CLK is a continuous clock signal (that is, the system is started, the signal always exists), TX_CLK is the reference clock signal from RS (Reconciliation sublayer) to PHY (physical layer interface); TX_data represents the transmitted data. RX_CLK is a continuous clock signal (that is, the system is started, the signal always exists), RX_CLK is provided by PHY, and is a clock signal directly generated by the PHY chip that is aligned with the data center. RX_data represents the received data. Among them, the reserved signal is to reduce the transmission bandwidth from TX to RX, thereby reducing the encoding and decoding frequency of the FPGA and reducing the power consumption of the FPGA; JTAG upgrade refers to the firmware upgrade of the FPGA chip through the JTAG interface.

[0107] On the contrary, the second FPGA module 142 can also compress and encode the multi-channel signals to be transmitted by the load circuit 126 to obtain the target signal, and then use fewer physical channels on the flexible circuit board 160 to transmit the target signal to the first FPGA module 122. Finally, the first FPGA module 122 decodes the target signal, restores the target signal to the multi-channel signal sent by the signal transmitting end, and distributes it to the signal receiving end, so that the signal receiving end (application processor 124) can accurately receive the multi-channel signal for subsequent operations.

[0108] In the embodiment of the present application, the electronic device includes a first FPGA module 122 and a second FPGA module 142, and the first FPGA module 122 and the second FPGA module 142 are electrically connected through a flexible circuit board 160. Since the first FPGA module 122 can compress and encode the multi-channel signals to be transmitted to obtain the target signal, the target signal can be transmitted to the second FPGA module 142 using fewer physical channels on the flexible circuit board 160. Then, the size of the flexible circuit board 160 can be greatly reduced, and the volume of the folding structure can be reduced, thereby greatly reducing the size of the electronic device and meeting the current user's demand for thin and light electronic devices. Finally, the target signal is decoded by the second FPGA module 142, and the target signal is restored to the multi-channel signal sent by the signal sending end, and distributed to the signal receiving end, so that the signal receiving end can accurately receive the multi-channel signal for subsequent operations. Therefore, the electronic device can compress and encode the multi-channel signal to be transmitted through the first FPGA module 122, and then transmit it to the second FPGA module 142 through the flexible circuit board 160, and the second FPGA module 142 decodes it, thereby ensuring the accuracy of signal transmission while greatly reducing the size of the electronic device.

[0109] It should be understood that, although the various steps in the above-mentioned flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the above-mentioned flow chart may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0110] In one embodiment, Fig.12As shown, a signal transmission device 1200 is provided, which is applied to an electronic device. The electronic device includes a first FPGA module 122 and a second FPGA module 142, and the first FPGA module 122 and the second FPGA module 142 are electrically connected via a flexible circuit board 160; the device includes: a signal encoding module 1220, which is used to compress and encode multiple signals to be transmitted through the first FPGA module 122 to obtain a target signal; a signal transmission module 1240, which is used to transmit the target signal to the second FPGA module 142 through the flexible circuit board 160; and a signal decoding module 1260, which is used to decode the target signal through the second FPGA module 142 to obtain a multiple signal.

[0111] The division of the various modules in the above-mentioned signal transmission device is only for illustration. In other embodiments, the signal transmission device can be divided into different modules as needed to complete all or part of the functions of the above-mentioned signal transmission device.

[0112] For the specific definition of the signal transmission device, please refer to the definition of the signal transmission method above, which will not be repeated here. Each module in the above-mentioned signal transmission device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0113] Fig.13 Schematic diagram of the internal structure of an electronic device in an embodiment. The electronic device can be any terminal device such as a mobile phone, a tablet computer, a laptop computer, a desktop computer, a PDA (Personal Digital Assistant), a POS (Point of Sales), a car computer, a wearable device, etc. The electronic device includes a processor and a memory connected via a system bus. Among them, the processor may include one or more processing units. The processor may be a CPU (Central Processing Unit) or a DSP (Digital Signal Processing), etc. The memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides a cache operating environment for the operating system computer program in the non-volatile storage medium. The computer program can be executed by the processor to implement the signal transmission method provided in the aforementioned embodiments.

[0114] Each module in the signal transmission device provided in the embodiment of the present application can be implemented in the form of a computer program. The computer program can be run on an electronic device. The program module constituted by the computer program can be stored in the memory of the electronic device. When the computer program is executed by the processor, the steps of the method described in the embodiment of the present application are implemented.

[0115] An embodiment of the present application also provides a chip, including a processor, and the processor is configured to execute the steps of the above-mentioned signal transmission method.

[0116] The embodiment of the present application also provides a computer-readable storage medium, one or more non-volatile computer-readable storage media containing computer-executable instructions, when the computer-executable instructions are executed by one or more processors, the processors execute the steps of the signal transmission method.

[0117] The embodiment of the present application also provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the signal transmission method.

[0118] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. An electronic device, characterized in that: The electronic device comprises a first FPGA module and a second FPGA module, wherein the first FPGA module and the second FPGA module are electrically connected via a flexible circuit board; The first FPGA module is used to compress and encode the multi-channel signals to be transmitted to obtain the target signal; The flexible circuit board is used to transmit the target signal to the second FPGA module; The second FPGA module is used to decode the target signal to obtain the multi-channel signal.

2. The electronic device according to claim 1, characterized in that: The first FPGA module includes a first encoding path and a second encoding path; The first encoding path is used to compress and encode the multiple non-protocol signals in the multiple signals to be transmitted to obtain target non-protocol signals; The second encoding path is used to compress and encode the multi-channel protocol type signals in the multi-channel signals to be transmitted to obtain the target protocol signals.

3. The electronic device according to claim 2, characterized in that: The first encoding path includes a first register and a first controller; the first register is connected to the first controller, and the first controller is connected to the second FPGA module; The first register is used to receive and store the multiple non-protocol signals; The first controller is used to read the multiple non-protocol signals from the first register, compress and encode the multiple non-protocol signals to obtain the target non-protocol signal, and transmit the target non-protocol signal to the second FPGA module.

4. The electronic device according to claim 2, characterized in that: The second encoding path includes a first protocol parsing unit, a second register and a second controller; the first protocol parsing unit is connected to the second register, the second register is connected to the second controller, and the second controller is connected to the second FPGA module; The first protocol analysis unit is used to receive the multiple protocol signals, perform protocol analysis on the multiple protocol signals, obtain multiple signals after protocol analysis, and transmit the multiple signals after protocol analysis to the second register; The second register is used to receive and store the multi-channel signal after the protocol is parsed; The second controller is used to read the multiple signals after the protocol parsing from the second register, compress and encode the multiple signals after the protocol parsing to obtain the target protocol signal, and transmit the target protocol signal to the second FPGA module.

5. The electronic device according to claim 2, characterized in that: The second FPGA module includes a first decoding path and a second decoding path; the first encoding path is connected to the first decoding path through the flexible circuit board, and the second encoding path is connected to the second decoding path through the flexible circuit board; The first decoding path is used to decode the target non-protocol signal to obtain the multiple non-protocol signals; The second decoding path is used to decode the target protocol signal to obtain the multi-channel protocol signal.

6. The electronic device according to claim 5, characterized in that: The first decoding path includes a third register and a third controller; the third register is connected to the first FPGA module and the third controller respectively; The third register is used to receive and store the target non-protocol signal from the first FPGA module; The third controller is used for reading the target non-protocol signal from the third register and decoding the target non-protocol signal to obtain the multi-channel non-protocol signals.

7. The electronic device according to claim 5, characterized in that: The second decoding path includes a second protocol parsing unit, a fourth register and a fourth controller; the fourth controller is respectively connected to the first FPGA module and the fourth register, and the fourth register is connected to the second protocol parsing unit; The fourth controller is used to receive the target protocol signal from the first FPGA module, and decode the target protocol signal to obtain the multi-channel protocol class signal; The fourth register is used to receive and store the multi-channel protocol signal; The second protocol analysis unit is used to read the multiple protocol signals from the fourth register, and perform protocol analysis on the multiple protocol signals to obtain multiple signals after protocol analysis.

8. The electronic device according to claim 2, characterized in that: The multi-channel protocol signal includes preset format data and empty packet format data following the preset format data.

9. The electronic device according to any one of claims 1 to 8, characterized in that: The electronic device also includes an application processor or a load circuit, and the application processor or the load circuit is electrically connected to the first FPGA module and is used to send the multi-channel signals to be transmitted to the first FPGA module.

10. The electronic device according to claim 9, characterized in that: The first FPGA module includes a first flash memory chip, and the second FPGA module includes a second flash memory chip. The application processor is also used to burn firmware into the first flash memory chip and the second flash memory chip.

11. The electronic device according to claim 10, characterized in that: When the application processor is in a high level mode, the application processor is used to control the first flash memory chip and the second flash memory chip to power on, and burn firmware into the first flash memory chip; The application processor is also used to burn firmware into the static random access memory of the first flash memory chip, and control the first FPGA chip to enter the transparent transmission mode, and burn firmware into the second flash memory chip of the second FPGA chip through the first FPGA chip.

12. The electronic device according to any one of claims 1 to 8, characterized in that: The electronic device also includes an application processor or a load circuit, and the application processor or the load circuit is electrically connected to the second FPGA module and is used to send the multi-channel signals to be transmitted to the second FPGA module.

13. The electronic device according to any one of claims 1 to 8, characterized in that: The electronic device comprises a first housing, a folding mechanism and a second housing; The electronic device also includes the flexible circuit board, a first circuit board and a second circuit board; wherein the first circuit board is arranged in the first shell, the second circuit board is arranged in the second shell, the first circuit board includes the first FPGA module, and the second circuit board includes the second FPGA module; the flexible circuit board passes through the folding mechanism to connect the first FPGA module and the second FPGA module.

14. A signal transmission method, characterized in that: Applied to an electronic device, the electronic device comprises a first FPGA module and a second FPGA module, the first FPGA module and the second FPGA module are electrically connected via a flexible circuit board; the method comprises: The first FPGA module compresses and encodes the multi-channel signals to be transmitted to obtain a target signal; Transmitting the target signal to the second FPGA module through the flexible circuit board; The target signal is decoded by the second FPGA module to obtain the multi-channel signal.

15. A signal transmission device, characterized in that: Applied to electronic equipment, the electronic equipment includes a first FPGA module and a second FPGA module, the first FPGA module and the second FPGA module are electrically connected through a flexible circuit board; the device includes: A signal encoding module, used for compressing and encoding the multi-channel signals to be transmitted through the first FPGA module to obtain a target signal; A signal transmission module, used for transmitting the target signal to the second FPGA module through the flexible circuit board; A signal decoding module is used to decode the target signal through the second FPGA module to obtain the multi-channel signal.

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