Processor interconnection resource adjusting method and device, equipment and medium

Abstract

The invention discloses a processor interconnection resource adjusting method and device, equipment and a medium, and belongs to the technical field of electronics, and the method comprises the steps: obtaining an interconnection bandwidth rate between a first processor and a second processor and a first interconnection bandwidth rate; obtaining first performance data of the processor; adjusting a channel signal state between the processor and a switch according to a processor interconnection bandwidth rate comparison result, and updating and calculating according to the first performance data of the processor to determine a target hardware connection topology mode; and adjusting the processor interconnection resources through the target hardware connection topology mode. According to the method, the interconnection signal resources between the processors can be adaptively optimized in real time through the algorithm model, and the performance of the processors is fully exerted.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method, device, equipment and medium for adjusting processor interconnection resources. Background Art

[0002] At present, with the acceleration of domestic informatization and the rapid development of the electronic information manufacturing industry, the rapid rise of domestic central processing units (CPUs) has also brought new hardware challenges to various basic model operations, mature model operations, domestic intelligent driving, and storage software and other related applications. For example, basic model operations include data collection, data preprocessing, data partitioning, model selection, model training, function operations, back propagation algorithms and optimization. Different calculation methods have different requirements for the number of CPU cores, main frequency, interconnection bandwidth, memory performance, etc.

[0003] The dual-channel CPU design currently used on servers generally has a fixed number of channel lanes for interconnection between CPUs. During the design process, the implementation scheme with the largest CPU interconnection bandwidth is generally selected to ensure the interconnection transmission speed of the CPU. However, the domestic CPU interconnection signals (such as high-speed parallel bus) and high-speed serial bus are multiplexed. When the CPU interconnection signals are maximized, the number of lanes of the high-speed serial bus will be reduced accordingly, reducing the scalability of the equipment.

[0004] At the same time, not all application settings require high-bandwidth CPU interconnection, especially in the current AI boom. Various basic algorithm models are constantly emerging, and there are different requirements for the underlying hardware platform. However, general hardware design can no longer meet various application scenarios. The hardware development iteration cycle is long, and the contradiction with complex demand scenarios is becoming increasingly prominent. Summary of the invention

[0005] In order to overcome the above technical defects, the purpose of this application is to provide a method, device, equipment and medium for adjusting processor interconnection resources, the method comprising: obtaining the interconnection bandwidth rate between the first processor and the second processor and the first interconnection bandwidth rate; obtaining the first performance data of the processor, wherein the first performance data of the processor includes bandwidth rate parameters and delay parameters; comparing the current processor interconnection bandwidth rate with the first interconnection bandwidth rate; adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode; adjusting the processor interconnection resources through the target hardware connection topology mode. This application can perform real-time adaptive optimization of the interconnection signal resources between processors through an algorithm model to give full play to the performance of the processor.

[0006] The specific technical solutions provided by the embodiments of this application are as follows:

[0007] In a first aspect, the present application provides a processor interconnection resource adjustment method, the method is applied to a processor interconnection resource adjustment system, the system includes a first processor, a second processor and a switch, the first processor is connected to the second processor, the first processor and the second processor are respectively connected to the switch, the method includes:

[0008] Obtaining an interconnection bandwidth rate and a first interconnection bandwidth rate between the first processor and the second processor; wherein the first interconnection bandwidth rate is a theoretical interconnection bandwidth rate between the first processor and the second processor;

[0009] Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0010] Comparing a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0011] Adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0012] The processor interconnection resources are adjusted through the target hardware connection topology mode.

[0013] In one embodiment, each processor includes a plurality of cores, the switch includes a plurality of switching areas, and the cores of the processors are interconnected; the second core of the first processor is connected to the first core of the second processor; the first core of the first processor and the second core of the second processor are respectively connected to the first switching area of ​​the switch; the third core of the first processor and the fourth core of the second processor are respectively connected to the second switching area of ​​the switch; the fourth core of the first processor and the third core of the second processor are respectively connected to the third switching area of ​​the switch.

[0014] In one embodiment, the channel signal state between the processor and the switch includes: a high-speed parallel bus signal and a high-speed serial bus signal;

[0015] When the channel signal state between the processor and the switch is a high-speed parallel bus signal, signal transmission between the first processor and the second processor is realized;

[0016] When the channel signal state between the processor and the switch is a high-speed serial bus signal, signal transmission between the first processor and the switch or signal transmission between the second processor and the switch is realized.

[0017] In one embodiment, adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode includes:

[0018] Setting the processor performance data obtained for the first time as second performance data;

[0019] In response to the current processor interconnection bandwidth rate being close to the first interconnection bandwidth rate, a first adjustment is performed on the channel signal state between the processor and the switch, wherein the first adjustment includes increasing the number of channels whose channel signal state between the processor and the switch is a high-speed parallel bus signal, and reducing the number of channels whose channel signal state between the processor and the switch is a high-speed serial bus signal;

[0020] Obtaining processor performance data after the first adjustment;

[0021] Comparing the processor performance data after the first adjustment with the second performance data;

[0022] In response to the processor performance data parameter value after the first adjustment being greater than the second performance data parameter value, updating the performance data of the processor, continuing to increase the number of channels whose channel signal states between the processor and the switch are high-speed parallel bus signals, and reducing the number of channels whose channel signal states between the processor and the switch are high-speed serial bus signals;

[0023] When the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate, the processor performance data when the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate is set as the third performance data.

[0024] In one embodiment, the adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode also includes:

[0025] In response to the current processor interconnection bandwidth rate being less than the first interconnection bandwidth rate, a second adjustment is performed on the channel signal state between the processor and the switch, wherein the second adjustment includes reducing the number of channels whose channel signal state between the processor and the switch is a high-speed parallel bus signal, and increasing the number of channels whose channel signal state between the processor and the switch is a high-speed serial bus signal;

[0026] Obtaining processor performance data after the second adjustment;

[0027] comparing the processor performance data after the second adjustment with the third performance data;

[0028] In response to the processor performance data parameter value after the second adjustment being greater than the third performance data parameter value, updating the performance data of the processor, continuing to reduce the number of channels whose channel signal states between the processor and the switch are high-speed parallel bus signals, and increasing the number of channels whose channel signal states between the processor and the switch are high-speed serial bus signals;

[0029] When the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data, the hardware connection topology mode when the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data is determined as the target hardware connection topology mode.

[0030] In one embodiment, the cores of the processor are interconnected, including:

[0031] The first core of the first processor is connected to the second core of the first processor, the second core of the first processor is connected to the fourth core of the first processor, the fourth core of the first processor is connected to the third core of the first processor, and the third core of the first processor is connected to the first core of the first processor; the first core of the first processor is connected to the fourth core of the first processor, and the second core of the first processor is connected to the third core of the first processor;

[0032] The first core of the second processor is connected to the second core of the second processor, the second core of the second processor is connected to the fourth core of the second processor, the fourth core of the second processor is connected to the third core of the second processor, and the third core of the second processor is connected to the first core of the second processor; the first core of the second processor is connected to the fourth core of the second processor, and the second core of the second processor is connected to the third core of the second processor.

[0033] In one embodiment, the method comprises:

[0034] The obtaining first performance data of the processor includes:

[0035] Collecting performance test data of the processor through monitoring software;

[0036] Creating a neural network model based on performance test data of the processor;

[0037] Testing the neural network model by cross-validation;

[0038] Optimizing and adjusting the neural network model;

[0039] Acquire first performance data of the processor through the optimized neural network model;

[0040] The method further includes: reacquiring the fifth performance data of the processor, adjusting the channel signal state between the processor and the switch according to the processor interconnection bandwidth rate comparison result, and re-updating the calculation according to the fifth performance data of the processor to determine the target hardware connection topology mode.

[0041] In a second aspect, the present application further provides a processor interconnection resource adjustment device, the device is applied to a processor interconnection resource adjustment system, the system includes a first processor, a second processor and a switch, the first processor is connected to the second processor, the first processor and the second processor are respectively connected to the switch, the device includes:

[0042] An acquisition module, configured to acquire the interconnection bandwidth rate between the first processor and the second processor and the first interconnection bandwidth rate; and acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0043] A comparison module, configured to compare a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0044] A determination module, configured to adjust the channel signal state between the processor and the switch according to the comparison result and to update the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0045] The adjustment module is used to adjust the processor interconnection resources through the target hardware connection topology mode.

[0046] In a third aspect, a processor interconnection resource adjustment device is also provided, comprising:

[0047] one or more processors;

[0048] A storage device for storing one or more programs;

[0049] When the one or more programs are executed by the one or more processors, the one or more processors implement the processor interconnection resource adjustment method as described in any one of the first aspects.

[0050] In a fourth aspect, the present application further provides a computer device, the device comprising:

[0051] A memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the processor interconnection resource adjustment method as described in any one of the first aspects.

[0052] In a fifth aspect, the present application further provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of any of the processor interconnection resource adjustment methods described in the first aspect.

[0053] In a sixth aspect, the present application further provides a computer storage medium, the medium comprising:

[0054] A computer program is stored thereon, and when the computer program is executed by a processor, the steps of any of the processor interconnection resource adjustment methods described in the first aspect are implemented.

[0055] Compared with the prior art, the method of the technical solution provided in the embodiment of the present application includes: obtaining the interconnection bandwidth rate and the first interconnection bandwidth rate between the first processor and the second processor; obtaining the first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter; comparing the current processor interconnection bandwidth rate with the first interconnection bandwidth rate; adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode; adjusting the processor interconnection resources through the target hardware connection topology mode. The present application can perform real-time adaptive optimization of the interconnection signal resources between processors through an algorithm model, adjust the channel signal state between the processor and the switch, and maximize the number of CPU interconnection channels and PCIE switch expansion channels under a specific application model, thereby quickly formulating the hardware topology required by the specific application model, realizing the architectural complementarity between the upper application model and the underlying hardware, and can also make corresponding adjustments as the application model changes, realizing the rapid adaptation of the underlying hardware architecture, and giving full play to the performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 A schematic diagram of the interconnection between the existing processors of this application;

[0058] Figure 2 A structural diagram of a processor interconnection resource adjustment system provided in Example 1 of the present application;

[0059] Figure 3 A first flow chart of the processor interconnection resource adjustment method provided in Embodiment 1 of the present application;

[0060] Figure 4 A second flow chart of the processor interconnection resource adjustment method provided in Embodiment 2 of the present application;

[0061] Figure 5 A specific flow chart of the processor interconnection resource adjustment method provided in Embodiment 2 of the present application;

[0062] Figure 6 A structural diagram of a processor interconnection resource adjustment device provided in Embodiment 3 of the present application;

[0063] Figure 7 The exemplary system provided for Embodiment 7 of the present application can be used to implement the various embodiments described in the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0065] It should be noted that, unless the context clearly requires otherwise, words such as “include”, “including” and similar words throughout the specification and claims should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is “including but not limited to”.

[0066] Furthermore, in the description of the present application, unless otherwise specified, “plurality” means two or more.

[0067] like Figure 1As shown, the server processor realizes the high-speed parallel bus signal interconnection of two CPUs through the central processing unit CPU base through the hardware circuit board design, such as the high-speed parallel bus XGMII; this general hardware implementation solution assumes that all application models require sufficient CPU interconnection performance, but according to the CPU architecture of different platforms and different algorithm models, the CPU interconnection performance is not the bottleneck point of the algorithm model application. On the contrary, in order to give full play to the performance of the CPU, more PCIE lanes are required. However, in the hardware design and development process, the designer will interconnect all the high-speed parallel bus signals of the CPU to ensure the interconnection transmission speed of the CPU. However, the domestic CPU interconnection XGMII signal and PCIE signal are multiplexed. When the CPU interconnection signal is maximized, the number of lanes of the PCIE signal will be reduced accordingly, reducing the scalability of the device. Since the general design is to fix the CPU interconnection signal on the PCBA, in the actual application process, it will encounter the situation that the number of lanes of the PCIE signal is insufficient and the CPU resources are relatively idle, and the CPU performance cannot be truly brought into play.

[0068] That is, the dual-channel design used on the server selects the implementation solution with the largest CPU interconnection bandwidth to ensure the CPU interconnection transmission speed. However, when the CPU interconnection signal is maximized, the number of PCIE lanes will be reduced accordingly, reducing the scalability of the device.

[0069] Embodiment 1

[0070] The present application embodiment provides a method for adjusting processor interconnection resources, such as Figure 2 , 3 As shown, the method is applied to a processor interconnection resource adjustment system, the system includes a first processor, a second processor and a switch, the first processor is connected to the second processor, the first processor and the second processor are respectively connected to the switch, and the method includes:

[0071] Obtaining an interconnection bandwidth rate between the first processor and the second processor and a first interconnection bandwidth rate;

[0072] Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0073] Comparing a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0074] Adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0075] The processor interconnection resources are adjusted through the target hardware connection topology mode.

[0076] Specifically, the present application proposes a CPU interconnection resource adaptive server design solution, which can perform real-time CPU interconnection signal adaptive optimization through different algorithm models, and control the number of CPU interconnection lanes and the number of switch (PCIE) lanes respectively, so as to maximize the number of CPU interconnection lanes and the number of PCIE device expansion lanes under a specific application model, thereby quickly formulating the hardware topology required for the specific model, realizing the architectural complementarity between the upper-level application and the underlying hardware, and can also make corresponding adjustments as the application model changes, so as to realize the rapid adaptation of the underlying hardware and optimize the CPU performance.

[0077] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0078] The present application can perform real-time adaptive optimization of interconnection signal resources between processors through an algorithm model, adjust the channel signal state between the processor and the switch, and maximize the number of CPU interconnection channels and PCIE switch expansion channels under a specific application model, thereby quickly formulating the hardware topology required for the specific application model, achieving architectural complementarity between the upper-layer application model and the underlying hardware, and also making corresponding adjustments as the application model changes, achieving rapid adaptation of the underlying hardware architecture, and giving full play to the performance of the processor.

[0079] Embodiment 2

[0080] The present application embodiment provides a method for adjusting processor interconnection resources, such as Figure 4 As shown, the method is applied to a processor interconnection resource adjustment system, the system includes a first processor, a second processor and a switch, and the method includes:

[0081] Step S01: Connect the first processor to the second processor, and connect the first processor to the second processor to the switch respectively.

[0082] Step S01 also includes:

[0083] Step S011, connecting the cores of the processor to each other;

[0084] connecting the second core of the first processor to the first core of the second processor;

[0085] Connecting the first core of the first processor and the second core of the second processor to the first switching area of ​​the switch respectively;

[0086] Connect the third core of the first processor and the fourth core of the second processor to the second switching area of ​​the switch respectively

[0087] The fourth core of the first processor and the third core of the second processor are respectively connected to the third switching area of ​​the switch.

[0088] Specifically, the present application proposes an adaptive conversion of XGMII signals and PCIE signals interconnected by CPUs. Each CPU has 4 cores (Die), and each Die has two groups of PCIE signals by default, one of which can be multiplexed as XGMII signals for CPU interconnection to achieve data communication between CPUs. The present application adds an implementation scheme of a switch (PCIE SW) based on the existing hardware design. By default, at least one group of XGMII signals is interconnected between the two CPUs to achieve necessary information communication. The remaining three groups are connected to the same switching zone (Zone) of the switch according to a normal interconnection relationship. By switching the internal channel of the PCIESW, the switching of the CPU's XGMII channel and the PCIE channel is achieved, thereby increasing the scalability of the device.

[0089] Step S012, connecting the first core of the first processor to the second core of the first processor, connecting the second core of the first processor to the fourth core of the first processor, connecting the fourth core of the first processor to the third core of the first processor, connecting the third core of the first processor to the first core of the first processor; connecting the first core of the first processor to the fourth core of the first processor, and connecting the second core of the first processor to the third core of the first processor;

[0090] Connect the first core of the second processor to the second core of the second processor, connect the second core of the second processor to the fourth core of the second processor, connect the fourth core of the second processor to the third core of the second processor, and connect the third core of the second processor to the first core of the second processor; connect the first core of the second processor to the fourth core of the second processor, and connect the second core of the second processor to the third core of the second processor.

[0091] Specifically, interconnecting each core of the processor can increase the transmission data rate of the cores within the processor.

[0092] Step S02, obtaining the interconnection bandwidth rate between the first processor and the second processor and the first interconnection bandwidth rate;

[0093] Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0094] The current processor interconnection bandwidth rate is compared with the first interconnection bandwidth rate.

[0095] Specifically, use the default settings, set the lane numbers of the CPU interconnect XGMII signal and the lane number of the PCIE signal, execute the applied algorithm model, obtain the current processor interconnection bandwidth rate and compare it with the CPU theoretical interconnection rate, and obtain the CPU performance data under the running algorithm model, such as bandwidth parameters, delay parameters, etc.

[0096] The first interconnection bandwidth rate is the CPU theoretical interconnection bandwidth rate: 50% (16GT / S) of the CPU standard interconnection bandwidth rate.

[0097] Here, the first performance data of the processor may be acquired through a Lin pack model.

[0098] Step S03: adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode.

[0099] Specifically, the channel signal state between the processor and the switch includes: a high-speed parallel bus (XGMII) signal and a high-speed serial bus (PCIE) signal;

[0100] When the channel signal state between the processor and the switch is an XGMII signal, signal transmission between the first processor and the second processor is realized;

[0101] When the channel signal state between the processor and the switch is a PCIE signal, signal transmission between the first processor and the switch or signal transmission between the second processor and the switch is implemented.

[0102] It is understandable that when a channel on a certain Die is not used as a PCIE signal, the switch PCIE SW sets the transmission mode in the same zone and only connects the hardware link. It actually transmits data according to the internal protocol of the CPU to realize the data transmission function of the XGMII signal between CPUs.

[0103] When a channel on a Die is used as a PCIE signal, it is necessary to set the corresponding Die interface to PCIE mode in the system BIOS. At the same time, the PCIE SW sets the transmission mode in the same Zone. It is actually implemented in the form of PCIE signals, so that each CPU can add a set of X16 PCIE devices. It can be set on the corresponding PCIE SW port, and the device support of PCIE X16, X8 or X4 hard disk NVMe can be realized in turn. Increasing PCIE devices further improves the scalability and application performance of the server.

[0104] Step S03 also includes:

[0105] Step S031, setting the processor performance data obtained for the first time as the second performance data;

[0106] In response to the current processor interconnection bandwidth rate being close to the first interconnection bandwidth rate, a first adjustment is performed on the channel signal state between the processor and the switch, wherein the first adjustment includes increasing the number of channels whose channel signal state between the processor and the switch is an XGMII signal, and reducing the number of channels whose channel signal state between the processor and the switch is a PCIE signal;

[0107] Obtaining processor performance data after the first adjustment;

[0108] Comparing the processor performance data after the first adjustment with the second performance data;

[0109] In response to the processor performance data parameter value after the first adjustment being greater than the second performance data parameter value, updating the performance data of the processor, continuing to increase the number of channels whose channel signal states between the processor and the switch are XGMII signals, and reducing the number of channels whose channel signal states between the processor and the switch are PCIE signals;

[0110] When the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate, the processor performance data when the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate is set as the third performance data.

[0111] Specifically, the CPU performance data obtained for the first time is used as the baseline value for subsequent data comparison. The actual bandwidth rate of the CPU interconnection is compared and analyzed with the theoretical bandwidth rate of the CPU interconnection. The next adjustment direction is executed according to the results of the comparison and analysis.

[0112] If the actual bandwidth rate of the CPU interconnection is close to the theoretical bandwidth rate of the CPU interconnection, it means that the theoretical bandwidth rate of the CPU interconnection has become or is close to the performance bottleneck of the execution algorithm model, and it is necessary to further increase the interconnection bandwidth of the CPU for further verification. By setting the XGMII port of the CPU and the port attributes of the PCIE in the system BIOS, and the setting of the Zone in the PCIE SW, restart the device to increase the bandwidth of the CPU interconnection XGMII signal and reduce the bandwidth of the PCIE signal; after obtaining the current performance data, compare it with the second performance data. If the performance data parameter value is higher than the parameter value of the second performance data, use this performance value as a new baseline value, repeat the operations before this step again, continue to increase the number of channels whose channel signal state between the processor and the switch is a high-speed parallel bus signal, and reduce the number of channels whose channel signal state between the processor and the switch is a high-speed serial bus signal, until the bandwidth rate of the CPU interconnection reaches the upper limit supported by the hardware or the upper limit of the algorithm model, and at the same time, the processor performance data when the processor interconnection bandwidth rate reaches the second interconnection bandwidth rate is set as the third performance data.

[0113] The bandwidth rate of the CPU interconnection reaches the upper limit of 32 GT / S supported by the hardware, and the upper limit of the algorithm model is 30 GT / S, that is, the second interconnection bandwidth rate.

[0114] Step S032: In response to the current processor interconnection bandwidth rate being less than the first interconnection bandwidth rate, a second adjustment is performed on the channel signal state between the processor and the switch, wherein the second adjustment includes reducing the number of channels whose channel signal state between the processor and the switch is an XGMII signal, and increasing the number of channels whose channel signal state between the processor and the switch is a PCIE signal;

[0115] Obtaining processor performance data after the second adjustment;

[0116] comparing the processor performance data after the second adjustment with the third performance data;

[0117] In response to the processor performance data parameter value after the second adjustment being greater than the third performance data parameter value, updating the performance data of the processor, continuing to reduce the number of channels whose channel signal states between the processor and the switch are XGMII signals, and increasing the number of channels whose channel signal states between the processor and the switch are PCIE signals;

[0118] When the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data, the hardware connection topology mode when the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data is determined as the target hardware connection topology mode.

[0119] Specifically, if the actual bandwidth of the CPU interconnection is lower than the theoretical bandwidth of the CPU interconnection, it means that the theoretical bandwidth of the CPU interconnection is excessive, and the CPU interconnection bandwidth needs to be further reduced for verification. By setting the port attributes of the CPU XGMII and PCIE in the system BIOS and the Zone settings in the switch PCIE SW, restart the device to achieve a reduction in the number of lanes of the CPU interconnection XGMII signal and an increase in the number of lanes of the PCIE signal; after obtaining the current CPU performance data, compare it with the third performance data. If the current CPU performance data parameter value is higher than the third performance data parameter value, use this performance value as a new baseline value, and repeat the operations before this step again until the obtained CPU performance data parameter value is consistent with the highest CPU performance data parameter value in history (the parameter value of the fourth performance data), then the hardware connection topology mode when the updated processor performance data parameter value is the same as the parameter value of the fourth performance data is determined as the target hardware connection topology mode.

[0120] When the obtained CPU performance data parameter value is consistent with the highest CPU performance data parameter value in history, it means that the hardware topology under the computing model has been optimized and this configuration can be imported into other server nodes.

[0121] Step S04, obtaining first performance data of the processor, includes:

[0122] Collecting performance test data of the processor through monitoring software;

[0123] Creating a neural network model based on performance test data of the processor;

[0124] Testing the neural network model by cross-validation;

[0125] Optimizing and adjusting the neural network model;

[0126] Acquire first performance data of the processor through the optimized neural network model;

[0127] The fifth performance data of the processor is reacquired, the channel signal state between the processor and the switch is adjusted according to the processor interconnection bandwidth rate comparison result, and the calculation is updated again according to the fifth performance data of the processor to determine the target hardware connection topology mode.

[0128] Specifically, if there is a new algorithm model, the fifth performance data of the processor can be re-acquired, the channel signal state between the processor and the switch can be adjusted according to the processor interconnection bandwidth rate comparison result, and the calculation can be updated again according to the fifth performance data of the processor to determine the target hardware connection topology mode, thereby increasing the flexibility of processor interconnection resource adjustment.

[0129] Here, the first performance data is the performance data obtained through the Lin pack model, and the fifth performance data is the performance data obtained through other new algorithm models.

[0130] like Figure 5 As shown, the present application proposes a CPU interconnect resource adaptive server design scheme, proposes an adaptive conversion between CPU interconnect XGMII signals and PCIE signals, performs model calculation of actual application algorithm through default CPU interconnect lane number and PCIE lane number, monitors the real-time bandwidth rate of CPU interconnect and CPU performance value (such as bandwidth or delay, etc.), automatically adjusts the CPU interconnect XGMII signal lane number and PCIE signal lane number according to the actually obtained CPU performance value, collects the performance of the algorithm model again, obtains the optimal performance value and corresponding hardware topology under the current application model through repeated calculations, and applies them to other server nodes.

[0131] That is, the implementation scheme of the switch PCIE SW is added on the basis of the general CPU interconnection hardware design of the present application. By default, at least one set of XGMII signal interconnection is established between the two CPUs to realize necessary information communication. The remaining three sets are connected to the same switching zone Zone of the switch PCIE SW according to the normal interconnection relationship. The switching of the internal channel of the switch PCIE SW is realized to realize the switching of the CPU's XGMII channel and the PCIE channel.

[0132] Through adaptive conversion of CPU interconnection signal XGMII signal and PCIE signal, according to the actual application algorithm model operation, the real-time bandwidth of CPU interconnection and the performance value of the algorithm model are calculated, the performance value obtained by statistical optimization operation is automatically adjusted, the lane number of CPU interconnection XGMII and the lane number of PCIE signal are automatically adjusted, and the optimal performance value and corresponding hardware topology under the current application model are obtained through repeated operation to give full play to the performance of the processor.

[0133] In addition, the processor interconnection resource adjustment strategy includes:

[0134] Allocating the processor interconnection resources through a topology manager;

[0135] Obtaining the topology information of the processor through the CPUID instruction to determine the processor interconnection resource adjustment strategy, wherein the topology information includes whether multi-threading is supported, the number of cores, and the number of threads;

[0136] Improving the performance of a specific type of computing task by optimizing the internal architecture of the processor, and allocating the interconnection resources of the processor, wherein the internal architecture of the processor includes memory access mode and data reuse structure;

[0137] Improving processor scalability and lower latency through a fat tree topology, allocating processor interconnect resources;

[0138] Confirm efficient use of processor resources by monitoring system load in real time and dynamically adjusting task allocation;

[0139] Design redundant paths and failover mechanisms, dynamically select the best path based on network conditions through adaptive routing algorithms, reduce latency and increase throughput to adjust the processor interconnection resources;

[0140] The method further comprises:

[0141] Obtaining the hardware topology of the system, wherein the hardware topology includes the layout of processors, memory, and I / O devices;

[0142] Identify key factors that influence processor performance data;

[0143] Determining a processor resource adjustment strategy based on the hardware topology of the system and key factors affecting processor performance data;

[0144] Implement the processor resource adjustment strategy by modifying configuration and / or writing specific code and / or updating hardware;

[0145] The processor resource adjustment strategy is verified and optimized.

[0146] These processor interconnect resource adjustment methods can be appropriately combined and adjusted according to specific application scenarios and hardware configurations to achieve optimal performance results.

[0147] The method for adjusting processor interconnection resources provided in the embodiment of the present application may be improved and optimized without departing from the technical solution of the present application, and these improvements and optimizations should also be regarded as within the scope of protection of the present application.

[0148] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0149] The present application can perform real-time adaptive optimization of interconnection signal resources between processors through an algorithm model, adjust the channel signal state between the processor and the switch, and maximize the number of CPU interconnection channels and PCIE switch expansion channels under a specific application model, thereby quickly formulating the hardware topology required for the specific application model, achieving architectural complementarity between the upper-layer application model and the underlying hardware, and also making corresponding adjustments as the application model changes, achieving rapid adaptation of the underlying hardware architecture, and giving full play to the performance of the processor.

[0150] Embodiment 3

[0151] The present application provides a processor interconnection resource adjustment device, such as Figure 6 As shown, the device includes a connection module, an acquisition module, a comparison module, a determination module, an adjustment module, and a processing module.

[0152] In this embodiment, the connection module is used to connect the first processor with the second processor, and connect the first processor and the second processor to the switch respectively;

[0153] An acquisition module, configured to acquire the interconnection bandwidth rate between the first processor and the second processor and the first interconnection bandwidth rate; and acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0154] A comparison module, configured to compare a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0155] A determination module, configured to adjust the channel signal state between the processor and the switch according to the comparison result and to update the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0156] The adjustment module is used to adjust the processor interconnection resources through the target hardware connection topology mode.

[0157] In one of the embodiments, a connection module is used to connect the cores of the processor to each other;

[0158] connecting the second core of the first processor to the first core of the second processor;

[0159] Connecting the first core of the first processor and the second core of the second processor to the first switching area of ​​the switch respectively;

[0160] Connect the third core of the first processor and the fourth core of the second processor to the second switching area of ​​the switch respectively

[0161] The fourth core of the first processor and the third core of the second processor are respectively connected to the third switching area of ​​the switch.

[0162] In one embodiment, the channel signal status between the processor and the switch includes: XGMII signal and PCIE signal;

[0163] When the channel signal state between the processor and the switch is an XGMII signal, signal transmission between the first processor and the second processor is realized;

[0164] When the channel signal state between the processor and the switch is a PCIE signal, signal transmission between the first processor and the switch or signal transmission between the second processor and the switch is implemented.

[0165] In one of the embodiments, the determination module is used to set the processor performance data obtained for the first time as the second performance data;

[0166] In response to the current processor interconnection bandwidth rate being close to the first interconnection bandwidth rate, a first adjustment is performed on the channel signal state between the processor and the switch, wherein the first adjustment includes increasing the number of channels whose channel signal state between the processor and the switch is an XGMII signal, and reducing the number of channels whose channel signal state between the processor and the switch is a PCIE signal;

[0167] Obtaining processor performance data after the first adjustment;

[0168] Comparing the processor performance data after the first adjustment with the second performance data;

[0169] In response to the processor performance data parameter value after the first adjustment being greater than the second performance data parameter value, updating the performance data of the processor, continuing to increase the number of channels whose channel signal states between the processor and the switch are XGMII signals, and reducing the number of channels whose channel signal states between the processor and the switch are PCIE signals;

[0170] When the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate, the processor performance data when the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate is set as the third performance data.

[0171] In one embodiment, the determination module is used to perform a second adjustment on the channel signal state between the processor and the switch in response to the current processor interconnection bandwidth rate being less than the first interconnection bandwidth rate, wherein the second adjustment includes reducing the number of channels whose channel signal state between the processor and the switch is an XGMII signal, and increasing the number of channels whose channel signal state between the processor and the switch is a PCIE signal;

[0172] Obtaining processor performance data after the second adjustment;

[0173] comparing the processor performance data after the second adjustment with the third performance data;

[0174] In response to the processor performance data parameter value after the second adjustment being greater than the third performance data parameter value, updating the performance data of the processor, continuing to reduce the number of channels whose channel signal states between the processor and the switch are XGMII signals, and increasing the number of channels whose channel signal states between the processor and the switch are PCIE signals;

[0175] When the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data, the hardware connection topology mode when the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data is determined as the target hardware connection topology mode.

[0176] In one embodiment, the connection module is used to connect the first core of the first processor to the second core of the first processor, connect the second core of the first processor to the fourth core of the first processor, connect the fourth core of the first processor to the third core of the first processor, and connect the third core of the first processor to the first core of the first processor; connect the first core of the first processor to the fourth core of the first processor, and connect the second core of the first processor to the third core of the first processor;

[0177] Connect the first core of the second processor to the second core of the second processor, connect the second core of the second processor to the fourth core of the second processor, connect the fourth core of the second processor to the third core of the second processor, and connect the third core of the second processor to the first core of the second processor; connect the first core of the second processor to the fourth core of the second processor, and connect the second core of the second processor to the third core of the second processor.

[0178] In one of the embodiments, the acquisition module is used to collect the performance test data of the processor through monitoring software;

[0179] Creating a neural network model based on performance test data of the processor;

[0180] Testing the neural network model by cross-validation;

[0181] Optimizing and adjusting the neural network model;

[0182] The first performance data of the processor is obtained through the optimized neural network model.

[0183] In one of the embodiments, the processing module is used to reacquire the fifth performance data of the processor, adjust the channel signal state between the processor and the switch according to the processor interconnection bandwidth rate comparison result, and re-update the calculation based on the fifth performance data of the processor to determine the target hardware connection topology mode.

[0184] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0185] The present application can perform real-time adaptive optimization of interconnection signal resources between processors through an algorithm model, adjust the channel signal state between the processor and the switch, and maximize the number of CPU interconnection channels and PCIE switch expansion channels under a specific application model, thereby quickly formulating the hardware topology required for the specific application model, achieving architectural complementarity between the upper-layer application model and the underlying hardware, and also making corresponding adjustments as the application model changes, achieving rapid adaptation of the underlying hardware architecture, and giving full play to the performance of the processor.

[0186] Embodiment 4

[0187] The present invention also provides a processor interconnection resource adjustment device, comprising:

[0188] one or more processors;

[0189] A storage device for storing one or more programs;

[0190] When the one or more programs are executed by the one or more processors, the one or more processors execute the following processor interconnection resource adjustment method:

[0191] Connecting the first processor to the second processor, and connecting the first processor and the second processor to the switch respectively;

[0192] Obtaining an interconnection bandwidth rate between the first processor and the second processor and a first interconnection bandwidth rate;

[0193] Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0194] Comparing a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0195] Adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0196] The processor interconnection resources are adjusted through the target hardware connection topology mode.

[0197] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0198] The present application can perform real-time adaptive optimization of interconnection signal resources between processors through an algorithm model, adjust the channel signal state between the processor and the switch, and maximize the number of CPU interconnection channels and PCIE switch expansion channels under a specific application model, thereby quickly formulating the hardware topology required for the specific application model, achieving architectural complementarity between the upper-layer application model and the underlying hardware, and also making corresponding adjustments as the application model changes, achieving rapid adaptation of the underlying hardware architecture, and giving full play to the performance of the processor.

[0199] Embodiment 5

[0200] The present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following method for adjusting processor interconnection resources can be executed:

[0201] Connecting the first processor to the second processor, and connecting the first processor and the second processor to the switch respectively;

[0202] Obtaining an interconnection bandwidth rate between the first processor and the second processor and a first interconnection bandwidth rate;

[0203] Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0204] Comparing a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0205] Adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0206] The processor interconnection resources are adjusted through the target hardware connection topology mode.

[0207] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0208] The present application can perform real-time adaptive optimization of interconnection signal resources between processors through an algorithm model, adjust the channel signal state between the processor and the switch, and maximize the number of CPU interconnection channels and PCIE switch expansion channels under a specific application model, thereby quickly formulating the hardware topology required for the specific application model, achieving architectural complementarity between the upper-layer application model and the underlying hardware, and also making corresponding adjustments as the application model changes, achieving rapid adaptation of the underlying hardware architecture, and giving full play to the performance of the processor.

[0209] Embodiment 6

[0210] The present application also provides a computer program product, including a computer program, which can implement the following method for adjusting processor interconnection resources when executed by a processor:

[0211] Connecting the first processor to the second processor, and connecting the first processor and the second processor to the switch respectively;

[0212] Obtaining an interconnection bandwidth rate between the first processor and the second processor and a first interconnection bandwidth rate;

[0213] Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0214] Comparing a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0215] Adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0216] The processor interconnection resources are adjusted through the target hardware connection topology mode.

[0217] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0218] The present application can perform real-time adaptive optimization of interconnection signal resources between processors through an algorithm model, adjust the channel signal state between the processor and the switch, and maximize the number of CPU interconnection channels and PCIE switch expansion channels under a specific application model, thereby quickly formulating the hardware topology required for the specific application model, achieving architectural complementarity between the upper-layer application model and the underlying hardware, and also making corresponding adjustments as the application model changes, achieving rapid adaptation of the underlying hardware architecture, and giving full play to the performance of the processor.

[0219] Embodiment 7

[0220] The present application provides a computer storage medium, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented:

[0221] Connecting the first processor to the second processor, and connecting the first processor and the second processor to the switch respectively;

[0222] Obtaining an interconnection bandwidth rate between the first processor and the second processor and a first interconnection bandwidth rate;

[0223] Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter;

[0224] Comparing a current processor interconnection bandwidth rate with the first interconnection bandwidth rate;

[0225] Adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode;

[0226] The processor interconnection resources are adjusted through the target hardware connection topology mode.

[0227] In one embodiment, each processor includes a plurality of cores, the switch includes a plurality of switch areas, and connecting the first processor to the second processor and connecting the first processor and the second processor to the switch respectively includes:

[0228] Connecting the cores of the processor to each other;

[0229] connecting the second core of the first processor to the first core of the second processor;

[0230] Connecting the first core of the first processor and the second core of the second processor to the first switching area of ​​the switch respectively;

[0231] Connect the third core of the first processor and the fourth core of the second processor to the second switching area of ​​the switch respectively

[0232] The fourth core of the first processor and the third core of the second processor are respectively connected to the third switching area of ​​the switch.

[0233] In one embodiment, the channel signal status between the processor and the switch includes: XGMII signal and PCIE signal;

[0234] When the channel signal state between the processor and the switch is an XGMII signal, signal transmission between the first processor and the second processor is realized;

[0235] When the channel signal state between the processor and the switch is a PCIE signal, signal transmission between the first processor and the switch or signal transmission between the second processor and the switch is implemented.

[0236] In one embodiment, adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the performance data of the processor to determine the target hardware connection topology mode includes:

[0237] Setting the processor performance data obtained for the first time as second performance data;

[0238] In response to the current processor interconnection bandwidth rate being close to the first interconnection bandwidth rate, a first adjustment is performed on the channel signal state between the processor and the switch, wherein the first adjustment includes increasing the number of channels whose channel signal state between the processor and the switch is an XGMII signal, and reducing the number of channels whose channel signal state between the processor and the switch is a PCIE signal;

[0239] Obtaining processor performance data after the first adjustment;

[0240] Comparing the processor performance data after the first adjustment with the second performance data;

[0241] In response to the processor performance data parameter value after the first adjustment being greater than the second performance data parameter value, updating the performance data of the processor, continuing to increase the number of channels whose channel signal states between the processor and the switch are XGMII signals, and reducing the number of channels whose channel signal states between the processor and the switch are PCIE signals;

[0242] When the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate, the processor performance data when the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate is set as the third performance data.

[0243] In one embodiment, the adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the performance data of the processor to determine the target hardware connection topology mode also includes:

[0244] In response to the current processor interconnection bandwidth rate being less than the first interconnection bandwidth rate, a second adjustment is performed on the channel signal state between the processor and the switch, wherein the second adjustment includes reducing the number of channels whose channel signal state between the processor and the switch is an XGMII signal, and increasing the number of channels whose channel signal state between the processor and the switch is a PCIE signal;

[0245] Obtaining processor performance data after the second adjustment;

[0246] comparing the processor performance data after the second adjustment with the third performance data;

[0247] In response to the processor performance data parameter value after the second adjustment being greater than the third performance data parameter value, updating the performance data of the processor, continuing to reduce the number of channels whose channel signal states between the processor and the switch are XGMII signals, and increasing the number of channels whose channel signal states between the processor and the switch are PCIE signals;

[0248] When the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data, the hardware connection topology mode when the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data is determined as the target hardware connection topology mode.

[0249] In one embodiment, interconnecting the cores of the processor includes:

[0250] Connecting the first core of the first processor to the second core of the first processor, connecting the second core of the first processor to the fourth core of the first processor, connecting the fourth core of the first processor to the third core of the first processor, and connecting the third core of the first processor to the first core of the first processor; connecting the first core of the first processor to the fourth core of the first processor, and connecting the second core of the first processor to the third core of the first processor;

[0251] Connect the first core of the second processor to the second core of the second processor, connect the second core of the second processor to the fourth core of the second processor, connect the fourth core of the second processor to the third core of the second processor, and connect the third core of the second processor to the first core of the second processor; connect the first core of the second processor to the fourth core of the second processor, and connect the second core of the second processor to the third core of the second processor.

[0252] In one embodiment, the method comprises:

[0253] The obtaining first performance data of the processor includes:

[0254] Collecting performance test data of the processor through monitoring software;

[0255] Creating a neural network model based on performance test data of the processor;

[0256] Testing the neural network model by cross-validation;

[0257] Optimizing and adjusting the neural network model;

[0258] Acquire first performance data of the processor through the optimized neural network model;

[0259] The fifth performance data of the processor is reacquired, the channel signal state between the processor and the switch is adjusted according to the processor interconnection bandwidth rate comparison result, and the calculation is updated again according to the fifth performance data of the processor to determine the target hardware connection topology mode.

[0260] This application can perform real-time adaptive optimization of interconnect signal resources between processors through an algorithm model to give full play to the performance of the processors.

[0261] Figure 7 An exemplary system provided for Embodiment 7 of the present application that can be used to implement various embodiments described in the present application;

[0262] like Figure 7 As shown, in some embodiments, the system can be used as any of the above-mentioned devices for processor interconnect resource adjustment in each of the described embodiments. In some embodiments, the system may include one or more computer-readable media (e.g., system memory or NVM / storage device) having results and one or more processors (e.g., (one or more) processors) coupled to the one or more computer-readable media and configured to execute the results to implement the module to perform the actions described in the present application.

[0263] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0264] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0265] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A processor interconnect resource adjustment method, the method being applied to a processor interconnect resource adjustment system, characterized in that: The system includes a first processor, a second processor, and a switch, the first processor is connected to the second processor, the first processor and the second processor are respectively connected to the switch, and the method includes: Obtaining an interconnection bandwidth rate between the first processor and the second processor and a first interconnection bandwidth rate, wherein the first interconnection bandwidth rate is a theoretical interconnection bandwidth rate between the first processor and the second processor; Acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter; Comparing a current processor interconnection bandwidth rate with the first interconnection bandwidth rate; Adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode; The processor interconnection resources are adjusted through the target hardware connection topology mode.

2. The processor interconnection resource adjustment method according to claim 1, characterized in that: Each processor includes several cores, and the switch includes several switching areas; the cores of the processors are interconnected; the second core of the first processor is connected to the first core of the second processor; the first core of the first processor and the second core of the second processor are respectively connected to the first switching area of ​​the switch; the third core of the first processor and the fourth core of the second processor are respectively connected to the second switching area of ​​the switch; the fourth core of the first processor and the third core of the second processor are respectively connected to the third switching area of ​​the switch.

3. The processor interconnect resource adjustment method according to claim 1, characterized in that: The channel signal state between the processor and the switch includes: a high-speed parallel bus signal and a high-speed serial bus signal; When the channel signal state between the processor and the switch is a high-speed parallel bus signal, signal transmission between the first processor and the second processor is realized; When the channel signal state between the processor and the switch is a high-speed serial bus signal, signal transmission between the first processor and the switch or signal transmission between the second processor and the switch is realized.

4. The processor interconnect resource adjustment method according to claim 3, characterized in that: The step of adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode includes: Setting the processor performance data obtained for the first time as second performance data; In response to the current processor interconnection bandwidth rate being close to the first interconnection bandwidth rate, a first adjustment is performed on the channel signal state between the processor and the switch, wherein the first adjustment includes increasing the number of channels whose channel signal state between the processor and the switch is a high-speed parallel bus signal, and reducing the number of channels whose channel signal state between the processor and the switch is a high-speed serial bus signal; Obtaining processor performance data after the first adjustment; Comparing the processor performance data after the first adjustment with the second performance data; In response to the processor performance data parameter value after the first adjustment being greater than the second performance data parameter value, updating the performance data of the processor, continuing to increase the number of channels whose channel signal states between the processor and the switch are high-speed parallel bus signals, and reducing the number of channels whose channel signal states between the processor and the switch are high-speed serial bus signals; When the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate, the processor performance data when the processor interconnect bandwidth rate reaches the second interconnect bandwidth rate is set as the third performance data.

5. The processor interconnection resource adjustment method according to claim 4, characterized in that: The step of adjusting the channel signal state between the processor and the switch according to the comparison result and updating the calculation according to the first performance data of the processor to determine the target hardware connection topology mode also includes: In response to the current processor interconnection bandwidth rate being less than the first interconnection bandwidth rate, a second adjustment is performed on the channel signal state between the processor and the switch, wherein the second adjustment includes reducing the number of channels whose channel signal state between the processor and the switch is a high-speed parallel bus signal, and increasing the number of channels whose channel signal state between the processor and the switch is a high-speed serial bus signal; Obtaining processor performance data after the second adjustment; comparing the processor performance data after the second adjustment with the third performance data; In response to the processor performance data parameter value after the second adjustment being greater than the third performance data parameter value, updating the performance data of the processor, continuing to reduce the number of channels whose channel signal states between the processor and the switch are high-speed parallel bus signals, and increasing the number of channels whose channel signal states between the processor and the switch are high-speed serial bus signals; When the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data, the hardware connection topology mode when the parameter value of the updated processor performance data is the same as the parameter value of the fourth performance data is determined as the target hardware connection topology mode.

6. The processor interconnection resource adjustment method according to claim 2, characterized in that: The cores of the processors are interconnected, including: the first core of the first processor is connected to the second core of the first processor, the second core of the first processor is connected to the fourth core of the first processor, the fourth core of the first processor is connected to the third core of the first processor, and the third core of the first processor is connected to the first core of the first processor; the first core of the first processor is connected to the fourth core of the first processor, and the second core of the first processor is connected to the third core of the first processor; The first core of the second processor is connected to the second core of the second processor, the second core of the second processor is connected to the fourth core of the second processor, the fourth core of the second processor is connected to the third core of the second processor, and the third core of the second processor is connected to the first core of the second processor; the first core of the second processor is connected to the fourth core of the second processor, and the second core of the second processor is connected to the third core of the second processor.

7. The processor interconnect resource adjustment method according to claim 1, characterized in that: The method comprises: The obtaining first performance data of the processor includes: Collecting performance test data of the processor through monitoring software; Creating a neural network model based on performance test data of the processor; Testing the neural network model by cross-validation; Optimizing and adjusting the neural network model; Acquire first performance data of the processor through the optimized neural network model; The method further includes: reacquiring the fifth performance data of the processor, adjusting the channel signal state between the processor and the switch according to the processor interconnection bandwidth rate comparison result, and re-updating the calculation according to the fifth performance data of the processor to determine the target hardware connection topology mode.

8. A processor interconnection resource adjustment device, the device is applied to a processor interconnection resource adjustment system, the system comprises a first processor, a second processor and a switch, the first processor is connected to the second processor, the first processor and the second processor are respectively connected to the switch, characterized in that: The device comprises: An acquisition module, configured to acquire the interconnection bandwidth rate between the first processor and the second processor and the first interconnection bandwidth rate to acquire first performance data of the processor, wherein the first performance data of the processor includes a bandwidth rate parameter and a delay parameter; A comparison module, configured to compare a current processor interconnection bandwidth rate with the first interconnection bandwidth rate; A determination module, configured to adjust the channel signal state between the processor and the switch according to the comparison result and to update the calculation according to the first performance data of the processor to determine the target hardware connection topology mode; The adjustment module is used to adjust the processor interconnection resources through the target hardware connection topology mode.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the processor interconnection resource adjustment method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the processor interconnection resource adjustment method according to any one of claims 1 to 7 are implemented.

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