Microprocessor architecture and computer equipment

Abstract

The invention provides a microprocessor architecture and computer equipment. The microprocessor architecture comprises a first processor, an input / output processor and at least one peripheral controller, the input / output processor comprises at least one special processor core; the processor core contained in the input / output processor is used as an intermediate medium when the first processor interacts with the at least one peripheral controller. According to the microprocessor architecture, resource consumption during interaction between the processor and the peripheral can be reduced, and the burden of the processor can be reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a microprocessor architecture and a computer device. Background Art

[0002] In the existing microprocessor architecture, the processor directly interacts with the peripheral controller, thereby realizing data communication between the processor and the peripheral controller.

[0003] As the functions of microprocessor architecture become more and more abundant, various peripheral controllers are integrated into the microprocessor architecture. At this time, the direct interaction between the processor and each peripheral controller will bring heavy workload to the processor and affect the performance of the processor. Summary of the invention

[0004] Based on the above technical problems, the present application proposes a microprocessor architecture and a computer device, which can reduce the resource consumption during the interaction between the processor and peripherals, and reduce the burden on the processor.

[0005] The first aspect of the present application proposes a microprocessor architecture, comprising: a first processor, an input-output processor and at least one peripheral controller; the input-output processor includes at least one dedicated processor core; the processor core contained in the input-output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller.

[0006] A second aspect of the present application provides a computer device, which includes the above-mentioned microprocessor architecture.

[0007] The microprocessor architecture proposed in the present application includes a first processor, an input-output processor and at least one peripheral controller; the input-output processor includes at least one dedicated processor core as an intermediate medium when the first processor interacts with the at least one peripheral controller. Based on the application of the above-mentioned input-output processor, when the first processor in the microprocessor architecture proposed in the present application needs to access any target peripheral controller among the peripheral controllers, it is not necessary to interact directly with the peripheral controller, and the processor core in the input-output processor acts as an intermediate medium to perform access to the target peripheral controller. The above-mentioned peripheral access method greatly reduces the resource consumption when the first processor interacts with the peripheral controller. In addition, since the first processor no longer interacts directly with the peripheral controller, it is not necessary to install the driver of the peripheral controller in the first processor, and there is no operation of upgrading or updating the driver of the peripheral controller, thereby further reducing the burden of the first processor and reducing resource consumption.

[0008] In some implementations, the processor core included in the input-output processor is used to send the access request to the target peripheral controller when receiving the access request sent by the first processor for the target peripheral controller; or, the processor core included in the input-output processor is used to obtain the data to be transmitted from the target peripheral controller when receiving the data transmission request initiated by the target peripheral controller, and send a notification message to the first processor, wherein the notification message is used to notify the first processor to read the data to be transmitted from the input-output processor; wherein the target peripheral controller is any peripheral controller among the at least one peripheral controller. Based on this implementation, the first processor can access the peripheral controller through the input-output processor, and the peripheral controller can also send data to the first processor through the input-output processor, thereby reducing the resource consumption of the first processor in both scenarios.

[0009] In some implementations, the microprocessor architecture further includes a second processor, wherein the second processor has a higher security level than the first processor, and the second processor is used to perform security control on the microprocessor architecture. Based on this implementation, reliable security control of the entire microprocessor architecture can be achieved through the second processor with a higher security level, thereby improving the security of the microprocessor architecture.

[0010] In some implementations, the microprocessor architecture is equipped with one or more of a common execution environment subsystem, a trusted execution environment subsystem, and a secure element subsystem; wherein the first processor is used to respond to access requests initiated by the common execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the secure element subsystem. Based on this implementation, the execution environments with different security levels are equipped in the microprocessor architecture, which can meet the running of programs with various security levels and ensure the security of the microprocessor architecture.

[0011] In some implementations, the input-output processor further includes: a network interconnection module, an SRAM, and a register array; wherein the network interconnection module is respectively connected to the first processor, the at least one peripheral controller, and various parts of the input-output processor, and is used to provide communication links for the first processor, the at least one peripheral controller, and various parts of the input-output processor; a shared storage space is provided in the SRAM, which is used to store the interaction information between the first processor and the processor core, and to store the startup program of the processor core; the register array includes registers required for the interaction between the first processor and the processor core, and interrupt registers. Based on this implementation, the SRAM and register array in the input-output processor are used to implement the interaction between the first processor and various peripheral controllers instead of the input-output processor, thereby reducing the resource consumption of the first processor caused by the interaction between the first processor and the peripheral controller.

[0012] In some implementations, the register array module further includes a hardware direct transfer register corresponding to each of the at least one peripheral controller; any of the hardware direct transfer registers is used to receive an access request sent by the first processor for the peripheral controller corresponding to the hardware direct transfer register, and forward the access request to the corresponding peripheral controller. Based on this implementation, the first processor can directly interact with the peripheral controller through the hardware direct transfer register, thereby saving computing resources of the processor core in the input and output processor.

[0013] In some implementations, the input-output processor also includes a direct memory access module connected to the network interconnection module; the processor core is also used to configure a data transmission task corresponding to the data transmission request in the direct memory access module when obtaining the data transmission request sent by the first processor; the data transmission request is used to request data transmission between the shared storage space and the peripheral controller, and the data transmission task includes information about the data to be transmitted; the direct memory access module is used to execute the data transmission task to transmit the data to be transmitted between the shared storage space and the peripheral controller. Based on this implementation, data transmission and movement are realized through the direct memory access module, which can improve data transmission efficiency and reduce resource consumption of the processor core of the input-output processor.

[0014] In some implementations, the SRAM has a shared storage space corresponding to each peripheral controller, the input / output processor further includes a first address remapping module, the first processor is connected to the first address remapping module, and the first address remapping module is connected to the network interconnection module; the first address remapping module is used to receive a first access request sent by the first processor for the first peripheral controller, modify the destination address of the first access request to the storage address of the shared storage space corresponding to the first peripheral controller, and send the modified first access request to the network interconnection module, so that the network interconnection module sends the first access request to the shared storage space corresponding to the first peripheral controller; wherein the first peripheral controller is any one of the at least one peripheral controller. Based on this implementation, the access request can be accurately sent to the shared storage space corresponding to the peripheral controller through address remapping, so that the shared storage space can be allocated to each peripheral controller based on the storage space actually required by the peripheral controller, and the upper system does not need to modify the shared storage space address set during initialization, so that the utilization rate of the storage space of the SRAM can be improved without the upper system being aware of it.

[0015] In some implementations, the input-output processor further includes a second address remapping module, the network interconnection module is connected to the second address remapping module, and the second address remapping module is connected to the processor core; the second address remapping module is used to receive a second access request sent by the processor core for the shared storage space corresponding to the second peripheral controller, modify the destination address of the second access request to the storage address of the shared storage space corresponding to the second peripheral controller, and send the modified second access request to the network interconnection module, so that the network interconnection module sends the second access request to the shared storage space corresponding to the second peripheral controller; wherein the second peripheral controller is any one of the at least one peripheral controller. Based on this implementation, the processor core can accurately access the actual shared storage space of the peripheral controller, and improve the storage space utilization of the SRAM without affecting the system settings.

[0016] In some implementations, the input-output processor further includes a direct memory access module and a third address remapping module; the network interconnection module is connected to the third address remapping module, and the third address remapping module is connected to the direct memory access module; the third address remapping module is used to receive a data read request for a shared storage space corresponding to a third peripheral controller sent by the direct memory access module, modify the destination address of the data read request to the storage address of the shared storage space corresponding to the third peripheral controller, and send the modified third access request to the network interconnection module, so that the network interconnection module sends the third access request to the shared storage space corresponding to the third peripheral controller; wherein the third peripheral controller is any one of the at least one peripheral controller. Based on this implementation, the direct memory access module can accurately access the actual shared storage space of the peripheral controller, thereby improving the storage space utilization of the SRAM without affecting the system settings.

[0017] In some implementations, the input / output processor further includes a trusted domain controller, the first processor is connected to the trusted domain controller, and the trusted domain controller is connected to the network interconnection module; the trusted domain controller is used to perform security control on the access request sent by the first processor. Based on this implementation, security control on the access request sent by the first processor can be achieved, thereby improving the access security of the first processor to the peripheral controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0019] Figure 1-Figure 12 They are schematic diagrams of the structures of various microprocessor architectures provided in the embodiments of the present application. DETAILED DESCRIPTION

[0020] The embodiment of the present application proposes an innovative microprocessor architecture, which has higher communication efficiency between the processor and the peripheral controller and can reduce resource consumption of data communication between the processor and the peripheral controller, thereby improving the processor performance of the microprocessor architecture.

[0021] Figure 1 A conventional microprocessor architecture is shown. Figure 1As shown, in the microprocessor architecture, the processor, DDR (Double Data Rate Synchronous Dynamic Random Access Memory), and the peripheral controller are interconnected through the on-chip network. A separate path is established between the processor and the peripheral controller through the on-chip network. When there are multiple peripheral controllers, the processor establishes a separate path with each peripheral controller through the on-chip network, so that the processor can directly communicate data with each peripheral controller.

[0022] The data communication process between the processor and the peripheral controller can be divided into several stages: the processor initiates a request, the peripheral controller responds to the request, the peripheral controller feeds back the response information to the processor, and the processor receives the response information. Since the processor interacts directly with the peripheral controller, during an interaction, the processor needs to wait until all the above stages are completed before executing other operations.

[0023] As the functions of microprocessor architecture become more and more abundant and the integration becomes higher and higher, more and more peripheral controllers are integrated into the microprocessor architecture. In this case, the communication interaction between the processor and the peripheral controller becomes more and more frequent, and the interaction with each peripheral controller goes through the above-mentioned multiple stages, which will cause the processor resources to be consumed for a long time in the communication and interaction process with the peripheral controller. Especially when the peripheral controller is a low-speed peripheral controller, the performance of the processor will be seriously affected due to the slow response speed of the peripheral controller.

[0024] In addition, the processor needs to load the peripheral controller driver for communication and interaction with the peripheral controller. When the number of peripheral controllers is large, the processor needs to load more peripheral controller drivers. Moreover, when the peripheral controller driver needs to be updated or upgraded, the processor needs to continue to upgrade the peripheral controller driver one by one. These processes will cause a lot of resource consumption to the processor.

[0025] In response to the above technical problems, the embodiments of the present application improve the structure and function of the existing microprocessor architecture and propose a new microprocessor architecture. The microprocessor architecture optimizes the communication method between the processor and the peripheral controller, thereby improving the communication efficiency between the processor and the peripheral controller, reducing the resource occupation of the processor, and helping to improve the processor performance.

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] The present application embodiment proposes a microprocessor architecture, see Figure 2 As shown, the microprocessor architecture includes:

[0028] A first processor 100 , an input output processor (IOP) 110 , and at least one peripheral controller 120 .

[0029] The first processor 100 is communicatively connected to the input / output processor 110 via an on-chip network 130 , and the input / output processor 110 is respectively connected to at least one peripheral controller 120 .

[0030] The on-chip network 130 is used as a communication network between various components within the entire microprocessor architecture, and is used to provide communication links between various components within the microprocessor architecture. Various types of buses, bus interfaces, etc. can be integrated in the on-chip network 130 to meet the communication requirements between the input and output processor 110 and various microprocessor architecture components such as the first processor 100, the second processor 140, and DDR based on any type of bus.

[0031] The input / output processor 110 includes at least one dedicated processor core 111 , which serves as an intermediate medium when the first processor 100 interacts with at least one peripheral controller 120 .

[0032] Specifically, the first processor 100 may be an application processor (AP) in a microprocessor architecture, and the application processor includes one or more processor cores, for example, the processor core may be an application processor core. The application processor core is the computing and control center of the entire processor architecture, and is used to execute instructions and operations.

[0033] At the same time, the application processor core, as the main processor core of the entire microprocessor architecture, is also used to start and control other processor cores in the microprocessor architecture, such as the processor core 111 in the input-output processor 110. For example, before the processor core 111 in the input-output processor 110 is started, the processor core of the first processor 100 copies the firmware program stored in the memory to the SRAM of the input-output processor 110, so that the processor core 111 in the input-output processor 110 can load the firmware program from the SRAM to start running.

[0034] At least one peripheral controller 120 in the above-mentioned microprocessor architecture may include any external device connected to the microprocessor architecture or a controller corresponding to an external device interface, such as a UART (Universal Asynchronous Receiver / Transmitter) controller, an I2C (Inter-Integrated Circuit) controller, an SPI (Serial Peripheral Interface) controller, an SD (Secure Digital) controller, a GMAC controller (Gigabit Media Access Controller), and the like.

[0035] In the embodiment of the present application, the above-mentioned peripheral controller 120 may include a low-speed peripheral controller. In this embodiment, the low-speed peripheral controller 120 is connected to the first processor 100 through the input-output processor 110, and the input-output processor 110 performs communication interaction with the low-speed peripherals, thereby avoiding the first processor 100 directly communicating with the low-speed peripherals and affecting the performance of the first processor 100.

[0036] In other embodiments, the high-speed peripheral controller in the microprocessor architecture can be directly connected to the first processor 100, so that the first processor 100 can directly communicate and interact with the high-speed peripheral controller, thereby ensuring the smooth execution of the high-speed peripheral interaction service.

[0037] In addition, in some embodiments, when the input / output processor 110 is operating at full capacity, the first processor 100 may interact directly with some low-speed peripheral controllers.

[0038] In some embodiments, it is possible to flexibly select which peripheral controllers are connected to the first processor 100 through the input / output processor 110, or flexibly select which peripheral controllers are directly connected to the first processor 100. Alternatively, for a certain peripheral controller, it is possible to enable the peripheral controller to interact directly with the first processor 100 in some cases, or to enable the interaction between the peripheral controller and the first processor 100 through the input / output processor 110 in some cases.

[0039] The input-output processor 110 is a hardware structure specially set in the microprocessor architecture in the embodiment of the present application for executing data communication operations between the first processor 100 and each peripheral controller 120. The input-output processor 110 includes at least one processor core 111 specially used for executing data communication operations between the first processor 100 and the peripheral controller 120.

[0040] In the embodiment of the present application, the above-mentioned processor core 111 is specifically a RISC-V (Reduced Instruction Set Computer-Five, the fifth generation reduced instruction set computer) core, that is, a processor core of the RISC-V instruction architecture, which mainly completes instruction access to modules with low real-time requirements such as low-speed peripherals.

[0041] The above-mentioned input-output processor 110 serves as an intermediate medium between the first processor 100 and each peripheral controller 120. The first processor 100 only needs to be connected to the input-output processor 110, and the input-output processor 110 is connected to each peripheral controller respectively. In this way, there is no need for the first processor 100 to establish a communication link with each peripheral controller separately.

[0042] At the same time, based on the above-mentioned setting of the input and output processor 110, in the interaction scenario between the first processor 100 and the peripheral controller, the input and output processor 110 can replace the first processor 100 to perform at least part of the interaction operations with the peripheral controller, thereby saving the processing resources of the first processor 100.

[0043] For example, when the first processor 100 needs to access any target peripheral controller among the peripheral controllers, it only needs to send an access request for the target peripheral controller to the input-output processor 110. The processor core 111 in the input-output processor 110 executes access to the target peripheral controller according to the access request sent by the first processor 100, such as sending the access request to the target peripheral controller, and when receiving the access result returned by the target peripheral controller for the access request, the access result returned by the target peripheral controller is fed back to the first processor 100. In the above process, the first processor 100 only needs to send the access request for the target peripheral controller to the input-output processor 110. At this time, the first processor 100 can perform other operations without performing subsequent interactive operations with the target peripheral controller. Instead, the input-output processor 110 sends the access request to perform actual access to the peripheral controller and feeds back the access result to the first processor 100. It can be seen that the above processing greatly reduces the resource consumption of the first processor 100 when interacting with the peripheral controller.

[0044] When any target peripheral controller among the peripheral controllers needs to send data to the first processor 100, a data transmission request is first sent to the input / output processor 110, and the data transmission request may be a set request or signal, such as an interrupt request or an interrupt signal; after receiving the data transmission request, the processor core 111 in the input / output processor 110 accesses the target peripheral controller to obtain the data to be transmitted, and stores the data to be transmitted in the input / output processor 110; then, the processor core 111 in the input / output processor 110 sends a notification message to the first processor 100, notifying the first processor to read the above-mentioned data to be transmitted from the input / output processor 110; when the first processor 100 receives the notification message, it may read the data to be transmitted from the input / output processor 110 at an appropriate time. In the above-mentioned data uplink interaction scenario, the input / output processor 110 executes the operations of receiving the data transmission request sent by the target peripheral controller and obtaining the data to be transmitted from the target peripheral controller. For the first processor 100, it only needs to read the data from the input / output processor 110 when receiving the notification message sent by the processor core 111 in the input / output processor 110. Compared with the direct interaction between the peripheral controller and the first processor 100, this process reduces the work disturbance to the first processor 100 and helps to reduce the work pressure of the first processor 100.

[0045] like Figure 2As shown, at least one peripheral controller 120 in the microprocessor architecture proposed in the embodiment of the present application is arranged outside the input-output processor 110, and at this time, each peripheral controller 120 is connected to the input-output processor 110 through the peripheral controller interface of the input-output processor 110. The above-mentioned peripheral controller setting method can more conveniently delete or add peripheral controllers connected to the input-output processor 110, so as to flexibly adjust the peripheral controller to communicate and interact directly with the first processor 100, or to communicate and interact with the first processor 100 through the input-output processor 110.

[0046] In other embodiments, one or more of the at least one peripheral controller 120 in the above-mentioned microprocessor architecture may be arranged inside the input-output processor 110, and the peripheral controller arranged inside the input-output processor 110 may be connected to other parts of the input-output processor 110 through the communication link inside the input-output processor 110. The above-mentioned peripheral controller arrangement method can, on the one hand, improve the security of the peripheral controller, that is, the first processor 100 must interact with the peripheral controller through the input-output processor 110, and the first processor 100 cannot interact with the peripheral controller directly, so that the security of the peripheral controller can be ensured by the input-output processor 110, for example, the input-output processor 110 performs security verification and security control on the interaction process between the first processor 100 and the peripheral controller; on the other hand, arranging the peripheral controller inside the input-output processor 110 can facilitate the modification, adjustment, optimization and other operations of the peripheral controller inside the input-output processor, so that the manufacturer of the input-output processor completely privatizes the peripheral controller without describing any information of the peripheral controller to the outside.

[0047] In the above embodiment, since the first processor 100 no longer performs actual interactive operations with at least part of the peripheral controllers (low-speed peripheral controllers), there is no need to install the drivers of these peripheral controllers in the first processor 100, and there is no operation to upgrade or update the drivers of these peripheral controllers, thereby further reducing the burden on the first processor 100 and reducing resource consumption.

[0048] In other embodiments, see Figure 3 As shown, the above-mentioned microprocessor architecture further includes a second processor 140 , which is connected to the first processor 100 , and is connected to other parts of the microprocessor architecture via an on-chip network 130 .

[0049] The security level of the second processor 140 is higher than that of the first processor 100, so it has higher security. Based on the high security level of the second processor 140, programs with high security requirements can be run on the second processor 140, and a security measurement service module can be installed in the second processor 140 to perform security measurement on other modules.

[0050] In practical applications, the second processor may be a security element SE, which may be used to perform security control on the microprocessor architecture.

[0051] In some embodiments, the security element SE includes a system control processor (SCP), which serves as the clock reset control center of the entire microprocessor architecture. It mainly provides a working clock and clock frequency adjustment for each module of the microprocessor architecture, and controls the reset of each module so that the chip can complete initialization normally after power-on, which also includes clock and reset control of the input and output processor 110.

[0052] It is also disclosed in other embodiments that the above-mentioned microprocessor architecture is also equipped with one or more of a Rich Execution Environment (REE) subsystem, a Trusted Execution Environment (TEE) subsystem, and a Secure Element (SE) subsystem.

[0053] Among them, the common execution environment subsystem REE may include a general operating system running on a processor, in which an application is installed. The application running in the REE can be called a common application (Client Application, CA), which has low security and is vulnerable to attacks. Although many security measures such as device access control, device data encryption mechanism, isolation mechanism during application runtime, and access control based on permission verification are taken in REE, the security of important data in the application cannot be guaranteed.

[0054] The trusted execution environment subsystem TEE can be an independent operating environment running outside the general operating system, which can provide trusted services to REE and be isolated from REE. One or more trusted applications (TEEApplication, TA) can be executed in TEE, which provides a trusted operating environment for the general execution environment subsystem REE through trusted applications, and then ensures end-to-end security through the protection of confidentiality, integrity and control of data access rights. In addition, TEE can run in parallel with REE, and for example, TEE interacts with REE through a secure application programming interface (Application ProgrammingInterface, API).

[0055] TEE provides an operating environment with a higher security level than REE, but cannot provide a secure key storage and key operating environment at the hardware isolation level. Generally, TEE can provide many application programming interfaces for REE to call TEE resources. The more application programming interfaces TEE provides for services, the greater the risk TEE faces. It is difficult to ensure that the application programming interface itself does not have security risks, such as security vulnerabilities, which in turn lead to security risks for resources such as keys in TEE. Furthermore, multiple trusted applications TA will run in TEE, and the trusted applications TA are completely dependent on the isolation mechanism provided by the TEE operating system, without hardware-level isolation. This means that if the trusted application TA itself has security vulnerabilities or the trusted application TA actively accesses the keys or root keys corresponding to other trusted applications TA, it will also lead to great security risks for sensitive resources such as keys.

[0056] The security element subsystem is a software system running on the security element SE, which provides security services based on the hardware of the security element SE. Since the security element subsystem is mounted in an independent hardware environment, it is easy to establish physical protection and implement security assurance, thereby improving the security strength of the security element subsystem to serve security systems with higher security requirements. As an example, TEE can pass a security service request to the security element subsystem to request the provision of corresponding security services and respond based on the request. For example, the security service can be a request for the security element subsystem to perform services related to cryptographic operations.

[0057] Figure 4The microprocessor architecture is shown in which the common execution environment subsystem REE and the trusted execution environment subsystem TEE are mounted on the first processor 100, and the security element subsystem is mounted on the second processor 140 (security element SE). The microprocessor architecture enables the security element subsystem to independently process tasks and respond to requests, so that the task execution of the security element subsystem is completely independent and not affected by the execution environment of other subsystems, which is conducive to improving the security of the microprocessor architecture and also conducive to improving the task execution efficiency of the security element subsystem. Furthermore, this implementation method can reduce the hardware resource consumption of the processor and improve the processing performance of the processor.

[0058] exist Figure 4 In the microprocessor architecture shown, the first processor 100 is used to respond to access requests initiated by the normal execution environment subsystem REE and / or the trusted execution environment subsystem TEE, such as responding to an access request initiated by the normal execution environment subsystem REE subsystem and / or the trusted execution environment subsystem TEE subsystem for any peripheral controller, and sending an access request corresponding to the peripheral controller to the input-output processor 110; the second processor 140 is used to respond to access requests initiated by the security element subsystem, such as responding to an access request initiated by the security element subsystem for any peripheral controller, and sending an access request corresponding to the peripheral controller to the input-output processor 110.

[0059] In some embodiments, see Figure 5 As shown, the input-output processor 100 in the above-mentioned microprocessor architecture further includes:

[0060] Network interconnect module 112 , SRAM 113 and register array 114 .

[0061] The network interconnection module 112 is connected to the on-chip network 130, so that the network interconnection module 112 is connected to the first processor 100 and the second processor 140 respectively. At the same time, the network interconnection module 112 is also connected to at least one peripheral controller 120 and other parts inside the input and output processor 100, such as Figure 5 As shown in FIG. 1 , the network interconnection module 112 is connected to the SRAM 113 , the processor core 111 and the register array 114 respectively.

[0062] The network interconnection module 112 serves as a communication route within the input / output processor 110 , and is used to provide communication links for the first processor 100 , the second processor 140 , the at least one peripheral controller 120 , and various parts within the input / output processor 110 .

[0063] Specifically, the network interconnection module 112 can send the access request sent by the first processor 100 for any target peripheral controller to the SRAM 113 and the register array 114, send the request sent by the processor core 111 to the SRAM 113 and the register array 114, and so on.

[0064] Various types of buses, bus interfaces, etc. can be integrated in the network interconnection module 112 to meet the communication requirements based on any type of bus between various parts within the input / output processor 110, and at the same time meet the communication requirements based on any type of bus between the input / output processor 110 and the first processor 100, the second processor 140, the peripheral controller 120 and other components.

[0065] A shared storage space is provided in the SRAM 113 . The shared storage space is mainly divided into two categories. One is used to store the interaction information between the first processor 100 and the processor core 111 , and the other is used to store the startup program of the processor core 111 .

[0066] For the above-mentioned first type of shared storage space, it can specifically include shared storage space corresponding to each peripheral controller 120, which is used to store data information for interaction between the first processor 100 and the corresponding peripheral controller 120, including data sent by the first processor 100 to the peripheral, and data sent by the peripheral to the first processor 100.

[0067] In some embodiments, see Figure 6 As shown, the microprocessor architecture further includes a DDR memory 150. Since the size of the SRAM 113 in the input / output processor 110 is limited, part or all of the firmware program of the processor core 111 can be stored in the DDR memory 150. At the same time, the processor core 111 has a path to read the firmware program from the DDR memory 150, thereby avoiding the situation where the space of the SRAM 113 is insufficient to store the firmware program of the processor core 111.

[0068] The register array 114 includes registers required for the first processor 100 to interact with the processor core 111 , and interrupt registers.

[0069] Specifically, the register array 114 is an array composed of a series of registers. For example, a register module may be provided corresponding to each peripheral controller in the microprocessor architecture, and the register modules corresponding to each peripheral controller constitute the register array 114 .

[0070] In the above-mentioned register module, registers required for the interaction between the first processor 100 and the processor core 111 and interrupt registers for generating interrupts may be included. Specifically, the register array 114 includes a sending head pointer register, a sending tail pointer register, a receiving head pointer register, a receiving tail pointer register, a spare head pointer register 0, a spare tail pointer register 0, a spare head pointer register 1, a spare tail pointer register 1, an interrupt mask register from the first processor 100 to the processor core 111, an interrupt status register from the first processor 100 to the processor core 111, an interrupt mask register from the processor core 111 to the first processor 100, an interrupt status register from the processor core 111 to the first processor 100, a peripheral occupied shared space actual size register, a sending or receiving ring depth number register, a spare 0 / 1 ring depth number register, a hardware direct transfer register, a hardware direct transfer address register, a software custom register, and a regional direct transfer register.

[0071] In other embodiments, see Figure 7 As shown, the input / output processor 110 further includes a watchdog 115 and a timer 116, both of which are connected to the network interconnection module 112. The watchdog 115 is used to monitor whether there is an abnormality in the operation of the processor core 111. Once an abnormality occurs, the watchdog 115 will reset the processor core 111 after a timeout, so that it returns to normal and restarts operation. The timer 116 is used for system timing of the processor core 111.

[0072] In some embodiments, for each peripheral controller 120 in the above-mentioned microprocessor architecture, a corresponding hardware direct transfer register is set in the register array 114 in the input / output processor 110, that is, a corresponding hardware direct transfer register is set for each peripheral controller 120.

[0073] In addition, in the register array 114, a hardware direct transfer address register corresponding to each peripheral controller 120 is also provided, which is used to store the direct transfer communication address of the peripheral controller 120. The hardware direct transfer address register and the peripheral controller 120 may be in a one-to-one relationship, that is, one peripheral controller 120 corresponds to one hardware direct transfer address register, and the hardware direct transfer address register is only used to store the direct transfer communication address of the corresponding peripheral controller 120; or, multiple peripheral controllers 120 may correspond to one hardware direct transfer address register, for example, two peripheral controllers 120 correspond to one hardware direct transfer address register, and different storage addresses in the hardware direct transfer address register are used to store the direct transfer communication addresses of different peripheral controllers 120 corresponding thereto.

[0074] The above-mentioned hardware direct transfer address register can only be accessed by the processor core 111 in the input / output processor 110 , and the processor core 111 configures the corresponding direct transfer communication address of the peripheral controller 120 in the hardware direct transfer address register.

[0075] Based on the direct communication addresses of the peripheral controllers 120 configured by the processor core 111 in the above-mentioned hardware direct address register, when the first processor 100 needs to access a certain target peripheral controller, it can directly send an access request to the hardware direct register corresponding to the target peripheral controller in the register array 114 in the input / output processor 110. The access request carries the identification information of the target peripheral controller.

[0076] When the hardware direct transfer register corresponding to the target peripheral controller receives an access request for the target peripheral controller, it can determine that the access request is an access request for the target peripheral controller based on the identification information in the access request; or, based on the one-to-one relationship between the hardware direct transfer register and the peripheral controller, when the hardware direct transfer register corresponding to the target peripheral controller receives an access request, based on the above one-to-one relationship, it can be determined that the access request is an access request for the target peripheral controller corresponding to the hardware direct transfer register.

[0077] Through the above processing, when the hardware direct transfer register corresponding to the target peripheral controller confirms that an access request for the target peripheral controller has been received, the direct transfer communication address of the target peripheral controller is obtained from the hardware direct transfer address register corresponding to the target peripheral controller, and then based on the direct transfer communication address, the received access request is directly forwarded to the target peripheral controller.

[0078] In another embodiment, it is disclosed that the hardware direct transfer register inside the register array 114 in the input-output processor 110 is connected to the APB bus in the network interconnection module 112 through the APB bus interface, and the APB bus is connected to the APB bus in the on-chip network 130 of the microprocessor architecture upward, thereby realizing the communication connection based on the APB bus with the first processor 100, the second processor 140, etc.; at the same time, the hardware direct transfer register is connected to the AHB bus in the network interconnection module 112 in the input-output processor 110 through the AHB bus interface, thereby realizing the communication connection based on the AHB bus with the peripheral controller 120.

[0079] Based on the above bus connection mode, the access request initiated by the first processor 100 for the target peripheral controller is sent to the hardware direct transfer register corresponding to the target peripheral controller via the APB bus. The hardware direct transfer register is provided with an APB bus to AHB bus module. When receiving the access request of the APB bus, the module converts the access request into an AHB bus access request carrying the direct transfer communication address of the target peripheral controller obtained from the hardware direct transfer address register, and sends the AHB bus access request to the target peripheral controller via the AHB bus of the network interconnection module 112. In the above process, the hardware direct transfer register realizes the conversion of the APB bus request into the AHB bus request, and sends the converted AHB bus to the target peripheral controller, realizing the direct access of the first processor 100 to the target peripheral controller.

[0080] The above-mentioned hardware direct transfer method enables the first processor 100 to only send an access request to the hardware direct transfer register corresponding to the target peripheral controller when it needs to access any target peripheral controller. The hardware direct transfer register can directly forward the access request to the target peripheral controller without the participation of the processor core 111 in the input and output processor 110. The processor core 111 only needs to configure the direct transfer communication address corresponding to the peripheral controller in the hardware direct transfer address register in advance.

[0081] In some embodiments, see Figure 8 As shown, the input and output processor 110 of the microprocessor architecture proposed in the embodiment of the present application also includes a direct memory access (DMA) module 117, and the DMA module 117 is connected to the network interconnection module 112, and can communicate with the processor core 111, SRAM 113 and the peripheral controller 120 through the network interconnection module 112.

[0082] Based on the setting of the DMA module 117, in this embodiment, the processor core 111 in the input / output processor 110 obtains the data transmission request sent by the first processor 100. For example, the first processor 100 stores the target data to be sent to any target peripheral controller in the shared storage space corresponding to the target peripheral controller in the SRAM 113 of the input / output processor 110, and writes the request information in the shared storage space. Then, the first processor 100 notifies the processor core 111 to read the data transmission request (target data and request information) from the shared storage space of the target peripheral controller by writing the relevant registers in the register array 114. At this time, the processor core 111 can obtain the data transmission request for the target peripheral controller sent by the first processor 100 by accessing the shared storage space of the target peripheral controller. The data transmission request is used to request the transmission of the above target data between the shared storage space of the SRAM 113 (the shared storage space corresponding to the target peripheral controller) and the target peripheral controller.

[0083] After obtaining the above data transmission request, the processor core 111 accesses the DMA module 117 through the network interconnection module 112, and configures a data transmission task corresponding to the above data transmission request in the DMA module 117. The data transmission task includes information of the data to be transmitted, that is, information of the above target data, such as the storage address of the target data in the SRAM 113, the target data size, the data type, etc. The data transmission task is used to transmit the data to be transmitted between the target peripheral controller and the shared storage space corresponding to the target peripheral controller according to the requirements of the above data transmission request.

[0084] After acquiring the data transmission task configured by the processor core 111, the DMA module 117 executes the data transmission task, that is, transmits the above-mentioned target data between the target peripheral controller and the shared storage space corresponding to the target peripheral controller. For example, the target data sent by the first processor 100 is read from the shared storage space corresponding to the target peripheral controller, and then the target data is sent to the target peripheral controller.

[0085] Alternatively, in other embodiments, the data transfer request sent by the first processor 100 to the processor core 111 may only include information of the target data to be transferred and corresponding request information, but not the data content of the target data itself. For example, when the first processor 100 needs to read the target data from the target peripheral controller, it may write a data transfer request containing relevant information of the target data, such as a data transfer request containing information such as the name, size, and type of the target data, to the shared storage space of the target peripheral controller, and then notify the processor core 111 through the register array 114 to obtain the data transfer request from the shared storage space of the target peripheral controller. After the processor core 111 obtains the data transfer request, it configures a data transfer task corresponding to the data transfer request in the DMA module 117, in which the relevant information of the target data to be transferred and the corresponding data transfer task information are included. When executing the data transfer task, the DMA module 117 obtains the target data from the target peripheral controller according to the relevant information of the target data to be transferred, and then sends the target data to the shared storage space corresponding to the target peripheral controller, so that the first processor 100 can obtain the target data from the shared storage space.

[0086] In other embodiments, when any target peripheral controller needs to send data to the first processor 100, a data transmission request is first sent to the processor core 111 in the input / output processor 110. When the processor core 111 in the input / output processor 110 obtains the data transmission request sent by the target peripheral controller, it accesses the DMA module 117 through the network interconnection module 112, and configures a data transmission task corresponding to the data transmission request in the DMA module 117. The data transmission task includes specific task information of the data transmission task, that is, obtaining the data to be transmitted from the target peripheral controller and storing it in the shared storage space corresponding to the target peripheral controller, and also includes the address information of the shared storage space corresponding to the target peripheral controller.

[0087] After acquiring the data transmission task configured by the processor core 111, the DMA module 117 executes the data transmission task, that is, reads the data to be transmitted from the target peripheral controller, and then sends the data to be transmitted to the shared storage space corresponding to the target peripheral controller. After completing the above-mentioned data reading and storage operations, the DMA module 117 sends a message to the processor core 111 in the input-output processor 110, informing the processor core 111 that the reading and storage of the data to be transmitted have been completed. Then, the processor core 111 can send a notification message to the first processor 100, informing the first processor 100 to read the data to be transmitted from the shared storage space corresponding to the above-mentioned target peripheral controller in the input-output processor 110.

[0088] After receiving the notification message, the first processor 100 can choose to access the shared storage space corresponding to the target peripheral controller in the input / output processor 110 and read the data to be transmitted.

[0089] In other embodiments, see Fig. 9 As shown, in the input-output processor 110 of the above-mentioned microprocessor architecture, a first address remapping module 118 is also provided, and the first address remapping module 118 is connected to the on-chip network 130, so as to realize connection with the first processor 100, the second processor 140, the DDR memory 150 and other components through the on-chip network 130. At the same time, the first address remapping module 118 is also connected to the network interconnection module 112 inside the input-output processor 110, so that the first address remapping module 118 can realize connection with each component in the input-output processor 110 through the network interconnection module 112.

[0090] As described in the above embodiment, a shared storage space corresponding to each peripheral controller is provided in the SRAM 113 in the input / output processor 100, for storing the interaction data between the first processor 100 and the peripheral controller. Based on the initialization definition of the upper layer of the computer system, a fixed-size shared storage space is provided in the SRAM 113 for each peripheral controller, for example, 4K of shared storage space is allocated to each peripheral controller.

[0091] Based on the above-mentioned fixed shared memory space allocation, when the computer system sends an access request to any target peripheral controller through the first processor 100, the access request is sent with the address of the fixed shared memory space allocated to the target peripheral controller as the access request destination address. In other words, the destination address of the access request to any target peripheral controller sent by the first processor 100 is the address of the fixed shared memory space allocated to the target peripheral controller.

[0092] However, in the SRAM 113 of the input / output processor 110, since the storage resources are limited, in order to expand the utilization rate of the storage resources of the SRAM 113 and avoid limiting the waste of storage space, the shared storage space can be flexibly allocated according to the size of the shared storage space actually required by each peripheral controller. That is, in actual situations, the shared storage space required by the peripheral controller may not reach 4K. At this time, if 4K of shared storage space is still allocated to the peripheral controller, it will cause a waste of storage space. When the number of peripheral controllers is large, it will also cause a large amount of storage space waste.

[0093] To avoid wasting SRAM storage space, in this embodiment, shared storage space is allocated in SRAM 113 based on the size of shared storage space actually required by each peripheral controller, rather than directly allocating a fixed-size shared storage space to each peripheral controller.

[0094] Specifically, the processor core 111 in the input / output processor 110 allocates a shared storage space of a required size to each peripheral controller in the SRAM 113 according to the size of the shared storage space required by each peripheral controller.

[0095] Based on the above-mentioned shared storage space allocation method, it is possible to avoid wasting SRAM storage space and improve the storage space utilization of SRAM 113 .

[0096] At the same time, in order to avoid the above-mentioned shared storage space allocation method from affecting the upper computer system, this embodiment does not force the upper computer system to change the storage address of the storage space of each peripheral controller, and the upper computer system can still send access requests to the peripheral controller according to the address of the initial shared storage space allocated to each peripheral controller. In other words, the destination address of the access request sent by the first processor 100 to the target peripheral controller is still the destination address of the shared storage space allocated to the target peripheral controller according to the fixed size when the system is initialized.

[0097] In this case, since the shared memory space of the target peripheral controller set by the system is inconsistent with the shared memory space actually allocated for the target peripheral controller, the network interconnection module 112 in the on-chip network 130 and the input / output processor 110 cannot accurately send the access request for the target peripheral controller to the actual shared memory space allocated for the target peripheral controller based on the destination address of the access request sent by the first processor 100.

[0098] In order to be able to accurately send the access request for any target peripheral controller sent by the first processor 100 to the actual shared storage space allocated for the target peripheral controller without modifying the initialization settings of the computer system, this embodiment sets a first address remapping module 118 inside the input and output processor 110, which is used to remap the destination address of the access request for the peripheral controller sent by the first processor 110 according to the address of the actual shared storage space allocated by the processor core 111 to each peripheral controller, and remap the destination address of the access request to the address of the actual shared storage space of the peripheral controller.

[0099] like Fig. 9As shown, the first address remapping module 118 is arranged on the path between the on-chip network 130 and the network interconnection module 112, and is used to perform address remapping on the access request sent by the first processor 100 to the peripheral controller.

[0100] Specifically, when the first address remapping module 118 receives the first access request sent by the first processor 100 for the first peripheral controller, the destination address of the first access request is modified to the storage address of the shared storage space corresponding to the first peripheral controller. The storage address of the shared storage space corresponding to the first peripheral controller here refers to the storage address of the shared storage space allocated to the first peripheral controller in the SRAM 113 by the processor core 111 in the input and output processor 110 according to the size of the shared storage space required by the first peripheral controller. Then, the first address remapping module sends the first access request with the modified destination address to the network interconnection module 112. The network interconnection module 112 routes and sends the first access request according to the destination address of the first access request with the modified destination address, and thus sends the first access request to the shared storage space actually allocated to the first peripheral controller. The above-mentioned first peripheral controller is any one of the at least one peripheral controller of the above-mentioned microprocessor architecture.

[0101] In some embodiments, it is disclosed that after allocating shared storage space for each peripheral controller, the processor core 111 in the input / output processor 110 may store the address of the shared storage space allocated for each peripheral controller in the relevant register of the register array 114. When the first address remapping module 118 performs address remapping on the first access request sent by the first processor 100 for the first peripheral controller, it first accesses the relevant register in the register array 114 to obtain the address information of the shared storage space allocated for the first peripheral controller, and then performs address remapping on the first access request according to the address information, that is, the destination address of the first access request is modified to the address of the shared storage space actually allocated by the first peripheral controller.

[0102] Through the above scheme, the shared storage space of each peripheral controller is set based on the size of the shared storage space required by each peripheral controller, thereby avoiding waste of storage space and improving the storage space utilization rate of SRAM113. At the same time, the first processor 100 can send an access request to the peripheral controller according to the system initialization setting, so that the access request sent by the first processor 100 can be accurately remapped to the actual shared storage space of the peripheral controller without the perception of the upper system.

[0103] In another embodiment, see Fig.10As shown, in the input-output processor 110, a second address remapping module 119 is also provided. The second address remapping module 119 is provided on the path between the network interconnection module 112 and the processor core 111, so that the interaction information between the network interconnection module 112 and the processor core 111 will pass through the second address remapping module 119.

[0104] The second address remapping module 119 is used to receive a second access request sent by the processor core 111 for the shared storage space corresponding to the second peripheral controller, and modify the destination address of the second access request to the storage address of the shared storage space corresponding to the second peripheral controller.

[0105] Exemplarily, when the first processor 100 sends an access request to the second peripheral controller, the access request is remapped to the actual shared storage space of the second peripheral controller for storage through the first address remapping module 118. Then, the first processor 100 notifies the processor core 111 to read the access request from the shared storage space of the second peripheral controller by configuring the registers in the register array 114.

[0106] Since the first processor 100 does not know the actual address of the shared storage space of the second peripheral controller, the information configured in the register array 114 still uses the address of the initial shared storage space allocated for the second peripheral controller. That is, the first processor 100 will notify the processor core to read the access request from the initial shared storage space allocated for the second peripheral controller through the configuration register array.

[0107] Correspondingly, after the processor core 111 obtains the corresponding request information from the register array 114, it issues a second access request to the shared storage space of the second peripheral controller. Since the address of the shared storage space of the second peripheral controller stored in the register array 114 is the initial address, the destination address of the second access request issued by the processor core 111 is also the address of the initial shared storage space of the second peripheral controller stored in the register array 114.

[0108] When the second access request is sent to the second address remapping module 119, the second address remapping module 119 modifies the destination address of the second access request to the address of the actual shared storage space of the second peripheral controller, and then sends the second access request with the modified destination address to the network interconnection module 112. The network interconnection module 112 sends the second access request to the actual shared storage space corresponding to the second peripheral controller according to the modified destination address of the second access request.

[0109] The second peripheral controller mentioned above is any one of the at least one peripheral controller of the microprocessor architecture.

[0110] In other embodiments, see Fig.11 As shown, the input-output processor 110 also includes a third address remapping module 1110, which is arranged on the path between the network interconnection module 112 and the DMA module 117, so that the interaction information between the network interconnection module 112 and the DMA module 117 will pass through the third address remapping module 1110.

[0111] The third address remapping module 1110 is used to receive a data read request for the shared storage space corresponding to the third peripheral controller sent by the DMA module 117, and modify the destination address of the data read request to the storage address of the actual shared storage space corresponding to the third peripheral controller.

[0112] Exemplarily, when the first processor 100 sends an access request to the third peripheral controller, the access request is remapped to the actual shared storage space of the third peripheral controller for storage through the first address remapping module 118. Then, the first processor 100 notifies the processor core 111 to read the access request from the shared storage space of the third peripheral controller by configuring the registers in the register array 114.

[0113] Since the first processor 100 does not know the actual shared storage space address of the third peripheral controller, the information configured in the register array 114 still uses the address of the initial shared storage space allocated for the third peripheral controller, that is, the first processor 100 will notify the processor core to read the access request from the initial shared storage space allocated for the third peripheral controller through the configuration register array.

[0114] Correspondingly, after the processor core 111 obtains the corresponding request information from the register array 114, it configures the data transmission task in the DMA module 117. Since the address of the shared memory space of the third peripheral controller stored in the register array 114 is the initial address, the data transmission task configured by the processor core 114 in the DMA module 117 also adopts the address of the initial shared memory space of the third peripheral controller stored in the register array 114.

[0115] When the data read request is sent to the third address remapping module 1110, the third address remapping module 1110 modifies the destination address of the data read request to the address of the actual shared storage space of the third peripheral controller, and then sends the data read request with the modified destination address to the network interconnection module 112. The network interconnection module 112 sends the data read request to the actual shared storage space corresponding to the third peripheral controller according to the modified destination address of the data read request.

[0116] The third peripheral controller mentioned above is any one of the at least one peripheral controller of the microprocessor architecture.

[0117] It is understandable that in the above Fig.10 and Fig.11 In the illustrated microprocessor architecture embodiment, the shared storage space of each peripheral controller of the microprocessor architecture is set based on the size of the shared storage space actually required by each peripheral controller, thereby avoiding waste of storage space and improving the storage space utilization rate of SRAM113. At the same time, when the first processor 100, the processor core 111 and the DMA module 117 need to access the shared storage space of any target peripheral controller, they can still send an access request to the shared storage space initially allocated to the target peripheral controller according to the system initialization setting, and then remap the access request through the above-mentioned address remapping modules, and remap the destination address of the access request to the address of the actual shared storage space, so as to achieve access to the actual shared storage space of the target peripheral controller, so that the access request for the target peripheral controller can be accurately remapped to the actual shared storage space of the target peripheral controller without the perception of the upper system.

[0118] In other embodiments, see Fig.12 As shown, in the microprocessor architecture of the embodiment, the input-output processor 110 also includes a trusted domain controller 1111, and the trusted domain controller 1111 is connected to the path between the on-chip network 130 and the network interconnection module 112. Through the on-chip network 130, the trusted domain controller 1111 is connected to the first processor 100, the second processor 140, etc., and through the network interconnection module 112, the trusted domain controller 1111 is connected to each part of the input-output processor 110 and each peripheral controller 120.

[0119] Based on the above connection relationship, the access request for any peripheral controller sent by the first processor 100 to the input / output processor 110 will pass through the trusted domain controller 1111 , and the trusted domain controller 1111 is used to perform security control on the access request sent by the first processor 100 .

[0120] Specifically, the present embodiment sets security attributes for each peripheral controller in advance. When an access request for any peripheral controller sent by the first processor 100 reaches the trusted domain controller 1111, the trusted domain controller 1111 first verifies the security attributes of the access request and the security attributes of the peripheral controller to be accessed by the access request, determines whether the security attributes of the access request match the security attributes of the peripheral controller to be accessed, and then determines whether the access request can be sent to the corresponding peripheral controller.

[0121] When the security attribute of the access request sent by the first processor 100 is the same as the security attribute of the peripheral controller to be accessed, the trusted domain controller 1111 can issue the access request, that is, allow the first processor 100 to access the peripheral controller to be accessed; when the security attribute of the access request sent by the first processor 100 is different from the security attribute of the peripheral controller to be accessed, and the security of the access request is lower than the security of the peripheral controller to be accessed, such as the access request is a non-secure access request, and the peripheral controller to be accessed is a secure peripheral controller, the trusted domain controller 1111 filters the access request and prohibits the issuance of the access request; if the security attribute of the access request sent by the first processor 100 is different from the security attribute of the peripheral controller to be accessed, and the security of the access request is higher than the security of the peripheral controller to be accessed, such as the access request is a secure access request, and the peripheral controller to be accessed is a non-secure peripheral controller, the trusted domain controller 1111 issues the access request, allowing the first processor 100 to access the peripheral controller to be accessed.

[0122] Through the above processing of the trusted domain controller 1111, the access request of the first processor 100 to the peripheral controller is securely controlled in the input / output processor 110, thereby preventing the non-secure access request from reaching the secure peripheral controller and affecting the security of the peripheral controller. Therefore, the application of the above-mentioned trusted domain controller 1111 improves the security of the peripheral controller of the entire microprocessor architecture.

[0123] In the above-mentioned embodiments, different design aspects of the microprocessor architecture proposed in the present application are introduced respectively. Those skilled in the art can understand that the above-mentioned embodiments do not limit the specific structure and function of the microprocessor architecture, but are a partial or partial introduction to the structure and function of the microprocessor architecture. The structure and function of the microprocessor architecture introduced in each embodiment can be combined with each other, or split and then combined. These are all determined by those skilled in the art based on the knowledge in the field, and will not be introduced in detail one by one in this specification.

[0124] In the above embodiments, the first processor 100, the second processor 140 and other processors are circuits with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and execution capabilities, such as a CPU, a microprocessor, a GPU, or a DSP; in another implementation, the processor can implement certain functions through the logical relationship of the hardware circuit, and the logical relationship of the hardware circuit is fixed or reconfigurable, such as a processor that is a hardware circuit implemented by an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the processor loads a configuration document to implement the process of hardware circuit configuration, which can be understood as the processor loading instructions to implement some or all of the above processor functions. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as an NPU, TPU, DPU, etc.

[0125] Based on the above-mentioned microprocessor architecture, another embodiment of the present application further proposes a computer device, which includes the microprocessor architecture introduced in any of the above-mentioned embodiments.

[0126] Exemplarily, the above-mentioned computer device can be any single device such as a personal computer, a server, an industrial computer, a workstation, a handheld terminal, a wearable device, a smart terminal, etc.

[0127] Since the computer device has the above-mentioned microprocessor architecture, the computer device has the functions or structural characteristics of the above-mentioned microprocessor architecture, and has the beneficial effects of the above-mentioned microprocessor architecture. The specific structure and function of the microprocessor architecture in the above-mentioned computer device can be found in the introduction of the above-mentioned microprocessor architecture embodiment, which will not be repeated here.

[0128] For the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0129] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0130] The steps in the methods of each embodiment of the present application can be adjusted in order, combined and deleted according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0131] The modules and sub-modules in the devices and terminals of the various embodiments of the present application can be combined, divided and deleted according to actual needs.

[0132] In the several embodiments provided in the present application, it should be understood that the disclosed terminals, devices and methods can be implemented in other ways. For example, the terminal embodiments described above are only schematic, for example, the division of modules or submodules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple submodules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0133] The modules or submodules described as separate components may or may not be physically separated, and the components of the modules or submodules may or may not be physical modules or submodules, that is, they may be located in one place, or they may be distributed on multiple network modules or submodules. Some or all of the modules or submodules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0134] In addition, each functional module or submodule in each embodiment of the present application may be integrated into one processing module, or each module or submodule may exist physically separately, or two or more modules or submodules may be integrated into one module. The above-mentioned integrated modules or submodules may be implemented in the form of hardware or in the form of software functional modules or submodules.

[0135] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0136] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly by hardware, software units executed by a processor, or a combination of the two. The software units may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0137] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0138] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A microprocessor architecture, characterized in that: include: a first processor, an input-output processor, and at least one peripheral controller; The input-output processor includes at least one dedicated processor core; The processor core included in the input-output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller.

2. The microprocessor architecture according to claim 1, characterized in that: The processor core included in the input / output processor is used for sending the access request to the target peripheral controller when receiving the access request sent by the first processor to the target peripheral controller; or, The processor core included in the input / output processor is used to obtain the data to be transmitted from the target peripheral controller when receiving a data transmission request initiated by the target peripheral controller, and send a notification message to the first processor, wherein the notification message is used to notify the first processor to read the data to be transmitted from the input / output processor; The target peripheral controller is any peripheral controller among the at least one peripheral controller.

3. The microprocessor architecture according to claim 1, characterized in that: The microprocessor architecture also includes a second processor, wherein the security level of the second processor is higher than that of the first processor, and the second processor is used to perform security control on the microprocessor architecture.

4. The microprocessor architecture according to claim 3, characterized in that: The microprocessor architecture is equipped with one or more of a common execution environment subsystem, a trusted execution environment subsystem, and a secure element subsystem; The first processor is used to respond to access requests initiated by the common execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the secure element subsystem.

5. The microprocessor architecture according to any one of claims 1 to 4, characterized in that: The input-output processor also includes: Network interconnect modules, SRAM, and register arrays; The network interconnection module is respectively connected to the first processor, the at least one peripheral controller and various parts of the input-output processor, and is used to provide communication links for the first processor, the at least one peripheral controller and various parts of the input-output processor; The SRAM is provided with a shared storage space for storing interaction information between the first processor and the processor core, and for storing a startup program of the processor core; The register array includes registers required for the first processor to interact with the processor core, and interrupt registers.

6. The microprocessor architecture according to claim 5, characterized in that: The register array module also includes a hardware direct transfer register corresponding to each of the at least one peripheral controller; any of the hardware direct transfer registers is used to receive an access request sent by the first processor to the peripheral controller corresponding to the hardware direct transfer register, and forward the access request to the corresponding peripheral controller.

7. The microprocessor architecture according to claim 5, characterized in that: The input-output processor also includes a direct memory access module connected to the network interconnection module; The processor core is further used for, when obtaining a data transmission request sent by the first processor, configuring a data transmission task corresponding to the data transmission request in the direct memory access module; the data transmission request is used to request data transmission between the shared storage space and the peripheral controller, and the data transmission task includes information of the data to be transmitted; The direct memory access module is used to execute the data transmission task to transmit the data to be transmitted between the shared storage space and the peripheral controller.

8. The microprocessor architecture according to claim 5, characterized in that: The SRAM has a shared storage space corresponding to each peripheral controller, the input-output processor further includes a first address remapping module, the first processor is connected to the first address remapping module, and the first address remapping module is connected to the network interconnection module; The first address remapping module is used to receive a first access request for a first peripheral controller sent by the first processor, modify the destination address of the first access request to a storage address of a shared storage space corresponding to the first peripheral controller, and send the modified first access request to the network interconnection module, so that the network interconnection module sends the first access request to the shared storage space corresponding to the first peripheral controller; The first peripheral controller is any one of the at least one peripheral controller.

9. The microprocessor architecture according to claim 8, characterized in that: The input-output processor further includes a second address remapping module, the network interconnection module is connected to the second address remapping module, and the second address remapping module is connected to the processor core; The second address remapping module is used to receive a second access request sent by the processor core for the shared storage space corresponding to the second peripheral controller, modify the destination address of the second access request to the storage address of the shared storage space corresponding to the second peripheral controller, and send the modified second access request to the network interconnection module, so that the network interconnection module sends the second access request to the shared storage space corresponding to the second peripheral controller; The second peripheral controller is any one of the at least one peripheral controller.

10. The microprocessor architecture according to claim 9, characterized in that: The input-output processor also includes a direct memory access module and a third address remapping module; The network interconnection module is connected to the third address remapping module, and the third address remapping module is connected to the direct memory access module; The third address remapping module is used to receive a data read request for a shared storage space corresponding to a third peripheral controller sent by the direct memory access module, modify a destination address of the data read request to a storage address of the shared storage space corresponding to the third peripheral controller, and send the modified third access request to the network interconnection module, so that the network interconnection module sends the third access request to the shared storage space corresponding to the third peripheral controller; The third peripheral controller is any one of the at least one peripheral controller.

11. The microprocessor architecture according to claim 5, characterized in that: The input-output processor further includes a trusted domain controller, the first processor is connected to the trusted domain controller, and the trusted domain controller is connected to the network interconnection module; The trusted domain controller is used to perform security control on the access request sent by the first processor.

12. The microprocessor architecture according to any one of claims 1 to 4, characterized in that: At least one of the at least one peripheral controller is disposed inside the input-output processor.

13. A computer device, characterized in that: Comprising a microprocessor architecture as claimed in any one of claims 1 to 12.

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