Large-bandwidth signal FFT generation method based on FPGA

Abstract

A large-bandwidth signal FFT (Fast Fourier Transform) generation method based on an FPGA (Field Programmable Gate Array) is characterized by comprising the following steps: step 1, a signal acquisition module acquires a large-bandwidth signal, divides the large-bandwidth signal into M frequency band signals according to frequency, and correspondingly inputs the large-bandwidth signal into M channels; step 2, in each channel, carrying out extraction, filtering, DFT calculation and frequency mixing processing on an input large-bandwidth signal X (n) in sequence, and outputting corresponding channel data to an FFT module; 3, the M channels correspondingly output channelized data of M frequency bands to the FFT module, the FFT module carries out fast Fourier transform on the M channelized data to obtain M FFT outputs, and the M FFT outputs are transmitted to a splicing module; and step 4, the splicing module splices the M FFT outputs to obtain a large-bandwidth FFT output. The method has the advantages that large-bandwidth signal FFT is achieved, the large-bandwidth FFT calculation amount is effectively reduced, and the calculation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a large bandwidth signal FFT generation method based on FPGA. Background Art

[0002] Discrete Fourier Transform DFT is a discrete form of Fourier Transform in both time domain and frequency domain, which transforms the sampling of time domain signal into the sampling of discrete time Fourier Transform DTFT frequency domain. In form, the sequences at both ends of the transformation (in time domain and frequency domain) are of finite length, but in fact, both sets of sequences should be considered as the main value sequences of discrete periodic signals. Even if DFT is performed on a discrete signal of finite length, it should be considered as a periodic signal after periodic extension before transformation.

[0003] Since the discrete Fourier transform (DFT) algorithm has a large amount of calculation and takes a long time, it is not conducive to the computer to process the signal in real time. Therefore, after the discovery of DFT, it could not be applied to actual engineering projects for a long time. It was not until a fast discrete Fourier calculation method, namely the fast Fourier transform (FFT), was discovered that the discrete Fourier transform was widely used in actual engineering.

[0004] The main process of traditional channelization is to first multiply each channel by The signal is shifted in the frequency domain, and the center frequency of each channel is 0 after the shift; then the high-frequency components are filtered out through a low-pass filter, and finally extracted. Since the signal of each channel is first mixed, then filtered, and then extracted, there will be a lot of data calculation loss in the middle. Therefore, a simplified method is needed to make the calculation more efficient. Summary of the invention

[0005] The present invention provides a large bandwidth signal FFT generation method based on FPGA, which realizes large bandwidth signal FFT and effectively reduces the large bandwidth FFT calculation amount.

[0006] To achieve the above object, the present invention provides a method for generating a large bandwidth signal FFT based on FPGA, the key of which is to include the following steps:

[0007] Step 1: The signal acquisition module acquires a large bandwidth signal X(n), divides the large bandwidth signal X(n) into M frequency bands according to the frequency, and then inputs the large bandwidth signal X(n) into M channels with the same logical structure respectively;

[0008] Step 2: In each of the channels, the input large bandwidth signal X(n) is sequentially subjected to extraction, filtering, DFT calculation, and mixing processing, and the corresponding channel data is output to the FFT module;

[0009] Step 3: The M channels output channelized data of M frequency bands to the FFT module, and the FFT module performs fast Fourier transform on the M channelized data respectively to obtain M FFT outputs, and transmits them to the splicing module;

[0010] Step 4: The splicing module splices the M FFT outputs to obtain a large-bandwidth FFT output.

[0011] Through the above design, channel division is achieved through a multi-phase structure, so that a large bandwidth signal can be divided into multiple small bandwidth signals, and then FFT is performed on the small bandwidth signal in each channel, and then the effective part of the FFT result of the effective channel is spliced, thereby realizing FFT of a large broadband signal.

[0012] The data of each channel is sequentially subjected to decimation, filtering, discrete Fourier transform DFT and mixing operations, thus realizing multi-phase filtering processing of large-bandwidth signals, effectively reducing the amount of computational effort in channelization processing and making large-bandwidth FFT calculations more efficient.

[0013] Preferably, in step 2, the i-th channel performs extraction, filtering, DFT calculation, and mixing processing on the input large bandwidth signal X(n), and the specific steps are as follows:

[0014] Step 2.1: The extraction module in the i-th channel performs D-times sampling extraction on the large bandwidth signal X(n) to obtain the i-th sampling data a(i), and transmits it to the filtering module;

[0015] Step 2.2: The filtering module performs filtering processing on the i-th sampling data a(i) to obtain the i-th filtered data b(i), and passes it to the DFT module;

[0016] Step 2.3: The DFT module performs a discrete Fourier transform on the i-th filtered data b(i) to obtain the i-th DFT output c(i), and passes it to the mixing module;

[0017] Step 2.4: The mixing module performs mixing processing on the i-th filtered data c(i) to obtain the i-th channelized data d(i), and passes it to the FFT module.

[0018] Preferably, steps 1-4 are all implemented in FPGA.

[0019] Preferably, the FPGA is provided with a signal acquisition processing module, an FFT mode selection module, a direct FFT acquisition module, a multi-phase filtering module, a multi-phase FFT acquisition module and an FFT module, and the multi-phase filtering module is provided with the signal acquisition module, the extraction module, the filtering module, the DFT module and the mixing module.

[0020] The polyphase filtering module realizes polyphase filtering processing of large bandwidth signals in FPGA, that is, parallel processing of multi-channel data information.

[0021] Preferably, the signal acquisition and processing module acquires the large bandwidth signal X(n), and converts the large bandwidth signal X(n) into a standard baseband signal and transmits it to the FFT mode selection module;

[0022] The FFT mode selection module passes the large-bandwidth baseband signal whose FFT point requirement is less than the threshold to the direct FFT acquisition module according to the FFT point requirement of the standard baseband signal, and passes the large-bandwidth baseband signal whose FFT point requirement is greater than or equal to the threshold to the multi-phase filtering module. The multi-phase filtering module performs multi-phase filtering on the large-bandwidth baseband signal and then passes it to the FFT module.

[0023] Through the above design, the signal acquisition and processing module is used to collect original bandwidth data and process the data into a standard baseband signal. The FFT mode selection module is based on the FFT point requirement of the standard baseband signal, and then the baseband signal with a small FFT point requirement is sent to the direct FFT acquisition module for direct FFT, and the large bandwidth baseband signal is sent to the multi-phase filtering module for multi-phase filtering processing before FFT.

[0024] Preferably, the signal acquisition and processing module is provided with an AD sampling unit, a down-conversion unit, a half-band extraction unit and a first asynchronous fifo unit.

[0025] First, the sampled large bandwidth signal is down-converted to a baseband signal, then half-band extracted, and then enters the asynchronous FIFO for clock domain conversion.

[0026] Preferably, the direct FFT acquisition module comprises a first serial-to-parallel conversion unit, a third asynchronous FIFO unit and a direct FFT acquisition unit.

[0027] The direct FFT acquisition module performs serial-to-parallel conversion on the baseband signal, and then enters the asynchronous fifo for clock domain conversion, and then collects the data to the FFT module through the direct FFT acquisition unit for FFT calculation.

[0028] Preferably, the multi-phase FFT acquisition module is provided with a second serial-to-parallel conversion unit, a fourth asynchronous fifo unit, a DDR3 control module, a parallel-to-serial conversion unit, a third serial-to-parallel conversion unit and a multi-phase mode FFT acquisition unit.

[0029] The multi-phase mode FFT acquisition module first converts the multi-phase filtering result into parallel and serial, then enters the asynchronous fifo for clock domain conversion, and then enters the DDR3 control module for cache reading. The read data is first converted into serial and then converted into parallel. Finally, the multi-phase mode FFT acquisition unit samples the data into the FFT module for FFT calculation.

[0030] Preferably, the DDR3 control module is provided with a DDR interface module and an address management module.

[0031] The beneficial effects of the present invention are as follows: channel division is achieved through a multi-phase structure, a large bandwidth signal is divided into multiple small bandwidth signals, and then FFT is performed on the small bandwidth signal in each channel, and then the effective part of the FFT result of the effective channel is spliced, thereby realizing FFT of a large broadband signal, effectively reducing the amount of large bandwidth FFT calculations and improving calculation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the process of Example 1;

[0033] Figure 2 This is a flowchart of the multiphase filtering process of a large bandwidth signal in Example 1;

[0034] Figure 3 It is a schematic diagram of FPGA structure;

[0035] Figure 4 This is a schematic diagram of the structure of the signal acquisition and processing module in Example 1;

[0036] Figure 5 This is a schematic diagram of the structure of the direct FFT acquisition module in Example 1;

[0037] Figure 6 This is a schematic diagram of the structure of the multi-phase FFT acquisition module in Example 1;

[0038] Figure 7 This is a block diagram for implementing Embodiment 3;

[0039] Figure 8 It is the design diagram of the HB filter in Example 3;

[0040] Fig. 9 The HB filter coefficients in Example 3 are quantized and designed;

[0041] Fig.10 It is the total FIR filter setting of the multi-phase filtering in Example 3. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below in conjunction with the accompanying drawings and specific examples. The following examples or drawings are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0043] Example 1: Figure 1 , Figure 2 As shown: A method for generating FFT of a large bandwidth signal based on FPGA, comprising the following steps:

[0044] Step 1: The signal acquisition module acquires a large bandwidth signal X(n), divides the large bandwidth signal X(n) into M frequency bands according to the frequency, and then inputs the large bandwidth signal X(n) into M channels with the same logical structure respectively;

[0045] Step 2: In each of the channels, the input large bandwidth signal X(n) is sequentially subjected to extraction, filtering, DFT calculation, and mixing processing, and the corresponding channel data is output to the FFT module;

[0046] Step 3: The M channels output channelized data of M frequency bands to the FFT module, and the FFT module performs fast Fourier transform on the M channelized data respectively to obtain M FFT outputs, and transmits them to the splicing module;

[0047] Step 4: The splicing module splices the M FFT outputs to obtain a large-bandwidth FFT output.

[0048] In step 2, the i-th channel performs extraction, filtering, DFT calculation, and mixing processing on the input large bandwidth signal X(n), and the specific steps are as follows:

[0049] Step 2.1: The extraction module in the i-th channel performs D-times sampling extraction on the large bandwidth signal X(n) to obtain the i-th sampling data a(i), and transmits it to the filtering module;

[0050] Step 2.2: The filtering module performs filtering processing on the i-th sampling data a(i) to obtain the i-th filtered data b(i), and passes it to the DFT module;

[0051] Step 2.3: The DFT module performs a discrete Fourier transform on the i-th filtered data b(i) to obtain the i-th DFT output c(i), and passes it to the mixing module;

[0052] Step 2.4: The mixing module performs mixing processing on the i-th filtered data c(i) to obtain the i-th channelized data d(i), and passes it to the FFT module.

[0053] The steps 1-4 are all implemented in FPGA.

[0054] like Figure 3As shown: the FPGA is provided with a signal acquisition processing module, an FFT mode selection module, a direct FFT acquisition module, a multi-phase filtering module, a multi-phase FFT acquisition module and an FFT module, and the multi-phase filtering module is provided with the signal acquisition module, the extraction module, the filtering module, the DFT module and the mixing module.

[0055] The signal acquisition and processing module obtains the large bandwidth signal X(n), and converts the large bandwidth signal X(n) into a standard baseband signal and transmits it to the FFT mode selection module;

[0056] The FFT mode selection module passes the large-bandwidth baseband signal whose FFT point requirement is less than the threshold to the direct FFT acquisition module according to the FFT point requirement of the standard baseband signal, and passes the large-bandwidth baseband signal whose FFT point requirement is greater than or equal to the threshold to the multi-phase filtering module. The multi-phase filtering module performs multi-phase filtering on the large-bandwidth baseband signal and then passes it to the FFT module.

[0057] like Figure 4 As shown: the signal acquisition and processing module is provided with an AD sampling unit, a down-conversion unit, a half-band extraction unit and a first asynchronous fifo unit.

[0058] like Figure 5 As shown: the direct FFT acquisition module comprises a first serial-to-parallel conversion unit, a third asynchronous fifo unit and a direct FFT acquisition unit.

[0059] like Figure 6 As shown: the multi-phase FFT acquisition module is provided with a second serial-to-parallel conversion unit, a fourth asynchronous fifo unit, a DDR3 control module, a parallel-to-serial conversion unit, a third serial-to-parallel conversion unit and a multi-phase mode FFT acquisition unit.

[0060] The DDR3 control module is provided with a DDR interface module and an address management module.

[0061] Embodiment 2:

[0062] Example 2 is based on Example 1, and specifically implements the FFT implementation algorithm design with a minimum physical resolution of 100 Hz for a signal with a RF bandwidth of 120 MHz, a sampling rate of 307.2 MHz, and an intermediate frequency of 230.4 MHz.

[0063] First, the data collected by AD is down-converted to baseband, and then HB filtering is performed and decimated by 2 to obtain a baseband signal with a sampling rate of 153.6MHz and a digital bandwidth of 120MHz.

[0064] Among them, the channel overlap size, channel bandwidth, channel sampling rate, and number of channels are designed as follows:

[0065] Since the ratio of channel sampling rate to channel bandwidth is designed to be about 1.28, as shown in formula (1), fs represents the sampling rate of the large bandwidth baseband signal, D represents the channel decimation multiple, fs / D represents the channel sampling rate, M represents the number of channels, fs / M represents the channel spacing, C represents the channel overlap size, and fs / M+C represents the channel bandwidth. The channel overlap is at least twice the physical resolution in order to make the FFT result of the signal at the channel boundary symmetrical.

[0066]

[0067] To achieve 100Hz resolution at 153.6MHz sampling rate and 120MHz digital bandwidth, the number of FFT points needs to be in the millions. The design results of channel overlap size, channel bandwidth, channel sampling rate, and number of channels are shown in Table 1:

[0068] Table 1 Channel overlap size, channel bandwidth, channel sampling rate, number of channels

[0069]

[0070]

[0071] To achieve a physical resolution of 100 Hz, 1.6 MHz / 100 Hz = 16000, so the number of FFT points required for each channel is 16384, and the physical resolution is 1600000 Hz / 16384

[0072] =97.65625Hz, the total number of FFT points actually achieved is 16384*128=2097152.

[0073] (2) Channel FFT splicing

[0074] Since the required bandwidth is 120MHz and the channel spacing is 1.2MHz, the number of effective channels to be spliced ​​is (120MHz / 1.2MHz)+1=101, and the effective channel numbers are k=0~50, k=78~127. Except for effective channels 50 and 78, the effective bandwidth required for effective channels to be spliced ​​is -1.2MHz / 2~1.2MHz / 2, the effective bandwidth required for effective channel 50 is -1.2MHz / 2~0, and the effective bandwidth required for effective channel 78 is 0~0.6MHz.

[0075] The splicing order is as follows:

[0076] Channel number (k=0,1,...127) corresponds to the frequency range after splicing (-60MHz~60MHz)

[0077]

[0078]

[0079] Embodiment 3:

[0080] Example 2 is based on Example 1, and specifically implements the FPGA implementation scheme design of 64-point to 2M-point FFT for a signal with a RF bandwidth of 120MHz, a sampling rate of 307.2MHz, and an intermediate frequency of 230.4MHz. The scheme block diagram is shown in FIG. Figure 7 shown.

[0081] like Figure 7 As shown, the intermediate frequency signal with a sampling rate of 307.2MHz, an intermediate frequency of 230.4MHz, and a bandwidth of 120MHz is first down-converted to a baseband signal, and then half-band extraction is performed before entering the asynchronous fifo, and the clock domain is changed from 307.2MHz to 153.6MHz. The baseband signal with a sampling rate of 153.6MHz and a bandwidth of 120MHz is down-sampled according to the digital bandwidth setting; the FFT implementation method is selected according to the FFT point number. If the FFT point number is 64 to 16384 points, direct FFT is selected. If the FFT point number is 32768 to 2M points, FFT based on polyphase filtering is selected.

[0082] In order to reduce the clock domain of the subsequent FFT calculation to 102.4MHz, when direct FFT is selected, the downsampled signal is serial-to-parallel and then enters the asynchronous fifo, and the clock domain is changed from 153.6MHz to 102.4MHz. Then the FFT channel is selected, and a frame of FFT data is first sent to the first FFT module, and then a frame of the second FFT data is sent to the FFT module, and the process is performed alternately.

[0083] For the FFT based on multi-phase filtering, the downsampled signal enters the asynchronous fifo, the clock domain changes from 153.6MHz to 204.8MHz, and then enters the multi-phase filtering. The multi-phase filtering result is first converted from serial to parallel, from 48bit to 128bit, and then enters the asynchronous fifo, the clock domain changes from 204.8MHz to 102.4MHz, and then enters the DDR3 control module, and then the output data is first converted from parallel to serial, 128bit to 48bit, and then converted from serial to parallel, 48bit to 96bit. The multi-phase output data of one multi-phase channel is sent to the first FFT module, and the multi-phase output data of another multi-phase channel is sent to the second FFT module.

[0084] Below Figure 7 The various modules are designed and explained:

[0085] (1) Down-conversion unit

[0086] The sampling rate is 307.2MHz, the unit intermediate frequency is 230.4MHz, the digital intermediate frequency is selected as 76.8MHz, the DDS frequency control word is selected as 32bit, and the frequency control word is (76.8 / 307.2)*2^32=32'd 1073741824.

[0087] (2) HB unit

[0088] HB filter design as Figure 8 As shown, the sampling rate is 307.2MHz and the passband is 60MHz. The filter coefficients are quantized to 18 bits and the optimal accuracy is selected, such as Fig. 9 shown.

[0089] (3) Asynchronous fifo1 unit

[0090] The clock domain is reduced from 307.2MHz to 153.6MHz. The asynchronous fifo3 bit width is set to 48 and the depth is set to 128.

[0091] (4) FFT mode selection module

[0092] If the number of FFT points is greater than or equal to 64 points and less than or equal to 16384 points, select direct FFT; if the number of FFT points is greater than or equal to 32768 points and less than or equal to 2M points, select FFT based on polyphase filtering.

[0093] (5) Asynchronous fifo2 unit

[0094] The clock domain changes from 153.6MHz to 204.8MHz. The asynchronous fifo3 bit width is set to 48 and the depth is set to 128. The read rdy is always 1'b1.

[0095] (6) Serial-to-parallel conversion unit (48 bits to 96 bits)

[0096] The downsampled output IQ bit width is 24 bits each, and here the serial-to-parallel conversion is to convert two 48-bits into 96-bit outputs. The first one is placed in the upper 48 bits, and the second one is placed in the lower 48 bits.

[0097] (7) Asynchronous fifo3 unit

[0098] The clock domain is changed from 153.6MHz to 102.4MHz. The asynchronous fifo3 bit width is set to 96 and the depth is set to 128.

[0099] (8) Direct FFT acquisition module

[0100] According to the number of FFT points, one frame of FFT is output, first to the first FFT module, and the next frame of FFT is output to the second FFT module, and this is done alternately. According to the acquisition start instruction Sample_start, the acquisition begins, and Sample_done indicates that the acquisition is completed.

[0101] (9) Multiphase filter module

[0102] The fir filter is set as Fig.10 As shown, the number of tap coefficients of the FIR filter for each channel is 1920 / 128=15.

[0103] The multiphase filter module contains four submodules: multiphase input, multiphase fir, multiphase fft, and multiphase output. The multiphase input module is responsible for decimating the input data by 32 times and changing the input order, so that the multiphase fir can complete 3 times decimation. The multiphase fir completes filtering and 3 times decimation. The multiphase fir output has a parallel-to-serial conversion. Pay attention to the parallel-to-serial conversion order. The multiphase fft completes the 128-point FFT. The multiphase output module needs to multiply the multiphase FFT output by Where M = 128, D = 96, so

[0104] (10) Multi-phase mode FFT acquisition module

[0105] According to the acquisition start instruction Sample_start, the acquisition starts, and Sample_done indicates that the acquisition is completed. The input of the multi-phase mode FFT acquisition module is a 48-bit multi-phase filter (24 bits each for IQ) and the output is 128 bits. Since there are only 101 channels in the 120MHz band among the 128 channels, in order to include the multi-phase filter output data of two channels in 128 bits, the multi-phase filter output data of 102 channels is required. The rule of serial-to-parallel conversion here is not to simply convert 48 bits to 128 bits according to the multi-phase filter output order, but to follow the subsequent spectrum splicing order. First, the data of channels K=51 and 50 are synthesized into 128 bits, and then the data of channels K=49 and 48 are synthesized into 128 bits... The specific FPGA implementation requires 2 block memory IPs with a bit width of 48 bits and a depth of 128, and 4 block memory IPs with a bit width of 96 bits and a depth of 64. When implemented in FPGA, the output of the multi-phase mode FFT acquisition module (48 bits to 128 bits) plus the last signal, 51 values ​​are grouped.

[0106] (11) Asynchronous fifo4 unit

[0107] Asynchronous fifo4 unit, the clock domain is changed from 204.8MHz to 102.4MHz. The input bit width is 128 bits and the depth is 128.

[0108] (12)DDR3 control module

[0109] The DDR3 control module is used to cache the data after serial conversion of the multi-phase filter output in DDR3 first, and then read it. In FPGA implementation, if the DDR3 model used is MT41K256M16XX-125. Each bank has 512Mb, and a bank is divided into two parts. Use similar ping pang operations, first write bank_ping, and then write a whole packet of multi-phase filter output data. If the number of FFT packets is greater than 1, read bank_ping once (8 addresses, 1 128-bit data), and write bank_pang once (8 addresses, 1 128-bit data). When writing, pay attention to every 51 128-bit data written, the address of the next data to be written starts from adding 8*14. When reading, the address interval is 8*64. If the number of FFT packets is equal to 1, read once every two beats.

[0110] The DDR3-1 control module includes a DDR interface module and an address management module. The DDR interface module refers to the J326 ddr3_interface module.

[0111] (13) Parallel-to-serial conversion unit (128 bits to 48 bits), serial-to-parallel conversion unit (48 bits to 96 bits)

[0112] The 128-bit data read from DDR is composed of three 128-bit data into 384-bit data, and then split into four 96-bit data. The last data of each channel is output as the last signal.

[0113] (14) Parallel-to-serial unit

[0114] Convert 96-bit data to 48-bit data. A fifo is needed with a width of 64 bits, 32 users, and a depth of 4096. The fifo is read once every two beats. The maximum writing speed of the fifo is 76.8MHz (96bit), and the reading clock is 102.4MHz.

[0115] (15) Windowing unit

[0116] The number of FFT points is 64 to 16384, so the window coefficients must also be 64 to 16384. Due to the symmetry of the window coefficients, the number of window coefficients stored in blockram is half of the number of FFT points.

[0117] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for generating FFT of a large bandwidth signal based on FPGA, characterized by: The following steps are involved: Step 1: The signal acquisition module acquires a large-bandwidth signal X(n), divides the large-bandwidth signal X(n) into M frequency bands according to frequency, and then inputs the large-bandwidth signal X(n) into M channels with consistent logical structures. Step 2: In each of the channels, the input wide bandwidth signal X(n) is sequentially subjected to decimation, filtering, DFT calculation, and mixing processing, and the corresponding channel data is output to the FFT module; Step 3: The M channels output M frequency bands of channelized data to the FFT module. The FFT module performs fast Fourier transform on the M channelized data to obtain M FFT outputs, and transmits them to the splicing module. Step 4: The splicing module splices the M FFT outputs to obtain a large-bandwidth FFT output.

2. The FPGA-based FFT generation method for large-bandwidth signals according to claim 1, wherein: In step 2, the i-th channel performs extraction, filtering, DFT calculation, and mixing processing on the input large bandwidth signal X(n). The specific steps are as follows: Step 2.1: The decimation module in the i-th channel performs D-times sampling on the large bandwidth signal X(n) to obtain the i-th sampled data a(i), and passes it to the filtering module; Step 2.2: The filtering module performs filtering on the i-th sample data a(i) to obtain the i-th filtered data b(i), and passes it to the DFT module; Step 2.3: The DFT module performs a discrete Fourier transform on the i-th filtered data b(i) to obtain the i-th DFT output c(i), and passes it to the mixing module; Step 2.4: The mixing module performs mixing processing on the i-th filtered data c(i) to obtain the i-th channelized data d(i), and passes it to the FFT module.

3. The FPGA-based FFT generation method for large-bandwidth signals according to claim 2, wherein: The steps 1-4 are all implemented in FPGA.

4. The FPGA-based FFT generation method for large-bandwidth signals according to claim 3, wherein: The FPGA is provided with a signal acquisition and processing module, an FFT mode selection module, a direct FFT acquisition module, a polyphase filtering module, a polyphase FFT acquisition module and an FFT module. The polyphase filtering module is provided with the signal acquisition module, the extraction module, the filtering module, the DFT module and the mixing module.

5. The FPGA-based FFT generation method for large-bandwidth signals according to claim 4, characterized in that: The signal acquisition and processing module obtains the large bandwidth signal X(n), and converts the large bandwidth signal X(n) into a standard baseband signal and transmits it to the FFT mode selection module; The FFT mode selection module passes the large-bandwidth baseband signal with an FFT point requirement less than a threshold to the direct FFT acquisition module based on the FFT point requirement of the standard baseband signal, and passes the large-bandwidth baseband signal with an FFT point requirement greater than or equal to the threshold to the polyphase filtering module. The polyphase filtering module performs polyphase filtering on the large-bandwidth baseband signal and then passes it to the FFT module.

6. The FPGA-based FFT generation method for large-bandwidth signals according to claim 4, characterized in that: The signal acquisition and processing module is provided with an AD sampling unit, a down-conversion unit, a half-band extraction unit and a first asynchronous fifo unit.

7. The FPGA-based FFT generation method for large-bandwidth signals according to claim 4, characterized in that: The direct FFT acquisition module comprises a first serial-to-parallel conversion unit, a third asynchronous FIFO unit and a direct FFT acquisition unit.

8. The FPGA-based FFT generation method for large-bandwidth signals according to claim 4, wherein: The multi-phase FFT acquisition module is provided with a second serial-to-parallel conversion unit, a fourth asynchronous FIFO unit, a DDR3 control module, a parallel-to-serial conversion unit, a third serial-to-parallel conversion unit and a multi-phase mode FFT acquisition unit.

9. The FPGA-based FFT generation method for large-bandwidth signals according to claim 8, characterized in that: The DDR3 control module is provided with a DDR interface module and an address management module.

10. The FPGA-based FFT generation method for large-bandwidth signals according to claim 2, characterized in that: In step 2, the FFT generation method with a minimum physical resolution of 100 Hz is performed on the large bandwidth signal X(n) with a radio frequency bandwidth of F, a sampling rate of E, and an intermediate frequency of G. The process is as follows: The signal acquisition and processing module obtains the large bandwidth signal X(n), and down-converts the large bandwidth signal X(n) to baseband, then performs HB filtering and decimation by 2 to obtain a sampling rate of Baseband signal with digital bandwidth F; The channel overlap size, channel bandwidth, channel sampling rate, and number of channels are designed as follows: The ratio of the channel sampling rate to the channel bandwidth is designed to be 1.28, as shown in formula (1): Where fs represents the sampling rate of the wide-bandwidth baseband signal, D represents the channel decimation factor, fs / D represents the channel sampling rate, M represents the number of channels, fs / M represents the channel spacing, C represents the channel overlap, and fs / M+C represents the channel bandwidth. The channel overlap is at least twice the physical resolution so that the FFT results of the signals at the channel boundaries are symmetrical. The design results of channel overlap size, channel bandwidth, channel sampling rate, and number of channels are shown in Table 1: Table 1 Channel overlap size, channel bandwidth, channel sampling rate, and number of channels The number of FFT points required for each channel is 16384, the physical resolution is 1600000 Hz / 16384 = 97.65625 Hz, and the total number of FFT points is 16384*128 = 2097152; The bandwidth is 120MHz, the channel spacing is 1.2MHz, the number of effective channels spliced ​​is (120MHz / 1.2MHz)+1=101, the effective channel numbers are k=0~50, k=78~127; except for effective channels 50 and 78, the effective bandwidth of the effective channel splicing is - 1.2MHz / 2~1.2MHz / 2, the effective bandwidth of 50 effective channels is -1.2MHz / 2~0, the effective bandwidth of 78 effective channels is 0~0.6MHz; The splicing order is: Channel number (k=0,1,...127) corresponds to the frequency range after splicing (-60MHz to 60MHz)

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