Semiconductor device and method for controlling the same

Abstract

The invention relates to the technical field of semiconductor manufacturing and operation, in particular to a semiconductor device and a control method thereof. The method comprises the following steps: acquiring semiconductor data; extracting manufacturing parameter data of the semiconductor data to obtain semiconductor manufacturing parameter data; performing spatial modeling according to the semiconductor manufacturing parameter data to generate a semiconductor manufacturing three-dimensional thermal model; performing manufacturing process heat distribution monitoring on the semiconductor data through the semiconductor manufacturing three-dimensional thermal model to generate manufacturing process heat distribution data; and performing thermal stability prediction on the semiconductor manufacturing parameter data based on the manufacturing process thermal distribution data to generate thermal stability prediction data. Therefore, through the Internet of Things technology, the data analysis technology, the self-adaptive control technology and the image mapping technology, accurate prediction of the thermal stability of the semiconductor is realized, so that the lattice structure of the semiconductor is optimized and adjusted; and the semiconductor electric signal performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing and operation technology, and in particular to a semiconductor device and a control method thereof. Background Art

[0002] The emergence of transistor technology gradually replaced traditional vacuum tubes and was widely used in computing devices and communication technologies. The original semiconductor device was based on a single transistor. With the advancement of technology, multiple transistors were integrated into a chip to form early integrated circuits. This technological advancement has greatly improved the performance and reliability of devices and promoted the widespread application of electronic products. With the continuous evolution of integrated circuit technology, the integration and complexity of semiconductor devices have gradually increased, and the control method has also evolved from simple hardware control to intelligent control systems combined with software. In order to adapt to more complex needs, the control method has been further developed, including intelligent adaptive control, real-time monitoring and adjustment technology, which has greatly improved the efficiency and function of semiconductor devices. Today, semiconductor devices and their control methods have become the core technology of modern electronic devices, widely used in multiple fields of communications, computing and consumer electronics, and have promoted the rapid progress of the entire technology industry. However, the existing semiconductor control methods are inaccurate in predicting thermal stability and are not optimized and adjusted according to the lattice structure of the semiconductor, resulting in low electrical signal performance. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor device and a control method thereof to solve at least one of the above technical problems.

[0004] To achieve the above object, a semiconductor control method is provided, the method comprising the following steps:

[0005] Step S1: Acquire semiconductor data; extract manufacturing parameter data of the semiconductor data to obtain semiconductor manufacturing parameter data; perform spatial modeling based on the semiconductor manufacturing parameter data to generate a three-dimensional thermal model for semiconductor manufacturing; monitor the thermal distribution of the semiconductor data during the manufacturing process through the three-dimensional thermal model for semiconductor manufacturing to generate thermal distribution data for the manufacturing process;

[0006] Step S2: Predicting the thermal stability of semiconductor manufacturing parameter data based on the thermal distribution data of the manufacturing process to generate thermal stability prediction data; extracting the design parameter information of the semiconductor data to obtain the semiconductor design parameters; simulating the semiconductor manufacturing parameter data according to the semiconductor design parameters to generate manufacturing process simulation data; evaluating the thermal management efficiency of the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient;

[0007] Step S3: Optimizing the thermal control strategy of the manufacturing process simulation data according to the thermal management efficiency evaluation coefficient to generate thermal control parameter optimization data; determining the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data to obtain manufacturing key time data; evaluating the electrical signal characteristics of the semiconductor data based on the manufacturing key time data to generate electrical signal characteristic evaluation data;

[0008] Step S4: performing carrier mobility analysis on the electrical signal characteristic evaluation data to obtain carrier mobility data; performing electrical signal performance optimization on the semiconductor data according to the carrier mobility data to generate an electrical signal performance optimization solution;

[0009] Step S5: extract the microstructure information of the semiconductor data to obtain the semiconductor microstructure information; perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; perform fine-tuning control on the semiconductor according to the semiconductor microstructure image to obtain a semiconductor fine-tuning control plan; integrate the semiconductor fine-tuning control plan and the electrical signal performance optimization plan to generate a semiconductor control optimization report.

[0010] The present invention ensures a comprehensive understanding of semiconductor characteristics by acquiring semiconductor data and extracting manufacturing parameter data; constructs a three-dimensional thermal model of semiconductor manufacturing to achieve accurate simulation of heat distribution in the manufacturing process; monitors heat distribution through the three-dimensional thermal model of semiconductor manufacturing to clarify the heat distribution of semiconductor manufacturing; uses the thermal distribution data of the manufacturing process to predict thermal stability, thereby improving the accuracy of predicting semiconductor thermal stability; extracts design parameter information and performs simulations to enhance the effectiveness evaluation of semiconductor design; and evaluates thermal stability predictions through manufacturing process simulation data to provide quantitative indicators for subsequent optimization. According to the thermal management efficiency evaluation coefficient, the thermal control strategy is optimized to improve the thermal efficiency of the semiconductor manufacturing process; the manufacturing key time nodes are determined to ensure the precise control of the key steps in the manufacturing process; the electrical signal characteristics are evaluated based on the key time nodes, which is helpful to improve the electrical performance of the semiconductor; the carrier mobility analysis is performed on the electrical signal characteristic evaluation data, and the carrier mobility is accurately calculated; the electrical signal performance is optimized according to the carrier mobility data, and the electrical signal performance optimization scheme is generated, which can optimize the electrical performance of the semiconductor; the microstructure information of the semiconductor is extracted and analyzed, and detailed microscopic level data is provided for fine-tuning control; the semiconductor microstructure image is generated by the graphic mapping technology, and the microscopic characteristics of the semiconductor are intuitively displayed; the fine-tuning control scheme is combined with the electrical signal performance optimization scheme, and the generated semiconductor control optimization report provides comprehensive optimization guidance for the manufacturing process. Therefore, the present invention realizes the accurate prediction of the thermal stability of the semiconductor through the Internet of Things technology, data analysis technology, adaptive control technology and image mapping technology, so as to optimize and adjust the lattice structure of the semiconductor; thereby improving the electrical signal performance of the semiconductor.

[0011] Preferably, step S1 comprises the following steps:

[0012] Step S11: using a sensor to acquire semiconductor data; performing manufacturing process feature recognition on the semiconductor data to obtain manufacturing process feature data; determining parameter information on the manufacturing process feature data to generate semiconductor manufacturing parameter data;

[0013] Step S12: performing thermal characteristic analysis on the semiconductor manufacturing parameter data to obtain semiconductor thermal characteristic data; performing spatial distribution mapping on the semiconductor thermal characteristic data to obtain spatial distribution mapping data;

[0014] Step S13: performing heat conduction analysis processing on the spatial distribution mapping data to obtain heat conduction analysis results; performing three-dimensional morphology construction on the heat conduction analysis results to obtain a three-dimensional thermal model of semiconductor manufacturing;

[0015] Step S14: perform heat flow tracing processing on the semiconductor manufacturing three-dimensional thermal model to obtain semiconductor heat flow tracing data; perform temperature field analysis on the semiconductor heat flow tracing data to obtain semiconductor temperature field data; perform thermal gradient calculation on the semiconductor temperature field data to obtain semiconductor thermal gradient data; perform thermal distribution monitoring of the semiconductor data during the manufacturing process based on the semiconductor thermal gradient data to generate thermal distribution data during the manufacturing process.

[0016] The present invention obtains semiconductor data by utilizing sensors, thereby ensuring the real-time and accuracy of data; through manufacturing process feature recognition, the grasp of key features of the semiconductor manufacturing process is improved; parameter information of manufacturing process feature data is determined, providing accurate input for subsequent thermal characteristic analysis; thermal characteristic analysis makes the thermal behavior of semiconductors clearer and provides a scientific basis for thermal management; the generation of spatial distribution mapping data provides detailed spatial information for heat conduction analysis; the heat conduction analysis results provide necessary data support for the construction of three-dimensional models; the construction of a three-dimensional thermal model of semiconductor manufacturing allows the thermal distribution in the semiconductor manufacturing process to be intuitively displayed; heat flow tracking data processing allows the heat flow changes in the semiconductor manufacturing process to be accurately tracked; temperature field data analysis provides an important reference for temperature control in the semiconductor manufacturing process; thermal gradient calculation provides key gradient information for subsequent thermal distribution monitoring.

[0017] Preferably, step S2 comprises the following steps:

[0018] Step S21: performing thermal behavior pattern recognition on the thermal distribution data of the manufacturing process to obtain thermal behavior pattern data; performing thermal stability trend analysis on the thermal behavior pattern data to obtain thermal stability trend data;

[0019] Step S22: performing thermal effect correlation analysis on the thermal stability trend data to obtain thermal effect correlation data; performing parameter sensitivity determination on the thermal effect correlation data to obtain parameter sensitivity data;

[0020] Step S23: constructing a thermal stability prediction model for the parameter sensitivity data to obtain a thermal stability prediction model; performing thermal stability prediction on the semiconductor manufacturing parameter data based on the thermal stability prediction model to obtain thermal stability prediction data;

[0021] Step S24: performing design parameter semantic analysis on the semiconductor data to obtain semiconductor design parameters; performing manufacturing process mapping on the semiconductor design parameters to obtain manufacturing process mapping data;

[0022] Step S25: simulating the semiconductor manufacturing parameter data according to the manufacturing process mapping data to generate manufacturing process simulation data;

[0023] Step S26: performing thermal management efficiency evaluation on the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient.

[0024] The present invention accurately captures the thermal characteristics of semiconductors during the manufacturing process through thermal behavior pattern recognition, providing a basis for subsequent thermal stability analysis; thermal stability trend analysis enables the prediction of thermal behavior of semiconductor materials under different conditions, providing guidance for the optimization of the manufacturing process; thermal effect correlation analysis helps to understand the interaction between different thermal characteristic parameters, thereby more comprehensively evaluating thermal stability; parameter sensitivity determination provides a key input for the thermal stability prediction model, ensuring the accuracy and reliability of the model prediction; the construction of the thermal stability prediction model is based on parameter sensitivity data, which improves the model's prediction accuracy for the thermal stability of semiconductors; using the thermal stability prediction model to predict manufacturing parameter data is helpful to evaluate and improve the thermal performance of semiconductors before manufacturing; design parameter semantic analysis of semiconductor data can effectively identify the design parameters of the manufacturing process; manufacturing process mapping of semiconductor design parameters provides accurate input for simulation; simulation is based on manufacturing process mapping data and can reflect the physical phenomena in the actual manufacturing process; thermal management efficiency evaluation of thermal stability prediction data through manufacturing process simulation data can quantify the performance of thermal management strategies, providing key indicators for further optimization of thermal control strategies.

[0025] Preferably, step S25 comprises the following steps:

[0026] Step S251: performing process digitization processing on the manufacturing process mapping data to obtain digital process flow data; constructing a virtual manufacturing model for the semiconductor manufacturing parameter data according to the digital process flow data to obtain a semiconductor virtual manufacturing model;

[0027] Step S252: performing physical field coupling analysis on the semiconductor virtual manufacturing model to obtain physical field coupling data; performing thermodynamic response simulation on the semiconductor virtual manufacturing model according to the physical field coupling data to obtain thermodynamic response simulation data;

[0028] Step S253: performing material stress evolution simulation on the semiconductor virtual manufacturing model through the thermodynamic response simulation data to obtain material stress evolution data; performing process condition simulation on the semiconductor virtual manufacturing model according to the material stress evolution data to obtain process condition simulation data;

[0029] Step S254: performing equipment performance boundary simulation on the semiconductor virtual manufacturing model to obtain equipment performance boundary simulation data; performing quality parameter simulation on the semiconductor virtual manufacturing model according to the equipment performance boundary simulation data and the process condition simulation data to obtain quality parameter simulation data;

[0030] Step S255: Integrate process condition simulation data, equipment performance boundary simulation data and quality parameter simulation data to generate manufacturing process simulation data.

[0031] The present invention improves the accuracy and operability of process design by converting manufacturing process mapping data into digital process flow data; constructs a semiconductor virtual manufacturing model, so that the actual manufacturing process can be simulated and evaluated in a virtual environment, thereby optimizing subsequent manufacturing parameters;

[0032] Physical field coupling analysis provides an in-depth understanding of the interaction of multiple physical phenomena in the semiconductor manufacturing process; the generation of thermodynamic response simulation data provides predictions for the behavior of materials under different thermal conditions, which helps to prevent and solve heat-related problems; material stress evolution simulation can simulate the stress changes of materials during the manufacturing process, thereby guiding the adjustment of process conditions, reducing defects and improving product reliability; the generation of process condition simulation data provides detailed process parameters for actual production, which helps to achieve more precise process control; the device performance boundary simulation of the semiconductor virtual manufacturing model evaluates the performance of the equipment under extreme conditions and ensures the stability and safety of the equipment operation; the quality parameter simulation of the semiconductor virtual manufacturing model is performed based on the device performance boundary simulation data and the process condition simulation data, and the quality parameter control plan is simulated to improve product quality; the process condition, equipment performance and quality parameter simulation data are integrated to generate manufacturing process simulation data, which provides a scientific basis for the optimization of the manufacturing process and improves production efficiency and product quality.

[0033] Preferably, step S26 includes the following steps:

[0034] Step S261: performing heat energy distribution feature recognition on the process condition simulation data to obtain heat energy distribution data; performing heat load definition processing on the equipment performance boundary simulation data to obtain heat load definition data; performing heat quality influence analysis on the quality parameter simulation data to obtain heat quality influence data;

[0035] Step S262: performing thermal management collaborative analysis on the thermal energy distribution data, the thermal load definition data and the thermal quality impact data to obtain thermal management collaborative data;

[0036] Step S263: performing thermal energy utilization efficiency measurement on the thermal stability prediction data according to the thermal management collaborative data to obtain thermal energy utilization efficiency measurement data; performing thermal efficiency trend identification on the thermal energy utilization efficiency measurement data to obtain thermal efficiency trend data;

[0037] Step S264: perform heat flow balance verification on the thermal efficiency trend data to obtain heat flow balance verification data; perform thermal management efficiency evaluation on the heat flow balance verification data to obtain thermal management efficiency evaluation data; perform efficiency evaluation coefficient measurement calculation on the thermal management efficiency evaluation data to obtain a thermal management efficiency evaluation coefficient.

[0038] The present invention identifies the heat energy distribution characteristics of process condition simulation data, which can predict the distribution of heat energy in the semiconductor manufacturing process and provide data support for subsequent thermal management; the equipment performance boundary simulation data performs heat load definition processing, which helps to clarify the performance of the equipment under different heat load conditions, thereby ensuring that the equipment operates in a safe and efficient state; the quality parameter simulation data performs thermal quality impact analysis, evaluates the impact of heat treatment on semiconductor quality, and provides key information for improving product quality; thermal management collaborative analysis integrates heat energy distribution, heat load and thermal quality impact data, provides a comprehensive thermal management perspective, and makes thermal management measures more coordinated and efficient. The thermal energy utilization efficiency measurement provides a quantitative assessment of the use of heat energy in the semiconductor manufacturing process, which helps to identify and implement energy efficiency improvement measures; thermal efficiency trend identification predicts the effect of future heat energy use by analyzing the changing trend of thermal energy utilization efficiency, and provides a basis for the formulation of subsequent thermal management strategies; heat flow balance verification ensures the uniform distribution of heat energy in the semiconductor manufacturing process, prevents local overheating or overcooling, and ensures the uniformity and reliability of semiconductor products; thermal management efficiency assessment provides an evaluation of the effectiveness of current thermal management measures, and provides an optimization direction for further optimizing thermal management.

[0039] Preferably, step S3 comprises the following steps:

[0040] Step S31: optimizing the process parameters of the process condition simulation data according to the thermal management efficiency evaluation coefficient to obtain process parameter optimization data; adjusting the equipment operation mode of the equipment performance boundary simulation data according to the thermal management efficiency evaluation coefficient to obtain equipment operation mode adjustment data; performing quality intelligent control on the quality parameter simulation data according to the thermal management efficiency evaluation coefficient to obtain quality intelligent control data;

[0041] Step S32: Integrate process parameter optimization data, equipment operation mode adjustment data and quality intelligent control data to obtain thermal control parameter optimization data;

[0042] Step S33: performing key operation identification on the manufacturing process simulation data according to the thermal control parameter optimization data to obtain key operation identification data; performing time series analysis on the manufacturing process simulation data according to the key operation identification data to obtain manufacturing process time series data; performing time node synchronization processing on the manufacturing process time series data to obtain time node synchronization data;

[0043] Step S34: determining the key time nodes of the semiconductor manufacturing parameter data according to the time node synchronization data to obtain manufacturing key time data;

[0044] Step S35: Evaluate the electrical signal characteristics of the semiconductor data based on the manufacturing critical time data to generate electrical signal characteristic evaluation data.

[0045] The present invention optimizes the process parameters of the process condition simulation data according to the thermal management efficiency evaluation coefficient, so that the semiconductor manufacturing process is more accurate and the production efficiency and product quality are improved; the equipment operation mode is adjusted for the equipment performance boundary simulation data according to the thermal management efficiency evaluation coefficient, the equipment performance is optimized, the equipment is ensured to operate in the best state, and the energy consumption and maintenance cost are reduced; the quality parameter simulation data is intelligently controlled according to the thermal management efficiency evaluation coefficient, and the consistency and reliability of semiconductor products are improved; the integration of the thermal control parameter optimization data provides an optimization scheme for the manufacturing process, and further improves the control accuracy and efficiency of the manufacturing process; the key operation identification of the manufacturing process simulation data according to the thermal control parameter optimization data makes it possible to identify and optimize the key steps in the manufacturing process, thereby improving the overall production efficiency; through time series analysis, the changing trend in the manufacturing process can be better understood and predicted; the generation of time node synchronization data ensures time coordination in the manufacturing process and improves the smoothness of the production process; the determination of manufacturing key time data provides precise time control for the key steps in the semiconductor manufacturing process, which helps to improve product performance and yield; the in-depth analysis of the semiconductor electrical signal characteristics can optimize the electrical signal performance and improve the electrical performance and stability of semiconductor devices.

[0046] Preferably, step S35 includes the following steps:

[0047] Step S351: performing electrical signal characteristic recognition on semiconductor data to obtain semiconductor electrical signal characteristic data;

[0048] Step S352: performing electrical signal characteristic test planning on the semiconductor electrical signal characteristic data based on the manufacturing key time data to obtain electrical signal characteristic test planning data;

[0049] Step S353: performing electrical signal simulation on the electrical signal characteristic test planning data to generate electrical signal simulation data; performing semiconductor signal response acquisition on the electrical signal simulation data to obtain signal response acquisition data; performing high-frequency signal demodulation processing on the signal response acquisition data to obtain high-frequency signal demodulation data;

[0050] Step S354: performing harmonic analysis on the high-frequency signal demodulation data to obtain high-frequency harmonic analysis data; performing phase noise measurement on the high-frequency harmonic analysis data to obtain phase noise measurement data; performing frequency stability test on the phase noise measurement data to obtain frequency stability test data; performing parasitic parameter identification on the semiconductor data according to the frequency stability test data to obtain semiconductor parasitic parameter data;

[0051] Step S355: perform microscale effect verification on semiconductor parasitic parameter data to obtain microscale effect verification data; perform material defect signal characterization recording on the microscale effect verification data to obtain material defect signal characterization data; perform electrical signal characteristic evaluation on semiconductor data based on the material defect signal characterization data to obtain electrical signal characteristic evaluation data.

[0052] The present invention accurately obtains the characteristic data of semiconductor electrical signals through electrical signal characteristic identification, providing basic information for subsequent electrical signal performance optimization; uses manufacturing key time data to plan electrical signal characteristic tests, ensuring the pertinence and systematicness of the test, and improving test efficiency and accuracy; electrical signal simulation generation and signal response acquisition simulate the electrical signal behavior under actual working conditions, providing experimental data for signal demodulation processing; high-frequency signal demodulation processing effectively extracts useful information from analog signals, providing accurate data for signal analysis; harmonic analysis and phase noise measurement evaluate the purity and stability of signals, which is crucial to improving signal quality; frequency stability testing ensures the frequency stability of semiconductor devices under different working conditions, which is of great significance to ensuring product reliability; conducts microscale effect verification and material defect signal characterization, deeply analyzes the microscopic characteristics of semiconductor materials, and provides a scientific basis for material and process optimization. Conducting electrical signal characteristic evaluation provides a comprehensive evaluation of the electrical performance of semiconductor devices.

[0053] Preferably, step S4 comprises the following steps:

[0054] Step S41: performing carrier power analysis on the electrical signal characteristic evaluation data to obtain carrier power data; performing mobility distribution pattern recognition on the carrier power data to obtain mobility distribution pattern data;

[0055] Step S42: performing carrier mobility calculation on the mobility distribution pattern data to obtain carrier mobility data; performing electrical signal performance correlation on the carrier mobility data to obtain electrical signal performance correlation data;

[0056] Step S43: performing process doping configuration analysis on the process condition simulation data to obtain process doping configuration data; performing mobility measurement on the process doping configuration data according to the electrical signal performance correlation data to obtain doping configuration mobility data; performing process ratio adjustment on the process condition simulation data according to the doping configuration mobility data to obtain process electrical signal optimization data;

[0057] Step S44: performing interface charge anomaly detection on the device performance boundary simulation data according to the electrical signal performance correlation data to obtain device interface charge anomaly data; performing interface charge passivation layer adjustment on the device performance boundary simulation data according to the device interface charge anomaly data to obtain device electrical signal optimization data;

[0058] Step S45: Integrate the process electrical signal optimization data and the equipment electrical signal optimization data to obtain an electrical signal performance optimization solution.

[0059] The present invention performs carrier dynamics analysis on the electrical signal characteristic evaluation data, laying a foundation for the subsequent mobility distribution pattern recognition; mobility distribution pattern recognition can accurately grasp the movement law of carriers in semiconductors, which is helpful to optimize the electrical performance of semiconductors; carrier mobility calculation provides key parameters for electrical signal performance, which can accurately evaluate and predict the electrical signal transmission efficiency of semiconductors; electrical signal performance correlation data analysis helps to identify key factors affecting semiconductor electrical signal performance and provides direction for performance optimization; process doping configuration analysis can adjust the doping level according to the electrical signal performance requirements, thereby optimizing the electrical characteristics of semiconductors; mobility measurement and process ratio adjustment provide precise process control parameters for semiconductor manufacturing, which is helpful to improve the consistency and reliability of semiconductor products; interface charge anomaly detection can identify interface problems that affect semiconductor performance and improve the stability of semiconductor devices; interface charge passivation layer adjustment optimizes the interface characteristics of semiconductor devices and helps to improve the overall performance of devices; the integration of process electrical signal optimization data and equipment electrical signal optimization data provides a semiconductor electrical signal performance optimization solution, which is helpful to improve the overall performance and reliability of semiconductor devices.

[0060] Preferably, step S5 comprises the following steps:

[0061] Step S51: recognizing crystal features of semiconductor data to obtain semiconductor crystal feature data; performing crystal layout detection on the semiconductor crystal feature data to obtain semiconductor crystal layout data;

[0062] Step S52: determining the lattice constant of the semiconductor crystal layout data to obtain lattice constant information; calculating the crystal bit density of the lattice constant information to obtain crystal bit density data;

[0063] Step S53: determining the electron energy level distribution of the crystal bit density data to obtain the electron energy level distribution data; performing band structure identification on the semiconductor crystal layout data according to the electron energy level distribution data to obtain semiconductor band structure information;

[0064] Step S54: integrating semiconductor crystal layout data, crystal bit density data and semiconductor energy band structure information to obtain semiconductor microstructure information; using graphic mapping technology to perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image;

[0065] Step S55: fine-tuning the layout mode of the semiconductor crystal layout data according to the semiconductor microstructure image to generate crystal layout fine-tuning control data; fine-tuning the lattice parameter of the crystal bit density data according to the semiconductor microstructure image to generate lattice parameter fine-tuning control data; integrating the crystal layout fine-tuning control data and the lattice parameter fine-tuning control data to generate a semiconductor fine-tuning control scheme;

[0066] Step S56: Integrate the semiconductor fine-tuning control solution and the electrical signal performance optimization solution to generate a semiconductor control optimization report.

[0067] The acquisition of semiconductor crystal characteristic data by the present invention provides a basis for subsequent crystal layout detection and helps to identify the structural characteristics of the crystal; the generation of semiconductor crystal layout data can perform detailed analysis on the arrangement and organization of the crystal, providing an intuitive embodiment for optimizing the crystal structure; the determination of lattice constant information clarifies the physical properties of semiconductor materials and directly affects the electronic properties of the materials; the calculation of crystal bit density data provides important parameters for controlling the electronic behavior of semiconductor materials and helps to improve device performance; the determination of electronic energy level distribution data helps to understand the electronic state in semiconductors; the acquisition of semiconductor band structure information is key information for predicting and controlling the electronic behavior of semiconductors and affects the working efficiency and performance of semiconductors; the integration of semiconductor microstructure information provides a comprehensive perspective to observe and analyze the microscopic characteristics of materials and helps to discover and improve potential defects of materials; the generation of semiconductor microstructure images can intuitively observe the microscopic layout of materials and provide an intuitive reference for the microscopic design and improvement of materials; the lattice parameter fine-tuning control of crystal bit density data based on the semiconductor microstructure image can accurately control the physical properties of the crystal, and the semiconductor control optimization report provides a comprehensive optimization guide for semiconductor control, which helps to achieve refined management and quality control of the manufacturing process.

[0068] In this specification, a semiconductor device is provided for executing the above-mentioned semiconductor control method, and the semiconductor device includes:

[0069] A data acquisition module is used to acquire semiconductor data; extract manufacturing parameter data of semiconductor data to obtain semiconductor manufacturing parameter data; perform spatial modeling based on semiconductor manufacturing parameter data to generate a three-dimensional thermal model of semiconductor manufacturing; monitor the thermal distribution of semiconductor data during the manufacturing process through the three-dimensional thermal model of semiconductor manufacturing to generate thermal distribution data of the manufacturing process;

[0070] The semiconductor manufacturing process simulation module is used to predict the thermal stability of semiconductor manufacturing parameter data based on the thermal distribution data of the manufacturing process and generate thermal stability prediction data; extract the design parameter information of the semiconductor data to obtain the semiconductor design parameters; simulate the semiconductor manufacturing parameter data according to the semiconductor design parameters to generate manufacturing process simulation data; evaluate the thermal management efficiency of the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient;

[0071] The electrical signal characteristic evaluation module is used to optimize the thermal control strategy of the manufacturing process simulation data according to the thermal management efficiency evaluation coefficient and generate thermal control parameter optimization data; determine the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data to obtain the manufacturing key time data; evaluate the electrical signal characteristics of the semiconductor data based on the manufacturing key time data to generate the electrical signal characteristic evaluation data;

[0072] The electrical signal performance optimization module is used to perform carrier mobility analysis on the electrical signal characteristic evaluation data to obtain carrier mobility data; perform electrical signal performance optimization on the semiconductor data according to the carrier mobility data to generate an electrical signal performance optimization plan;

[0073] The microstructure control optimization module is used to extract the microstructure information of semiconductor data to obtain semiconductor microstructure information; perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; perform fine-tuning control on the semiconductor data according to the semiconductor microstructure image to obtain a semiconductor fine-tuning control plan; integrate the semiconductor fine-tuning control plan and the electrical signal performance optimization plan to generate a semiconductor control optimization report.

[0074] The present invention acquires semiconductor data and extracts manufacturing parameter data through a data acquisition module, thereby ensuring a comprehensive understanding of semiconductor characteristics; constructs a three-dimensional thermal model of semiconductor manufacturing, thereby realizing an accurate simulation of heat distribution in the manufacturing process; monitors heat distribution through the three-dimensional thermal model of semiconductor manufacturing, thereby clarifying the heat distribution of semiconductor manufacturing; predicts thermal stability using the thermal distribution data of the manufacturing process through a semiconductor manufacturing process simulation module, thereby improving the accuracy of predicting semiconductor thermal stability; extracts design parameter information and performs simulation, thereby enhancing the effectiveness evaluation of semiconductor design; and evaluates thermal stability prediction through manufacturing process simulation data, thereby providing quantitative indicators for subsequent optimization. The thermal control strategy is optimized according to the thermal management efficiency evaluation coefficient through the electrical signal characteristic evaluation module, thereby improving the thermal efficiency of the semiconductor manufacturing process; determining the key manufacturing time nodes ensures the precise control of the key steps in the manufacturing process; evaluating the electrical signal characteristics based on the key time nodes helps to improve the electrical performance of the semiconductor; the electrical signal performance optimization module performs carrier mobility analysis on the electrical signal characteristic evaluation data, and accurately calculates the carrier mobility; optimizes the electrical signal performance according to the carrier mobility data, generates an electrical signal performance optimization scheme, and can optimize the electrical performance of the semiconductor; extracts and analyzes the microstructure information of the semiconductor through the microstructure control optimization module, and provides detailed microscopic level data for fine-tuning control; generates a semiconductor microstructure image through graphic mapping technology, and intuitively displays the microscopic features of the semiconductor; the fine-tuning control scheme is combined with the electrical signal performance optimization scheme, and the generated semiconductor control optimization report provides comprehensive optimization guidance for the manufacturing process. Therefore, the present invention realizes the accurate prediction of the thermal stability of the semiconductor through the Internet of Things technology, data analysis technology, adaptive control technology and image mapping technology, so as to optimize and adjust the lattice structure of the semiconductor; thereby improving the electrical signal performance of the semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 A schematic flow chart of the steps of a semiconductor control method;

[0076] Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart;

[0077] Figure 3 for Figure 1 Detailed implementation steps of step S5 are shown in the flowchart.

[0078] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0079] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0080] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0081] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0082] To achieve this, please refer to Figures 1 to 3 , a semiconductor control method, the method comprising the following steps:

[0083] Step S1: Acquire semiconductor data; extract manufacturing parameter data of the semiconductor data to obtain semiconductor manufacturing parameter data; perform spatial modeling based on the semiconductor manufacturing parameter data to generate a three-dimensional thermal model for semiconductor manufacturing; monitor the thermal distribution of the semiconductor data during the manufacturing process through the three-dimensional thermal model for semiconductor manufacturing to generate thermal distribution data for the manufacturing process;

[0084] Step S2: Predicting the thermal stability of semiconductor manufacturing parameter data based on the thermal distribution data of the manufacturing process to generate thermal stability prediction data; extracting the design parameter information of the semiconductor data to obtain the semiconductor design parameters; simulating the semiconductor manufacturing parameter data according to the semiconductor design parameters to generate manufacturing process simulation data; evaluating the thermal management efficiency of the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient;

[0085] Step S3: Optimizing the thermal control strategy of the manufacturing process simulation data according to the thermal management efficiency evaluation coefficient to generate thermal control parameter optimization data; determining the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data to obtain manufacturing key time data; evaluating the electrical signal characteristics of the semiconductor data based on the manufacturing key time data to generate electrical signal characteristic evaluation data;

[0086] Step S4: performing carrier mobility analysis on the electrical signal characteristic evaluation data to obtain carrier mobility data; performing electrical signal performance optimization on the semiconductor data according to the carrier mobility data to generate an electrical signal performance optimization solution;

[0087] Step S5: extract the microstructure information of the semiconductor data to obtain the semiconductor microstructure information; perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; perform fine-tuning control on the semiconductor data according to the semiconductor microstructure image to obtain a semiconductor fine-tuning control plan; integrate the semiconductor fine-tuning control plan and the electrical signal performance optimization plan to generate a semiconductor control optimization report.

[0088] The present invention ensures a comprehensive understanding of semiconductor characteristics by acquiring semiconductor data and extracting manufacturing parameter data; constructs a three-dimensional thermal model of semiconductor manufacturing to achieve accurate simulation of heat distribution in the manufacturing process; monitors heat distribution through the three-dimensional thermal model of semiconductor manufacturing to clarify the heat distribution of semiconductor manufacturing; uses the thermal distribution data of the manufacturing process to predict thermal stability, thereby improving the accuracy of predicting semiconductor thermal stability; extracts design parameter information and performs simulations to enhance the effectiveness evaluation of semiconductor design; and evaluates thermal stability predictions through manufacturing process simulation data to provide quantitative indicators for subsequent optimization. According to the thermal management efficiency evaluation coefficient, the thermal control strategy is optimized to improve the thermal efficiency of the semiconductor manufacturing process; the manufacturing key time nodes are determined to ensure the precise control of the key steps in the manufacturing process; the electrical signal characteristics are evaluated based on the key time nodes, which is helpful to improve the electrical performance of the semiconductor; the carrier mobility analysis is performed on the electrical signal characteristic evaluation data, and the carrier mobility is accurately calculated; the electrical signal performance is optimized according to the carrier mobility data, and the electrical signal performance optimization scheme is generated, which can optimize the electrical performance of the semiconductor; the microstructure information of the semiconductor is extracted and analyzed, and detailed microscopic level data is provided for fine-tuning control; the semiconductor microstructure image is generated by the graphic mapping technology, and the microscopic characteristics of the semiconductor are intuitively displayed; the fine-tuning control scheme is combined with the electrical signal performance optimization scheme, and the generated semiconductor control optimization report provides comprehensive optimization guidance for the manufacturing process. Therefore, the present invention realizes the accurate prediction of the thermal stability of the semiconductor through the Internet of Things technology, data analysis technology, adaptive control technology and image mapping technology, so as to optimize and adjust the lattice structure of the semiconductor; thereby improving the electrical signal performance of the semiconductor.

[0089] In the embodiment of the present invention, reference Figure 1 The above is a schematic flow chart of the steps of a semiconductor control method of the present invention. In this example, the semiconductor control method includes the following steps:

[0090] Step S1: Acquire semiconductor data; extract manufacturing parameter data of the semiconductor data to obtain semiconductor manufacturing parameter data; construct spatial modeling based on the semiconductor manufacturing parameter data to generate a three-dimensional thermal model of semiconductor manufacturing; monitor the thermal distribution of the semiconductor data during the manufacturing process through the three-dimensional thermal model of semiconductor manufacturing to generate thermal distribution data of the manufacturing process;

[0091] In an embodiment of the present invention, semiconductor data is acquired in real time through a high-precision wafer temperature measurement system (such as an RTD wireless wafer temperature measurement system), wherein the semiconductor data includes the temperature of the wafer, the thermal conductivity of the material, the doping distribution, the device structure and the material properties, etc.; the manufacturing parameter data of the semiconductor data is extracted to obtain the semiconductor manufacturing parameter data; a three-dimensional thermal model is constructed according to the semiconductor manufacturing parameter data using finite element analysis software (such as COMSOL Multiphysics); specifically, in the process of model construction, parameters such as doping distribution, device structure and material properties are modeled; for example, the npn doping structure of the bipolar transistor, the geometry and structure of the device area and the electrical connection all need to be accurately modeled; in addition, in order to ensure the accuracy of the model, an effective grid is created, involving a structured swept grid, in which the resolution in the z direction is the largest near the pn junction and near the electrical contacts on the top and bottom surfaces; the semiconductor manufacturing process thermal distribution is monitored through the semiconductor manufacturing three-dimensional thermal model to obtain the thermal distribution data of the semiconductor device during the manufacturing process, specifically, such as etching time and temperature, thereby generating the manufacturing process thermal distribution data.

[0092] Step S2: Predicting the thermal stability of semiconductor manufacturing parameter data based on the thermal distribution data of the manufacturing process to generate thermal stability prediction data; extracting the design parameter information of the semiconductor data to obtain the semiconductor design parameters; simulating the semiconductor manufacturing parameter data according to the semiconductor design parameters to generate manufacturing process simulation data; evaluating the thermal management efficiency of the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient;

[0093] In the embodiment of the present invention, based on the thermal distribution data of the manufacturing process, the semiconductor manufacturing parameter data is subjected to finite element analysis (FEA) using thermal simulation software (such as ANSYS CFD) to predict the heat transfer processes such as conduction, convection and radiation, and obtain the thermal response of the semiconductor device under different working conditions, thereby generating thermal stability prediction data; using parasitic parameter extraction technology, such as StarRC technology, the design parameter information of the semiconductor data is analyzed, and key design parameters, such as device size, shape and material properties, are extracted to obtain semiconductor design parameters. Semiconductor manufacturing process simulation software, such as COMSOL Multiphysics, is used to simulate the semiconductor manufacturing parameter data; specifically, key manufacturing steps such as lithography, etching, and deposition are simulated; then, processes such as wafer preparation, etching, lithography, ion implantation, and thin film deposition are simulated, as well as the thermal behavior of vacuum systems, electrostatic chucks, and heat treatment equipment in the semiconductor manufacturing process, to obtain comprehensive manufacturing process simulation data; using a thermal efficiency calculator, the thermal stability prediction data is evaluated for thermal management efficiency according to the manufacturing process simulation data, specifically, by defining indicators of thermal management efficiency, such as thermal resistance, heat flux, etc., the evaluation coefficient is calculated to generate a thermal management efficiency evaluation coefficient.

[0094] Step S3: Optimizing the thermal control strategy of the manufacturing process simulation data according to the thermal management efficiency evaluation coefficient to generate thermal control parameter optimization data; determining the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data to obtain manufacturing key time data; evaluating the electrical signal characteristics of the semiconductor data based on the manufacturing key time data to generate electrical signal characteristic evaluation data;

[0095] In the embodiment of the present invention, semiconductor industry software (such as COMSOL Multiphysics) is used to analyze the manufacturing process simulation data through the thermal management efficiency evaluation coefficient; specifically, thermal response analysis under different working conditions including conduction, convection and radiation is performed to obtain thermal response analysis results; and process control technology APC (Advanced Process Control), optimize the thermal control parameters of the manufacturing process simulation data according to the analysis results, specifically, such as adjusting the coolant flow, changing the design of the heat exchanger and modifying the process parameters, and using the R2R control technology (Run-to-Run control technology) to adjust the process parameters to reduce the fluctuation between batches; use the semiconductor manufacturing process simulation software to determine the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data. The key time nodes include determining the time required in a specific process step, such as the time nodes of key process links such as thin film deposition, lithography and etching; based on the manufacturing key time data, the electrical signal characteristics of the semiconductor data are evaluated by the electrical signal characteristic analysis (ESA) technology; specifically, through high-speed acquisition and data analysis, non-invasive technology for fault diagnosis is applied to electric-driven rotating equipment; through electrical signal analysis, the degradation trend of semiconductor devices is judged, specifically, the electrical performance of semiconductor devices is tested, such as IV characteristic test, capacitance-voltage test, etc., to evaluate the electrical signal characteristics of the device.

[0096] Step S4: performing carrier mobility analysis on the electrical signal characteristic evaluation data to obtain carrier mobility data; optimizing the electrical signal performance of the semiconductor according to the carrier mobility data to generate an electrical signal performance optimization plan;

[0097] In the embodiment of the present invention, IV and CV parameter tests are performed using a semiconductor parameter analyzer to collect basic data of carrier mobility; the Hall effect method, the transit time method and other technologies are used to perform detailed measurements of carrier mobility; the semiconductor module of the COMSOL Multiphysics software is used to simulate the performance of the semiconductor device according to the carrier mobility data; the design of the semiconductor device is optimized in combination with the carrier mobility data, such as adjusting the doping concentration and changing the device structure; and the semiconductor device is tested again using a semiconductor parameter test instrument using the optimized electrical signal performance solution to verify the optimization effect.

[0098] Step S5: extract the microstructure information of the semiconductor data to obtain the semiconductor microstructure information; perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; perform fine-tuning control on the semiconductor data according to the semiconductor microstructure image to obtain a semiconductor fine-tuning control plan; integrate the semiconductor fine-tuning control plan and the electrical signal performance optimization plan to generate a semiconductor control optimization report.

[0099] In the embodiment of the present invention, scanning electron microscope (SEM) and atomic force microscope (AFM) and other material characterization technologies are used to obtain microstructure image data of semiconductor materials and obtain semiconductor microstructure information. Image processing technology, such as fuzzy logic and neural network methods, is used to automatically detect and classify microstructure images during sintering. Specifically, a deep convolutional neural network (DCNN) is used to classify different types of metal microstructure images obtained by optical microscopy technology to generate semiconductor microstructure images; based on the semiconductor microstructure images, machine learning technology, such as the machine learning toolbox in MATLAB, is used to automatically identify and fine-tune the material microstructure of semiconductor data to obtain a semiconductor fine-tuning control solution; the fine-tuning control solution is combined with the electrical signal performance optimization solution using an EDA platform to generate a semiconductor control optimization report.

[0100] Preferably, step S1 comprises the following steps:

[0101] Step S11: using a sensor to acquire semiconductor data; performing manufacturing process feature recognition on the semiconductor data to obtain manufacturing process feature data; determining parameter information on the manufacturing process feature data to generate semiconductor manufacturing parameter data;

[0102] Step S12: performing thermal characteristic analysis on the semiconductor manufacturing parameter data to obtain semiconductor thermal characteristic data; performing spatial distribution mapping on the semiconductor thermal characteristic data to obtain spatial distribution mapping data;

[0103] Step S13: performing heat conduction analysis processing on the spatial distribution mapping data to obtain heat conduction analysis results; performing three-dimensional morphology construction on the heat conduction analysis results to obtain a three-dimensional thermal model of semiconductor manufacturing;

[0104] Step S14: perform heat flow tracing processing on the semiconductor manufacturing three-dimensional thermal model to obtain semiconductor heat flow tracing data; perform temperature field analysis on the semiconductor heat flow tracing data to obtain semiconductor temperature field data; perform thermal gradient calculation on the semiconductor temperature field data to obtain semiconductor thermal gradient data; perform thermal distribution monitoring of the semiconductor data during the manufacturing process based on the semiconductor thermal gradient data to generate thermal distribution data during the manufacturing process.

[0105] In an embodiment of the present invention, sensors, such as temperature, pressure and light sensors, are used to monitor key parameters in a semiconductor production environment in real time. These sensors are managed through an AWorks system, and each sensor channel is assigned a unique ID. Data is acquired through a unified interface, and the characteristics of the manufacturing process are identified to obtain manufacturing process characteristic data; parameter information of the manufacturing process characteristic data is determined to determine key parameters in the semiconductor manufacturing process; specifically, statistical analysis of the data is performed to generate semiconductor manufacturing parameter data; thermal characteristic analysis of the semiconductor manufacturing parameter data is performed, specifically using thermal simulation software, such as COMSOL Multiphysics, which can simulate heat conduction and heat convection processes and analyze the thermal behavior of semiconductor materials; spatial distribution mapping is performed through the thermal simulation results; specifically, the simulated thermal characteristic data is compared with the actual semiconductor device structure to obtain spatial distribution mapping data. Utilize analytical methods, such as Fourier's law, to conduct detailed analysis on the heat conduction of semiconductor devices and obtain analytical results of heat conduction; construct a three-dimensional thermal model of semiconductor manufacturing based on the analytical results of heat conduction; specifically, use three-dimensional modeling software to create a geometric model of semiconductor devices and simulate their thermal behavior under actual working conditions; perform heat flow tracing on the three-dimensional thermal model of semiconductor manufacturing, which specifically involves simulating the heat flow path and calculating the heat flux density to obtain semiconductor heat flow tracing data; perform temperature field analysis based on the heat flow tracing data to obtain semiconductor temperature field data; use an infrared thermal imager to measure the temperature distribution on the device surface; calculate the semiconductor thermal gradient data based on the semiconductor temperature field data, which specifically involves mathematical processing of the temperature field data to obtain the temperature change rate; monitor the thermal distribution of the semiconductor data during the manufacturing process based on the semiconductor thermal gradient data to generate thermal distribution data during the manufacturing process, thereby ensuring the thermal stability and reliability of semiconductor devices during the production process.

[0106] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0107] Step S21: performing thermal behavior pattern recognition on the thermal distribution data of the manufacturing process to obtain thermal behavior pattern data; performing thermal stability trend analysis on the thermal behavior pattern data to obtain thermal stability trend data;

[0108] Step S22: performing thermal effect correlation analysis on the thermal stability trend data to obtain thermal effect correlation data; performing parameter sensitivity determination on the thermal effect correlation data to obtain parameter sensitivity data;

[0109] Step S23: constructing a thermal stability prediction model for the parameter sensitivity data to obtain a thermal stability prediction model; performing thermal stability prediction on the semiconductor manufacturing parameter data based on the thermal stability prediction model to obtain thermal stability prediction data;

[0110] Step S24: performing design parameter semantic analysis on the semiconductor data to obtain semiconductor design parameters; performing manufacturing process mapping on the semiconductor design parameters to obtain manufacturing process mapping data;

[0111] Step S25: simulating the semiconductor manufacturing parameter data according to the manufacturing process mapping data to generate manufacturing process simulation data;

[0112] Step S26: performing thermal management efficiency evaluation on the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient.

[0113] In an embodiment of the present invention, thermal imaging technology is used to collect data on thermal distribution in a semiconductor manufacturing process; then, thermal behavior pattern recognition is performed on the collected thermal distribution data through a pattern recognition algorithm, such as a support vector machine (SVM) or an artificial neural network (ANN), to form thermal behavior pattern data; then, thermal stability trend analysis is performed on the thermal behavior pattern data using time series analysis or statistical process control (SPC) technology, thereby obtaining thermal stability trend data; thermal effect association analysis is performed on the thermal stability trend data using multiple regression analysis or correlation analysis to determine the mutual influence between different thermal parameters; then, parameter sensitivity is determined on the thermal effect association data using a sensitivity analysis method, such as Monte Carlo simulation or variance analysis, to obtain parameter sensitivity data. A thermal stability prediction model is constructed for the parameter sensitivity data; specifically, the model adopts a multilayer perceptron (MLP) structure; input layer: contains the number of neurons corresponding to the input parameters, for example, if there are 10 parameter sensitivity data, the input layer has 10 neurons. Hidden layer: at least one hidden layer, each hidden layer consists of a certain number of neurons, for example, two hidden layers are set, the first hidden layer has 20 neurons, the second hidden layer has 15 neurons, and these neurons are connected to the input layer through a nonlinear activation function (such as ReLU). Output layer: a single neuron, outputting the predicted value of thermal stability. During the training process, set a suitable learning rate and optimizer, such as Adam, to update the weight of the model; through multiple iterations of training, the thermal stability prediction data is obtained. Using EDA tools, the design parameter semantic analysis is performed on the semiconductor design parameters to obtain the semiconductor design parameters; then, the design parameters are mapped to the manufacturing process through the manufacturing execution system (MES) to obtain the manufacturing process mapping data; using simulation software such as ANSYS or COMSOL Multiphysics, the semiconductor manufacturing parameter data is simulated according to the manufacturing process mapping data to generate the manufacturing process simulation data; the thermal management efficiency of the thermal stability prediction data is evaluated through the manufacturing process simulation data, specifically, the thermal management efficiency evaluation coefficient, such as thermal impedance or thermal efficiency, is calculated to quantify the performance of the thermal management system.

[0114] Preferably, step S25 comprises the following steps:

[0115] Step S251: performing process digitization processing on the manufacturing process mapping data to obtain digital process flow data; constructing a virtual manufacturing model for the semiconductor manufacturing parameter data according to the digital process flow data to obtain a semiconductor virtual manufacturing model;

[0116] Step S252: performing physical field coupling analysis on the semiconductor virtual manufacturing model to obtain physical field coupling data; performing thermodynamic response simulation on the semiconductor virtual manufacturing model according to the physical field coupling data to obtain thermodynamic response simulation data;

[0117] Step S253: performing material stress evolution simulation on the semiconductor virtual manufacturing model through the thermodynamic response simulation data to obtain material stress evolution data; performing process condition simulation on the semiconductor virtual manufacturing model according to the material stress evolution data to obtain process condition simulation data;

[0118] Step S254: performing equipment performance boundary simulation on the semiconductor virtual manufacturing model to obtain equipment performance boundary simulation data; performing quality parameter simulation on the semiconductor virtual manufacturing model according to the equipment performance boundary simulation data and the process condition simulation data to obtain quality parameter simulation data;

[0119] Step S255: Integrate process condition simulation data, equipment performance boundary simulation data and quality parameter simulation data to generate manufacturing process simulation data.

[0120] In an embodiment of the present invention, the manufacturing process mapping data is digitally processed to obtain digital process flow data; computer-aided design (CAD) software is used to construct a virtual manufacturing model of semiconductor manufacturing parameter data according to the digital process flow data, including all key components of the equipment and the relationships between them; a physical field coupling analysis is performed on the virtual manufacturing model, including the interaction of multiple physical fields such as thermodynamics, fluid dynamics and structural mechanics; specifically, the multi-physical field coupling function in COMSOL Multiphysics software is used to simulate how they influence each other in the semiconductor manufacturing process; then, based on the physical field coupling data, the behavior of semiconductor materials under different temperature and pressure conditions is simulated to obtain thermodynamic response simulation data; finite element analysis (FEA) software is used to simulate the material stress evolution according to the thermodynamic response simulation number, specifically simulating the stress and strain conditions of the material during the manufacturing process; in addition, the process conditions are simulated according to the material stress evolution data, including simulating different temperature curves, pressure conditions and material processing steps to obtain process condition simulation data. Simulate the equipment performance boundary and evaluate the performance of the equipment under extreme conditions to obtain equipment performance boundary simulation data. Then, combine the equipment performance boundary simulation data and process condition simulation data to simulate the quality parameters, including simulating the quality changes of the product under different manufacturing conditions to obtain quality parameter simulation data. Use data integration and analysis tools to integrate the process condition simulation data, equipment performance boundary simulation data and quality parameter simulation data to generate manufacturing process simulation data.

[0121] Preferably, step S26 includes the following steps:

[0122] Step S261: performing heat energy distribution feature recognition on the process condition simulation data to obtain heat energy distribution data; performing heat load definition processing on the equipment performance boundary simulation data to obtain heat load definition data; performing heat quality influence analysis on the quality parameter simulation data to obtain heat quality influence data;

[0123] Step S262: performing thermal management collaborative analysis on the thermal energy distribution data, the thermal load definition data and the thermal quality impact data to obtain thermal management collaborative data;

[0124] Step S263: performing thermal energy utilization efficiency measurement on the thermal stability prediction data according to the thermal management collaborative data to obtain thermal energy utilization efficiency measurement data; performing thermal efficiency trend identification on the thermal energy utilization efficiency measurement data to obtain thermal efficiency trend data;

[0125] Step S264: perform heat flow balance verification on the thermal efficiency trend data to obtain heat flow balance verification data; perform thermal management efficiency evaluation on the heat flow balance verification data to obtain thermal management efficiency evaluation data; perform efficiency evaluation coefficient measurement calculation on the thermal management efficiency evaluation data to obtain a thermal management efficiency evaluation coefficient.

[0126] In an embodiment of the present invention, a temperature distribution map in a manufacturing process is obtained by using thermal imaging technology, and high temperature areas and low temperature areas of heat energy distribution are identified through image processing technology, such as edge detection and threshold segmentation, to obtain heat energy distribution data; then, a heat load definition process is performed on the equipment performance boundary simulation data, and a finite element analysis (FEA) software is used to simulate the thermal response of the equipment under different working conditions, and the maximum heat load and stable working temperature range of the equipment are determined to obtain heat load definition data; a thermal quality influence analysis is performed on the quality parameter simulation data, and the influence of different manufacturing parameters on the thermal quality of semiconductor materials is evaluated through thermal analysis technologies such as thermogravimetric analysis (TGA) and differential scanning calorimeter (DSC), to obtain thermal quality influence data, including thermal physical parameters such as thermal stability, thermal conductivity and specific heat capacity of the material; the heat energy distribution data, heat load definition data and thermal quality influence data are combined, and multi-physics simulation software such as COMSOL Multiphysics is used for simulation analysis; the transfer path and distribution characteristics of heat energy in the semiconductor manufacturing process are specifically analyzed, the key links of thermal management are identified, and thermal management collaborative data are obtained. According to the thermal management collaborative data, the thermal energy utilization efficiency of the thermal stability prediction data is measured, and the heat pump-phase change heat storage coupling technology is used to optimize the thermal energy utilization efficiency to obtain the thermal energy utilization efficiency measurement data; the thermal efficiency trend is identified for the thermal energy utilization efficiency measurement data, and statistical analysis methods, such as regression analysis, are used to determine the changing trend of thermal efficiency to obtain thermal efficiency trend data; the thermal flow balance is verified for the thermal efficiency trend data, and the balance of heat flow in the semiconductor manufacturing process is verified through simulation and experiment to obtain the thermal flow balance verification data; the thermal management efficiency is evaluated for the thermal flow balance verification data, and the second law of thermodynamics analysis method is used to evaluate the efficiency of the thermal management process to obtain the thermal management efficiency evaluation data; finally, the efficiency evaluation coefficient is measured and calculated for the thermal management efficiency evaluation data, and the thermal management efficiency evaluation coefficient is calculated by using the principles of conservation of energy and mass conservation in combination with the thermodynamic efficiency evaluation data.

[0127] Preferably, step S3 comprises the following steps:

[0128] Step S31: optimizing the process parameters of the process condition simulation data according to the thermal management efficiency evaluation coefficient to obtain process parameter optimization data; adjusting the equipment operation mode of the equipment performance boundary simulation data according to the thermal management efficiency evaluation coefficient to obtain equipment operation mode adjustment data; performing quality intelligent control on the quality parameter simulation data according to the thermal management efficiency evaluation coefficient to obtain quality intelligent control data;

[0129] Step S32: Integrate process parameter optimization data, equipment operation mode adjustment data and quality intelligent control data to obtain thermal control parameter optimization data;

[0130] Step S33: performing key operation identification on the manufacturing process simulation data according to the thermal control parameter optimization data to obtain key operation identification data; performing time series analysis on the manufacturing process simulation data according to the key operation identification data to obtain manufacturing process time series data; performing time node synchronization processing on the manufacturing process time series data to obtain time node synchronization data;

[0131] Step S34: determining the key time nodes of the semiconductor manufacturing parameter data according to the time node synchronization data to obtain manufacturing key time data;

[0132] Step S35: Evaluate the electrical signal characteristics of the semiconductor data based on the manufacturing critical time data to generate electrical signal characteristic evaluation data.

[0133] In an embodiment of the present invention, the thermal management efficiency evaluation coefficient is used to analyze the process condition simulation data to determine the optimal setting values ​​of key process parameters such as temperature, pressure and time; specifically, the process parameter optimization technology is used, such as the response surface method (RSM) or genetic algorithm (GA) to identify the optimal parameter combination; then, the equipment performance boundary simulation data is adjusted to adjust the equipment operation mode, including the application of variable frequency drive (VFD) to adjust the equipment operation speed, and the use of intelligent sensors and control systems to achieve adaptive adjustment of the equipment; finally, the quality parameter simulation data is intelligently controlled, and machine learning algorithms such as support vector machines (SVM) or neural networks are used to control product quality parameters to ensure that the product meets quality standards. Using data fusion technology, specifically using OPC Unified Architecture (OPC The invention adopts the process parameter optimization data, the equipment operation mode adjustment data and the quality intelligent control data as the standard for data exchange; integrates the process parameter optimization data, the equipment operation mode adjustment data and the quality intelligent control data to form the thermal control parameter optimization data; identifies the key operations of the manufacturing process simulation data according to the thermal control parameter optimization data, specifically, uses the process analysis technology (PAT) to monitor and analyze the key steps in the manufacturing process to obtain the key operation identification data; performs time series analysis on the manufacturing process simulation data, and uses the time series analysis technology, such as the autoregressive moving average model (ARMA) or the autoregressive integrated moving average model (ARIMA), to identify the trends and patterns in the manufacturing process; finally, uses the timestamp technology and the data alignment algorithm to synchronize the time nodes of the manufacturing process time series data; uses the real-time data monitoring system to track the key events in the manufacturing process and ensures that the specific operations are performed at the predetermined time points to obtain the manufacturing key time data; evaluates the electrical signal characteristics of the semiconductor data based on the manufacturing key time data, specifically including using the high-speed oscilloscope and the spectrum analyzer to measure and analyze the characteristics of the electrical signal, such as the frequency, amplitude and phase, and evaluates the characteristics of the electrical signal to generate the electrical signal characteristic evaluation data.

[0134] Preferably, step S35 includes the following steps:

[0135] Step S351: performing electrical signal characteristic recognition on semiconductor data to obtain semiconductor electrical signal characteristic data;

[0136] Step S352: performing electrical signal characteristic test planning on the semiconductor electrical signal characteristic data based on the manufacturing key time data to obtain electrical signal characteristic test planning data;

[0137] Step S353: performing electrical signal simulation on the electrical signal characteristic test planning data to generate electrical signal simulation data; performing semiconductor signal response acquisition on the electrical signal simulation data to obtain signal response acquisition data; performing high-frequency signal demodulation processing on the signal response acquisition data to obtain high-frequency signal demodulation data;

[0138] Step S354: performing harmonic analysis on the high-frequency signal demodulation data to obtain high-frequency harmonic analysis data; performing phase noise measurement on the high-frequency harmonic analysis data to obtain phase noise measurement data; performing frequency stability test on the phase noise measurement data to obtain frequency stability test data; performing parasitic parameter identification on the semiconductor data according to the frequency stability test data to obtain semiconductor parasitic parameter data;

[0139] Step S355: perform microscale effect verification on semiconductor parasitic parameter data to obtain microscale effect verification data; perform material defect signal characterization recording on the microscale effect verification data to obtain material defect signal characterization data; perform electrical signal characteristic evaluation on semiconductor data based on the material defect signal characterization data to obtain electrical signal characteristic evaluation data.

[0140] In an embodiment of the present invention, a high-speed oscilloscope and a spectrum analyzer are used to identify the electrical signal characteristics of a semiconductor device to obtain semiconductor electrical signal characteristic data, including parameters such as signal amplitude, frequency, phase and noise level; an electrical signal characteristic test plan is performed on the semiconductor electrical signal characteristic data based on manufacturing key time data, specifically using an automated test equipment (ATE) test sequence and parameters, wherein the test plan data includes test conditions, test frequency range and test signal type, etc.; electrical signal simulation is performed on the electrical signal characteristic test plan data, and analog data is generated using a signal generator; then, the analog signals are responded to and collected through the semiconductor device to obtain signal response collection data; then, the signal response collection data is subjected to high-frequency signal demodulation processing, usually using digital demodulation technology such as Hilbert transform or phase-locked loop (PLL) demodulation to obtain high-frequency signal demodulation data; harmonic analysis is performed on the high-frequency signal demodulation data, specifically using Fourier transform (FFT) technology to obtain high-frequency harmonic analysis data; then, a phase noise analyzer is used to analyze the high-frequency signal. Phase noise is measured on harmonic analysis data to obtain phase noise measurement data; in addition, frequency stability analysis technology is used to perform frequency stability test on phase noise measurement data, and specific analysis technologies include Allan variance (ADEV), time variance (TDEV) and Hadamard variance (HDEV) to obtain frequency stability test data; finally, parasitic parameters of semiconductor data are identified based on frequency stability test data, and parameter extraction technology, such as S-parameter-based extraction method, is used to obtain semiconductor parasitic parameter data; microscale effect verification is performed on semiconductor parasitic parameter data using microscale tunneling effect or microscale capacitance effect test technology to obtain microscale effect verification data; then, electron paramagnetic resonance (EPR) spectroscopy or positron annihilation lifetime spectroscopy (PALS) and other technologies are used to record material defect signal characterization of microscale effect verification data to obtain material defect signal characterization data; data analysis and signal processing technology are used to evaluate the electrical signal characteristics of semiconductor data based on the material defect signal characterization data to obtain electrical signal characteristic evaluation data.

[0141] Preferably, step S4 comprises the following steps:

[0142] Step S41: performing carrier power analysis on the electrical signal characteristic evaluation data to obtain carrier power data; performing mobility distribution pattern recognition on the carrier power data to obtain mobility distribution pattern data;

[0143] Step S42: performing carrier mobility calculation on the mobility distribution pattern data to obtain carrier mobility data; performing electrical signal performance correlation on the carrier mobility data to obtain electrical signal performance correlation data;

[0144] Step S43: performing process doping configuration analysis on the process condition simulation data to obtain process doping configuration data; performing mobility measurement on the process doping configuration data according to the electrical signal performance correlation data to obtain doping configuration mobility data; performing process ratio adjustment on the process condition simulation data according to the doping configuration mobility data to obtain process electrical signal optimization data;

[0145] Step S44: performing interface charge anomaly detection on the device performance boundary simulation data according to the electrical signal performance correlation data to obtain device interface charge anomaly data; performing interface charge passivation layer adjustment on the device performance boundary simulation data according to the device interface charge anomaly data to obtain device electrical signal optimization data;

[0146] Step S45: Integrate the process electrical signal optimization data and the equipment electrical signal optimization data to obtain an electrical signal performance optimization solution.

[0147] In the embodiment of the present invention, a semiconductor parameter analyzer is used to identify the characteristics of semiconductor electrical signals to obtain electrical signal characteristic data, wherein the electrical signal characteristic data includes parameters such as carrier concentration, mobility and lifetime; then, carrier dynamics simulation software such as COMSOL The semiconductor module in Multiphysics analyzes the carrier dynamics to obtain carrier dynamics data; then, the mobility distribution pattern recognition technology is used to analyze the migration behavior of carriers under the action of the electric field to obtain the mobility distribution pattern data; the Hall effect method or time-of-flight (TOF) technology is used to calculate the carrier mobility of the mobility distribution pattern data to obtain the carrier mobility data; the electrical signal simulation software is used to correlate the carrier mobility data with the electrical signal performance to obtain the electrical signal performance correlation data; the semiconductor process simulation software (such as TCAD tool) is used to simulate the doping process, and the process doping configuration analysis is performed on the process condition simulation data to obtain the process doping configuration data; then, the mobility of the process doping configuration data is measured according to the electrical signal performance correlation data to obtain the doping configuration mobility data; finally, the process ratio of the process condition simulation data is adjusted according to the doping configuration mobility data to obtain the process electrical signal optimization data. According to the electrical signal performance correlation data, the interface charge anomaly detection is performed on the device performance boundary simulation data. Specifically, a high-resolution electron microscope (such as a transmission electron microscope TEM) or a scanning capacitance microscope (SCM) is used to observe the distribution of interface charge to obtain the device interface charge anomaly data; then, the interface charge passivation layer is adjusted for the device interface charge anomaly data, and the interface characteristics are optimized by changing the material or thickness of the passivation layer to obtain the device electrical signal optimization data; using data fusion technology, the process electrical signal optimization data and the device electrical signal optimization data are integrated to obtain the electrical signal performance optimization plan.

[0148] As an example of the present invention, refer to Figure 3 As shown, in this example, step S5 includes:

[0149] Step S51: recognizing crystal features of semiconductor data to obtain semiconductor crystal feature data; performing crystal layout detection on the semiconductor crystal feature data to obtain semiconductor crystal layout data;

[0150] Step S52: determining the lattice constant of the semiconductor crystal layout data to obtain lattice constant information; calculating the crystal bit density of the lattice constant information to obtain crystal bit density data;

[0151] Step S53: determining the electron energy level distribution of the crystal bit density data to obtain the electron energy level distribution data; performing band structure identification on the semiconductor crystal layout data according to the electron energy level distribution data to obtain semiconductor band structure information;

[0152] Step S54: integrating semiconductor crystal layout data, crystal bit density data and semiconductor energy band structure information to obtain semiconductor microstructure information; using graphic mapping technology to perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image;

[0153] Step S55: fine-tuning the layout mode of the semiconductor crystal layout data according to the semiconductor microstructure image to generate crystal layout fine-tuning control data; fine-tuning the lattice parameter of the crystal bit density data according to the semiconductor microstructure image to generate lattice parameter fine-tuning control data; integrating the crystal layout fine-tuning control data and the lattice parameter fine-tuning control data to generate a semiconductor fine-tuning control scheme;

[0154] Step S56: Integrate the semiconductor fine-tuning control solution and the electrical signal performance optimization solution to generate a semiconductor control optimization report.

[0155] In an embodiment of the present invention, X-ray diffraction (XRD) technology is used to identify the crystal characteristics of the semiconductor material to obtain semiconductor crystal characteristic data; then, an atomic force microscope (AFM) or a scanning electron microscope (SEM) is used to detect the crystal layout to obtain semiconductor crystal layout data, specifically, the crystal surface morphology and size distribution are detected; the lattice constant of the semiconductor crystal layout data is determined, specifically by XRD data analysis software, such as using JADE software for data processing; then, the crystal bit density is calculated by calculating the lattice constant and the crystal volume to obtain crystal bit density data; the electron energy level distribution of the crystal bit density data is determined, specifically using electron spectroscopy technology, such as ultraviolet photoelectron spectroscopy (UPS) or X-ray photoelectron spectroscopy (XPS), to analyze the electron energy level and state density; then, based on the electron energy level distribution data, density functional theory (DFT) calculation and simulation software is used to identify the band structure of the semiconductor crystal layout data to obtain semiconductor band structure information. Integrate semiconductor crystal layout data, crystal bit density data and semiconductor band structure information to obtain semiconductor microstructure information; then, use graphic mapping technology, such as three-dimensional visualization software, to perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; based on the semiconductor microstructure image, use image processing and analysis software to fine-tune the layout mode of the semiconductor crystal layout data to generate crystal layout fine-tuning control data; at the same time, perform lattice parameter fine-tuning control on the crystal bit density data based on the image to generate lattice parameter fine-tuning control data; finally, integrate the crystal layout fine-tuning control data and the lattice parameter fine-tuning control data to generate a semiconductor fine-tuning control plan; use process control technology (APC) software, such as Profimatics or Aspen Tech, to integrate the semiconductor fine-tuning control plan with the electrical signal performance optimization plan to generate a semiconductor control optimization report; this report will perform control optimization on the semiconductor to improve the overall performance of the semiconductor device.

[0156] In this specification, a semiconductor device is provided for executing the above-mentioned semiconductor control method, and the semiconductor device includes:

[0157] A data acquisition module is used to acquire semiconductor data; extract manufacturing parameter data of semiconductor data to obtain semiconductor manufacturing parameter data; perform spatial modeling based on semiconductor manufacturing parameter data to generate a three-dimensional thermal model of semiconductor manufacturing; monitor the thermal distribution of semiconductor data during the manufacturing process through the three-dimensional thermal model of semiconductor manufacturing to generate thermal distribution data of the manufacturing process;

[0158] The semiconductor manufacturing process simulation module is used to predict the thermal stability of semiconductor manufacturing parameter data based on the thermal distribution data of the manufacturing process and generate thermal stability prediction data; extract the design parameter information of the semiconductor data to obtain the semiconductor design parameters; simulate the semiconductor manufacturing parameter data according to the semiconductor design parameters to generate manufacturing process simulation data; evaluate the thermal management efficiency of the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient;

[0159] The electrical signal characteristic evaluation module is used to optimize the thermal control strategy of the manufacturing process simulation data according to the thermal management efficiency evaluation coefficient and generate thermal control parameter optimization data; determine the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data to obtain the manufacturing key time data; evaluate the electrical signal characteristics of the semiconductor data based on the manufacturing key time data to generate the electrical signal characteristic evaluation data;

[0160] The electrical signal performance optimization module is used to perform carrier mobility analysis on the electrical signal characteristic evaluation data to obtain carrier mobility data; perform electrical signal performance optimization on the semiconductor data according to the carrier mobility data to generate an electrical signal performance optimization plan;

[0161] The microstructure control optimization module is used to extract the microstructure information of semiconductor data to obtain semiconductor microstructure information; perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; perform fine-tuning control on the semiconductor data according to the semiconductor microstructure image to obtain a semiconductor fine-tuning control plan; integrate the semiconductor fine-tuning control plan and the electrical signal performance optimization plan to generate a semiconductor control optimization report.

[0162] The present invention acquires semiconductor data and extracts manufacturing parameter data through a data acquisition module, thereby ensuring a comprehensive understanding of semiconductor characteristics; constructs a three-dimensional thermal model of semiconductor manufacturing, thereby realizing an accurate simulation of heat distribution in the manufacturing process; monitors heat distribution through the three-dimensional thermal model of semiconductor manufacturing, thereby clarifying the heat distribution of semiconductor manufacturing; predicts thermal stability using the thermal distribution data of the manufacturing process through a semiconductor manufacturing process simulation module, thereby improving the accuracy of predicting semiconductor thermal stability; extracts design parameter information and performs simulation, thereby enhancing the effectiveness evaluation of semiconductor design; and evaluates thermal stability prediction through manufacturing process simulation data, thereby providing quantitative indicators for subsequent optimization. The thermal control strategy is optimized according to the thermal management efficiency evaluation coefficient through the electrical signal characteristic evaluation module, thereby improving the thermal efficiency of the semiconductor manufacturing process; determining the key manufacturing time nodes ensures the precise control of the key steps in the manufacturing process; evaluating the electrical signal characteristics based on the key time nodes helps to improve the electrical performance of the semiconductor; the electrical signal performance optimization module performs carrier mobility analysis on the electrical signal characteristic evaluation data, and accurately calculates the carrier mobility; optimizes the electrical signal performance according to the carrier mobility data, generates an electrical signal performance optimization scheme, and can optimize the electrical performance of the semiconductor; extracts and analyzes the microstructure information of the semiconductor through the microstructure control optimization module, and provides detailed microscopic level data for fine-tuning control; generates a semiconductor microstructure image through graphic mapping technology, and intuitively displays the microscopic features of the semiconductor; the fine-tuning control scheme is combined with the electrical signal performance optimization scheme, and the generated semiconductor control optimization report provides comprehensive optimization guidance for the manufacturing process. Therefore, the present invention realizes the accurate prediction of the thermal stability of the semiconductor through the Internet of Things technology, data analysis technology, adaptive control technology and image mapping technology, so as to optimize and adjust the lattice structure of the semiconductor; thereby improving the electrical signal performance of the semiconductor.

[0163] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0164] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A semiconductor control method, It is characterized in that The following steps are involved: Step S1: Acquire semiconductor data; extract manufacturing parameter data of the semiconductor data to obtain semiconductor manufacturing parameter data; Perform spatial modeling based on semiconductor manufacturing parameter data to generate a three-dimensional thermal model of semiconductor manufacturing; Monitor the thermal distribution of semiconductor data during the manufacturing process through a three-dimensional thermal model of semiconductor manufacturing, and generate thermal distribution data of the manufacturing process; Step S2: Predicting the thermal stability of semiconductor manufacturing parameter data based on the thermal distribution data of the manufacturing process to generate thermal stability prediction data; extracting the design parameter information of the semiconductor data to obtain semiconductor design parameters; simulating the semiconductor manufacturing parameter data according to the semiconductor design parameters to generate manufacturing process simulation data; The thermal management efficiency is evaluated on the thermal stability prediction data through the manufacturing process simulation data to generate the thermal management efficiency evaluation coefficient; Step S3: Optimizing the thermal control strategy of the manufacturing process simulation data according to the thermal management efficiency evaluation coefficient to generate thermal control parameter optimization data; determining the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data to obtain manufacturing key time data; Performing electrical signal characteristic evaluation on semiconductor data based on manufacturing key time data to generate electrical signal characteristic evaluation data; Step S4: performing carrier mobility analysis on the electrical signal characteristic evaluation data to obtain carrier mobility data; performing electrical signal performance optimization on the semiconductor data according to the carrier mobility data to generate an electrical signal performance optimization solution; Step S5: extracting microstructure information of semiconductor data to obtain semiconductor microstructure information; Graphically map semiconductor microstructure information to generate semiconductor microstructure images; Fine-tune and control semiconductor data according to the semiconductor microstructure image to obtain a semiconductor fine-tune control solution; Integrate semiconductor fine-tuning control solutions and electrical signal performance optimization solutions to generate semiconductor control optimization reports.

2. The semiconductor control method according to claim 1, It is characterized in that Step S1 includes the following steps: Step S11: using a sensor to acquire semiconductor data; performing manufacturing process feature recognition on the semiconductor data to obtain manufacturing process feature data; determining parameter information on the manufacturing process feature data to generate semiconductor manufacturing parameter data; Step S12: performing thermal characteristic analysis on the semiconductor manufacturing parameter data to obtain semiconductor thermal characteristic data; performing spatial distribution mapping on the semiconductor thermal characteristic data to obtain spatial distribution mapping data; Step S13: performing heat conduction analysis processing on the spatial distribution mapping data to obtain heat conduction analysis results; performing three-dimensional morphology construction on the heat conduction analysis results to obtain a three-dimensional thermal model of semiconductor manufacturing; Step S14: perform heat flow tracing processing on the semiconductor manufacturing three-dimensional thermal model to obtain semiconductor heat flow tracing data; perform temperature field analysis on the semiconductor heat flow tracing data to obtain semiconductor temperature field data; perform thermal gradient calculation on the semiconductor temperature field data to obtain semiconductor thermal gradient data; perform thermal distribution monitoring of the semiconductor data during the manufacturing process based on the semiconductor thermal gradient data to generate thermal distribution data during the manufacturing process.

3. The semiconductor control method according to claim 1, It is characterized in that Step S2 includes the following steps: Step S21: performing thermal behavior pattern recognition on the thermal distribution data of the manufacturing process to obtain thermal behavior pattern data; performing thermal stability trend analysis on the thermal behavior pattern data to obtain thermal stability trend data; Step S22: performing thermal effect correlation analysis on the thermal stability trend data to obtain thermal effect correlation data; performing parameter sensitivity determination on the thermal effect correlation data to obtain parameter sensitivity data; Step S23: constructing a thermal stability prediction model for the parameter sensitivity data to obtain a thermal stability prediction model; performing thermal stability prediction on the semiconductor manufacturing parameter data based on the thermal stability prediction model to obtain thermal stability prediction data; Step S24: performing design parameter semantic analysis on the semiconductor data to obtain semiconductor design parameters; performing manufacturing process mapping on the semiconductor design parameters to obtain manufacturing process mapping data; Step S25: simulating the semiconductor manufacturing parameter data according to the manufacturing process mapping data to generate manufacturing process simulation data; Step S26: performing thermal management efficiency evaluation on the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient.

4. The semiconductor control method according to claim 3, It is characterized in that Step S25 includes the following steps: Step S251: performing process digitization processing on the manufacturing process mapping data to obtain digital process flow data; constructing a virtual manufacturing model for the semiconductor manufacturing parameter data according to the digital process flow data to obtain a semiconductor virtual manufacturing model; Step S252: performing physical field coupling analysis on the semiconductor virtual manufacturing model to obtain physical field coupling data; performing thermodynamic response simulation on the semiconductor virtual manufacturing model according to the physical field coupling data to obtain thermodynamic response simulation data; Step S253: performing material stress evolution simulation on the semiconductor virtual manufacturing model through the thermodynamic response simulation data to obtain material stress evolution data; performing process condition simulation on the semiconductor virtual manufacturing model according to the material stress evolution data to obtain process condition simulation data; Step S254: performing equipment performance boundary simulation on the semiconductor virtual manufacturing model to obtain equipment performance boundary simulation data; performing quality parameter simulation on the semiconductor virtual manufacturing model according to the equipment performance boundary simulation data and the process condition simulation data to obtain quality parameter simulation data; Step S255: Integrate process condition simulation data, equipment performance boundary simulation data and quality parameter simulation data to generate manufacturing process simulation data.

5. The semiconductor control method according to claim 3, It is characterized in that Step S26 includes the following steps: Step S261: performing heat energy distribution feature recognition on the process condition simulation data to obtain heat energy distribution data; performing heat load definition processing on the equipment performance boundary simulation data to obtain heat load definition data; performing heat quality influence analysis on the quality parameter simulation data to obtain heat quality influence data; Step S262: performing thermal management collaborative analysis on the thermal energy distribution data, the thermal load definition data and the thermal quality impact data to obtain thermal management collaborative data; Step S263: performing thermal energy utilization efficiency measurement on the thermal stability prediction data according to the thermal management collaborative data to obtain thermal energy utilization efficiency measurement data; performing thermal efficiency trend identification on the thermal energy utilization efficiency measurement data to obtain thermal efficiency trend data; Step S264: perform heat flow balance verification on the thermal efficiency trend data to obtain heat flow balance verification data; perform thermal management efficiency evaluation on the heat flow balance verification data to obtain thermal management efficiency evaluation data; perform efficiency evaluation coefficient measurement calculation on the thermal management efficiency evaluation data to obtain a thermal management efficiency evaluation coefficient.

6. The semiconductor control method according to claim 1, It is characterized in that Step S3 includes the following steps: Step S31: optimizing the process parameters of the process condition simulation data according to the thermal management efficiency evaluation coefficient to obtain process parameter optimization data; adjusting the equipment operation mode of the equipment performance boundary simulation data according to the thermal management efficiency evaluation coefficient to obtain equipment operation mode adjustment data; performing quality intelligent control on the quality parameter simulation data according to the thermal management efficiency evaluation coefficient to obtain quality intelligent control data; Step S32: Integrate process parameter optimization data, equipment operation mode adjustment data and quality intelligent control data to obtain thermal control parameter optimization data; Step S33: performing key operation identification on the manufacturing process simulation data according to the thermal control parameter optimization data to obtain key operation identification data; performing time series analysis on the manufacturing process simulation data according to the key operation identification data to obtain manufacturing process time series data; performing time node synchronization processing on the manufacturing process time series data to obtain time node synchronization data; Step S34: determining the key time nodes of the semiconductor manufacturing parameter data according to the time node synchronization data to obtain manufacturing key time data; Step S35: Evaluate the electrical signal characteristics of the semiconductor data based on the manufacturing critical time data to generate electrical signal characteristic evaluation data.

7. The semiconductor control method according to claim 6, It is characterized in that Step S35 includes the following steps: Step S351: performing electrical signal characteristic recognition on semiconductor data to obtain semiconductor electrical signal characteristic data; Step S352: performing electrical signal characteristic test planning on the semiconductor electrical signal characteristic data based on the manufacturing key time data to obtain electrical signal characteristic test planning data; Step S353: performing electrical signal simulation on the electrical signal characteristic test planning data to generate electrical signal simulation data; performing semiconductor signal response acquisition on the electrical signal simulation data to obtain signal response acquisition data; performing high-frequency signal demodulation processing on the signal response acquisition data to obtain high-frequency signal demodulation data; Step S354: performing harmonic analysis on the high-frequency signal demodulation data to obtain high-frequency harmonic analysis data; performing phase noise measurement on the high-frequency harmonic analysis data to obtain phase noise measurement data; performing frequency stability test on the phase noise measurement data to obtain frequency stability test data; performing parasitic parameter identification on the semiconductor data according to the frequency stability test data to obtain semiconductor parasitic parameter data; Step S355: perform microscale effect verification on semiconductor parasitic parameter data to obtain microscale effect verification data; perform material defect signal characterization recording on the microscale effect verification data to obtain material defect signal characterization data; perform electrical signal characteristic evaluation on semiconductor data based on the material defect signal characterization data to obtain electrical signal characteristic evaluation data.

8. The semiconductor control method according to claim 1, It is characterized in that Step S4 includes the following steps: Step S41: performing carrier power analysis on the electrical signal characteristic evaluation data to obtain carrier power data; performing mobility distribution pattern recognition on the carrier power data to obtain mobility distribution pattern data; Step S42: performing carrier mobility calculation on the mobility distribution pattern data to obtain carrier mobility data; performing electrical signal performance correlation on the carrier mobility data to obtain electrical signal performance correlation data; Step S43: performing process doping configuration analysis on the process condition simulation data to obtain process doping configuration data; performing mobility measurement on the process doping configuration data according to the electrical signal performance correlation data to obtain doping configuration mobility data; performing process ratio adjustment on the process condition simulation data according to the doping configuration mobility data to obtain process electrical signal optimization data; Step S44: performing interface charge anomaly detection on the device performance boundary simulation data according to the electrical signal performance correlation data to obtain device interface charge anomaly data; performing interface charge passivation layer adjustment on the device performance boundary simulation data according to the device interface charge anomaly data to obtain device electrical signal optimization data; Step S45: Integrate the process electrical signal optimization data and the equipment electrical signal optimization data to obtain an electrical signal performance optimization solution.

9. The semiconductor control method according to claim 1, It is characterized in that Step S5 includes the following steps: Step S51: recognizing crystal features of semiconductor data to obtain semiconductor crystal feature data; performing crystal layout detection on the semiconductor crystal feature data to obtain semiconductor crystal layout data; Step S52: determining the lattice constant of the semiconductor crystal layout data to obtain lattice constant information; calculating the crystal bit density of the lattice constant information to obtain crystal bit density data; Step S53: determining the electron energy level distribution of the crystal bit density data to obtain the electron energy level distribution data; performing band structure identification on the semiconductor crystal layout data according to the electron energy level distribution data to obtain semiconductor band structure information; Step S54: integrating semiconductor crystal layout data, crystal bit density data and semiconductor energy band structure information to obtain semiconductor microstructure information; using graphic mapping technology to perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; Step S55: fine-tuning the layout mode of the semiconductor crystal layout data according to the semiconductor microstructure image to generate crystal layout fine-tuning control data; fine-tuning the lattice parameter of the crystal bit density data according to the semiconductor microstructure image to generate lattice parameter fine-tuning control data; integrating the crystal layout fine-tuning control data and the lattice parameter fine-tuning control data to generate a semiconductor fine-tuning control scheme; Step S56: Integrate the semiconductor fine-tuning control solution and the electrical signal performance optimization solution to generate a semiconductor control optimization report.

10. A semiconductor device, It is characterized in that For executing the semiconductor control method according to claim 1, the semiconductor device comprises: A data acquisition module is used to acquire semiconductor data; extract manufacturing parameter data of semiconductor data to obtain semiconductor manufacturing parameter data; perform spatial modeling based on semiconductor manufacturing parameter data to generate a three-dimensional thermal model of semiconductor manufacturing; monitor the thermal distribution of semiconductor data during the manufacturing process through the three-dimensional thermal model of semiconductor manufacturing to generate thermal distribution data of the manufacturing process; The semiconductor manufacturing process simulation module is used to predict the thermal stability of semiconductor manufacturing parameter data based on the thermal distribution data of the manufacturing process and generate thermal stability prediction data; extract the design parameter information of the semiconductor data to obtain the semiconductor design parameters; simulate the semiconductor manufacturing parameter data according to the semiconductor design parameters to generate manufacturing process simulation data; evaluate the thermal management efficiency of the thermal stability prediction data through the manufacturing process simulation data to generate a thermal management efficiency evaluation coefficient; The electrical signal characteristic evaluation module is used to optimize the thermal control strategy of the manufacturing process simulation data according to the thermal management efficiency evaluation coefficient and generate thermal control parameter optimization data; determine the key time nodes of the semiconductor manufacturing parameter data according to the thermal control parameter optimization data to obtain the manufacturing key time data; evaluate the electrical signal characteristics of the semiconductor data based on the manufacturing key time data to generate the electrical signal characteristic evaluation data; The electrical signal performance optimization module is used to perform carrier mobility analysis on the electrical signal characteristic evaluation data to obtain carrier mobility data; perform electrical signal performance optimization on the semiconductor data according to the carrier mobility data to generate an electrical signal performance optimization plan; The microstructure control optimization module is used to extract the microstructure information of semiconductor data to obtain semiconductor microstructure information; perform graphic mapping on the semiconductor microstructure information to generate a semiconductor microstructure image; perform fine-tuning control on the semiconductor data according to the semiconductor microstructure image to obtain a semiconductor fine-tuning control plan; integrate the semiconductor fine-tuning control plan and the electrical signal performance optimization plan to generate a semiconductor control optimization report.

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