Method and device for realizing initialization process of control state machine

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a method and device for achieving the initialization process of a control state machine, the control state machine is arranged in a programmable logic circuit of an FPGA chip, and the method comprises the steps that after the control state machine is powered on, resetting and firmware loading are conducted on the control state machine; and after firmware loading processing is completed, a target initialization instruction is obtained, and initialization processes in the TX sending direction and / or the RX receiving direction are combined and independently run according to the target initialization instruction. According to the scheme, the control state machine and the initialization process of the control state machine are realized in the programmable logic circuit of the FPGA chip, and the high flexibility and reconfigurability of the FPGA are fully utilized, so that the initialization process of the control state machine can be flexibly combined and independently operated according to different application scenes and requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a method and device for realizing an initialization process of a control state machine. Background Art

[0002] In traditional ASIC (Application Specific Integrated Circuit) design, the SERDES (Serializer / Deserializer) control state machine usually completes the overall initialization process based on a specific protocol. It includes steps such as PCS (Physical Coding Sublayer), PMA (Physical Medium Attachment), PLL (Phase Locked Loop), RX equalization, and rate switching. These initialization steps are to ensure that the control state machine can correctly process data, achieve interface connection with the physical medium, and meet specific communication protocol requirements.

[0003] However, in the FPGA (Field-Programmable Gate Array) scenario, the application scenarios of the control state machine are more diverse, so the initialization process of the control state machine is required to be more flexible. This means that it is necessary to be able to flexibly control the initialization process of each lane (channel) such as PCS, PMA, PLL, and the use of RX equalization and rate switching. This difference leads to the need for the initialization process and control mechanism of SERDES in FPGA design to be more flexible and programmable to meet diverse application requirements. Summary of the invention

[0004] In view of this, the present invention provides a method and device for implementing a control state machine initialization process, so as to solve the problem of poor flexibility of the control state machine initialization process in the prior art.

[0005] In a first aspect, the present invention provides a method for implementing a control state machine initialization process, wherein the control state machine is arranged in a programmable logic circuit of an FPGA chip, and the method comprises:

[0006] After the control state machine is powered on, resetting and firmware loading processing is performed on the control state machine;

[0007] After the firmware loading process is completed, a target initialization instruction is obtained, and the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently operated according to the target initialization instruction; the initialization process of the TX sending direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and sending rate switching; the initialization process of the RX receiving direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and receiving rate switching.

[0008] The above scheme implements the control state machine and its initialization process in the programmable logic circuit of the FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, helping to optimize the allocation and utilization of hardware resources and reduce resource waste.

[0009] In an optional implementation, after the control state machine is powered on, resetting and firmware loading processing is performed on the control state machine, including:

[0010] Powering on the control state machine digitally and analogly;

[0011] After power-on is completed, resetting the control state machine to put the control state machine in a silent state;

[0012] After the reset is completed, the control state machine is released from the reset process and the firmware is loaded.

[0013] In an optional implementation, when the target initialization instruction indicates that the initialization process is automatically executed according to the process sequence, the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently run according to the target initialization instruction, including:

[0014] In the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are performed in sequence, and,

[0015] In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence.

[0016] In an optional implementation, in the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are performed in sequence, including:

[0017] Release the PLL phase-locked loop reset, and configure the register of the PLL phase-locked loop through the APB interface to perform the PLL initialization;

[0018] After the PLL initialization is completed, a lock signal is given through the PLL phase-locked loop, and the TX PMA lanereset is released, and the corresponding bit width and lane clock are configured to perform the TX PMA initialization;

[0019] After the lane clock is stable, the TX PCS lane reset is released, and the corresponding protocol is adapted according to the register configuration to perform the TX PCS initialization;

[0020] After the TX PCS initialization is completed, TX PCSreset and TXPMA reset are reset, registers are reconfigured, and the TX PMA initialization and the TX PCS initialization are re-executed to perform the transmission rate switching.

[0021] In an optional implementation, in the initialization process of the RX receiving direction, sequentially performing the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation, and the receiving rate switching includes:

[0022] Release RX PMA reset and perform the RX PMA initialization according to the register configuration;

[0023] After the RX PMA initialization is completed, wait for the RX side clock to be stable, and use rxX_data_valid as an indication signal to perform the clock verification;

[0024] After the clock verification is completed, the RX PCS reset is released, and the RX PCS is initialized according to the APB configuration value;

[0025] After the RX PCS initialization is completed and it is determined to be a target high-speed scenario, a handshake process is initiated and the EQ operation is performed;

[0026] After the EQ operation is completed, the RX PCS reset and the RX PMA reset are reset, the registers are reconfigured, and the RX PCS initialization and the EQ operation are re-executed to perform the receiving rate switching.

[0027] In an optional implementation, when the target initialization instruction indicates to combine or independently execute the target initialization process, then the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently executed according to the target initialization instruction, including:

[0028] When the target initialization instruction indicates to execute the PCS and PMA initialization process in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, and the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed;

[0029] When the target initialization instruction indicates to perform unidirectional high-speed TX interface initialization, each initialization process of the TX transmission direction is executed in sequence;

[0030] When the target initialization instruction indicates that the initialization of the TX transmission direction and the RX reception direction are to be performed independently based on different protocols, each initialization process of the TX transmission direction and each initialization process of the RX reception direction are to be performed independently at different rates;

[0031] When the target initialization instruction indicates separate initialization under PCS abnormality, the TX PCS initialization in the TX transmission direction is independently performed, and the RX PCS initialization in the RX reception direction is independently performed;

[0032] When the target initialization instruction indicates that the PMA is initialized separately, the TXPMA initialization in the TX transmission direction is performed independently, and the RX PMA initialization in the RX reception direction is performed independently;

[0033] When the target initialization instruction instructs the PLL to be initialized independently, the PLL initialization in the TX transmission direction is performed independently.

[0034] In a second aspect, the present invention provides a device for implementing a control state machine initialization process, wherein the control state machine is arranged in a programmable logic circuit of an FPGA chip, and the device comprises:

[0035] A reset and firmware loading module, used for resetting and loading firmware on the control state machine after the control state machine is powered on;

[0036] A combination and independent operation module is used to obtain a target initialization instruction after the firmware loading process is completed, and combine and independently operate the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction according to the target initialization instruction; the initialization process of the TX sending direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and sending rate switching; the initialization process of the RX receiving direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and receiving rate switching.

[0037] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute a method for implementing a control state machine initialization process according to the first aspect or any corresponding embodiment thereof.

[0038] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a method for implementing a control state machine initialization process according to the first aspect or any corresponding embodiment thereof.

[0039] In a fifth aspect, the present invention provides a computer program product, including computer instructions, which are used to enable a computer to execute a method for implementing a control state machine initialization process according to the first aspect or any corresponding embodiment thereof.

[0040] The technical solution provided by the present invention may include the following beneficial effects:

[0041] The present invention implements a control state machine and its initialization process in a programmable logic circuit of an FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, so that the initialization process of the control state machine can be compatible with the initialization process requirements under various different protocols, which helps to optimize the allocation and utilization of hardware resources and reduce resource waste. The present invention can significantly accelerate the entire initialization process by subdividing the initialization process into multiple steps that can be run independently and allowing them to be combined as needed. The initialization process of the control state machine can be flexibly combined and independently run according to different application scenarios and requirements. This parallel processing or on-demand execution method reduces unnecessary waiting time and improves the system startup speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 is a schematic diagram of an architecture for integrating a control state machine into a SerDes IP in an ASIC design according to an embodiment of the present invention;

[0044] Figure 2 is a flow chart of a method for implementing a control state machine initialization process according to an embodiment of the present invention;

[0045] Figure 3 is a schematic diagram of a SERDES control state machine architecture based on FPGA characteristics according to an embodiment of the present invention;

[0046] Figure 4 is a flowchart of another method for implementing a control state machine initialization process according to an embodiment of the present invention;

[0047] Figure 5 is a flowchart of another method for implementing the control state machine initialization process according to an embodiment of the present invention;

[0048] Figure 6 is a schematic diagram of initializing a TX PCS lane according to an embodiment of the present invention;

[0049] Figure 7 is a schematic diagram of an RX EQ process in a target high-speed scenario according to an embodiment of the present invention;

[0050] Figure 8 is a structural block diagram of a device for implementing an initialization process of a control state machine according to an embodiment of the present invention;

[0051] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0053] It should be noted that in ASIC design, since different communication protocols (such as low-speed Ethernet, PCIe, etc.) have their own specific requirements for the physical coding sublayer (PCS), the PCS is protocol-defined. This design method results in the initialization state machine supporting the PCS also needing to be different according to different protocols. Figure 1As shown, in order to optimize the chip area and improve the user experience, the control state machine is often integrated into the SerDes IP in the above-mentioned ASIC design. Among them, RX represents the receiving end, TX represents the transmitting end, and PLL represents the phase-locked loop. The present invention separates the control state machine of PCS+PMA (physical medium attachment) from the hard IP and uses soft logic (such as the programmable logic of FPGA) to process it. The soft logic can be modified repeatedly as needed to adapt to different protocols or application scenarios, thereby improving the flexibility and response speed of the system. By implementing the control state machine with soft logic, system developers can more easily adjust and optimize the initialization process without relying on fixed hardware design.

[0054] According to an embodiment of the present invention, a method embodiment for implementing a control state machine initialization process is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0055] In this embodiment, a method for implementing a control state machine initialization process is provided. The control state machine is set in a programmable logic circuit of an FPGA chip. Figure 2 is a flow chart of a method for implementing a control state machine initialization process according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0056] Step S201, after the control state machine is powered on, the control state machine is reset and firmware is loaded.

[0057] For further information, see Figure 3 The schematic diagram of the SERDES control state machine architecture based on FPGA characteristics is shown. In this embodiment, the control state machine is separated from the hard IP and processed by soft logic (such as the programmable logic of the FPGA). By implementing the control state machine with soft logic, system developers can more easily adjust and optimize the initialization process without relying on fixed hardware design. In this embodiment, when the FPGA chip is powered on, the control state machine (i.e., the SERDES control state machine) needs to be reset first. During the reset process, it is ensured that the control state machine starts from a known initial state and clears any potential error states. After the reset is completed, this embodiment will load the firmware required for the control state machine, which may contain the program code required for initialization and operation control.

[0058] Step S202, after the firmware loading process is completed, obtain the target initialization instruction, and combine and independently operate the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction according to the target initialization instruction; the initialization process of the TX sending direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and sending rate switching; the initialization process of the RX receiving direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and receiving rate switching.

[0059] Further, after the firmware is loaded, the system obtains the target initialization instruction. The target initialization instruction defines the specific initialization tasks that the control state machine needs to perform. According to the initialization instruction, this embodiment initializes multiple steps in the transmission (TX) and reception (RX) directions, including PLL configuration, PMA initialization, PCS initialization, rate switching, clock verification, and EQ operation. These steps can be combined or performed independently to ensure the correct initialization and operation of the system. Among them, PLL initialization: configure the phase-locked loop (PLL) to generate the required clock frequency to ensure the correct timing of the transmitted signal.

[0060] The PLL initialization refers to configuring a phase locked loop (PLL) to generate a required clock frequency to ensure that the timing of the transmitted signal is correct.

[0061] TX PMA initialization means: initializing the transmitter physical medium attachment layer (TX PMA), which is responsible for encoding the transmission data and preparing it for transmission.

[0062] TX PCS initialization refers to initializing the transmitter physical coding sublayer (TX PCS) to perform physical layer coding of data.

[0063] Send rate switching means switching the sending rate as needed to match the requirements of the target communication protocol.

[0064] RX PMA initialization refers to initializing the receiving end physical medium attachment layer (RX PMA), processing the received data and decoding it.

[0065] Clock verification refers to verifying whether the clock signal at the receiving end is stable and synchronized.

[0066] RX PCS initialization refers to initializing the receiving end physical coding sublayer (RX PCS) and decoding the received data.

[0067] EQ operation refers to: performing equalization operation (EQ) to optimize the quality of the received signal.

[0068] Receiving rate switching means switching the receiving rate as needed to match the requirements of the target communication protocol.

[0069] In summary, this embodiment implements the control state machine and its initialization process in the programmable logic circuit of the FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, so that the initialization process of the control state machine can be compatible with the initialization process requirements under various protocols, which helps to optimize the allocation and utilization of hardware resources and reduce resource waste. This embodiment can significantly speed up the entire initialization process by subdividing the initialization process into multiple steps that can be run independently and allowing them to be combined as needed. The initialization process of the control state machine can be flexibly combined and independently run according to different application scenarios and requirements. This parallel processing or on-demand execution method reduces unnecessary waiting time and improves the system startup speed.

[0070] In this embodiment, another method for implementing the initialization process of a control state machine is provided. The control state machine is set in a programmable logic circuit of an FPGA chip. Figure 4 is a flowchart of another method for implementing the control state machine initialization process according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0071] Step S401, powering on the digital and analog circuits of the control state machine.

[0072] For further information, see Figure 5 A flowchart of another method for implementing the control state machine initialization process is shown. Figure 5 The control state machine in the FPGA is implemented by soft logic. Figure 5 Each step in the process can be disassembled and reassembled. Figure 5 The left side includes steps 1 to 4.8, wherein step 1 is: the chip system is powered on as a whole, and SERDES completes the power-on of digital and analog circuits. That is, in this embodiment, the entire FPGA chip system is powered on, including the digital and analog circuit parts of the SERDES control state machine. Ensure that each part of the SERDES control state machine has obtained the necessary power supply.

[0073] Step S402: after power-on is completed, the control state machine is reset to put the control state machine in a silent state.

[0074] Further, such as Figure 5As shown, step 2 is: the por_rst of the SERDES control state machine is reset to ensure that the SERDES control state machine is silent. That is, after the power-on is completed, this embodiment uses the Power-On Reset (POR) signal to reset the SERDES control state machine to the initial state to ensure that it is in a known state after full power-on. At this time, the SERDES control state machine is in a reset state and does not perform any operation.

[0075] Step S403: After the reset is completed, the control state machine is released from the reset process and the firmware is loaded.

[0076] Further, such as Figure 5 As shown, step 3 is: the por_rst of the SERDES control state machine releases the reset, and the SERDES control state machine performs the firmware loading process. That is to say, once the system is stable, the POR reset is released, and the reset signal is released at this time, allowing the SERDES control state machine to start the firmware loading process. The SERDES control state machine loads and executes the necessary firmware (fireware) to prepare for subsequent initialization operations.

[0077] Step S404: after the firmware loading process is completed, a target initialization instruction is obtained.

[0078] Step S405, when the target initialization instruction indicates to automatically execute the initialization process according to the process sequence, in the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are executed in sequence, and,

[0079] In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence.

[0080] In some optional implementations, step S405 includes:

[0081] In the initialization process of the TX transmission direction, the PLL phase-locked loop reset is released, and the register of the PLL phase-locked loop is configured through the APB interface to perform the PLL initialization;

[0082] After the PLL initialization is completed, a lock signal is given through the PLL phase-locked loop, and the TX PMA lanereset is released, and the corresponding bit width and lane clock are configured to perform the TX PMA initialization;

[0083] After the lane clock is stable, the TX PCS lane reset is released, and the corresponding protocol is adapted according to the register configuration to perform the TX PCS initialization;

[0084] After the TX PCS initialization is completed, TX PCSreset and TXPMA reset are reset, registers are reconfigured, and the TX PMA initialization and the TX PCS initialization are re-executed to perform the transmission rate switching.

[0085] In some optional implementations, step S405 includes:

[0086] In the initialization process of the RX receiving direction, the RX PMA reset is released, and the RX PMA initialization is performed according to the register configuration;

[0087] After the RX PMA is initialized, wait for the RX side clock to stabilize, and use rxX_data_valid as the indication signal to perform the clock verification;

[0088] After the clock verification is completed, the RX PCS reset is released and the RX PCS is initialized according to the APB configuration value;

[0089] After the RX PCS is initialized and the target high-speed scenario is determined, a handshake process is initiated and the EQ operation is performed;

[0090] After the EQ operation is completed, the RX PCS reset and the RX PMA reset are reset, the registers are reconfigured, and the RX PCS initialization and the EQ operation are re-executed to perform the receiving rate switching.

[0091] Further, such as Figure 5 As shown, step 4 is: detailed process disassembly of TX sending direction:

[0092] 4.1. After the firmware loading of the SERDES control state machine is completed, the PLL reset of the control state machine is released, and the soft logic configures the register configuration of the PLL through the APB interface to configure the corresponding frequency. That is to say, this embodiment first completes the loading of the firmware (fireware) of the SERDES control state machine, and the firmware contains the necessary code and configuration information required for the initialization of the Serdes module. Subsequently, the reset of the PLL (phase-locked loop) is released. PLL is a key component in the SERDES control state machine for generating a stable clock signal. Through the APB (Advanced Peripheral Bus) interface, the soft logic configures the register of the PLL to set the required frequency, thereby ensuring that the TX path can generate a clock signal of the correct frequency.

[0093] 4.2. After configuration is completed, the PLL gives a lock signal, indicating that the PLL has completed initialization. That is, after configuration is completed, the PLL will send a lock signal, indicating that it has successfully locked to the specified frequency point and is ready to provide a stable clock signal for the TX path.

[0094] 4.3. The PMA lane reset of TX is released. The PMA of TX is configured to the corresponding bit width according to the initial value given by APB, and the corresponding associated clock is given. That is, this embodiment releases the lane reset of the physical medium adaptation layer (PMA) in the TX sending direction. The PMA is the component responsible for sending and receiving physical layer signals. Afterwards, the PMA of TX is configured to the corresponding bit width according to the initial value provided by the APB interface, and generates the corresponding associated clock. The associated clock is a clock signal transmitted together with the data signal, which is used for synchronization and data recovery at the receiving end.

[0095] 4.4. The TX clock is stable. That is, ensure that the clock signal provided by the PMA is stable and meets the system requirements.

[0096] 4.5. PMA gives a TX link enable indication (TX PMA done). That is, when the TX PMA configuration is completed and the slave clock is stable, PMA will send a TX PMA done signal, indicating that the TX link is ready to send data.

[0097] 4.6. The PCS lane reset in the TX transmission direction is released, and the PCS adapts to the corresponding protocol according to the configuration of the register. That is, this embodiment releases the lane reset of the physical coding sublayer (PCS) in the TX transmission direction. The PCS is responsible for converting parallel data into serial data, and performing encoding and error detection, etc. Afterwards, the PCS adapts to the corresponding communication protocol according to the configuration of the register to ensure that the transmitted data conforms to the format and protocol expected by the receiving end.

[0098] 4.7、TX PCS done is given to indicate that the TX PCS direction reset initialization process is completed. That is, when the PCS is initialized and ready to send data, a TX PCS done signal will be issued, indicating that the TX PCS direction reset initialization process has been completed.

[0099] 4.8. If the TX transmission direction needs to switch the rate.

[0100] 4.8.1、The system resets the PCS reset and PMA reset in the TX transmission direction. That is, if the rate in the TX transmission direction needs to be changed, the system needs to reset the PCS and PMA reset in the TX transmission direction to avoid interference during the rate switching process.

[0101] 4.8.2. APB reconfigures PCS and PMA registers. That is, this embodiment modifies the register settings of PCS and PMA through the APB interface to adapt to the new rate requirements.

[0102] 4.8.3. Initialization Complete the process from step 4.3 to step 4.7 again. That is, re-execute the initialization process from step 4.3 to step 4.7 to ensure that the TX path can be correctly initialized and work stably at the new rate.

[0103] Further, such as Figure 5 As shown, step 5 is: detailed process disassembly of RX receiving direction:

[0104] 5.1. RX PMA reset is released, and PMA performs lane initialization of PMA according to the register configuration value. That is, this embodiment first releases the reset of the physical medium adaptation layer (PMA) at the RX end. PMA is the underlying physical interface responsible for signal reception and transmission, and is directly connected to the physical medium (such as optical fiber, copper wire). This step allows PMA to start initializing its lane (channel) according to the configuration value of the register, including setting parameters such as signal strength and equalizer.

[0105] 5.2. Wait for the RX side clock problem, and use rxX_data_valid as the indication signal. That is, this embodiment waits for the RX receiving end clock to be stable, and uses the rxX_data_valid signal as an indication of clock stability. Ensure that the clock is stable before the data starts to be effectively received, and then correctly receive the data.

[0106] 5.3. PMA gives RX PMA reset done. That is, after the PMA completes initialization, this embodiment will send a signal (such as RX_PMA_RESET_DONE) to indicate that the PMA is ready to receive data. RX_PMA_RESET_DONE is a signal to continue the subsequent process, indicating that the PMA layer has completed initialization and can start normal operation.

[0107] 5.4. Release RX PCS reset, and initialize PCS according to the current APB configuration value. That is, this embodiment releases the reset of the physical coding sublayer (PCS) in the RX receiving direction, and initializes PCS according to the current APB (Advanced Peripheral Bus) configuration value.

[0108] 5.5. If it is determined to be a high-speed scenario (>10Gbps), initiate the handshake process and trigger PMA to perform an EQ. That is, if the system works in a high-speed scenario (such as >10Gbps), initiate the handshake process and trigger PMA to perform an equalization (EQ operation) process. The handshake process is used to confirm the parameter matching at both ends of the link, while EQ is used to adjust the signal quality to compensate for the loss in the channel and ensure that the data can be received correctly.

[0109] 5.6. After the EQ operation is completed, the PCS gives a reset done. After the EQ operation is completed, the PCS will send a signal (such as PCS_RESET_DONE) to indicate that the PCS has completed initialization and is ready to process data. This indicates that the bottom layer and the middle layer of the receiving path have completed initialization and can start receiving and processing data.

[0110] 5.7. If the user does not meet the requirements after the first EQ operation, he can initiate another EQ operation. That is, if the user believes that the result of the first EQ operation does not meet the requirements, he can initiate additional EQ operations, allowing the system to make multiple EQ adjustments as needed to optimize the signal quality.

[0111] 5.8. If the RX receiving direction needs to switch the rate:

[0112] 5.8.1. The system resets the PCS reset and PMA reset in the TX transmission direction. That is, if the rate switching is required in the RX receiving direction, the system first resets the PCS and PMA reset in the TX transmission direction to avoid interference during the rate switching process.

[0113] 5.8.2. The user changes the registers of PCS and PMA through APB. That is, the user changes the register configuration of PCS and PMA through APB to adapt to the new rate.

[0114] 5.8.3. Initialization is completed again from step 5.4->step 5.6. That is, the steps from step 5.4 to step 5.6 are re-executed to complete the initialization and stabilization process of PCS and PMA at the new rate.

[0115] In summary, in order to achieve the effects of automation and flexibility, this embodiment triggers the entire initialization process by providing an initialization reset signal, and this process will execute all necessary initialization actions in the current scenario in sequence. This method greatly simplifies user operations and improves the degree of automation of the system. It includes: designing a global reset signal, which will start a preset initialization process when it is triggered; the initialization process contains multiple sub-processes, each sub-process corresponds to the initialization of one or more hardware components; the sub-processes are executed in a certain order to ensure that all necessary initialization actions are executed correctly; at the end of the process, the system will send an initialization completion signal to inform the user that all initialization actions have been completed.

[0116] Step S406, when the target initialization instruction indicates to combine or independently execute the target initialization process, the initialization process of the TX transmission direction and / or the initialization process of the RX reception direction are combined or independently executed.

[0117] In some optional implementations, step S406 includes:

[0118] When the target initialization instruction indicates to execute the PCS and PMA initialization process in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, and the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed;

[0119] When the target initialization instruction indicates to execute the unidirectional high-speed TX interface initialization, each initialization process of the TX transmission direction is executed in sequence;

[0120] When the target initialization instruction indicates to independently perform initialization of the TX transmission direction and the RX reception direction based on different protocols, each initialization process of the TX transmission direction and each initialization process of the RX reception direction are independently performed at different rates;

[0121] When the target initialization instruction indicates separate initialization under PCS abnormality, the TX PCS initialization in the TX transmission direction is independently performed, and the RX PCS initialization in the RX reception direction is independently performed;

[0122] When the target initialization instruction indicates that the PMA is initialized separately, the TX PMA initialization in the TX transmission direction is performed independently, and the RX PMA initialization in the RX reception direction is performed independently;

[0123] When the target initialization instruction instructs the PLL to be initialized independently, the PLL initialization in the TX transmission direction is performed independently.

[0124] Furthermore, this embodiment provides a flexible configuration and usage of different components (such as PCS, PMA, PLL, EQ, etc.) in a Serdes (serializer / deserializer) system. Including:

[0125] 1.1 If it is low-speed PCS+PMA, users can bypass EQ related processes:

[0126] In low-speed communication scenarios, since signal attenuation and distortion are relatively small, complex equalization (EQ) operations may not be required. Therefore, the system allows users to bypass the EQ operation-related processes and directly initialize the PCS and PMA. This can reduce unnecessary processing time and improve system efficiency.

[0127] 1.2 If the user only wants to use the TX sending direction as a high-speed interface, the user only needs to follow the TX sending direction initialization process:

[0128] In some application scenarios, users may only need to use the TX transmission direction of Serdes for high-speed data transmission, without the RX reception direction. In this case, users can choose to only perform the initialization process of the TX transmission direction, including TX PCS, TX PMA, and related clock and signal configuration. This can save resources and focus on performance optimization in the TX transmission direction.

[0129] 1.3 If the user wants TX and RX to use different protocols, TX and RX can be initialized separately and configured with different rates:

[0130] The SERDES control state machine supports independent configuration of the TX transmission direction and the RX reception direction, including the protocol and rate. That is, the user can select different protocols and rates for the TX transmission direction and the RX reception direction as needed. During the initialization process, the user can configure the PCS layer of the TX transmission direction and the RX reception direction separately to adapt to different protocol requirements and set the corresponding rate, so that the SERDES control state machine can be widely used in a variety of communication scenarios.

[0131] 1.4 If only the PCS is abnormal, you can perform PCS initialization alone:

[0132] During the operation of the SERDES control state machine, if an abnormality is detected in the PCS layer (such as data error, synchronization loss, etc.), the user can choose to reinitialize only the PCS layer without resetting the entire SERDES control state machine. This can quickly restore the normal function of the PCS layer while keeping the status of other components (such as PMA, PLL, etc.) unchanged. This local initialization method helps to reduce system recovery time and improve system stability.

[0133] 1.5 If you do not need to use PCS, you can go through the PMA initialization process alone:

[0134] If the user may not need to use the PCS layer for protocol processing, but directly serialize and deserialize the data through the PMA layer, in this case, the present embodiment can only execute the PMA initialization process, configure the corresponding clock and signal parameters, thereby simplifying the system structure and reducing power consumption and cost.

[0135] 1.6 If you only use PLL, you can go through the PLL initialization process alone to provide the clock from PLL:

[0136] PLL (Phase Locked Loop) is a key component in the SERDES control state machine for generating a stable clock signal. If the user only needs to use PLL to provide a clock signal without data transmission, then only the PLL initialization process can be executed. During the initialization process, the user can configure the parameters of the PLL (such as frequency, phase, etc.) to generate a clock signal that meets the requirements. This method allows the PLL to be used as an independent clock source to provide a stable clock reference for other system components.

[0137] Furthermore, this embodiment can realize flexible combination of block diagrams and component reset. The system allows users to flexibly combine components in the block diagram as needed and reset any component. This flexibility enables the system to adapt to a variety of different application scenarios and user needs. For example, if the user wants to initialize only a lane of the PCS in the TX transmission direction, please refer to Figure 6 The schematic diagram of initializing the TX PCS lane is shown in Figure 6 In the TX PCS lane initialization process, the user can choose to trigger only the TX PCS lane initialization process. If the user wants to perform EQ (equalization) operation on the RX receiving direction in the target high-speed scenario, please refer to Figure 7 The schematic diagram of the RX EQ process in the target high-speed scenario is shown in Figure 7 In , the user can directly trigger the EQ operation process without performing the initialization of the entire RX path.

[0138] In summary, this embodiment implements the control state machine and its initialization process in the programmable logic circuit of the FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, so that the initialization process of the control state machine can be compatible with the initialization process requirements under various protocols, which helps to optimize the allocation and utilization of hardware resources and reduce resource waste. This embodiment can significantly speed up the entire initialization process by subdividing the initialization process into multiple steps that can be run independently and allowing them to be combined as needed. The initialization process of the control state machine can be flexibly combined and independently run according to different application scenarios and requirements. This parallel processing or on-demand execution method reduces unnecessary waiting time and improves the system startup speed.

[0139] In the present embodiment, a device for realizing the initialization process of the control state machine is also provided, and the device is used to realize the above-mentioned embodiment and preferred implementation mode, and the descriptions which have been made are not repeated here. As used below, the term "module" can realize the combination of software and / or hardware of the predetermined function. Although the device described in the following embodiments is preferably realized by software, the realization of hardware, or the combination of software and hardware is also possible and conceived.

[0140] This embodiment provides a device for implementing the initialization process of a control state machine, wherein the control state machine is arranged in a programmable logic circuit of an FPGA chip, such as Figure 8 As shown, including:

[0141] The reset and firmware loading module 801 is used to reset and load the firmware of the control state machine after the control state machine is powered on;

[0142] The combination and independent operation module 802 is used to obtain the target initialization instruction after the firmware loading process is completed, and combine and independently operate the initialization process of the TX transmission direction and / or the initialization process of the RX reception direction according to the target initialization instruction; the initialization process of the TX transmission direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and transmission rate switching; the initialization process of the RX reception direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and reception rate switching.

[0143] In some optional implementations, the reset and firmware loading module 801 is further used to:

[0144] Powering on the control state machine digitally and analogly;

[0145] After power-on is completed, the control state machine is reset to put the control state machine in a silent state;

[0146] After the reset is completed, the control state machine is released from the reset process and the firmware is loaded.

[0147] In some optional implementations, when the target initialization instruction indicates to automatically execute the initialization process according to the process sequence, the combined and independent operation module 802 is further used to:

[0148] In the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TXPCS initialization and the transmission rate switching are performed in sequence, and,

[0149] In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence.

[0150] In some optional implementations, the combined and independent operation module 802 is further used to:

[0151] Release the PLL phase-locked loop reset, and configure the register of the PLL phase-locked loop through the APB interface to perform the PLL initialization;

[0152] After the PLL initialization is completed, a lock signal is given through the PLL phase-locked loop, and the TX PMA lanereset is released, and the corresponding bit width and lane clock are configured to perform the TX PMA initialization;

[0153] After the lane clock is stable, the TX PCS lane reset is released, and the corresponding protocol is adapted according to the register configuration to perform the TX PCS initialization;

[0154] After the TX PCS initialization is completed, TX PCSreset and TXPMA reset are reset, registers are reconfigured, and the TX PMA initialization and the TX PCS initialization are re-executed to perform the transmission rate switching.

[0155] In some optional implementations, the combined and independent operation module 802 is further used to:

[0156] Release RX PMA reset and perform RX PMA initialization according to register configuration;

[0157] After the RX PMA is initialized, wait for the RX side clock to stabilize, and use rxX_data_valid as the indication signal to perform the clock verification;

[0158] After the clock verification is completed, the RX PCS reset is released and the RX PCS is initialized according to the APB configuration value;

[0159] After the RX PCS is initialized and the target high-speed scenario is determined, a handshake process is initiated and the EQ operation is performed;

[0160] After the EQ operation is completed, the RX PCS reset and the RX PMA reset are reset, the registers are reconfigured, and the RX PCS initialization and the EQ operation are re-executed to perform the receiving rate switching.

[0161] In some optional implementations, when the target initialization instruction indicates to perform the target initialization process in combination or independently, the combination and independent operation module 802 is further used to:

[0162] When the target initialization instruction indicates to execute the PCS and PMA initialization process in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, and the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed;

[0163] When the target initialization instruction indicates to execute the unidirectional high-speed TX interface initialization, each initialization process of the TX transmission direction is executed in sequence;

[0164] When the target initialization instruction indicates to independently perform initialization of the TX transmission direction and the RX reception direction based on different protocols, each initialization process of the TX transmission direction and each initialization process of the RX reception direction are independently performed at different rates;

[0165] When the target initialization instruction indicates separate initialization under PCS abnormality, the TX PCS initialization in the TX transmission direction is independently performed, and the RX PCS initialization in the RX reception direction is independently performed;

[0166] When the target initialization instruction indicates that the PMA is initialized separately, the TX PMA initialization in the TX transmission direction is performed independently, and the RX PMA initialization in the RX reception direction is performed independently;

[0167] When the target initialization instruction instructs the PLL to be initialized independently, the PLL initialization in the TX transmission direction is performed independently.

[0168] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0169] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0170] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0171] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0172] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0173] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0174] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0175] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0176] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0177] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. A method for implementing a control state machine initialization process, characterized in that: The control state machine is arranged in a programmable logic circuit of an FPGA chip, and the method comprises: After the control state machine is powered on, resetting and firmware loading processing is performed on the control state machine; After the firmware loading process is completed, a target initialization instruction is obtained, and the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently operated according to the target initialization instruction; the initialization process of the TX sending direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and sending rate switching; the initialization process of the RX receiving direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and receiving rate switching.

2. The method according to claim 1, characterized in that: After the control state machine is powered on, resetting and firmware loading processing are performed on the control state machine, including: Powering on the control state machine digitally and analogly; After power-on is completed, resetting the control state machine to put the control state machine in a silent state; After the reset is completed, the control state machine is released from the reset process and the firmware is loaded.

3. The method according to claim 1, characterized in that When the target initialization instruction indicates that the initialization process is automatically executed according to the process sequence, the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently run according to the target initialization instruction, including: In the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are performed in sequence, and, In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence.

4. The method according to claim 3, characterized in that In the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are performed in sequence, including: Release the PLL phase-locked loop reset, and configure the register of the PLL phase-locked loop through the APB interface to perform the PLL initialization; After the PLL initialization is completed, a lock signal is given through the PLL phase-locked loop, and the TX PMA lanereset is released, and the corresponding bit width and lane clock are configured to perform the TX PMA initialization; After the lane clock is stable, the TX PCS lane reset is released, and the corresponding protocol is adapted according to the register configuration to perform the TX PCS initialization; After the TX PCS initialization is completed, TX PCSreset and TXPMA reset are reset, registers are reconfigured, and the TX PMA initialization and the TX PCS initialization are re-executed to perform the transmission rate switching.

5. The method according to claim 3, characterized in that: In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence, including: Release RX PMA reset and perform the RX PMA initialization according to the register configuration; After the RX PMA initialization is completed, wait for the RX side clock to be stable, and use rxX_data_valid as an indication signal to perform the clock verification; After the clock verification is completed, the RX PCS reset is released, and the RX PCS is initialized according to the APB configuration value; After the RX PCS initialization is completed and it is determined to be a target high-speed scenario, a handshake process is initiated and the EQ operation is performed; After the EQ operation is completed, the RX PCS reset and the RX PMA reset are reset, the registers are reconfigured, and the RX PCS initialization and the EQ operation are re-executed to perform the receiving rate switching.

6. The method according to claim 1, characterized in that When the target initialization instruction indicates to combine or independently execute the target initialization process, the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently executed according to the target initialization instruction, including: When the target initialization instruction indicates to execute the PCS and PMA initialization process in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, and the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed; When the target initialization instruction indicates to perform unidirectional high-speed TX interface initialization, each initialization process of the TX transmission direction is executed in sequence; When the target initialization instruction indicates that the initialization of the TX transmission direction and the RX reception direction are to be performed independently based on different protocols, each initialization process of the TX transmission direction and each initialization process of the RX reception direction are to be performed independently at different rates; When the target initialization instruction indicates separate initialization under PCS abnormality, the TX PCS initialization in the TX transmission direction is independently performed, and the RX PCS initialization in the RX reception direction is independently performed; When the target initialization instruction indicates that the PMA is initialized separately, the TX PMA initialization in the TX transmission direction is performed independently, and the RX PMA initialization in the RX reception direction is performed independently; When the target initialization instruction instructs the PLL to be initialized independently, the PLL initialization in the TX transmission direction is performed independently.

7. A device for implementing a control state machine initialization process, characterized in that: The control state machine is arranged in a programmable logic circuit of an FPGA chip, and the device comprises: A reset and firmware loading module, used for resetting and loading firmware on the control state machine after the control state machine is powered on; A combination and independent operation module is used to obtain a target initialization instruction after the firmware loading process is completed, and combine and independently operate the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction according to the target initialization instruction; the initialization process of the TX sending direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and sending rate switching; the initialization process of the RX receiving direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and receiving rate switching.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes a method for implementing a control state machine initialization process as described in any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute a method for implementing a control state machine initialization process according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute a method for implementing an initialization process of a control state machine according to any one of claims 1 to 6.

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