Methods and devices for establishing time margins, electronic equipment, and storage media

Abstract

This invention proposes a method, apparatus, electronic device, and storage medium for adjusting the setup time margin. The method includes a one-step repair and a one-step adjustment of the setup time margin. Each step is based on different categories of timing paths. First, all timing paths with setup time violations are collected and their violations are repaired to ensure the functional correctness of the digital circuit. Then, timing paths with excessive setup time margins are collected and their setup time margins are adjusted to prevent over-repair, while simultaneously reducing the power consumption and area of ​​the digital circuit. This invention provides detailed specifications for each step of the adjustment for each category, forming a coded adjustment process that facilitates automated adjustment via storage devices and processors, effectively improving repair efficiency. The adjustment degree of each step in the adjustment method is relatively small, reducing the possibility of repeated adjustments and improving the accuracy and stability of the adjustment.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a method and apparatus for establishing time margin, electronic equipment, and storage medium. Background Technology

[0002] In integrated circuit design, good timing convergence is required. Timing convergence includes both setup time convergence and hold time convergence. Failure to meet setup time requirements can affect circuit functionality or cause the circuit's operating frequency to fall short of design specifications. Therefore, fixing setup time violations is crucial for digital chip design. Furthermore, power consumption and area are key performance indicators in integrated circuit design; therefore, power consumption and area must be considered when fixing setup time violations.

[0003] As integrated circuit design scales up, chip timing convergence becomes increasingly difficult. Current setup time violation repair schemes include: inserting buffers on the clock path using useful offsets, replacing logic cells on the data path with larger sizes, or replacing the threshold voltage of logic cells on the data path with lower threshold voltages. Each of these three schemes has limited timing improvement and increases chip power consumption or area. More optimized schemes combine two or three of these schemes, improving the repair effect to some extent, but still failing to address the drawbacks of increased power consumption and area. Furthermore, the choice of which repair scheme to use requires the designer's judgment, often involving repeated trials and constant re-simulation to verify the success of the repair, resulting in low repair efficiency.

[0004] In addition, existing repair solutions may introduce the problem of excessive repair of setup time violations after fixing setup time violations, resulting in an excessively large setup time margin. Although the functional correctness of the circuit is guaranteed, it leads to a waste of power consumption and area. Summary of the Invention

[0005] To overcome the above shortcomings, embodiments of the present invention provide a method and apparatus for establishing time margin, an electronic device, and a storage medium.

[0006] The technical solutions adopted in the embodiments of the present invention are as follows:

[0007] According to a first aspect of the present invention, a method for adjusting time margin is provided, comprising:

[0008] S1: Extract the time margin S for all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T suIn the formula, T is the clock period of the digital circuit, and Δ is the deviation between the clock source and the clock input terminals of the two registers, that is, the time T it takes for the clock source to reach the clock input terminal of the second register. clk2 Subtract the time T to reach the first register clock. clk1 T co T data These represent the maximum propagation delay and maximum logic delay of the timing path, respectively. su This refers to the establishment time of the time sequence path;

[0009] S2: For situations where the time margin S is less than the acceptable threshold S min The timing path is repaired to increase its time margin to the acceptable threshold S. min In the above, the time margin S0 before repair and the degree of time repair ΔS are used to determine whether the time margin of the timing path after repair reaches S. min above;

[0010] S3: After repair, calculate the power consumption and area of ​​the digital circuit. If the power consumption is greater than the power consumption requirement value P of the digital circuit... max Or the area is greater than the required area value A max Then, for a time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin, thereby reducing the power consumption of the digital circuit to P. max The following describes how to reduce the area of ​​a digital circuit to A. max The following section determines whether the power consumption of the digital circuit has been reduced to P after adjustment, based on the time margin S0', power consumption P0', area A0' before adjustment, and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA'. max Below, has the area been reduced to A? max Next, has the timing margin of the timing path decreased to S? max The following and in S min above;

[0011] Specifically, for time margin S less than the qualified threshold S min Repair the timing path, including:

[0012] Repair solution a is to add a buffer between the clock source and the second register clock input in the clock path of the digital circuit timing path, increasing T. clk2 This increases the deviation Δ between the clock source and the clock inputs of the two registers, thus increasing the setup time margin S;

[0013] Solution b is to increase the size of logic elements by one level in the data path of the digital circuit timing path. This increases the driving capability of the elements, reduces the element delay, and thus reduces T. dataIncrease the setup time margin S;

[0014] Solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T. data Increase the setup time margin S;

[0015] Specifically, for a time margin S greater than a surplus threshold S max The timing path needs to be adjusted, including:

[0016] Adjustment scheme a' is as follows: In the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock input, reducing T. clk2 This reduces Δ, decreases the settling time margin S, and improves power consumption and area;

[0017] Adjustment scheme b' is as follows: In the data path of the digital circuit timing path, reduce the size of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area;

[0018] Adjustment scheme c' is as follows: In the data path of the digital circuit timing path, increase the threshold voltage of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area.

[0019] According to a second aspect of the present invention, an adjustment device for establishing a time margin is provided, comprising:

[0020] The extraction module is used to extract the time margin S of all timing paths in a digital circuit, where S = T + Δ - (T co +T data )-T su In the formula, T is the clock period of the digital circuit, and Δ is the deviation between the clock source and the clock input terminals of the two registers, that is, the time T it takes for the clock source to reach the clock input terminal of the second register. clk2 Subtract the time T to reach the first register clock. clk1 T co T data These represent the maximum propagation delay and maximum logic delay of the timing path, respectively. su This refers to the establishment time of the time sequence path;

[0021] The repair module is used to address situations where the time margin S is less than the acceptable threshold S. min The timing path is repaired to increase its time margin to the acceptable threshold S. min In the above, the time margin S0 before repair and the degree of time repair ΔS are used to determine whether the time margin of the timing path after repair reaches S. minabove;

[0022] The adjustment module is used to calculate the power consumption and area of ​​the digital circuit after repair. If the power consumption is greater than the power consumption requirement value P of the digital circuit, the adjustment module will adjust the power consumption accordingly. max Or the area is greater than the required area value A max Then, for a time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin, thereby reducing the power consumption of the digital circuit to P. max The following describes how to reduce the area of ​​a digital circuit to A. max The following section determines whether the power consumption of the digital circuit has been reduced to P after adjustment, based on the time margin S0', power consumption P0', area A0' before adjustment, and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA'. max Below, has the area been reduced to A? max Next, has the timing margin of the timing path decreased to S? max The following and in S min above;

[0023] Specifically, for time margin S less than the qualified threshold S min Repair the timing path, including:

[0024] Repair solution a is to add a buffer between the clock source and the second register clock input in the clock path of the digital circuit timing path, increasing T. clk2 This increases the deviation Δ between the clock source and the clock inputs of the two registers, thus increasing the setup time margin S;

[0025] Solution b is to increase the size of logic elements by one level in the data path of the digital circuit timing path. This increases the driving capability of the elements, reduces the element delay, and thus reduces T. data Increase the setup time margin S;

[0026] Solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T. data Increase the setup time margin S;

[0027] Specifically, for a time margin S greater than a surplus threshold S max The timing path needs to be adjusted, including:

[0028] Adjustment scheme a' is as follows: In the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock input, reducing T. clk2 This reduces Δ, decreases the settling time margin S, and improves power consumption and area;

[0029] Adjustment scheme b' is as follows: In the data path of the digital circuit timing path, reduce the size of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area;

[0030] Adjustment scheme c' is as follows: In the data path of the digital circuit timing path, increase the threshold voltage of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area.

[0031] According to a third aspect of the present invention, an electronic device is provided, comprising:

[0032] One or more processors;

[0033] Memory, used to store one or more programs;

[0034] When the one or more programs are executed by the one or more processors, the one or more processors perform the method as described in the first aspect.

[0035] According to a fourth aspect of the present invention, a computer-readable storage medium is provided having computer instructions stored thereon that, when executed by a processor, implement the steps of the method as described in the first aspect.

[0036] The beneficial effects of the embodiments of the present invention are as follows:

[0037] 1. Timing paths are divided into two categories based on setup time margin for repair and adjustment. First, the faulty timing paths with setup time margin less than the qualified threshold are repaired. After the repair is completed, the timing paths with excessive setup time margin are adjusted. While ensuring the correctness of digital circuit function, the over-repair of setup time margin is prevented, thus achieving optimization of power consumption and area.

[0038] 2. Before the adjustment begins, the degree of adjustment for each step is digitally processed by querying the process library or routine testing. This allows for quick determination of whether the time margin, power consumption, and area meet the requirements through addition and subtraction operations during the adjustment process. Adjustment can be stopped at any time based on the judgment result, avoiding the need to re-simulate the time margin, power consumption, or area of ​​the digital circuit with simulation software for each adjustment step. This greatly saves adjustment time, improves adjustment efficiency, and enhances the predictability and controllability of the adjustment process.

[0039] 3. Specific and detailed regulations were made for each step of the repair and adjustment plan, forming a codeable repair and adjustment process, which facilitates automated repair and adjustment through storage devices and processors, saving time and labor costs.

[0040] 4. The degree of adjustment for each step in the adjustment method is set to be small and easy to implement, which can effectively avoid excessive adjustment of the setup time, reduce the possibility of repeated adjustments, and improve the accuracy and stability of the adjustment. Attached Figure Description

[0041] Figure 1 This is a flowchart illustrating a method for establishing a time margin adjustment according to an embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of the timing path topology and the relationship between various signals provided in an embodiment of the present invention.

[0043] Figure 3 This is a flowchart illustrating the process of repairing a time violation path according to an embodiment of the present invention.

[0044] Figure 4 This is a schematic diagram illustrating a specific repair scheme for establishing a time violation path according to an embodiment of the present invention.

[0045] Figure 5 This is a flowchart illustrating the process of adjusting a path with excessively large establishment time margin, as provided in an embodiment of the present invention.

[0046] Figure 6 This is a schematic diagram illustrating a specific adjustment scheme for establishing a path with excessive time margin, provided in an embodiment of the present invention.

[0047] Figure 7 This is a block diagram of a time margin adjustment device provided in an embodiment of the present invention.

[0048] Figure 8 This is a schematic diagram of an electronic device provided according to an embodiment of the present invention. Detailed Implementation

[0049] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0050] In this invention, before adjustment, it is necessary to obtain the time repair degree of three repair schemes, as well as the time adjustment degree, power consumption adjustment degree, and area adjustment degree of three adjustment schemes. The power consumption and area of ​​the buffers on the clock path, logic elements of different sizes, and logic elements with different threshold voltages can be obtained by querying process library parameters, thereby obtaining the power consumption adjustment degree and area adjustment degree of the three adjustment schemes.

[0051] To determine the degree of time adjustment, a test is needed to obtain the delay of the buffer, logic elements of different sizes, and logic elements with different threshold voltages under the operating clock of the digital circuit. This will allow us to determine the degree of time adjustment for the three adjustment schemes. This test can be easily performed using conventional techniques.

[0052] The following details a method for adjusting time margins according to embodiments of the present invention, with reference to... Figure 1 The method includes the following steps:

[0053] S1: Extract the time margin S of all timing paths in the digital circuit;

[0054] Specifically, the tools for extracting the timing margin of all timing paths in a digital circuit include, but are not limited to, PrimeTime and Design Compiler.

[0055] like Figure 2 The formula for calculating the time margin is S = T + Δ - (T co +T data )-T su In the formula, T is the clock period of the digital circuit, and Δ is the deviation between the clock source and the clock input terminals of the two registers, that is, the time T it takes for the clock source to reach the clock input terminal of the second register. clk2 Subtract the time T to reach the first register clock. clk1 T co T data These represent the maximum propagation delay and maximum logic delay of the timing path, respectively. su This refers to the setup time of the timing path. To ensure the correct functioning of the digital circuit, the setup time margin S needs to be greater than the acceptable threshold S0. min .

[0056] S2: For situations where the time margin S is less than the acceptable threshold S min The timing path is repaired to increase its time margin to the acceptable threshold S. min In the above, the time margin S0 before repair and the degree of time repair ΔS are used to determine whether the time margin of the timing path after repair reaches S. min above;

[0057] Specifically, for time margin S less than the qualified threshold S min Repairing the timing path involves the following three solutions, as detailed below:

[0058] Repair solution a is to add a buffer between the clock source and the second register clock input in the clock path of the digital circuit timing path, increasing T. clk2This increases the deviation Δ between the clock source and the clock inputs of the two registers, thus increasing the setup time margin S; the time repair degree ΔS of this repair scheme is ΔS a However, adding a buffer will increase the chip's power consumption and area.

[0059] Solution b is to increase the size of logic elements by one level in the data path of the digital circuit timing path. This increases the driving capability of the elements, reduces the element delay, and thus reduces T. data Increase the establishment time margin S; the time repair degree ΔS of this repair scheme is ΔS b However, increasing the size of logic elements will increase the chip's power consumption and area.

[0060] Solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T. data Increase the establishment time margin S; the time repair degree ΔS of this repair scheme is ΔS c However, reducing the threshold voltage of logic elements will increase the chip's power consumption and area.

[0061] S3: After repair, calculate the power consumption and area of ​​the digital circuit. If the power consumption is greater than the power consumption requirement value P of the digital circuit... max Or the area is greater than the required area value A max Then, for a time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin, thereby reducing the power consumption of the digital circuit to P. max The following describes how to reduce the area of ​​a digital circuit to A. max The following section determines whether the power consumption of the digital circuit has been reduced to P after adjustment, based on the time margin S0', power consumption P0', area A0' before adjustment, and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA'. max Below, has the area been reduced to A? max Next, has the timing margin of the timing path decreased to S? max The following and in S min above;

[0062] Specifically, all three repair schemes have drawbacks that negatively impact chip power consumption and area. Therefore, after repairing the setup time violation, power consumption analysis and area analysis tools are needed to calculate the power consumption and area of ​​the digital circuit. Then, while ensuring the correct functioning of the digital circuit, the setup time margin S is adjusted to be less than the excess margin S0. max This prevents excessive setup time repair and reduces the power consumption and area of ​​digital circuits to meet the required specifications.

[0063] The analysis tools for calculating the power consumption and area of ​​digital circuits include, but are not limited to: Innovus, ICCompiler, PowerArtist, etc.

[0064] For time margin S greater than the surplus threshold S max The timing path adjustment includes the following three adjustment schemes, as detailed below:

[0065] Adjustment scheme a' is as follows: In the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock input, reducing T. clk2 This reduces Δ, decreases the settling time margin S, and improves power consumption and area; the time adjustment degree ΔS' of this adjustment scheme is -ΔS' a The power consumption adjustment level ΔP' is -ΔP' a The area adjustment degree ΔA' is -ΔA' a .

[0066] Adjustment scheme b' is as follows: In the data path of the digital circuit timing path, reduce the size of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area; the time adjustment degree ΔS' of this adjustment scheme is -ΔS'. b The power consumption adjustment level ΔP' is -ΔP' b The area adjustment degree ΔA' is -ΔA' b .

[0067] The size levels of the logic elements are divided into small size, standard size, large size, and maximum size; the area of ​​the small size is 0.5 to 0.8 times that of the standard size, the area of ​​the large size is 2 to 3 times that of the standard size, and the area of ​​the maximum size is 3 to 5 times that of the standard size.

[0068] Adjustment scheme c' is as follows: In the data path of the digital circuit timing path, increase the threshold voltage of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area; the time adjustment degree ΔS' of this adjustment scheme is -ΔS'. c The power consumption adjustment level ΔP' is -ΔP' c The area adjustment degree ΔA' is -ΔA' c .

[0069] The threshold voltage levels of the logic elements are divided into ultra-low threshold voltage, low threshold voltage, standard threshold voltage, and high threshold voltage. The ultra-low threshold voltage is 0.5 to 0.7 times the standard voltage, the low threshold voltage is 0.7 to 0.9 times the standard voltage, and the high threshold voltage is 1.1 to 1.5 times the standard voltage.

[0070] In S3, if the time margin S of all time-series paths is less than the surplus threshold S max If the power consumption or area still cannot meet the requirements, then the excess threshold S is lowered. max Then, further adjustments are made to ensure that power consumption and area meet the requirements.

[0071] In one embodiment, the excess threshold S max Decrease by one clock cycle to form a new surplus threshold S max Then, further adjustments are made to ensure that power consumption and area meet the requirements.

[0072] It is worth noting that during the adjustment of the setup time margin, each path requiring adjustment is iterated in the order of schemes a, b, c or a', b', c' until the time margin S or power consumption and area meet the required requirements. When adjusting paths with excessive setup time margins, if the time margin S of all timing paths is already less than the redundancy threshold S... max If the power consumption or area still cannot meet the requirements, then the excess threshold S is lowered. max Decrease by one clock cycle T to form a new surplus threshold S. max Then continue to cycle through schemes a', b', and c' in order to ensure that power consumption and area meet the requirements.

[0073] As can be seen from the above embodiments, before the adjustment begins, this application digitizes the degree of adjustment of each step of the adjustment scheme by querying the process library or conducting routine tests. This allows for quick determination of whether the time margin, power consumption, and area meet the requirements through addition and subtraction operations during the adjustment process. The adjustment can be stopped at any time based on the determination result, avoiding the need to re-simulate the time margin, power consumption, or area of ​​the digital circuit through simulation software for each adjustment step. This greatly saves adjustment time, improves adjustment efficiency, and enhances the predictability and controllability of the adjustment process.

[0074] By configuring the qualified threshold S min and surplus threshold S max This application categorizes timing paths into two types based on the size of the time margin for repair and adjustment. First, it addresses timing paths where the time margin S is less than the acceptable threshold S. min The abnormal paths are repaired to ensure the functional correctness of the digital circuits. Then, for cases where the time margin S is greater than the redundancy threshold S... max The path is adjusted to avoid wasting power consumption and area due to over-repair, thereby optimizing power consumption and area.

[0075] Furthermore, this application specifies each step of the adjustment scheme in detail, forming a coded adjustment process that facilitates automated adjustment via storage devices and processors, saving time and labor costs. Moreover, the adjustment degree of each step in the adjustment method is relatively small, effectively avoiding excessive setup time adjustments, reducing the possibility of repeated adjustments, and improving the accuracy and stability of the adjustment.

[0076] Example 1:

[0077] Please see Figure 3 , Figure 3 This is a flowchart illustrating the process of establishing a timing violation path for repair according to an embodiment of this application, wherein, firstly, a qualified threshold S for the time margin is configured. min Determine the time repair level ΔS for each repair scheme, and then extract the setup time margin S for all timing paths in the digital circuit.

[0078] Collection time margin S < S min Establishment time violation path S1~S n S1 to S2 in sequence n Repair will be carried out, and the specific repair plan is as follows: Figure 4 As shown. Taking path S1 as an example, the initial time margin S of path S1 is... 01 <S min The S1 path loop is repaired using schemes a, b, and c. First, a buffer is added between the clock source and the second register clock in the S1 path clock path to establish a time margin and repair it to S. 01 +ΔS a <S min Then, in the data path of path S1, increase the size of logic element U1 by one level to establish a time margin to repair it to S. 01 +ΔS a +ΔS b <S min Then, in the data path of path S1, the threshold voltage of logic element U1 is reduced by one level to establish a time margin for repair to S. 01 +ΔS a +ΔS b +ΔS c <S min .

[0079] The first round of repair for path S1 has been completed, but the setup time of S1 is still violated. Therefore, the next round of repair begins. A buffer is added between the clock source and the clock input of the second register. The size of logic element U2 is increased by one level, and the threshold voltage of logic element U2 is decreased by one level, completing the second round of repair for S1. If the setup time margin of S1 is S at this point... 01 +2ΔS a +2ΔSb +2ΔS c >S min Once the establishment time violation of path S1 is corrected, the process begins to correct the next violation path S2, ensuring its establishment time margin is greater than S1. min Similarly, repair all paths S1 to S2 that have creation time violations. n .

[0080] All illegal paths S1 to S n After the repair is completed, use a digital circuit power consumption and area analysis tool to calculate the power consumption and area of ​​the digital circuit. If the power consumption and area meet the requirements, the timing repair is complete.

[0081] Example 2:

[0082] Please see Figure 5 , Figure 5 This is a flowchart illustrating the process of adjusting the path with excessive time margin according to an embodiment of this application. First, a qualified threshold S for the time margin is configured. min and surplus threshold S max Determine the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA' for each adjustment scheme, and determine the power consumption requirement value P of the digital circuit. max Area requirement value A max Then, the setup time margin S of all timing paths in the digital circuit is extracted.

[0083] After repairing the setup time violation path according to the setup time violation repair scheme in Embodiment 1 of this application, the power consumption and area of ​​the digital circuit are calculated using a digital circuit power consumption and area analysis tool. If the power consumption is greater than P... max or area greater than A max Then the collection and establishment time margin S > S max The setup time margin is too large for path S1'~S n ', sequentially for S1' to S n Adjustments will be made, and the specific adjustment plan is as follows: Figure 6 As shown. Taking path S1' as an example, the initial time margin S of path S1' is... 01 >S max Adjustment schemes a', b', and c' for the S1' path loop are as follows: First, in the clock path of the S1' path, remove a buffer between the clock source and the second register clock input, establishing a time margin adjusted to S. 01 '-ΔS' a >S max The power consumption of the digital circuit is adjusted to P0'-ΔP' a >P max The area of ​​the digital circuit is adjusted to A0'-ΔA' a >Amax Then, in the data path of path S1', the size of logic element U1 is reduced by one level, and the setup time margin is adjusted to S. 01 '-ΔS' a -ΔS' b >S max The power consumption of the digital circuit is adjusted to P0'-ΔP' a -ΔP' b >P max The area of ​​the digital circuit is A0'-ΔA' a -ΔA' b >A max Then, in the data path of path S1', the threshold voltage of logic element U1 is increased by one level, and the setup time margin is adjusted to S. 01 '-ΔS' a -ΔS' b -ΔS' c >S max The power consumption of the digital circuit is adjusted to P0'-ΔP' a -ΔP' b -ΔP' c >P max The area of ​​the digital circuit is A0'-ΔA' a -ΔA' b -ΔA' c >A max .

[0084] The first round of adjustments to the S1' path has been completed, but the power consumption and area of ​​the digital circuit still do not meet the requirements. Therefore, the next round of adjustments to the S1' path begins until the setup time margin of the S1' path is less than S. max And > S min After completing the setup time margin adjustment for path S1', begin adjusting path S2' to ensure its setup time margin is less than S. max And > S min Similarly, adjust all paths S1' to S1' with excessively large time margins. n '.

[0085] In the above process, when the power consumption of the digital circuit is less than P max And the area is smaller than A max If the time margin for all paths S1' to S1' is too large, the adjustment process will end immediately. n 'The adjusted setup time margin is all < S max And > S min However, the power consumption and area of ​​digital circuits still do not meet the requirements, so the surplus threshold S is... max Reduce the clock cycle by one to create a new margin threshold, and repeat the above process until the power consumption and area of ​​the digital circuit meet the requirements.

[0086] Corresponding to the aforementioned embodiments of the adjustment method for establishing time margin, this application also provides embodiments of the adjustment device for establishing time margin.

[0087] Figure 7 This is a block diagram illustrating a time margin adjustment device according to an exemplary embodiment. (Refer to...) Figure 7 The device includes:

[0088] Extraction module 1 is used to extract the time margin S of all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T su In the formula, T is the clock period of the digital circuit, and Δ is the deviation between the clock source and the clock input terminals of the two registers, that is, the time T it takes for the clock source to reach the clock input terminal of the second register. clk2 Subtract the time T to reach the first register clock. clk1 T co T data These represent the maximum propagation delay and maximum logic delay of the timing path, respectively. su This refers to the establishment time of the time sequence path;

[0089] Repair module 2 is used to address situations where the time margin S is less than the acceptable threshold S. min The timing path is repaired to increase its time margin to the acceptable threshold S. min In the above, the time margin S0 before repair and the degree of time repair ΔS are used to determine whether the time margin of the timing path after repair reaches S. min above;

[0090] Adjustment module 3 is used to calculate the power consumption and area of ​​the digital circuit after repair. If the power consumption is greater than the power consumption requirement value P of the digital circuit, then... max Or the area is greater than the required area value A max Then, for a time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin, thereby reducing the power consumption of the digital circuit to P. max The following describes how to reduce the area of ​​a digital circuit to A. max The following section determines whether the power consumption of the digital circuit has been reduced to P after adjustment, based on the time margin S0', power consumption P0', area A0' before adjustment, and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA'. max Below, has the area been reduced to A? max Next, has the timing margin of the timing path decreased to S? max The following and in S min above;

[0091] Specifically, for time margin S less than the qualified threshold S min Repair the timing path, including:

[0092] Repair solution a is to add a buffer between the clock source and the second register clock input in the clock path of the digital circuit timing path, increasing T. clk2 This increases the deviation Δ between the clock source and the clock inputs of the two registers, thus increasing the setup time margin S;

[0093] Solution b is to increase the size of logic elements by one level in the data path of the digital circuit timing path. This increases the driving capability of the elements, reduces the element delay, and thus reduces T. data Increase the setup time margin S;

[0094] Solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T. data Increase the setup time margin S;

[0095] Specifically, for a time margin S greater than a surplus threshold S max The timing path needs to be adjusted, including:

[0096] Adjustment scheme a' is as follows: In the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock input, reducing T. clk2 This reduces Δ, decreases the settling time margin S, and improves power consumption and area;

[0097] Adjustment scheme b' is as follows: In the data path of the digital circuit timing path, reduce the size of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area;

[0098] Adjustment scheme c' is as follows: In the data path of the digital circuit timing path, increase the threshold voltage of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area.

[0099] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0100] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0101] Accordingly, this application also provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; and, when the one or more programs are executed by the one or more processors, causing the one or more processors to implement the setup time margin adjustment method as described above. Figure 8 The diagram shown is a hardware structure diagram of any data processing-capable device where a time margin adjustment device is provided in an embodiment of the present invention. Except for... Figure 8 In addition to the processor, memory, DMA controller, disk, and non-volatile memory shown, any data processing device in the embodiment may also include other hardware depending on the actual function of the data processing device, which will not be described in detail here.

[0102] Accordingly, this application also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the setup time margin adjustment method described above. The computer-readable storage medium can be an internal storage unit of any data-processing device as described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium can also be an external storage device, such as a plug-in hard disk, smart media card (SMC), SD card, flash card, etc., equipped on the device. Furthermore, the computer-readable storage medium can include both internal storage units of any data-processing device and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the data-processing device, and can also be used to temporarily store data that has been output or will be output.

[0103] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0104] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for adjusting time margin, characterized in that, include: S1: Extract the time margin S for all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T su In the formula, T is the clock period of the digital circuit, and Δ is the deviation between the clock source and the clock input terminals of the two registers, that is, the time T it takes for the clock source to reach the clock input terminal of the second register. clk2 Subtract the time T to reach the first register clock. clk1 T co T data These represent the maximum propagation delay and maximum logic delay of the timing path, respectively. su This refers to the establishment time of the time sequence path; S2: For situations where the time margin S is less than the acceptable threshold S min The timing path is repaired to increase its time margin to the acceptable threshold S. min In the above, the time margin S0 before repair and the degree of time repair ΔS are used to determine whether the time margin of the timing path after repair reaches S. min above; S3: After repair, calculate the power consumption and area of ​​the digital circuit. If the power consumption is greater than the power consumption requirement value P of the digital circuit... max Or the area is greater than the required area value A max Then, for a time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin, thereby reducing the power consumption of the digital circuit to P. max The following describes how to reduce the area of ​​a digital circuit to A. max The following section determines whether the power consumption of the digital circuit has been reduced to P after adjustment, based on the time margin S0', power consumption P0', area A0' before adjustment, and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA'. max Below, has the area been reduced to A? max Next, has the timing margin of the timing path decreased to S? max The following and in S min above; Specifically, for time margin S less than the qualified threshold S min Repair the timing path, including: Repair solution a is to add a buffer between the clock source and the second register clock input in the clock path of the digital circuit timing path, increasing T. clk2 This increases the deviation Δ between the clock source and the clock inputs of the two registers, thus increasing the setup time margin S; Solution b is to increase the size of logic elements by one level in the data path of the digital circuit timing path. This increases the driving capability of the elements, reduces the element delay, and thus reduces T. data Increase the setup time margin S; Solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T. data Increase the setup time margin S; Specifically, for a time margin S greater than a surplus threshold S max The timing path needs to be adjusted, including: Adjustment scheme a' is as follows: In the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock input, reducing T. clk2 This reduces Δ, decreases the settling time margin S, and improves power consumption and area; Adjustment scheme b' is as follows: In the data path of the digital circuit timing path, reduce the size of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area; Adjustment scheme c' is as follows: In the data path of the digital circuit timing path, increase the threshold voltage of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area.

2. The adjustment method according to claim 1, characterized in that, The tool used to extract the timing margin of all timing paths in a digital circuit is PrimeTime and Design Compiler.

3. The adjustment method according to claim 1, characterized in that, The size levels of the logic elements are divided into small size, standard size, large size, and maximum size; the area of ​​the small size is 0.5 to 0.8 times that of the standard size, the area of ​​the large size is 2 to 3 times that of the standard size, and the area of ​​the maximum size is 3 to 5 times that of the standard size.

4. The adjustment method according to claim 1, characterized in that, The threshold voltage levels of the logic elements are divided into ultra-low threshold voltage, low threshold voltage, standard threshold voltage, and high threshold voltage. The ultra-low threshold voltage is 0.5 to 0.7 times the standard voltage, the low threshold voltage is 0.7 to 0.9 times the standard voltage, and the high threshold voltage is 1.1 to 1.5 times the standard voltage.

5. The adjustment method according to claim 1, characterized in that, In S3, if the time margin S of all time-series paths is less than the surplus threshold S max If the power consumption or area still cannot meet the requirements, then the excess threshold S is lowered. max Then, further adjustments are made to ensure that power consumption and area meet the requirements.

6. The adjustment method according to claim 5, characterized in that, For the surplus threshold S max Decrease by one clock cycle to form a new surplus threshold S max Then, further adjustments are made to ensure that power consumption and area meet the requirements.

7. The adjustment method according to claim 1, characterized in that, The analysis tools for calculating the power consumption and area of ​​the digital circuits are selected from Innovus, IC Compiler, and PowerArtist.

8. A device for establishing a time margin, characterized in that, include: The extraction module is used to extract the time margin S of all timing paths in a digital circuit, where S = T + Δ - (T co +T data )-T su In the formula, T is the clock period of the digital circuit, and Δ is the deviation between the clock source and the clock input terminals of the two registers, that is, the time T it takes for the clock source to reach the clock input terminal of the second register. clk2 Subtract the time T to reach the first register clock. clk1 T co T data These represent the maximum propagation delay and maximum logic delay of the timing path, respectively. su This refers to the establishment time of the time sequence path; The repair module is used to address situations where the time margin S is less than the acceptable threshold S. min The timing path is repaired to increase its time margin to the acceptable threshold S. min In the above, the time margin S0 before repair and the degree of time repair ΔS are used to determine whether the time margin of the timing path after repair reaches S. min above; The adjustment module is used to calculate the power consumption and area of ​​the digital circuit after repair. If the power consumption is greater than the power consumption requirement value P of the digital circuit, the adjustment module will adjust the power consumption accordingly. max Or the area is greater than the required area value A max Then, for a time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin, thereby reducing the power consumption of the digital circuit to P. max The following describes how to reduce the area of ​​a digital circuit to A. max The following section determines whether the power consumption of the digital circuit has been reduced to P after adjustment, based on the time margin S0', power consumption P0', area A0' before adjustment, and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA'. max Below, has the area been reduced to A? max Next, has the timing margin of the timing path decreased to S? max The following and in S min above; Specifically, for time margin S less than the qualified threshold S min Repair the timing path, including: Repair solution a is to add a buffer between the clock source and the second register clock input in the clock path of the digital circuit timing path, increasing T. clk2 This increases the deviation Δ between the clock source and the clock inputs of the two registers, thus increasing the setup time margin S; Solution b is to increase the size of logic elements by one level in the data path of the digital circuit timing path. This increases the driving capability of the elements, reduces the element delay, and thus reduces T. data Increase the setup time margin S; Solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T. data Increase the setup time margin S; Specifically, for a time margin S greater than a surplus threshold S max The timing path needs to be adjusted, including: Adjustment scheme a' is as follows: In the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock input, reducing T. clk2 This reduces Δ, decreases the settling time margin S, and improves power consumption and area; Adjustment scheme b' is as follows: In the data path of the digital circuit timing path, reduce the size of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area; Adjustment scheme c' is as follows: In the data path of the digital circuit timing path, increase the threshold voltage of the logic element by one level, thereby increasing T. data This reduces the setup time margin S, improving power consumption and area.

9. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-7.

10. A computer-readable storage medium storing computer instructions thereon, characterized in that, When executed by the processor, this instruction implements the steps of the method as described in any one of claims 1-7.

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