Computing system and integrated circuit design system using same

Abstract

A computing system and an integrated circuit design system using the same are provided. The integrated circuit design system using a computing system includes: a processor; and a memory configured to store instructions that allow the processor to perform a method of designing an integrated circuit, the integrated circuit including a substrate, a front-end-of-line (FEOL) in at least a portion of the substrate and on the substrate, and a back-end-of-line (BEOL) formed on the FEOL, a method of designing an integrated circuit includes: selecting a first metal layer included in a BEOL and disposed at a first level from a substrate; generating a first barrier layer surrounding the first metal layer disposed at the first level; generating at least one first upper barrier layer disposed at a level higher than the first level from the substrate; and generating at least one first lower barrier layer disposed at a level lower than the first level from the substrate.

Description

[0001] This application claims priority and all benefits arising from Korean Patent Application No. 10-2023-0078022 filed in the Korean Intellectual Property Office on June 19, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a computing system and an integrated circuit design system using the computing system. Background Art

[0003] For the development of semiconductor chip technology, fine processes have been developed. In addition, the width between metal layers of integrated circuits (ICs) has been continuously reduced to increase the integration of integrated circuits and reduce the size of chips. In particular, dummy patterns can be added between metal layers to which electrical signals are actually routed to prevent dishing that occurs during a chemical mechanical polishing (CMP) process. In this case, parasitic capacitance can increase between the metal layer and the dummy pattern, resulting in performance loss of the integrated circuit. Summary of the invention

[0004] An object of the present disclosure is to provide an integrated circuit design system using a computing system with improved reliability.

[0005] Another object of the present disclosure is to provide a computing system with improved reliability.

[0006] The objects of the present disclosure are not limited to the above-mentioned objects, and additional objects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0007] According to one aspect of the present disclosure, an integrated circuit design system using a computing system is provided, the integrated circuit design system comprising: a memory configured to store instructions; and a processor configured to execute the instructions to enable the integrated circuit design system to design an integrated circuit, wherein the integrated circuit comprises a substrate, a front-end process (FEOL) in at least a portion of and on the substrate, and a back-end process (BEOL) formed on the FEOL, and wherein, when the processor executes the instructions to enable the integrated circuit design system to design the integrated circuit, the processor is configured to: select a first metal layer included in the BEOL and disposed at a first level from the substrate; generate a first barrier layer disposed at the first level and surrounding the first metal layer; generate at least one first upper barrier layer disposed at a level higher than the first level from the substrate; and generate at least one first lower barrier layer disposed at a level lower than the first level from the substrate.

[0008] According to one aspect of the present disclosure, an integrated circuit design system using a computing system is provided, the integrated circuit design system comprising: a memory configured to store instructions; and a processor configured to execute the instructions to enable the integrated circuit design system to design an integrated circuit, wherein the integrated circuit comprises a substrate, a front end process (FEOL) in at least a portion of and on the substrate, a back end process (BEOL) formed on the FEOL, and a passive element formed in the BEOL, wherein the passive element comprises a first metal layer and a second metal layer; the first metal layer is included in the BEOL and is disposed at a first level from the substrate; the second metal layer is included in the BEOL, is disposed at a second level higher than the first level from the substrate, and is connected to the first metal layer through a via, and wherein, when the processor executes the instructions to enable the integrated circuit design system to design the integrated circuit, the processor is configured to: select the first metal layer; generate a first barrier layer surrounding the first metal layer disposed at the first level; generate a second barrier layer surrounding the second metal layer disposed at the second level; generate at least one upper barrier layer disposed at a level higher than the second level from the substrate; and generate at least one lower barrier layer disposed at a level lower than the first level from the substrate.

[0009] According to one aspect of the present disclosure, a computing system is provided, the computing system comprising: a memory configured to store instructions; and a processor configured to execute the instructions so that the computing system designs an integrated circuit, wherein the integrated circuit comprises a substrate, a front-end process (FEOL) formed in at least a portion of the substrate and on the substrate, and a back-end process (BEOL) formed on the FEOL, wherein when the processor executes the instructions so that the computing system designs the integrated circuit, the processor is configured to: select a first metal layer included in the BEOL and disposed at a first level away from the substrate; generate a first barrier layer disposed at the first level and surrounding the first metal layer; generate at least one first upper barrier disposed at a level higher than the first level from the substrate; a barrier layer; generating at least one first lower barrier layer disposed at a level lower than the first level from the substrate; selecting a passive element, the passive element comprising a second metal layer and a third metal layer, the second metal layer being included in the BEOL, disposed at the first level from the substrate and not overlapping with the first metal layer, the third metal layer being included in the BEOL, disposed at a second level higher than the first level from the substrate and connected to the second metal layer through a via; generating a second barrier layer disposed at the first level and surrounding the second metal layer; generating a third barrier layer disposed at the second level and surrounding the third metal layer; generating at least one second upper barrier layer disposed at a level higher than the second level from the substrate; and generating at least one second lower barrier layer disposed at a level lower than the first level from the substrate.

[0010] According to one aspect of the present disclosure, a method for designing an integrated circuit is provided, the integrated circuit including a substrate, a front-end process (FEOL) in at least a portion of and on the substrate, and a back-end process (BEOL) formed on the FEOL, the method including: selecting a first metal layer included in the BEOL and disposed at a first level from the substrate; generating a first barrier layer surrounding the first metal layer disposed at the first level; generating at least one first upper barrier layer disposed at a level higher than the first level from the substrate; and generating at least one first lower barrier layer disposed at a level lower than the first level from the substrate.

[0011] According to one aspect of the present disclosure, a method for designing an integrated circuit is provided, the integrated circuit including a substrate, a front-end process (FEOL) in at least a portion of and on the substrate, a back-end process (BEOL) formed on the FEOL, and passive components formed in the BEOL, the method including: selecting a first metal layer, the first metal layer included in the BEOL and disposed at a first level from the substrate; generating a first barrier layer disposed at the first level and surrounding the first metal layer; generating a second barrier layer disposed at a second level and surrounding the second metal layer, the second metal layer included in the BEOL, disposed at a second level higher than the first level from the substrate, and connected to the first metal layer through a via; generating at least one upper barrier layer disposed at a level higher than the second level from the substrate; and generating at least one lower barrier layer disposed at a level lower than the first level from the substrate.

[0012] According to one aspect of the present disclosure, a method for designing an integrated circuit is provided, the integrated circuit comprising a substrate, a front-end process (FEOL) formed in at least a portion of the substrate and on the substrate, and a back-end process (BEOL) formed on the FEOL, the method comprising: selecting a first metal layer included in the BEOL and disposed at a first level from the substrate; generating a first barrier layer surrounding the first metal layer disposed at the first level; generating at least one first upper barrier layer disposed at a level higher than the first level from the substrate; generating at least one first lower barrier layer disposed at a level lower than the first level from the substrate; selecting a passive component, The passive component includes a second metal layer and a third metal layer, the second metal layer is included in the BEOL, is disposed at a first level from the substrate and does not overlap with the first metal layer, the third metal layer is included in the BEOL, is disposed at a second level higher than the first level from the substrate and is connected to the second metal layer through a via; a second barrier layer is generated around the second metal layer at the first level; a third barrier layer is generated around the third metal layer at the second level; at least one second upper barrier layer is generated at a level higher than the second level from the substrate; and at least one second lower barrier layer is generated at a level lower than the first level from the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0014] Figure 1 is an exemplary diagram illustrating an integrated circuit design system using a computing system according to example embodiments.

[0015] Figure 2 and Figure 3 is a diagram showing how to use Figure 1 An exemplary flow chart of a method for designing an integrated circuit by a design system.

[0016] Figures 4 to 16 is a diagram showing how to use Figure 1 An exemplary diagram of a method for designing an integrated circuit by a design system.

[0017] Figures 17 to 19 is a diagram showing how to use Figure 1 An exemplary diagram of a method for designing an integrated circuit by a design system.

[0018] Figure 20 to Figure 22 is an exemplary diagram illustrating effects of an integrated circuit manufactured according to example embodiments.

[0019] Fig.23 is an exemplary flow chart illustrating a method of manufacturing an integrated circuit according to example embodiments.

[0020] Fig.24 It is shown that including Fig.23 An exemplary schematic diagram of a semiconductor device of a fabricated integrated circuit.

[0021] Fig.25 It shows that according to Fig.23 An exemplary block diagram of a fabricated integrated circuit. DETAILED DESCRIPTION

[0022] Hereinafter, a computing system and an integrated circuit design system using the same according to some embodiments will be described with reference to the accompanying drawings. Like reference numerals denote like elements throughout.

[0023] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as " / ".

[0024] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. Unless otherwise indicated by the context, these terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part (for example, as a naming convention). Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below in one part of the specification may be referred to as the second element, component, region, layer or part in another part of the specification or in the claims. In addition, in certain cases, even if "first", "second", etc. are not used to describe the term in the specification, the term may still be referred to as "first" or "second" in the claims to distinguish different elements claimed for protection from each other.

[0025] Figure 1 is an exemplary diagram illustrating an integrated circuit design system using a computing system according to example embodiments.

[0026] Reference Figure 1 The integrated circuit design system 100 using a computing system may be a stationary computing system such as a desktop computer, a workstation, and a server, or may be a portable computing system such as a laptop computer. Hereinafter, the integrated circuit design system 100 using a computing system will be referred to as the design system 100.

[0027] Integrated circuits (ICs) according to some embodiments may be designed and manufactured using the design system 100. For example, the design system 100 may be used to generate a layout and physical design of an integrated circuit, and then the integrated circuit may be manufactured based on the generated layout and physical design of the integrated circuit. Fig.23 Methods of manufacturing integrated circuits based on their layout and physical design are described.

[0028] The design system 100 may include a processor 101, a memory 102, a storage device (or storage apparatus) 103, an input / output (I / O) device 104, and a network interface 105. The processor 101, the memory 102, the storage device 103, the input / output device 104, and the network interface 105 may be connected to a bus 106, and may perform communication with each other via the bus 106.

[0029] Processor 101 may be referred to as a processing unit and may include at least one core (e.g., a microprocessor, an application processor (AP), a digital signal processor (DSP), and a graphics processor (GPU)) capable of executing any instruction set (e.g., IA-32 (Intel Architecture-32), 64-bit extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). Processor 101 may access memory 102 via bus 106 and may execute instructions 102A stored in memory 102. When instructions 102A are executed by processor 101, instructions 102A may allow processor 101 to design the layout and physical design of an integrated circuit. Instructions 102A may represent a single instruction and / or multiple instructions.

[0030] The memory 102 may store instructions 102A or at least a portion of the instructions 102A for manufacturing an integrated circuit according to some embodiments. The instructions 102A may include a plurality of instruction languages ​​that can be executed by the processor 101. The instructions 102A may allow the processor 101 to perform at least a portion of the steps included in the method of designing and manufacturing an integrated circuit.

[0031] Even if the power supplied to the design system 100 is cut off, the storage device 103 may not lose the stored data. For example, the storage device 103 may include a non-volatile integrated circuit, or may include a storage medium such as a tape, an optical disk, and / or a magnetic disk. In addition, the storage device 103 may be detachable from the design system 100.

[0032] The storage device 103 may store the instruction 102A, and may load the instruction 102A or at least a portion of the instruction 102A from the storage device 103 into the memory 102 before the instruction 102A is executed by the processor 101. In another embodiment, the storage device 103 may store a file written in a program language, and may load the instruction 102A or at least a portion of the instruction 102A generated from the file by a compiler or the like into the memory 102. In addition, the storage device 103 may store a database (DB) 103A, and the database 103A may include information (e.g., a cell library) required for designing an integrated circuit.

[0033] The storage device 103 may store data to be processed by the processor 101 or data processed by the processor 101. For example, the processor 101 may generate new data by processing the data stored in the storage device 103 according to the instruction 102A, and may store the newly generated data in the storage device 103. For example, the storage device 103 may store register transfer level (RTL) data, a netlist, and / or a layout.

[0034] The input / output device 104 may include an input device (such as a keyboard, a pointing device, etc.), and may include an output device (such as a display device, a printer, etc.). For example, through the input / output device 104, a user (such as a designer of a semiconductor integrated circuit) may trigger the execution of the instruction 102A by the processor 101, input RTL data and / or a netlist, or confirm a layout.

[0035] The network interface 105 may provide access to a network external to the design system 100. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, and / or any other type of links.

[0036] Figure 2 and Figure 3 is shown by using Figure 1 An exemplary flow chart of a method for designing an integrated circuit by a design system. Figures 4 to 16 is shown by using Figure 1 An exemplary diagram of a method for designing an integrated circuit by a design system of Figures 2 to 16 A method for designing an integrated circuit by using a computing system according to an example embodiment is described. When instruction 102A is executed by processor 101, Figure 1 A method of designing an integrated circuit according to an example embodiment, which will be described below, is performed in the design system 100 of the integrated circuit.

[0037] First, let’s refer to Figure 2 and Figure 4 , a layout of an integrated circuit can be provided (S100).

[0038] Figure 4 is a diagram exemplarily showing a layout of the provided integrated circuit 1000, and Figure 5 It is shown exemplarily Figure 4 Schematic diagram of the front-end of line (FEOL) process of an integrated circuit. Figure 6 and Figure 7 It is shown Figure 4 Schematic diagram of the stacking structure of the integrated circuit 1000. Figure 6 and Figure 7 , for ease of description, the transistor TR included in the integrated circuit 1000 is omitted, and sizes of the gate electrode GT, source / drain contacts CA, gate vias CB, landing vias LA, metal layers M1 to M4, and vias V1 to V3 are arbitrarily shown. Figure 6 and Figure 7 may be different from the actual cross-sectional view of the integrated circuit 1000. Figures 4 to 7 An integrated circuit 1000 according to an example embodiment is described.

[0039] The integrated circuit 1000 may include a substrate (SUB) 200, a front end process (FEOL) and a back end process (BEOL). The substrate 200 may be disposed on a plane defined by a first direction X and a second direction Y. The substrate 200 may be a silicon substrate or a silicon on insulator (SOI) substrate. Alternatively, the substrate 200 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. The substrate 200 may be implemented as a P-type substrate or an N-type substrate according to an embodiment, but is not limited thereto.

[0040] The FEOL may be formed in and on at least a portion of the substrate 200. The FEOL may include an active region RX, source / drain (S / D) regions, a gate electrode GT, a gate via CB, source / drain contacts CA, and a landing via LA.

[0041] The active region RX may be formed inside the substrate 200. The active region RX may be a portion of the substrate 200 (e.g., formed by etching the substrate 200), or may be formed on the substrate 200 (e.g., may be an epitaxial layer grown from the substrate 200). In example embodiments, an upper surface of the active region RX may be coplanar with an upper surface of the substrate 200. The active region RX may be formed to extend in a first direction X and a second direction Y. The active region RX may include a plurality of impurity regions (e.g., a P-type impurity region (p+) and / or an N-type impurity region (n+)), and the plurality of impurity regions may include an S / D region. At least one transistor TR may be defined by the impurity region.

[0042] Each of the transistors TR may be arranged to extend longitudinally (or "longitudinally") along the first direction X. In some embodiments, the transistor TR may include, but is not limited to, a fin field effect transistor (FinFET), a tunneling field effect transistor (tunneling FET), a three-dimensional (3D) transistor or a vertical field effect transistor (vertical FET), a planar transistor, a field effect transistor (FET) based on a two-dimensional (2D) material and its heterostructure, a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, a transistor including a nanowire or a nanosheet, or a multi-bridge channel field effect transistor (MBCFET). TM ).

[0043] The gate electrode GT of the transistor TR may be disposed to extend longitudinally along the second direction Y on the substrate, and a plurality of gate electrodes GT may be disposed to be spaced apart from each other in the first direction X. A gate via CB may be disposed to extend along the third direction Z on the gate electrode GT. The gate via CB may contact the gate electrode GT. The gate via CB may connect the gate electrode GT to the BEOL.

[0044] The source / drain contact CA may be arranged to extend longitudinally along the second direction Y between the gate electrodes GT. A plurality of source / drain contacts CA may be arranged to be spaced apart from each other in the first direction X. In this way, the source / drain contact CA may extend longitudinally along the second direction Y to contact a plurality of S / D regions arranged between the gate electrodes GT. A bonding via LA may be arranged to extend along a third direction Z on the source / drain contact CA. The bonding via LA may contact the source / drain contact CA. The bonding via LA may connect the source / drain contact CA to the BEOL.

[0045] The BEOL may include a plurality of metal layers M1, M2, M3, and M4 and a plurality of vias V1, V2, and V3 connecting the plurality of metal layers M1, M2, M3, and M4. The plurality of metal layers M1, M2, M3, and M4 and the plurality of vias V1, V2, and V3 may be metal lines that transmit electrical signals to the transistor TR and may include a conductive material such as, for example, a metal such as Cu, Ag, Au, Al, or W, but is not limited thereto. Although the integrated circuit 1000 is Figure 4 , Figure 6 and Figure 7 1000 is shown as including four metal layers M1, M2, M3, and M4, but the number of metal layers included in the BEOL is not limited thereto. The number of metal layers included in the BEOL of the integrated circuit 1000 may be less than or greater than four.

[0046] A plurality of metal layers M1, M2, M3, and M4 may be sequentially stacked from the substrate 200 in the third direction Z. Hereinafter, the position at which each of the metal layers M1, M2, M3, and M4 is disposed from the substrate 200 along the third direction Z will be defined as a level. For example, a position at which the metal layer M1 is disposed may be level LV1, a position at which the metal layer M2 is disposed may be level LV2, a position at which the metal layer M3 is disposed may be level LV3, and a position at which the metal layer M4 is disposed may be level LV4. In addition, a position at which any metal layer Mx is disposed may be level LVx (x is an integer greater than or equal to 1).

[0047] A portion of the metal layer M1 may be disposed to extend along the first direction X. The metal layer M1 extending along the first direction X may combine some of the plurality of gate electrodes GT into one, and may be partially disconnected, but is not limited thereto. Another portion of the metal layer M1 may be disposed to extend along the second direction Y on the active region RX so that it will be connected to the bonding via LA. A portion of the metal layer M1 may be connected to the gate electrode GT through the gate via CB, and another portion of the metal layer M1 may be connected to the source / drain contact CA through the bonding via LA. For example, the lower surface of the metal layer M1 may contact the upper surface of the gate via CB and the upper surface of the bonding via LA.

[0048] The metal layer M2 may be arranged to extend along the second direction Y. A portion of the metal layer M2 may be arranged to extend along the second direction Y and may be connected to the metal layer M1 connected to the gate via CB through the via V1. Another portion of the metal layer M2 may be connected to the metal layer M1 connected to the bonding via LA through the via V1. For example, the lower surface of the metal layer M2 may contact the upper surface of the via V1.

[0049] The metal layer M3 may be arranged to extend along the second direction Y, and may be connected to the metal layer M2 through the via V2. For example, the lower surface of the metal layer M3 may contact the upper surface of the via V2, and the lower surface of the via V2 may contact the upper surface of the metal layer M2. A portion of the metal layer M3 may be connected to the gate electrode GT, and another portion of the metal layer M3 may be connected to the source / drain contact CA.

[0050] The metal layer M4 may be arranged to extend along the first direction X, and may be connected to the metal layer M3 through the via V3. For example, the lower surface of the metal layer M4 may contact the upper surface of the via V3, and the lower surface of the via V3 may contact the upper surface of the metal layer M3. A portion of the metal layer M4 may be connected to the gate electrode GT, and another portion of the metal layer M4 may be connected to the source / drain contact CA. The metal layer M4 may include a power rail that transmits any one of the power supply voltage (or driving voltage) VDD and the ground voltage VSS to the transistor TR.

[0051] at the same time, Figure 4 Examples of integrated circuits are shown, and the construction and arrangement of the FEOL and BEOL of the integrated circuit according to some embodiments may vary according to the embodiment.

[0052] Reference Figure 6 and Figure 7 , the gate electrode GT, the gate via CB, the source / drain contact CA, and the bonding via LA may be formed in the first layer F1. The sum of the heights of the gate electrode GT and the gate via CB may be equal to the sum of the heights of the source / drain contact CA and the bonding via LA. The active region RX and the S / D region of the substrate 200 and the first layer F1 on the substrate 200 may be formed by a FEOL process, and the second layer F2 to the eighth layer F8 may be formed by a BEOL process. In addition, the contact area may decrease from the second layer F2 toward the eighth layer F8. The second layer F2 on which the metal layer M1 is disposed may correspond to the level LV1, the fourth layer F4 on which the metal layer M2 is disposed may correspond to the level LV2, the sixth layer F6 on which the metal layer M3 is disposed may correspond to the level LV3, and the eighth layer F8 on which the metal layer M4 is disposed may correspond to the level LV4. The via V1 may be disposed in the third layer F3 , the via V2 may be disposed in the fifth layer F5 , and the via V3 may be disposed in the seventh layer F7 .

[0053] like Figure 6 As shown in FIG. 1 , the portion of the metal layers M1 to M4 that transmits the electrical signal to the gate electrode GT may be disconnected from the portion of the metal layers M1 to M4 that transmits the electrical signal to the S / D region, but the embodiment is not limited thereto. Figure 7 As shown in the figure, metal layers M2, M3 and M4 can be connected as one, so that the electrical signal to be transmitted to the gate electrode GT and the source / drain (S / D) region can be sent simultaneously through the metal layer M4, the via V3, the metal layer M3, the via V2 and the metal layer M2.

[0054] Return to reference Figure 2 , a net may be selected from a provided layout of an integrated circuit (S101). For example, in the provided layout of an integrated circuit, a net having an increased requirement for preventing performance degradation due to RC (resistance-capacitance) delay may be selected from the provided layout of an integrated circuit. For example, a net may be selected Figure 4 OUTA and OUTB are shown as nets. Figure 2 and Figure 8 , a metal layer for a selected net may be extracted (S102). The metal layer for the selected net may include at least one of metal layers M1, M2, M3, and M4 constituting BEOL included in the integrated circuit 1000. For example, when OUTA and OUTB are selected as nets from the layout of the integrated circuit 1000, the metal layers M1, M2, M3, and M4 connected to OUTA and OUTB may be extracted from the netlist.

[0055] In some embodiments, a schematic diagram of the integrated circuit may be provided first before providing a layout of the integrated circuit. In this case, a specific net among the input nets of the integrated circuit may be selected from the schematic diagram of the integrated circuit. Thereafter, a layout of the integrated circuit may be provided, and a metal layer for the pre-selected specific net may be extracted.

[0056] Any metal layer Mx included in the BEOL of the integrated circuit 1000 and disposed at a specific level from the substrate 200 along the third direction Z may be selected through steps S100, S101, and S102. For example, the metal layer Mx may be Figure 8 In the following, it is assumed that an arbitrary metal layer Mx disposed at a level LVx from the substrate 200 is selected, but the description of the metal layer Mx is equally applicable to any metal layer Mx disposed at a level LVx from the substrate 200. Figure 8 All metal layers M1, M2, M3 and M4 used in the selected mesh shown in FIG.

[0057] Return to reference Figure 2 , a blocking layer disposed at the same level from the substrate 200 relative to the selected metal layer and surrounding the selected metal layer may be generated (S103). Figure 2 Refer to Fig. 9 , Fig. 9 2 is a diagram exemplarily showing a case where a barrier layer Mx_BL is generated at the same level as the metal layer Mx when there is no metal layer disposed adjacent to the same level as the metal layer Mx. Fig. 9 As shown in , when the metal layer Mx has a polygonal shape, the barrier layer Mx_BL may be generated to surround the metal layer Mx while having a predetermined interval L1 with the metal layer Mx. For example, the barrier layer Mx_BL may have the same polygonal shape as the metal layer Mx.

[0058] The interval L1 between the metal layer Mx and the barrier layer Mx_BL may be constantly formed according to a default value based on the type of the metal layer Mx. The interval L1 between the metal layer Mx and the barrier layer Mx_BL may be determined by a metal max space design rule according to the type of the metal layer Mx. When designing an integrated circuit, the metal max space design rule is determined by a maximum interval between metal patterns (e.g., metal layers and / or dummy patterns) included in the BEOL.

[0059] For example, when a dummy pattern to which an electrical signal is not actually routed is generated near a metal layer Mx to which an electrical signal is actually routed, since both the metal layer Mx and the dummy pattern include metal, the dummy pattern should be able to be generated near the metal layer Mx in consideration of a metal maximum space design rule. At this time, the maximum interval between the metal layer Mx and the dummy pattern may be determined by the design rule according to the type of the metal layer Mx.

[0060] The interval L1 between the metal layer Mx and the barrier layer Mx_BL may correspond to half of the maximum metal space of the corresponding metal layer Mx. For example, when the metal layer Mx is a metal layer disposed at a relatively low level from the substrate 200, the interval L1 between the metal layer Mx and the barrier layer Mx_BL may be, for example, 0.2 μm. Alternatively, when the metal layer Mx is a metal layer disposed at a relatively high level from the substrate 200, the interval L1 between the metal layer Mx and the barrier layer Mx_BL may be, for example, 0.6 μm. However, the interval L1 between the metal layer Mx and the barrier layer Mx_BL is not limited to the numerical value.

[0061] Reference Fig.10 ,and Fig. 9Differently, when there is a metal layer Mxa disposed adjacently at the same level LVx as the metal layer Mx from the substrate 200, barrier layers Mx_BL and Mxa_BL may be generated with respect to the metal layers Mx and Mxa, respectively. In this case, the barrier layer Mxa_BL of the metal layer Mxa may also be generated to surround the metal layer Mxa at the same level LVx as the metal layer Mxa while having a predetermined interval L1 with the metal layer Mxa according to the metal maximum space design rule.

[0062] In addition, the barrier layers Mx_BL and Mxa_BL generated adjacent to each other may be generated with a minimum interval L2 for inserting a dummy pattern D generated later between the barrier layers Mx_BL and Mxa_BL. For example, the minimum interval L2 for inserting the dummy pattern D between the barrier layers Mx_BL and Mxa_BL may be the sum of the minimum width L3 of the dummy pattern D, the minimum interval L4 from the dummy pattern D to the barrier layer Mx_BL, and the minimum interval L4 from the dummy pattern D to the barrier layer Mxa_BL. For example, when the minimum width L3 of the dummy pattern D is 0.08 μm and the minimum interval L4 from the dummy pattern D to each of the barrier layers Mx_BL and Mxa_BL is 0.22 μm, the minimum interval L2 between the barrier layers Mx_BL and Mxa_BL may be 0.52 μm, but is not limited thereto.

[0063] Return to reference Figure 2 , an upper barrier layer and a lower barrier layer may be generated relative to the selected metal layer (S104). Figures 11 to 13 A method of generating upper barrier layers Mx+1_BL and Mx+2_BL and lower barrier layers Mx-1_BL and Mx-2_BL with respect to metal layers Mxb, Mxc, Mxd, and Mxe is described.

[0064] First, refer to Fig.11 , all metal layers Mxb, Mxc, Mxd and Mxe may be metal layers disposed at the same level from the substrate 200. For example, the metal layers Mxb, Mxc, Mxd and Mxe may all be disposed at a level LVx from the substrate 200. The widths of the metal layers Mxb, Mxc, Mxd and Mxe disposed at the same level may be different from each other. For example, the widths of the metal layers Mxb and Mxc in the first direction X may be T4, and the width of the metal layer Mxd in the first direction X may be T3 which is larger than T4. The metal layer Mxe may be in the form of a polygon in which elements extending longitudinally in the first direction X and elements extending longitudinally in the second direction Y are combined with each other. The width of the elements of the metal layer Mxe extending longitudinally in the first direction X in the second direction Y may be T1, and the width of the elements of the metal layer Mxe extending longitudinally in the second direction Y in the first direction X may be T2 which is smaller than T1.

[0065] Hereinafter, the case where upper barrier layers Mx+1_BL and Mx+2_BL and lower barrier layers Mx-1_BL and Mx-2_BL are generated relative to the metal layer Mxb will be described as an example, but the upper barrier layers Mx+1_BL and Mx+2_BL and lower barrier layers Mx-1_BL and Mx-2_BL can be generated in the same manner relative to other metal layers Mxc, Mxd and Mxe set at the same level as the metal layer Mxb.

[0066] The upper barrier layer Mx+1_BL may be generated at a level LVx+1 one level higher than the level LVx from the substrate 200 relative to the metal layer Mxb disposed at the level LVx from the substrate 200. In addition, the upper barrier layer Mx+2_BL may be generated at a level LVx+2 two levels higher than the level LVx from the substrate 200 relative to the metal layer Mxb.

[0067] Similarly, a lower barrier layer Mx-1_BL may be generated at level LVx-1 one level lower than level LVx from substrate 200 relative to metal layer Mxb. In addition, a lower barrier layer Mx-2_BL may be generated at level LVx-2 two levels lower than level LVx from substrate 200 relative to metal layer Mxb.

[0068] In this manner, the lower barrier layer Mx-2_BL, the lower barrier layer Mx-1_BL, the upper barrier layer Mx+1_BL, and the upper barrier layer Mx+2_BL of the metal layer Mxb may be respectively disposed at different levels from the substrate 200 in the third direction Z.

[0069] Fig.11 It is shown that two upper barrier layers Mx+1_BL and Mx+2_BL are generated at the upper level of the metal layers Mxb, Mxc, Mxd, and Mxe, and two lower barrier layers Mx-1_BL and Mx-2_BL are generated at the lower level of the metal layers Mxb, Mxc, Mxd, and Mxe, but the embodiment is not limited thereto. For example, in some embodiments, one upper barrier layer or three or more upper barrier layers may be generated at the high level of the metal layers Mxb, Mxc, Mxd, and Mxe. Alternatively or additionally, one lower barrier layer or three or more lower barrier layers may be generated at the lower level of the metal layers Mxb, Mxc, Mxd, and Mxe.

[0070] For example, when the metal layers Mxb, Mxc, Mxd, and Mxe are disposed at a relatively low level from the substrate 200, sufficient space for generating a dummy pattern may not be formed at a level LVx-2 two levels lower than the level LVx at which the metal layers Mxb, Mxc, Mxd, and Mxe are disposed. In this case, the lower barrier layer of the metal layers Mxb, Mxc, Mxd, and Mxe may be generated only at a level LVx-1 one level lower than the level LVx at which the metal layers Mxb, Mxc, Mxd, and Mxe are disposed.

[0071] The upper barrier layers Mx+1_BL and Mx+2_BL and the lower barrier layers Mx-1_BL and Mx-2_BL may be generated along the shape of each of the metal layers Mxb, Mxc, Mxd, and Mxe. In this case, the width L5 of the upper barrier layers Mx+1_BL and Mx+2_BL and the lower barrier layers Mx-1_BL and Mx-2_BL may be determined according to the metal maximum space design rule. For example, Fig.11 As shown in, when the corresponding widths T4, T4, T3 and T2 of the metal layers Mxb, Mxc, Mxd and Mxe are different from each other, the width L5 of the upper barrier layers Mx+1_BL and Mx+2_BL and the width L5 of the lower barrier layers Mx-1_BL and Mx-2_BL can be generated as the maximum width of the space remaining after subtracting the minimum space used to generate the dummy pattern.

[0072] Hereinafter, a case where an upper barrier layer Mx+1_BL of metal layers Mxb, Mxc, Mxd, and Mxe is generated at a level LVx+1 from the substrate 200 will be described as an example. The description can be equally applied to a case where an upper barrier layer Mx+2_BL of metal layers Mxb, Mxc, Mxd, and Mxe is generated at a level LVx+2 from the substrate 200, a case where a lower barrier layer Mx-1_BL of metal layers Mxb, Mxc, Mxd, and Mxe is generated at a level LVx-1 from the substrate 200, and a case where a lower barrier layer Mx-2_BL of metal layers Mxb, Mxc, Mxd, and Mxe is generated at a level LVx-2 from the substrate 200.

[0073] First, refer to Fig.11 , upper barrier layers Mx+1_BL may be generated respectively for metal layers Mxb, Mxc, Mxd, and Mxe disposed at a level LVx from the substrate 200. The upper barrier layer Mx+1_BL may be disposed at a level LVx+1 from the substrate 200 and may have a predetermined width L5.

[0074] Next, refer to Fig.12, resizing may be performed on the upper barrier layer Mx+1_BL of each of the metal layers Mxb, Mxc, Mxd, and Mxe. Resizing refers to an operation of increasing and decreasing the width of each of the upper barrier layers Mx+1_BL of the metal layers Mxb, Mxc, Mxd, and Mxe by a predetermined interval. In this case, referring to Fig.11 Since there is a sufficient gap between the upper barrier layer Mx+1_BL of the metal layer Mxd and the upper barrier layer Mx+1_BL of the metal layer Mxe, even if the widths of the upper barrier layer Mx+1_BL of the metal layer Mxd and the upper barrier layer Mx+1_BL of the metal layer Mxe are increased by a predetermined gap from the existing width L5 during size adjustment, the upper barrier layer Mx+1_BL of the metal layer Mxd and the upper barrier layer Mx+1_BL of the metal layer Mxe may not be merged with each other.

[0075] However, since the upper barrier layer Mx+1_BL of the metal layer Mxb and the upper barrier layer Mx+1_BL of the metal layer Mxc are relatively close to each other, when the widths of the upper barrier layer Mx+1_BL of the metal layer Mxb and the upper barrier layer Mx+1_BL of the metal layer Mxc are increased by a predetermined interval from the existing width L5 during size adjustment, as shown in FIG. Fig.12 As shown in FIG. 4 , the upper barrier layer Mx+1_BL of the metal layer Mxb and the upper barrier layer Mx+1_BL of the metal layer Mxc may be merged with each other to have a width L6 .

[0076] In this case, since there is not enough space for inserting the dummy pattern between the upper barrier layer Mx+1_BL of the metal layer Mxb and the upper barrier layer Mx+1_BL of the metal layer Mxc, Fig.13 As shown in FIG. 1 , the upper barrier layer Mx+1_BL of the metal layer Mxb and the upper barrier layer Mx+1_BL of the metal layer Mxc may be removed.

[0077] Next, refer to Figure 3 , determine whether the selected metal layer is connected to the passive element (i.e., select the passive element) (S105). When the selected metal layer is not connected to the passive element (S105-N), the step may be terminated. When the selected metal layer is connected to the passive element (S105-Y), a barrier layer of the metal layer included in the passive element may be generated (S106).

[0078] Reference Fig.14 ,exist Figure 2A portion of the metal layer Mx extracted in step S102 may be connected to the passive element PE. The passive element PE may be, for example, a vertical native capacitor (VNCAP), and may include a metal layer Mx disposed at a level LVx and a metal layer Mx+1 disposed at a level LVx+1 that is one level higher than the level LVx. The metal layer Mx and the metal layer Mx+1 of the passive element PE may be connected to each other through a via VX.

[0079] A barrier layer Mx_BL surrounding the metal layer Mx may be generated at the same level LVx as the metal layer Mx from the substrate 200. Similarly, a barrier layer Mx+1_BL surrounding the metal layer Mx+1 may be generated at the same level LVx as the metal layer Mx+1 from the substrate 200.

[0080] Despite Fig.14 VNCAP is described as an example, but the type of the passive element PE is not limited thereto. For example, the passive element PE according to some embodiments may include metal layers Mx and Mx+1, and may include inductors, resistors, capacitors, etc. formed in the BEOL of the integrated circuit 1000.

[0081] Return to reference Figure 3 , an upper barrier layer and a lower barrier layer may be generated relative to the metal layer included in the passive element (S107). Fig.15 and Fig.16 A method of generating upper barrier layers Mx+2_BL and Mx+3_BL and lower barrier layers Mx-1_BL and Mx-2_BL relative to metal layers Mx and Mx+1 included in the passive element PE is described. In addition, in the following description, it is assumed that the metal layer Mx is disposed at a level LVx from the substrate 200, and the metal layer Mx+1 is disposed at a level LVx+1 from the substrate 200, which is one level higher than the level LVx.

[0082] First, refer to Fig.15 , the upper barrier layer Mx+2_BL may be disposed at a level LVx+2 that is one level higher than the level LVx+1 from the substrate 200 relative to the metal layer Mx+1, and is disposed at a level higher than the metal layers Mx and Mx+1 included in the passive element PE. In addition, the upper barrier layer Mx+3_BL may be disposed at a level LVx+3 that is two levels higher than the level LVx+1 from the substrate 200.

[0083] In addition, the lower barrier layer Mx-1_BL may be disposed at a level LVx-1 one level lower than the level LVx from the substrate 200 relative to the metal layer Mx disposed at the lower level among the metal layers Mx and Mx+1 included in the passive element PE. In addition, the lower barrier layer Mx-2_BL may be disposed at a level LVx-2 two levels lower than the level LVx from the substrate 200.

[0084] exist Fig.15 , the passive element PE is shown as including two metal layers Mx and Mx+1, but the embodiment is not limited thereto. For example, in some embodiments, the passive element PE may include three or more metal layers disposed at different levels from the substrate 200. In this case, an upper barrier layer may be generated relative to a metal layer disposed at the highest level among the metal layers included in the passive element PE, and a lower barrier layer may be generated relative to a metal layer disposed at the lowest level among the metal layers included in the passive element PE.

[0085] exist Fig.15 , two upper barrier layers Mx+2_BL and Mx+3_BL are shown as being generated at the upper level of the metal layer Mx+1, and two lower barrier layers Mx-1_BL and Mx-2_BL are shown as being generated at the lower level of the metal layer Mx, but the embodiment is not limited thereto. For example, in some embodiments, one upper barrier layer or three or more upper barrier layers may be generated at the upper level of the metal layer Mx+1, and one lower barrier layer or three or more lower barrier layers may be generated at the lower level of the metal layer Mx. For example, when the metal layer Mx is disposed at a relatively low level from the substrate 200, sufficient space for generating a dummy pattern may not be formed at a level LVx-2 that is two levels lower than the level LVx at which the metal layer Mx is disposed. In this case, the lower barrier layer of the metal layer Mx may be generated only at a level LVx-1 that is one level lower than the level LVx at which the metal layer Mx is disposed.

[0086] like Fig.15As shown in , the upper barrier layers Mx+2_BL and Mx+3_BL and the lower barrier layers Mx-1_BL and Mx-2_BL may be arranged to extend longitudinally along the first direction X, and the upper barrier layers Mx-2_BL, Mx-1_BL, Mx+2_BL and Mx+3_BL arranged at the same level may be arranged to be spaced apart from each other in the second direction Y. In addition, the upper barrier layers Mx+2_BL and Mx+3_BL and the lower barrier layers Mx-1_BL and Mx-2_BL may be arranged to overlap with the passive element PE in a plan view. At this time, the respective widths P1 of the upper barrier layers Mx+2_BL and Mx+3_BL and the lower barrier layers Mx-1_BL and Mx-2_BL, and the interval P2 of each of the upper barrier layers and the lower barrier layers Mx-2_BL, Mx-1_BL, Mx+2_BL and Mx+3_BL in the second direction Y may be determined according to the metal maximum space design rule.

[0087] In addition, a dummy pattern D may be inserted between upper and lower barrier layers Mx-2_BL, Mx-1_BL, Mx+2_BL, and Mx+3_BL disposed at the same levels LVx-2, LVx-1, LVx+2, and LVx+3 where upper and lower barrier layers Mx-2_BL, Mx-1_BL, Mx+2_BL, and Mx+3_BL are disposed.

[0088] However, the shapes of the upper barrier layers Mx+2_BL and Mx+3_BL and the lower barrier layers Mx-2_BL and Mx-1_BL of the passive element PE are not limited to Fig.15 For example, refer to Fig.16 , the upper barrier layers Mx+2_BL and Mx+3_BL and the lower barrier layers Mx-2_BL and Mx-1_BL of the passive element PE may be arranged to extend longitudinally along the second direction Y, and the upper and lower barrier layers Mx-2_BL, Mx-1_BL, Mx+2_BL, and Mx+3_BL arranged at the same level may be arranged to be spaced apart from each other in the first direction X. In addition, the dummy pattern D may be inserted between the upper and lower barrier layers Mx-2_BL, Mx-1_BL, Mx+2_BL, and Mx+3_BL arranged at the same level at each level LVx-2, LVx-1, LVx+2, and LVx+3 where the upper and lower barrier layers Mx-2_BL, Mx-1_BL, Mx+2_BL, and Mx+3_BL are arranged. Fig.15 and Fig.16 As shown in FIG. 1 , the dummy pattern D may overlap at least a portion of the metal layer Mx and the metal layer Mx+1 in a plan view.

[0089] Figures 17 to 19 is shown by using Figure 1An exemplary diagram of a method for designing an integrated circuit by a design system.

[0090] Fig.17 It is exemplarily shown in Figure 2 Schematic diagram of the metal layers Mx and Mx+1 used in the mesh selected in step S101. Fig.17 , the metal layer Mx may be disposed at a level LVx from the substrate 200, and the metal layer Mx+1 may be disposed at a level LVx+1 from the substrate 200. For example, the metal layer Mx+1 may be disposed at a level one level higher than the level of the metal layer Mx from the substrate 200. The metal layer Mx may be disposed to extend longitudinally along a first direction X, and the metal layer Mx+1 may be disposed to extend longitudinally along a second direction Y. The metal layer Mx and the metal layer Mx+1 may be connected to each other through a via Vx extending along a third direction Z. The metal layers Mx and Mx+1 may be routed to transmit an electrical signal to a transistor TR formed in a FEOL of the integrated circuit 1000, and may include a conductive material.

[0091] Next, refer to Fig.18 , a barrier layer 401A surrounding the metal layer Mx and disposed at the same level LVx as the metal layer Mx from the substrate 200 may be generated relative to the metal layer Mx. In addition, relative to the metal layer Mx, an upper barrier layer 402A may be generated at a level LVx+1 that is one level higher than the level LVx from the substrate 200, and an upper barrier layer 405A may be generated at a level LVx+2 that is two levels higher than the level LVx. In addition, relative to the metal layer Mx, a lower barrier layer 403A may be generated at a level LVx-1 that is one level lower than the level LVx from the substrate 200, and a lower barrier layer 404 may be generated at a level LVx-2 that is two levels lower than the level LVx.

[0092] Similarly, a barrier layer 402B surrounding the metal layer Mx+1 and disposed at the same level LVx+1 as the metal layer Mx+1 from the substrate 200 may be generated relative to the metal layer Mx+1. Furthermore, relative to the metal layer Mx+1, an upper barrier layer 405B may be generated at a level LVx+2 one level higher than the level LVx+1 from the substrate 200, and an upper barrier layer 406 may be generated at a level LVx+3 two levels higher than the level LVx+1. In addition, relative to the metal layer Mx+1, a lower barrier layer 401B may be generated at a level LVx one level lower than the level LVx+1 from the substrate 200, and a lower barrier layer 403B may be generated at a level LVx-1 two levels lower than the level LVx+1.

[0093] In this case, the barrier layers disposed at the same level may be generated as a whole. For example, the barrier layer 401A disposed at the level LVx of the metal layer Mx and the lower barrier layer 401B disposed at the same level LVx of the metal layer Mx+1 may be generated as a whole Mx_BL 401. In addition, the upper barrier layer 402A disposed at the level LVx+1 of the metal layer Mx and the barrier layer 402B disposed at the same level LVx+1 of the metal layer Mx+1 may be generated as a whole Mx+1_BL 402.

[0094] Similarly, an upper barrier layer 405A of the metal layer Mx disposed at the level LVx+2 and an upper barrier layer 405B of the metal layer Mx+1 disposed at the same level LVx+2 may be generated as an entirety Mx+2_BL 405 .

[0095] Furthermore, a lower barrier layer 403A of the metal layer Mx disposed at a level LVx- 1 and a lower barrier layer 403B of the metal layer Mx+1 disposed at the same level LVx- 1 may be generated as a whole Mx- 1_BL 403 .

[0096] Next, refer to Fig.19 , a dummy pattern D may be generated near the metal layers Mx and Mx+1. In this case, the dummy pattern D may be generated outside the space where the barrier layers 401, 402, 403, 404, 405, and 406 are generated near the metal layers Mx and Mx+1. Fig.19 As shown in , dummy pattern D may be generated in BEOL in a space near metal layers Mx and Mx+1 where barrier layers 401, 402, 403, 404, 405, and 406 are not generated. In some embodiments, dummy pattern D may not overlap metal layers Mx and Mx+1 in a plan view.

[0097] Figure 20 to Figure 22 is an exemplary diagram illustrating effects of an integrated circuit manufactured according to example embodiments.

[0098] Fig. 20 1 is a top view showing the metal layer Mx, the dummy patterns Mx_D, Mx+1_D, Mx+2_D, Mx-1_D and Mx-2_D, and the barrier layers Mx_BL, Mx+1_BL, Mx+2_BL, Mx-1_BL and Mx-2_BL as viewed from the top. Fig.21 is an exemplary diagram showing a metal layer Mx, a dummy pattern Mx_D, and barrier layers Mx_BL, Mx+1_BL, Mx+2_BL, Mx-1_BL, and Mx-2_BL as viewed from the side. Fig. 22 is an exemplary diagram illustrating adding dummy patterns Mx+1_D, Mx+2_D, Mx-1_D, and Mx-2_D.

[0099] First, refer to Fig. 20 and Fig.21 , the barrier layer Mx_BL surrounding the metal layer Mx can be formed at the same level as the metal layer Mx, the upper barrier layers Mx+1_BL and Mx+2_BL of the metal layer Mx can be generated at a higher level than the metal layer Mx, and the lower barrier layers Mx-1_BL and Mx-2_BL of the metal layer Mx can be generated at a lower level than the metal layer Mx. Fig. 20 , two upper barrier layers and two lower barrier layers of the metal layer Mx are shown, but the number of each of the upper barrier layers and the lower barrier layers of the metal layer Mx may vary according to embodiments.

[0100] The dummy pattern Mx_D disposed at the same level as the metal layer Mx may be generated in a region where the barrier layer Mx_BL is not generated, that is, outside the barrier layer Mx_BL near the metal layer Mx.

[0101] Next, refer to Fig. 20 and Fig. 22 , the dummy patterns Mx+1_D, Mx+2_D, Mx-1_D, and Mx-2_D disposed at the upper and lower levels of the metal layer Mx may be generated in the regions of the upper barrier layers Mx+1_BL and Mx+2_BL and the lower barrier layers Mx-1_BL and Mx-2_BL where the metal layer Mx is not generated, that is, outside the upper and lower barrier layers Mx+1_BL, Mx+2_BL, Mx-1_BL, and Mx-2_BL near the metal layer Mx. Therefore, as Fig. 20 As shown in FIG. 1 , the dummy patterns Mx+1_D, Mx+2_D, Mx-1_D, and Mx-2_D disposed at upper and lower levels of the metal layer Mx may not overlap the metal layer Mx in a plan view.

[0102] The dummy pattern Mx_D disposed at the same level as the metal layer Mx and the dummy patterns Mx+1_D, Mx+2_D, Mx-1_D, and Mx-2_D disposed at a different level from the metal layer Mx may include a conductive material such as a metal.

[0103] Unlike the metal layer Mx, the dummy patterns Mx_D, Mx+1_D, Mx+2_D, Mx-1_D, and Mx-2_D are not metal patterns that actually route electrical signals, but may fill empty spaces between metal layers to prevent undesired depressions from occurring in the metal layer of BEOL when a chemical mechanical polishing (CMP) process of a semiconductor manufacturing process is performed later. In this case, when the metal layer and the dummy pattern are close to each other, parasitic capacitance may increase between the metal layer and the dummy pattern. Therefore, the RC delay of the integrated circuit may be aggravated, and the performance of the metal layer may be degraded. To solve this problem, the metal layer and the dummy pattern should be spaced apart from each other at a predetermined interval.

[0104] In this case, the barrier layer Mx_BL, upper barrier layers Mx+1_BL and Mx+2_BL, and lower barrier layers Mx-1_BL and Mx-2_BL generated near the metal layer Mx can prevent parasitic capacitance from increasing due to the dummy patterns Mx_D, Mx+1_D, Mx+2_D, Mx-1_D, and Mx-2_D being disposed too close to the metal layer Mx.

[0105] Fig.23 is an exemplary flow chart illustrating a method of manufacturing an integrated circuit according to example embodiments.

[0106] Reference Fig.23 , the cell library D12 may include information including Figure 4 The cell library D12 may include information of the logic cell of the transistor TR. For example, the cell library D12 may include function information, characteristic information, layout information, etc. of the logic cell. The cell library D12 may include data D12_1, D12_2, etc. defining the layout of the logic cell. The logic cell may include a standard cell. The standard cell may have a structure that meets a predetermined standard.

[0107] In step S10, a logic synthesis operation of generating netlist data D13 from RTL data D11 may be performed. For example, a semiconductor design tool (such as Electronic Design Automation (EDA)) may generate netlist data D13 including a bitstream or a netlist by performing logic synthesis from RTL data D11 written in a hardware description language (HDL) by referring to a cell library D12. HDL may include a very high speed integrated circuit (VHSIC) hardware description language (VHDL), Verilog, etc. The cell library D12 may include information (such as the height of the logic cell, the number of pins included in the logic cell, and the number of tracks corresponding to the logic cell). In the logic synthesis process, the logic cell may be included in an integrated circuit (IC) by referring to the information of the cell library D12.

[0108] In step S20, a Placement & Routing (P&R) operation of generating layout data D14 from netlist data D13 may be performed. The Placement & Routing step S20 may include a plurality of steps S21, S22, and S23.

[0109] In step S21 , an operation of placing logic cells may be performed. For example, a semiconductor design tool (eg, a P&R tool) may place a plurality of logic cells according to the netlist data D13 with reference to the cell library D12 .

[0110] In step S21, a power rail layout operation may be performed. For example, the power rail layout operation may be performed on the power rails included in the Figure 4An operation of laying out a power rail of the transistor that transmits any one of the driving voltage VDD and the ground voltage VSS in the metal layer M4.

[0111] In step S22, an operation of generating interconnections may be performed. Through the interconnection operation, the output pin and the input pin of the logic unit may be electrically connected to each other. The logic unit may include at least one via.

[0112] In step S23, an operation of generating layout data D14 may be performed. The layout data D14 may include geometric information of cells and interconnections. The layout data D14 may have a format such as GDSII. For example, the layout data D14 may correspond to Figure 4 The layout of integrated circuit 1000 is shown in FIG.

[0113] In step S30, optical proximity correction (OPC) may be performed on the layout data D14, so that the pattern on the mask may be determined. For example, a distortion phenomenon (such as refraction) due to the characteristics of light may be corrected, so that a pattern of a desired shape may be formed with the layout data D14. In some embodiments, the layout of the integrated circuit may be modified to a limited extent in step S30. Therefore, the structure of the integrated circuit may be optimized. Step S30 may be referred to as design polishing.

[0114] In step S40, an operation of manufacturing a mask may be performed. At least one mask may be manufactured to form the pattern determined in step S30. The mask may include a photomask.

[0115] The barrier layer, upper barrier layer and lower barrier layer according to the example embodiment may be included in the layout data D14. For example, the barrier layer, upper barrier layer and lower barrier layer may be displayed in the layout data in the form of a GDS file in which the information about the layer of the integrated circuit (IC) is compressed. However, the barrier layer, upper barrier layer and lower barrier layer are to appropriately widen the interval between the metal layer and the dummy pattern in the layout design step to the interval where the parasitic capacitance does not exist with its increased interval. In the exposure process using the mask manufactured in step S40, the barrier layer, upper barrier layer and lower barrier layer may not be actually displayed. Therefore, the above-mentioned barrier layer, upper barrier layer and lower barrier layer may not exist in the integrated circuit manufactured in the following steps.

[0116] In step S50, an operation of manufacturing an integrated circuit may be performed. For example, the at least one mask manufactured in step S40 may be used to pattern a plurality of layers, thereby manufacturing an integrated circuit. Fig.23 As shown in , step S50 may include step S51 and step S52.

[0117] In step S51, a FEOL process may be performed. The FEOL process may refer to a step of forming an independent element in a substrate. The independent element may include a transistor, a capacitor, a resistor, etc. The FEOL process may include a step of planarizing the substrate, a step of cleaning the substrate, a step of forming a trench, a step of forming an active region and an impurity region, a step of forming a gate line, and a step of forming a source and a drain region. For example, the FEOL process may correspond to forming Figure 6 and Figure 7 The first layer F1 and the substrate 200 are formed.

[0118] In step S52, a back-end-of-line (BEOL) process may be performed. The BEOL process may refer to a process of interconnecting independent components. For example, the BEOL process may include a step of silicide of gate and source and drain regions, a step of adding a dielectric, a step of planarization, a step of forming a hole, a step of adding a metal layer, a step of forming a via, and a step of forming a passivation layer. For example, the BEOL process may correspond to forming Figure 6 and Figure 7 The steps of the second layer F2 to the eighth layer F8.

[0119] After step S52 , the integrated circuit (IC) may be packaged and used as a part of various applications.

[0120] Fig.24 It is shown that including Fig.23 An exemplary schematic diagram of a semiconductor device of a fabricated integrated circuit.

[0121] Reference Fig.24 , the semiconductor device 600 includes a substrate 601, a functional block (intellectual property (IP)), a transistor TR, front-side wiring lines M1 to My, Mx-1, Mx and Mx+1, back-side wiring lines 603, 605, 607, 607a and 609a, back-side wiring vias 604, 606, 606a and 608a, through silicon vias (TSV, also called through silicon vias) 608 and 610a, a bump 614 and a cover 602.

[0122] The substrate 601 may be a silicon substrate or a silicon on insulator (SOI) substrate, and may be implemented as a P-type substrate or an N-type substrate according to an embodiment, but is not limited thereto. The substrate 601 disposed on a plane defined by the first direction X and the second direction Y may have a front side and a rear side facing each other in a third direction Z. The front side of the substrate 601 may be disposed at a position higher than the rear side of the substrate 601 in the third direction Z.

[0123] The functional block IP and the transistor TR may be formed on the substrate 601. The functional block IP may represent a functional block that may be used in an integrated circuit (IC), a system on chip (SoC), or an application processor (AP). Fig.25 Describe the functional block IP. The transistor TR may correspond to Figure 4 For example, the transistor TR may include, but is not limited to, a fin field effect transistor (FinFET) or a multi-bridge channel field effect transistor (MBCFET). TM ).

[0124] The semiconductor device 600 may have a backside power delivery network (BSPDN) structure. Front side line lines M1 to My, Mx-1, Mx, and Mx+1 corresponding to the signal lines that send signals to the functional block IP and the transistor TR may be arranged on the front side of the substrate 601, and back side line lines 603, 605, 607, 607a, and 609a that transmit power to the functional block IP and the transistor TR and back side line vias 604, 606, 606a, and 608a may be arranged on the back side of the substrate 601. The back side line line 603 may be connected to the bump 614 to receive power from the outside. TSVs 608 and 610a may transmit power to the functional block IP and the transistor TR by passing through the substrate 601 in the third direction Z. The ground line 611 arranged on the front side of the substrate 601 may be connected to a pad 613 formed to be embedded in the substrate 601 to transmit the ground voltage to the element formed on the substrate 601. In addition, in the semiconductor device 600 having the BSPDN structure, some power lines 612 may be disposed on the front side of the substrate 601. The cover 602 may include silicon and may protect the front side line lines M1 to My, Mx-1, Mx, and Mx+1, the ground line 611, and the power line 612.

[0125] When Figure 2 When selecting a net of the semiconductor device 600 in step S101, a net having a greater requirement for preventing performance degradation due to RC delay may be selected. For example, when a net corresponding to the transistor TR has a greater requirement for preventing performance degradation due to RC delay than a net corresponding to the functional block IP, the net corresponding to the transistor TR may be selected to generate a barrier layer, an upper barrier layer, and a lower barrier layer according to some embodiments with respect to the metal layer Mx connected to the transistor TR.

[0126] Usually, if Fig.24As shown in , a shield is generated near the metal layer Mx to widen the interval between the metal layer and the dummy pattern, thereby preventing the parasitic capacitance from increasing. However, when the shield includes a conductive material (such as metal), another problem of parasitic capacitance being generated and increased between the shield and the dummy pattern occurs. Therefore, in some embodiments, in the design step of the semiconductor device 600, a barrier layer, an upper barrier layer, and a lower barrier layer may be generated near the metal layer Mx to prevent the performance of the metal layer Mx from being reduced. In addition, in the integrated circuit of the semiconductor device 600 completed by the semiconductor manufacturing process, a barrier layer, an upper barrier layer, and a lower barrier layer that are generated only in the step of designing a layout of the integrated circuit to manufacture a semiconductor mask and are not actually implemented in the integrated circuit of the semiconductor device 600 completed by the semiconductor manufacturing process can be generated near the metal layer Mx in the semiconductor design process, rather than being actually implemented as a shielding member including a conductive material (such as, metal), thereby reducing the area occupied by the metal layer Mx and the metal layer Mx-1 and the metal layer Mx+1 arranged near the metal layer Mx, and improving the integration of the semiconductor device 600.

[0127] Fig.25 It shows that according to Fig.23 An exemplary block diagram of a fabricated integrated circuit.

[0128] Reference Fig.25 , the semiconductor system 700 may include a Fig.23 The semiconductor system 700 may include an interconnect 701, a plurality of functional blocks 710, 715, 720, 725, 730, 740, 750, 760, 770, and 780, a first memory device (eg, flash memory) 735, a display 745, a second memory device (eg, memory) 755, and a camera 775.

[0129] The semiconductor system 700 may be implemented as a personal computer (PC) or a mobile device. The mobile device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device (PND) or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, or an e-book.

[0130] In some embodiments, interconnect 701 and multiple functional blocks 710, 715, 720, 725, 730, 740, 750, 760, 770, and 780 may be implemented in a system on chip. Functional blocks 710, 715, 720, 725, 730, 740, 750, 760, 770, and 780 may correspond to Fig.24 Functional block IP or including Fig.24 The functional block of transistor TR.

[0131] The central processing unit (CPU) 710 may control the operation of each of the plurality of functional blocks 715, 720, 725, 730, 740, 750, 760, 770, and 780 via the interconnection 701. For example, the interconnection 701 may be implemented as a bus. The communication module 715 may control data exchanged between an external communication device and the semiconductor system 700. For example, the communication module 715 may include a transceiver (or Bluetooth) 715-1 for Bluetooth communication, a transceiver (or Wi-Fi) 715-2 for wireless fidelity (Wi-Fi) communication, and a GPS receiver 715-3 for receiving a global positioning system (GPS) signal. The data processed by the communication module 715 may be sent to at least one of the plurality of functional blocks 710, 720, 725, 730, 740, 750, 760, 770, and 780 via the interconnection 701.

[0132] The GPU 720 may process graphic data. The I / O interface 725 may transmit data input from a user to the interconnect 701, or transmit data transmitted from the interconnect 701 to an I / O device. The first memory controller 730 may write data into or read data from the first memory device 735 under the control of the CPU 710 or the GPU 720. For example, the first memory device 735 may be a nonvolatile memory device. The display controller 740 may control the operation of the display 745 under the control of the CPU 710 or the GPU 720. For example, the display controller 740 may transmit display data to the display 745.

[0133] The second memory controller 750 may write data into or read data from the second memory device 755 under the control of the CPU 710 or the GPU 720. For example, the second memory device 755 may be a volatile memory device.

[0134] A universal serial bus (USB) controller 760 may transmit or receive data to or from a USB host. A camera controller 770 may process data output from a camera 775 and transmit the processed data to an interconnect 701. A debug controller 780 may control debugging of the semiconductor system 700.

[0135] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims

1. An integrated circuit design system using a computing system, the integrated circuit design system include: a memory configured to store instructions; as well as a processor configured to execute the instructions to design an integrated circuit, The integrated circuit includes a substrate, a front-end process in at least a portion of the substrate and on the substrate, and a back-end process formed on the front-end process, and Wherein, when the processor executes the instructions to design an integrated circuit, the processor is configured to: selecting a first metal layer included in the back-end process and disposed at a first level from the substrate; generating a first barrier layer disposed at the first level and surrounding the first metal layer; generating at least one first upper barrier layer disposed at a level higher than the first level from the substrate; and At least one first lower barrier layer disposed at a level lower than the first level from the substrate is generated.

2. The integrated circuit design system according to claim 1, in, When the processor generates the first upper barrier layer, the processor is configured to: generating a second barrier layer disposed at a second level higher than the first level from the substrate; and A third barrier layer is generated that is disposed at a third level higher than the second level from the substrate.

3. The integrated circuit design system according to claim 2, in, When the processor executes the instructions to design an integrated circuit, the processor is further configured to: generating a first dummy pattern at a second level; and generating a second dummy pattern at a third level, The first dummy pattern and the second dummy pattern do not overlap with the first metal layer in a plan view.

4. The integrated circuit design system according to claim 2, in, When the processor generates the first lower barrier layer, the processor is configured to: A fourth barrier layer disposed at a fourth level lower than the first level from the substrate is generated.

5. The integrated circuit design system according to claim 4, in, When the processor generates the first lower barrier layer, the processor is further configured to: A fifth barrier layer disposed at a fifth level lower than the fourth level from the substrate is generated.

6. The integrated circuit design system according to claim 5, when the processor executes the instructions to design the integrated circuit, the processor is further configured to: generating a third dummy pattern at a fourth level; and generating a fourth dummy pattern at the fifth level, in, The third dummy pattern and the fourth dummy pattern do not overlap the first metal layer in a plan view.

7. The integrated circuit design system according to claim 1, in, The integrated circuit includes passive components, and The passive component includes a second metal layer and a third metal layer; the second metal layer is included in the back-end process, is arranged at a first level from the substrate, and does not overlap with the first metal layer; the third metal layer is included in the back-end process, and is arranged at a second level higher than the first level from the substrate, and The second metal layer and the third metal layer are connected to each other through vias.

8. The integrated circuit design system according to claim 7, in, When the processor executes the instructions to design an integrated circuit, the processor is further configured to: generating a second barrier layer disposed at the first level and surrounding the second metal layer; and A third barrier layer is generated that is disposed at the second level and surrounds the third metal layer.

9. The integrated circuit design system according to claim 8, in, When the processor executes the instructions to design an integrated circuit, the processor is further configured to: generating at least one second upper barrier layer disposed at a level higher than the second level from the substrate; and At least one second lower barrier layer disposed at a level lower than the first level from the substrate is generated.

10. The integrated circuit design system according to claim 9, in, The second upper barrier layer overlaps at least a portion of the second metal layer and the third metal layer in a plan view, and The second lower barrier layer overlaps at least a portion of the second metal layer and the third metal layer in a plan view.

11. The integrated circuit design system according to claim 10, in, When the processor generates the second upper barrier layer, the processor is configured to: generating a fourth barrier layer disposed at a third level higher than the second level from the substrate; and A fifth barrier layer is generated that is disposed at a fourth level higher than the third level from the substrate.

12. The integrated circuit design system according to claim 11, in, When the processor generates the second lower barrier layer, the processor is configured to: generating a sixth barrier layer disposed at a fifth level lower than the first level from the substrate; and A seventh barrier layer disposed at a sixth level lower than the fifth level from the substrate is generated.

13. An integrated circuit design system using a computing system, the integrated circuit design system include: a memory configured to store instructions; as well as a processor configured to execute the instructions to design an integrated circuit, The integrated circuit includes a substrate, a front-end process in at least a portion of the substrate and on the substrate, a back-end process formed on the front-end process, and a passive component formed in the back-end process. The passive element includes a first metal layer and a second metal layer; the first metal layer is included in the back-end process and is arranged at a first level from the substrate; the second metal layer is included in the back-end process, is arranged at a second level higher than the first level from the substrate, and is connected to the first metal layer through a via, and Wherein, when the processor executes the instructions to design an integrated circuit, the processor is configured to: Select the first metal layer; generating a first barrier layer disposed at a first level around the first metal layer; generating a second barrier layer disposed at a second level around the second metal layer; generating at least one upper barrier layer disposed at a level higher than the second level from the substrate; and At least one lower barrier layer disposed at a level lower than the first level from the substrate is generated.

14. The integrated circuit design system according to claim 13, in, When the processor generates the upper barrier layer, the processor is configured to: generating a third barrier layer disposed at a third level higher than the second level from the substrate; and A fourth barrier layer is generated that is disposed at a fourth level higher than the third level from the substrate.

15. The integrated circuit design system according to claim 14, in, When the processor executes the instructions to design an integrated circuit, the processor is further configured to: Insert the first dummy pattern into the third level, The first dummy pattern does not overlap with the third barrier layer.

16. The integrated circuit design system according to claim 15, in, The first dummy pattern overlaps at least a portion of the first metal layer and the second metal layer in a plan view.

17. The integrated circuit design system according to claim 13, in, When the processor generates the lower barrier layer, the processor is configured to: A fifth barrier layer disposed at a fifth level lower than the first level from the substrate is generated.

18. The integrated circuit design system according to claim 17, in, When the processor generates the lower barrier layer, the processor is further configured to: A sixth barrier layer disposed at a sixth level lower than the fifth level from the substrate is generated.

19. A computing system, include: a memory configured to store instructions; as well as a processor configured to execute the instructions to design an integrated circuit, The integrated circuit includes a substrate, a front-end process formed in at least a portion of the substrate and on the substrate, and a back-end process formed on the front-end process. Wherein, when the processor executes the instructions to design an integrated circuit, the processor is configured to: selecting a first metal layer included in the back-end process and disposed at a first level from the substrate; generating a first barrier layer disposed at the first level and surrounding the first metal layer; generating at least one first upper barrier layer disposed at a level higher than the first level from the substrate; generating at least one first lower barrier layer disposed at a level lower than the first level from the substrate; Selecting a passive component, the passive component comprising a second metal layer and a third metal layer; the second metal layer is included in the back-end process, is disposed at a first level from the substrate, and does not overlap with the first metal layer; the third metal layer is included in the back-end process, is disposed at a second level higher than the first level from the substrate, and is connected to the second metal layer through a via; generating a second barrier layer disposed at the first level and surrounding the second metal layer; generating a third barrier layer disposed at the second level and surrounding the third metal layer; generating at least one second upper barrier layer disposed at a level higher than the second level from the substrate; and At least one second lower barrier layer disposed at a level lower than the first level from the substrate is generated.

20. The computing system of claim 19, in, When the instructions are executed by the processor, the processor is further configured to: inserting a first dummy pattern near a first metal layer at a first level; inserting a second dummy pattern into a level higher than the first level from the substrate; and The third dummy pattern is inserted into a level lower than the first level from the substrate.

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