Production process of ultra-fine circuit of chip

Abstract

The present application provides a production process for ultra-fine circuits of a chip, which relates to the field of intelligent chip production. It uses image processing and analysis techniques based on deep learning to extract features and optimize significant features of a microscopic image of a circuit pattern and a circuit pattern design image, and automatically generates a defect detection result based on the comparison between the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image features and a preset threshold. In this way, it can identify tiny defects that are difficult to discover by traditional methods, improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and wafers of different batches, improving the flexibility and automation level of the detection system.

Description

Technical Field

[0001] This application relates to the field of intelligent chip production, and more specifically, to a production process for ultra-fine circuits of a chip. Background Art

[0002] With the progress of technology, electronic products are developing towards smaller, faster, and more intelligent directions. This not only drives higher requirements for chip performance and functional density but also promotes the development of ultra-fine circuit chip technology. Ultra-fine circuit technology enables chips to achieve higher circuit density and more efficient energy efficiency while maintaining a small size, which is crucial for modern electronic devices such as smart phones, wearable devices, and Internet of Things terminals. Therefore, defect detection has become a key link to ensure chip quality and reliability.

[0003] However, although traditional simple automatic optical inspection (AOI) can improve the inspection speed, due to its dependence on preset templates and rules, it is difficult to cope with complex and variable defect types. Especially in the case of ultra-fine circuits, subtle defects are often difficult to be accurately identified. In addition, since the detection algorithm of the AOI system is usually based on threshold setting, this method of fixed threshold is not flexible enough when dealing with wafers of different batches or different types and is difficult to adapt to diverse detection requirements. Specifically, in the manufacturing process of ultra-fine circuits, any minor deviation may lead to serious quality problems. Due to its inherent limitations, traditional AOI systems are difficult to meet the requirements of high precision and high reliability in modern chip manufacturing.

[0004] Therefore, an optimized production process for ultra-fine circuits of a chip is desired. Summary of the Invention

[0005] To solve the above technical problems, this application is proposed. Embodiments of this application provide a production process for ultra-fine circuits of a chip, which uses image processing and analysis technology based on deep learning to perform feature extraction and significant feature optimization on the microscopic image of the circuit pattern and the design image of the circuit pattern. Based on this, the defect detection result is automatically generated by comparing the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image features with a preset threshold. In this way, it is possible to identify tiny defects that are difficult to discover by traditional methods, improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and wafers of different batches, improving the flexibility and automation level of the detection system.

[0006] According to one aspect of this application, a production process for ultra-fine circuits of a chip is provided, which includes:

[0007] Providing a silicon wafer;

[0008] Place the silicon wafer in a high-temperature furnace for oxidation treatment to form a layer of silicon dioxide film on the surface of the silicon wafer to obtain an oxidized silicon wafer;

[0009] Coat a layer of photoresist on the oxidized silicon wafer, and use a lithography machine to project the designed circuit pattern onto the photoresist, and perform exposure treatment with ultraviolet light to obtain the circuit pattern;

[0010] Perform defect detection on the circuit pattern based on microscopic images to obtain a defect detection result;

[0011] In response to the defect detection result indicating no defect, perform etching treatment on the oxidized silicon wafer with the circuit pattern to remove the exposed silicon layer and form the required ultra-fine circuit;

[0012] Based on the circuit design requirements, introduce impurity atoms in specific regions to change the electrical properties of the specific regions, and fabricate interconnecting circuits to obtain a chip;

[0013] Perform electrical performance testing on the chip to obtain a test result;

[0014] In response to the test result indicating no defect, package the chip.

[0015] Combined with the first aspect of the present application, in a production process of ultra-fine circuits of a chip in the first aspect of the present application, performing defect detection on the circuit pattern based on microscopic images to obtain a defect detection result includes: collecting microscopic images of the circuit pattern; extracting the design image of the circuit pattern from a database; respectively inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map; inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module guided by grid energy saliency to obtain a circuit pattern microscopic optimized feature map and a circuit pattern design optimized feature map; inputting the circuit pattern microscopic optimized feature map and the circuit pattern design optimized feature map into a sequence-to-sequence matching network based on energy-intensive interaction distribution to obtain a sequence-to-sequence semantic matching coefficient; and generating the defect detection result based on the sequence-to-sequence semantic matching coefficient.

[0016] Compared with the prior art, the production process of the ultra-fine circuit of the chip provided in this application uses image processing and analysis technology based on deep learning to extract features and optimize significant features of the microscopic image of the circuit pattern and the design image of the circuit pattern. Based on this, the defect detection result is automatically generated by comparing the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image features with a preset threshold. In this way, it is possible to identify tiny defects that are difficult to discover by traditional methods, improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and wafers of different batches, improving the flexibility and automation level of the detection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In the drawings:

[0018] Figure 1 It is a flowchart of the production process of the ultra-fine circuit of the chip according to the embodiment of this application.

[0019] Figure 2 It is a flowchart of defect detection based on the microscopic image of the circuit pattern to obtain the defect detection result in the production process of the ultra-fine circuit of the chip according to the embodiment of this application.

[0020] Figure 3 It is a schematic diagram of data flow for defect detection based on the microscopic image of the circuit pattern to obtain the defect detection result in the production process of the ultra-fine circuit of the chip according to the embodiment of this application.

[0021] Figure 4 It is a flowchart of inputting the microscopic feature map of the circuit pattern and the design feature map of the circuit pattern into the feature gating enhancement module guided by grid energy saliency to obtain the optimized microscopic feature map of the circuit pattern and the optimized design feature map of the circuit pattern in the production process of the ultra-fine circuit of the chip according to the embodiment of this application.

[0022] Figure 5 It is a flowchart of inputting the optimized microscopic feature map of the circuit pattern and the optimized design feature map of the circuit pattern into the sequence matching network based on energy-intensive interaction distribution to obtain the inter-sequence semantic matching coefficient in the production process of the ultra-fine circuit of the chip according to the embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] Next, exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments of the present application. It should be understood that the present application is not limited by the exemplary embodiments described herein.

[0024] Technological progress is leading electronic products towards a direction of being thinner, lighter, more energy-efficient, and intelligent. This trend not only sets higher standards for the performance and functional integration of chips but also gives rise to the demand for ultra-fine line technology. This technology enables chips to achieve higher circuit density and better energy efficiency while maintaining a small volume, which is crucial for modern electronic devices such as smartphones, smart wearable devices, and Internet of Things devices. Against this backdrop, defect detection has become a core step in ensuring the quality and reliability of chips.

[0025] However, traditional automatic optical inspection (AOI) technology, although it has played a role in improving the inspection speed, its inspection method based on preset templates and rules is unable to cope when faced with complex and diverse defect types. Especially in the production of ultra-fine lines, tiny defects are often difficult to be accurately identified. In addition, the inspection algorithms of AOI systems usually rely on fixed thresholds, and this rigid method lacks flexibility when dealing with wafers of different batches or different types, and it is difficult to adapt to changing inspection requirements. In the process of ultra-fine line manufacturing, even a tiny deviation may lead to serious quality problems. Therefore, due to its inherent limitations, traditional AOI systems are difficult to meet the strict requirements of modern chip manufacturing for high precision and high reliability.

[0026] Based on this, the present application proposes an optimized production process for ultra-fine lines of chips. Figure 1 The flowchart of the production process for ultra-fine lines of chips according to an embodiment of the present application is as follows. Figure 1As shown, according to the production process of the ultra-fine circuit of the chip provided by the embodiment of the present application, it includes: S110, providing a silicon wafer; S120, putting the silicon wafer into a high-temperature furnace for oxidation treatment to form a layer of silicon dioxide film on the surface of the silicon wafer to obtain an oxidized silicon wafer; S130, coating a layer of photoresist on the oxidized silicon wafer, using a lithography machine to project the designed circuit pattern onto the photoresist, and performing exposure treatment with ultraviolet light to obtain a circuit pattern; S140, performing defect detection on the circuit pattern based on a microscopic image to obtain a defect detection result; S150, in response to the defect detection result indicating no defect, etching the oxidized silicon wafer with the circuit pattern to remove the exposed silicon layer and form the required ultra-fine circuit; S160, introducing impurity atoms in a specific area based on the circuit design requirements to change the electrical properties of the specific area, and fabricating interconnecting lines to obtain a chip; performing electrical performance testing on the chip to obtain a test result; S170, in response to the test result indicating no defect, packaging the chip.

[0027] In the production process of ultra-fine chip circuits, first, a silicon wafer needs to be prepared. The silicon wafer is the basic material for chip manufacturing. It has good semiconductor properties and is widely used in integrated circuit manufacturing. Next, the silicon wafer is placed in a high-temperature furnace to react silicon with oxygen to grow a layer of silicon dioxide film on the surface of the silicon wafer. The generated silicon dioxide film has good insulation performance and chemical stability, which can prevent impurities from diffusing into the interior of the silicon wafer and can provide a suitable surface for the construction of circuit patterns. Immediately afterwards, a layer of photoresist is coated on the oxidized silicon wafer. The photoresist is a light-sensitive material that can form circuit patterns in the subsequent exposure process. As a key device in chip manufacturing, the lithography machine can accurately project the pre-designed circuit pattern onto the photoresist, and then through ultraviolet exposure, the photoresist in the exposed area undergoes chemical changes, so that the circuit pattern is obtained on the oxidized silicon wafer. During the chip manufacturing process, any tiny defect may lead to a decline or even failure of the chip performance. Subsequently, defect detection based on microscopic images of the circuit pattern is required to timely detect defects in the circuit pattern, such as broken lines and short circuits. After determining that the circuit pattern has no defects, an etching operation is performed on the oxidized silicon wafer with the circuit pattern. The etching process selectively removes the exposed silicon layer. Through precise etching, ultra-fine lines with very small dimensions can be formed. These lines are the key structures for the chip to achieve various functions (such as signal transmission, logical operations, etc.). Then, according to the circuit design requirements of the chip, impurity atoms (such as boron, phosphorus, etc.) are introduced into specific regions. This doping process can change the electrical properties of silicon, such as forming P-type or N-type semiconductor regions, so as to construct various devices such as transistors and diodes, and fabricate interconnecting lines to connect the various devices, enabling the chip to operate normally according to the designed circuit functions. Next, electrical performance tests are carried out on the fabricated chip to check whether the electrical parameters (such as current, voltage, resistance, etc.) of the chip meet the design requirements to determine whether the chip can operate normally. When the electrical performance test results of the chip show no defects, finally, a packaging operation is required. Packaging can protect the chip from the influence of the external environment (such as physical impact, chemical corrosion, etc.), and at the same time provide an interface for the chip to connect to the external circuit, enabling the chip to be easily integrated into various electronic devices.

[0028] Accordingly, in the defect detection of the circuit pattern based on the microscopic image to obtain the defect detection result, it collects the microscopic image of the circuit pattern, extracts the design image of the circuit pattern from the database, and uses image processing and analysis techniques based on deep learning to perform feature extraction and significant feature optimization on the microscopic image and the design image. Based on this, the defect detection result is automatically generated by comparing the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image feature with a preset threshold. In this way, it is possible to identify tiny defects that are difficult to discover by traditional methods, improving the sensitivity and accuracy of the detection. At the same time, it can adapt to different types of defects and wafers of different batches, improving the flexibility and automation level of the detection system.

[0029] Figure 2 It is a flowchart for defect detection of the circuit pattern based on the microscopic image to obtain the defect detection result in the production process of the ultra-fine circuit of the chip according to the embodiment of the present application. Figure 3 It is a schematic diagram of data flow for defect detection of the circuit pattern based on the microscopic image to obtain the defect detection result in the production process of the ultra-fine circuit of the chip according to the embodiment of the present application. As Figure 2 and Figure 3 shown, defect detection of the circuit pattern based on the microscopic image to obtain the defect detection result includes: S141, collecting the microscopic image of the circuit pattern; S142, extracting the design image of the circuit pattern from the database; S143, respectively inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map; S144, inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module guided by grid energy saliency to obtain a circuit pattern microscopic optimized feature map and a circuit pattern design optimized feature map; S145, inputting the circuit pattern microscopic optimized feature map and the circuit pattern design optimized feature map into a sequence-to-sequence matching network based on energy-intensive interaction distribution to obtain a sequence-to-sequence semantic matching coefficient; S146, generating the defect detection result based on the sequence-to-sequence semantic matching coefficient.

[0030] In steps S141 and S142, a microscopic image of the circuit pattern is collected, and a design image of the circuit pattern is extracted from the database. It should be understood that the microscopic image of the circuit pattern usually contains the microscopic structure and features of the wafer surface, such as the width of the lines, the spacing, the edge sharpness, the integrity of the pattern, etc. It can reveal physical defects on the wafer, such as broken lines, bridges, depressions, particles, protrusions, etc. The design image of the circuit pattern usually contains the detailed layout information of all microscopic circuit elements on the chip. It is the reference standard in the defect detection process and is used to compare with the microscopic image to identify deviations and defects in the actual manufacturing process.

[0031] In step S143, the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map. Specifically, in the embodiment of the present application, inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map includes: inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor based on a dilated convolutional neural network model to obtain the circuit pattern microscopic feature map and the circuit pattern design feature map. It should be understood that the microscopic image of the circuit pattern contains the microscopic structure and features of the wafer surface, and the design image of the circuit pattern contains the detailed layout information of all microscopic circuit elements on the chip. Considering that the dilated convolution coding method in the dilated convolutional neural network model can expand the receptive field by introducing intervals in the convolutional kernel without increasing the amount of computation and the number of parameters, thereby capturing more extensive context information of the input data, which is beneficial to improving the accuracy of defect detection. Based on this, in the technical solution of the present application, the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into a circuit pattern feature extractor based on a dilated convolutional neural network model to respectively capture and extract the microscopic detail features and design layout information in the circuit pattern, obtaining a circuit pattern microscopic feature map and a circuit pattern design feature map.

[0032] In step S144, the microscopic feature map of the circuit pattern and the design feature map of the circuit pattern are input into a feature gating enhancement module guided by grid energy saliency to obtain a microscopic optimized feature map of the circuit pattern and a design optimized feature map of the circuit pattern. Accordingly, considering that both the microscopic feature map of the circuit pattern and the design feature map of the circuit pattern contain key and significant circuit pattern features, that is, the importance varies between different regions. For example, in a circuit pattern, certain connection points may be more important than other regions because they are key channels for electronic signal transmission. For instance, key connection points and sensitive component areas may be more important than other regions. In order to enhance and highlight the contrast of the key features in the microscopic feature map of the circuit pattern and the design feature map of the circuit pattern, thereby improving the accuracy of defect detection, in the technical solution of this application, the microscopic feature map of the circuit pattern and the design feature map of the circuit pattern are input into a feature gating enhancement module guided by grid energy saliency to obtain a microscopic optimized feature map of the circuit pattern and a design optimized feature map of the circuit pattern. Specifically, the feature gating enhancement module guided by grid energy saliency defines a grid to delimit the region of interest and simulates an attention mechanism based on the saliency of energy, thereby enhancing the expressiveness of the feature map and improving the overall performance of the model. This method introduces attention focus during the feature extraction process, enabling the model to more accurately capture the key information in the image, thereby improving the accuracy of recognition or classification.

[0033] Here, a detailed description will be given using the microscopic feature map of the circuit pattern. First, the microscopic feature map of the circuit pattern is divided into grids to divide a large entire feature map into multiple smaller local regions, obtaining a set of microscopic local feature maps of the circuit pattern. This helps to perform more detailed analysis and extraction of local features within each small region. Then, the energy significance description factor of each local feature map is calculated to obtain a set of microscopic local energy significance description factors of the circuit pattern. Specifically, the energy significance description factor is obtained based on statistical features such as the maximum value, minimum value, mean value, and variance of each local feature map, so as to quantify the importance of each local region within the entire image domain range, thereby better identifying and focusing on those regions that are most likely to contain key information, providing a basis for subsequent data analysis. Subsequently, each energy significance description factor is input into a local feature adaptive selector based on a gating function to obtain a set of microscopic local significant modulation weights corresponding to the microscopic local feature maps of the circuit pattern. It should be understood that the gating mechanism can be regarded as an information filter, which can determine which information is important and which can be ignored based on the energy significance description factor of each local feature, and thus make dynamic adjustments according to different input data. This means that the model can adaptively optimize different input images, enabling the model to focus more on the key circuit parts in the microscopic image. Furthermore, each microscopic local significant modulation weight of the circuit pattern is used as a weight to weight each microscopic local feature map of the circuit pattern, so that the model attaches more importance to certain local regions with significant energy in the feature map. For example, those regions that may contain defects or key features are emphasized, and those unimportant parts are suppressed. In particular, the essence of the weighted enhancement step is attention application, because the attention of the model is guided to the most important parts of the image, which helps to improve the sensitivity of the model to small but important details in the image. After that, each weighted feature is aggregated according to the grid division method to obtain a microscopic local significant guidance enhanced feature map of the circuit pattern. Finally, in order to achieve uniform distribution of features, a feature dispersion module based on a dilated convolutional layer is used to process the microscopic local significant guidance enhanced feature map to obtain a microscopic optimized feature map of the circuit pattern, so as to reduce the discontinuity of feature expression at the boundaries caused by grid division. That is, through the dilation characteristics of dilated convolution, the features at the grid edges can be effectively smoothed and fused, thereby achieving more consistent feature expression throughout the feature map to eliminate the boundary effects introduced by grid division.

[0034] Specifically, Figure 4 In the production process of the ultra-fine circuit of the chip according to the embodiment of the present application, the flowchart of inputting the microscopic feature map of the circuit pattern and the design feature map of the circuit pattern into the feature gating enhancement module guided by grid energy significance to obtain the microscopic optimized feature map of the circuit pattern and the design optimized feature map of the circuit pattern. AsFigure 4 As shown, input the microscopic feature map of the circuit pattern and the design feature map of the circuit pattern into the feature gated enhancement module guided by grid energy saliency to obtain the microscopic optimized feature map of the circuit pattern and the design optimized feature map of the circuit pattern, including: S1441, perform grid division on the microscopic feature map of the circuit pattern to obtain a set of microscopic local feature maps of the circuit pattern; S1442, calculate the energy saliency description factors of each microscopic local feature map in the set of microscopic local feature maps of the circuit pattern to obtain a set of microscopic local energy saliency description factors; S1443, input the set of microscopic local energy saliency description factors into the local feature adaptive selector based on the gating function to obtain a set of microscopic local significant modulation weights; S1444, use each microscopic local significant modulation weight in the set of microscopic local significant modulation weights as weights to respectively weight each microscopic local feature map in the set of microscopic local feature maps of the circuit pattern to obtain a set of microscopic local enhanced feature maps; S1445, perform feature aggregation on the set of microscopic local enhanced feature maps in the manner of the grid division to obtain a microscopic local significant guidance enhanced feature map; S1446, input the microscopic local significant guidance enhanced feature map into the feature equalization and dispersion module based on the dilated convolutional layer to obtain the microscopic optimized feature map of the circuit pattern.

[0035] More specifically, in the embodiment of the present application, calculating the energy saliency description factors of each microscopic local feature map in the set of microscopic local feature maps of the circuit pattern to obtain a set of microscopic local energy saliency description factors includes: respectively extracting the maximum value and the minimum value of the microscopic local feature map to obtain the microscopic local feature maximum value and the microscopic local feature minimum value; calculating the difference between the microscopic local feature maximum value and the microscopic local feature minimum value to obtain the microscopic local feature difference value; respectively calculating the global mean and variance of the microscopic local feature map to obtain the microscopic local feature mean and the microscopic local feature variance; adding the value obtained by multiplying the microscopic local feature variance by the constant two and the microscopic local feature mean with the hyperparameter to obtain the microscopic local feature statistical modulation value; dividing the microscopic local feature difference value by the microscopic local feature statistical modulation value to obtain the microscopic local energy saliency description factor corresponding to the microscopic local feature map.

[0036] More specifically, in the embodiments of the present application, inputting the set of circuit pattern microscopic local energy significance description factors into a local feature adaptive selector based on a gating function to obtain a set of circuit pattern microscopic local significant modulation weights includes: calculating an exponential function with the negative of each circuit pattern microscopic local energy significance description factor in the set of circuit pattern microscopic local energy significance description factors as the exponent with the natural constant e as the base to obtain a set of circuit pattern microscopic local energy significance description exponential factors; calculating the reciprocal of the sum of each circuit pattern microscopic local energy significance description exponential factor in the set of circuit pattern microscopic local energy significance description exponential factors and the constant one to obtain a set of normalized circuit pattern microscopic local energy significance description factors; and inputting each normalized circuit pattern microscopic local energy significance description factor in the set of normalized circuit pattern microscopic local energy significance description factors into a gating function for masking processing to obtain the set of circuit pattern microscopic local significant modulation weights.

[0037] In the embodiments of the present application, specifically, inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module guided by grid energy significance to obtain a circuit pattern microscopic optimized feature map and a circuit pattern design optimized feature map includes: inputting the circuit pattern microscopic feature map into the feature gating enhancement module guided by grid energy significance and processing it according to the following significant gating enhancement formula to obtain the circuit pattern microscopic optimized feature map; where the significant gating enhancement formula is:

[0038] Where is the circuit pattern microscopic feature map, is a grid division operation, are respectively each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps, is the th circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps, and respectively extract the maximum and minimum values in the feature map, and are respectively 's mean and variance, is a hyperparameter, represents the circuit pattern microscopic local energy significance description factor corresponding to the th circuit pattern microscopic local feature map, is a masking process, is the The circuit pattern microscopic local significant modulation weight corresponding to the microscopic local feature map of the circuit pattern, where θ is a predetermined threshold, For performing a feature aggregation operation on each weighted feature map, is the microscopic local significant guidance enhanced feature map of the circuit pattern, is an atrous convolution operation, is the microscopic optimized feature map of the circuit pattern. Similarly, the encoding method of the design image of the circuit pattern is also as shown in the above formula.

[0039] In step S145, the microscopic optimized feature map of the circuit pattern and the design optimized feature map of the circuit pattern are input into a sequence - to - sequence matching network based on energy - intensive interaction distribution to obtain a sequence - to - sequence semantic matching coefficient. It should be understood that in order to more finely evaluate the semantic matching similarity between the microscopic image and the design image, thereby detecting possible defects or deviations and improving the accuracy of defect detection, in the technical solution of this application, the microscopic optimized feature map of the circuit pattern and the design optimized feature map of the circuit pattern are input into a sequence - to - sequence matching network based on energy - intensive interaction distribution to obtain a sequence - to - sequence semantic matching coefficient. Specifically, first, the microscopic optimized feature map of the circuit pattern and the design optimized feature map of the circuit pattern are unfolded to obtain a sequence of microscopic optimized feature vectors of the circuit pattern and a sequence of design optimized feature vectors of the circuit pattern, providing a basis for subsequent local regions. Then, feature selection is performed on the sequence of vectors obtained after unfolding to select the features most relevant to the target variable and eliminate irrelevant or redundant features, obtaining a sequence of selected feature vectors. Next, the energy co - response values between the pairs of selected feature vectors are calculated to quantify the interaction and cooperation effect between the feature vectors. That is, here, by capturing the local fine - grained semantic association interaction between the microscopic features and the design features, the semantic association matching relationship between local regions is more carefully characterized to obtain a microscopic - design optimized feature co - energy fine - grained global distribution matrix of the circuit pattern. Subsequently, atrous convolution encoding is performed on the global distribution matrix to capture semantic association interaction relationships in a wider range and depict the overall semantic association to obtain a microscopic - design optimized feature co - energy fine - grained global distribution feature matrix. Finally, the global distribution feature matrix is input into a sequence - to - sequence matching degree measurement network to perform semantic similarity matching calculation between the two sequences to obtain the final sequence - to - sequence semantic matching coefficient.

[0040] Specifically, Figure 5 In the production process of the ultra - fine circuit of the chip according to the embodiment of the present application, the flowchart of inputting the microscopic optimized feature map of the circuit pattern and the design optimized feature map of the circuit pattern into a sequence - to - sequence matching network based on energy - intensive interaction distribution to obtain a sequence - to - sequence semantic matching coefficient is as follows. As Figure 5As shown, inputting the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern into the inter-sequence matching network based on the energy-intensive interaction distribution to obtain the inter-sequence semantic matching coefficient includes: S1451, expanding the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern to obtain a sequence of microscopic optimization feature vectors of the circuit pattern and a sequence of design optimization feature vectors of the circuit pattern; S1452, performing feature selection on the sequence of microscopic optimization feature vectors of the circuit pattern and the sequence of design optimization feature vectors of the circuit pattern to obtain a selected sequence of microscopic optimization feature vectors of the circuit pattern and a selected sequence of design optimization feature vectors of the circuit pattern; S1453, calculating the energy collaborative response value between any pair of the selected microscopic optimization feature vectors of the circuit pattern and the selected design optimization feature vectors of the circuit pattern in the selected sequence of microscopic optimization feature vectors of the circuit pattern and the selected sequence of design optimization feature vectors of the circuit pattern to obtain a microscopic-design optimization feature collaborative energy fine-grained global distribution matrix of the circuit pattern; S1454, performing dilated convolution coding on the microscopic-design optimization feature collaborative energy fine-grained global distribution matrix of the circuit pattern to obtain a microscopic-design optimization feature collaborative energy fine-grained global distribution feature matrix of the circuit pattern; S1455, inputting the microscopic-design optimization feature collaborative energy fine-grained global distribution feature matrix of the circuit pattern into the inter-sequence matching degree measurement network to obtain the inter-sequence semantic matching coefficient.

[0041] More specifically, in the embodiment of the present application, performing feature selection on the sequence of microscopic optimization feature vectors of the circuit pattern and the sequence of design optimization feature vectors of the circuit pattern to obtain a selected sequence of microscopic optimization feature vectors of the circuit pattern and a selected sequence of design optimization feature vectors of the circuit pattern includes: using a first importance measurement function to calculate the microscopic optimization importance factor of each microscopic optimization feature vector in the sequence of microscopic optimization feature vectors of the circuit pattern; based on the comparison between each microscopic optimization importance factor and a first preset threshold, performing feature selection on the sequence of microscopic optimization feature vectors of the circuit pattern to obtain the selected sequence of microscopic optimization feature vectors of the circuit pattern; using a second importance measurement function to calculate the design optimization importance factor of each design optimization feature vector in the sequence of design optimization feature vectors of the circuit pattern; based on the comparison between each design optimization importance factor and a second preset threshold, performing feature selection on the sequence of design optimization feature vectors of the circuit pattern to obtain the selected sequence of design optimization feature vectors of the circuit pattern.

[0042] In the embodiments of the present application, specifically, calculating the circuit pattern microscopic optimization importance factor of each circuit pattern microscopic optimization feature vector in the sequence of the circuit pattern microscopic optimization feature vectors by using a first importance metric function includes: calculating the circuit pattern microscopic optimization importance factor of each circuit pattern microscopic optimization feature vector in the sequence of the circuit pattern microscopic optimization feature vectors by using the first importance metric function according to the following formula; wherein, the calculation formula is:

[0043]

[0044] Wherein, are respectively each circuit pattern microscopic optimization feature vector in the sequence of the circuit pattern microscopic optimization feature vectors, is the circuit pattern microscopic weight matrix, is the circuit pattern microscopic bias vector, represents the tanh function, is the weight coefficient vector, are the circuit pattern microscopic optimization importance factors.

[0045] More specifically, in the embodiments of the present application, calculating the energy co-response value between any pair of the selected circuit pattern microscopic optimization feature vectors and the selected circuit pattern design optimization feature vectors in the sequence of the selected circuit pattern microscopic optimization feature vectors and the sequence of the selected circuit pattern design optimization feature vectors to obtain a circuit pattern microscopic-pattern design optimization feature co-energy fine-grained global distribution matrix, including: calculating the element-wise division between the selected circuit pattern microscopic optimization feature vector and the selected circuit pattern design optimization feature vector to obtain a selected circuit pattern microscopic-design local area matching feature vector; extracting the maximum value of the selected circuit pattern microscopic-design local area matching feature vector to obtain a selected circuit pattern microscopic-design local area matching feature maximum value; respectively calculating the mean and variance of the selected circuit pattern microscopic-design local area matching feature vector to obtain a selected circuit pattern microscopic-design local area matching feature mean value and a selected circuit pattern microscopic-design local area matching feature variance value; multiplying the value obtained by adding the selected circuit pattern microscopic-design local area matching feature variance value and the bias term by four to obtain a first energy co-response value of the selected circuit pattern microscopic-design local area matching feature; calculating the square of the difference between the selected circuit pattern microscopic-design local area matching feature maximum value and the selected circuit pattern microscopic-design local area matching feature mean value to obtain a selected circuit pattern microscopic-design local area feature difference value; adding the modulated selected circuit pattern microscopic-design local area matching feature variance obtained by multiplying the selected circuit pattern microscopic-design local area matching feature variance value by two, the value obtained by multiplying the bias term by two, and the selected circuit pattern microscopic-design local area feature difference value to obtain a second energy co-response value of the selected circuit pattern microscopic-design local area matching feature; dividing the first energy co-response value of the selected circuit pattern microscopic-design local area matching feature by the second energy co-response value of the selected circuit pattern microscopic-design local area matching feature to obtain the energy co-response value between the selected circuit pattern microscopic optimization feature vector and the selected circuit pattern design optimization feature vector.

[0046] In the embodiments of the present application, specifically, inputting the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern into the inter-sequence matching network based on the energy-intensive interaction distribution to obtain the inter-sequence semantic matching coefficient includes: expanding the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern to obtain a sequence of microscopic optimization feature vectors of the circuit pattern and a sequence of design optimization feature vectors of the circuit pattern; inputting the sequence of microscopic optimization feature vectors of the circuit pattern and the sequence of design optimization feature vectors of the circuit pattern into the inter-sequence matching network based on the energy-intensive interaction distribution, and processing them with the following inter-sequence matching formula to obtain the inter-sequence semantic matching coefficient; wherein, the inter-sequence matching formula is: Wherein, and are respectively the sequence of microscopic optimization feature vectors of the circuit pattern and the sequence of design optimization feature vectors of the circuit pattern, is for performing a feature selection operation, and are respectively the sequence of selected microscopic optimization feature vectors of the circuit pattern and the sequence of selected design optimization feature vectors of the circuit pattern, and respectively represent the th selected microscopic optimization feature vector of the circuit pattern and the th selected design optimization feature vector of the circuit pattern in the sequence of selected microscopic optimization feature vectors of the circuit pattern and the sequence of selected design optimization feature vectors of the circuit pattern, represents calculating the energy collaborative response value between two vectors, is the eigenvalue at the th position in the microscopic-circuit pattern design optimization feature collaborative energy fine-grained global distribution matrix, is to extract the maximum value of the vector, is the th selected microscopic optimization feature vector of the circuit pattern and the th selected design optimization feature vector of the circuit pattern and the selected microscopic-circuit design local area matching feature vector therebetween, and are respectively the mean and variance, is the bias term, E is the microscopic-circuit pattern design optimization feature collaborative energy fine-grained global distribution matrix, is the dilated convolution encoding, is the microscopic-circuit pattern design optimization feature collaborative energy fine-grained global distribution feature matrix, is the inter-sequence matching degree measurement operation, is the semantic matching coefficient between the sequences.

[0047] In step S146, based on the semantic matching coefficient between the sequences, the defect detection result is generated. Specifically, in the embodiments of the present application, generating the defect detection result based on the semantic matching coefficient between the sequences includes: generating the defect detection result based on the comparison between the semantic matching coefficient between the sequences and a preset threshold. That is, the defect detection result is automatically generated by comparing the semantic interaction matching coefficient obtained by performing sequence semantic matching on the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern with the preset threshold. In this way, tiny defects that are difficult to discover by traditional methods can be identified, improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and wafers of different batches, improving the flexibility and automation level of the detection system.

[0048] In a preferred example, since the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern respectively represent local spatial enhanced image semantic features based on the energy significance of the grid distribution of image semantic features of the microscopic image and the design image of the circuit pattern, when the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern are input into the sequence matching network based on the energy-intensive interaction distribution, there will also be an aggregation matching offset of the image semantic features caused by the inconsistent energy-intensive interaction matching distribution of the local spatial image semantic distribution based on the difference in the semantic distribution of the source images, thereby affecting the accuracy of the semantic matching coefficient between the sequences.

[0049] Therefore, when the present application inputs the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern into the inter-sequence matching network based on the energy-intensive interaction distribution to obtain the inter-sequence semantic matching coefficient, it jointly optimizes the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern, including the steps of: respectively expanding the microscopic optimization feature map of the circuit pattern and the design optimization feature map of the circuit pattern into a microscopic optimization feature vector of the circuit pattern and a design optimization feature vector of the circuit pattern; cascading the microscopic optimization feature vector of the circuit pattern and the design optimization feature vector of the circuit pattern into a microscopic-design optimization feature vector of the circuit pattern; subtracting the 0-norm of the microscopic-design optimization feature vector of the circuit pattern from the length of the microscopic-design optimization feature vector of the circuit pattern to obtain a microscopic-design optimization isolated representation value of the circuit pattern; calculating the base-2 logarithm of the sum of the square of the microscopic-design optimization isolated representation value of the circuit pattern and the microscopic-design optimization isolated representation value of the circuit pattern to obtain a microscopic-design optimization information order value of the circuit pattern; calculating a power function with each eigenvalue of the microscopic-design optimization feature vector of the circuit pattern as the base and the difference between the microscopic-design optimization isolated representation value of the circuit pattern minus one as the exponent, and performing a dot product with the microscopic-design optimization information order value of the circuit pattern to obtain a microscopic-design optimization prior vector of the circuit pattern; performing a dot product on the microscopic-design optimization feature vector of the circuit pattern with the difference between the microscopic-design optimization isolated representation value of the circuit pattern minus one, and then performing a dot product with the reciprocal of the microscopic-design optimization isolated representation value of the circuit pattern to obtain a microscopic-design optimization field constraint vector of the circuit pattern; calculating an exponential function with the natural constant e as the base and each eigenvalue of the microscopic-design optimization field constraint vector of the circuit pattern as the exponent to obtain a microscopic-design optimization field bias vector of the circuit pattern; performing a dot addition on the microscopic-design optimization prior vector of the circuit pattern and the microscopic-design optimization field bias vector of the circuit pattern to obtain an optimized microscopic-design optimization feature vector of the circuit pattern; splitting the optimized microscopic-design optimization feature vector of the circuit pattern into an optimized microscopic optimization feature vector of the circuit pattern and an optimized design optimization feature vector of the circuit pattern, and restoring them to an optimized microscopic optimization feature map of the circuit pattern and an optimized design optimization feature map of the circuit pattern.

[0050] Among them, the optimization process of the microscopic-design optimization feature vector of the circuit pattern is expressed as:

[0051] Among them, is the microscopic-design optimization feature vector of the circuit pattern, represents the length of the microscopic-design optimization feature vector of the circuit pattern, represents the 0-norm of the vector, and n represents the microscopic-design optimization isolated representation value of the circuit pattern. Denotes dot product by position, For calculating a power function with each eigenvalue of the micro - design optimization feature vector of the circuit pattern as the base and the difference between the isolated representation value of the micro - design optimization of the circuit pattern minus one as the exponent, Denotes logarithm to the base 2, Denotes addition by position, Denotes the natural exponential function, Denotes the optimized micro - design optimization feature vector of the circuit pattern.

[0052] Thus, for the high - dimensional feature manifolds of the micro - optimized feature map of the circuit pattern and the design - optimized feature map of the circuit pattern, a vector field representation with the eigenvalues of the feature set as the aggregation dimension is used. The superimposed value of the vector field of the micro - design optimization feature vector of the circuit pattern at the isolated zero position is used as the order information to fix the local position of the eigenvalues of its feature set, and a bias for the reversibility of the feature regression distribution field of the micro - design optimization feature vector of the circuit pattern is added as a reward to achieve the mapping target tracking of the regression distribution of the micro - design optimization feature vector of the circuit pattern for the eigenvalue position, so that the feature sets of the micro - optimized feature map of the circuit pattern and the design - optimized feature map of the circuit pattern sense the mapping migration to the aggregation distribution, thereby improving the understandability of the image semantic feature matching mapping of the micro - optimized feature map of the circuit pattern and the design - optimized feature map of the circuit pattern through the accuracy of the semantic matching coefficient between sequences. In this way, tiny defects that are difficult to discover by traditional methods can be identified, improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and different batches of wafers, improving the flexibility and automation level of the detection system.

[0053] In summary, the production process of the ultra - fine circuit of the chip based on the embodiments of the present application is clarified. It uses deep - learning - based image processing and analysis techniques to extract features and optimize significant features of the micro - image of the circuit pattern and the design image of the circuit pattern, and automatically generates a defect detection result based on the comparison between the semantic interaction matching coefficient between the optimized micro - image and the optimized design image features and a preset threshold. In this way, tiny defects that are difficult to discover by traditional methods can be identified, improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and different batches of wafers, improving the flexibility and automation level of the detection system.

[0054] The basic principles of the present application have been described above in connection with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not limitations, and it cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. Additionally, the specific details of the above application are only for the purposes of illustration and facilitating understanding, rather than limitations. The above details do not limit the present application to necessarily implement using the above specific details.

Claims

1. A production process for ultra-fine circuits on a chip, characterized in that: include: Provide silicon wafers; Placing the silicon wafer in a high temperature furnace for oxidation treatment to form a layer of silicon dioxide film on the surface of the silicon wafer to obtain an oxidized silicon wafer; Coating a layer of photoresist on the silicon oxide wafer, projecting a designed circuit pattern onto the photoresist using a photolithography machine, and performing exposure treatment with ultraviolet rays to obtain a circuit pattern; Performing defect detection based on a microscopic image on the circuit pattern to obtain a defect detection result; In response to the defect detection result indicating that there is no defect, etching the silicon oxide wafer having the circuit pattern to remove the exposed silicon layer and form the desired ultra-fine circuit; Based on circuit design requirements, impurity atoms are introduced into specific regions to change the electrical properties of the specific regions, and interconnection lines are made to obtain a chip; Performing an electrical performance test on the chip to obtain a test result; In response to the test result indicating that there is no defect, packaging the chip; Wherein, performing defect detection based on a microscopic image on the circuit pattern to obtain a defect detection result includes: collecting a microscopic image of the circuit pattern; extracting a design image of the circuit pattern from a database; Inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map respectively; Inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module based on grid energy significance guidance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map; Inputting the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map into an inter-sequence matching network based on energy-intensive interaction distribution to obtain an inter-sequence semantic matching coefficient; Based on the semantic matching coefficient between the sequences, generating the defect detection result; The circuit pattern microscopic feature map and the circuit pattern design feature map are input into a feature gating enhancement module based on grid energy significance guidance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map, including: Performing grid division on the circuit pattern microscopic feature map to obtain a set of circuit pattern microscopic local feature maps; Calculating the energy significance description factor of each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps to obtain a set of circuit pattern microscopic local energy significance description factors; Inputting the set of circuit pattern microscopic local energy significance description factors into a local feature adaptive selector based on a gating function to obtain a set of circuit pattern microscopic local significance modulation weights; Using each circuit pattern microscopic local significant modulation weight in the set of circuit pattern microscopic local significant modulation weights as a weight, weighting each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps to obtain a set of circuit pattern microscopic local enhanced feature maps; Performing feature aggregation on the set of the circuit pattern microscopic local enhancement feature maps according to the grid division method to obtain the circuit pattern microscopic local significant guidance enhancement feature map; The circuit pattern microscopic local significant guided enhanced feature map is input into a feature dispersion module based on a hole convolution layer to obtain the circuit pattern microscopic optimized feature map.

2. The process for producing ultra-fine circuits on a chip according to claim 1, characterized in that: The microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map, including: the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into a circuit pattern feature extractor based on a hole convolutional neural network model to obtain the circuit pattern microscopic feature map and the circuit pattern design feature map.

3. The process for producing ultra-fine circuits on a chip according to claim 2, characterized in that: Calculating the energy significance description factor of each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps to obtain a set of circuit pattern microscopic local energy significance description factors, including: Respectively extracting the maximum value and the minimum value of the circuit pattern microscopic local feature map to obtain the circuit pattern microscopic local feature maximum value and the circuit pattern microscopic local feature minimum value; Calculating the difference between the maximum value of the microscopic local feature of the circuit pattern and the minimum value of the microscopic local feature of the circuit pattern to obtain a difference value of the microscopic local feature of the circuit pattern; Respectively calculating the global mean and variance of the circuit pattern microscopic local feature map to obtain the circuit pattern microscopic local feature mean and the circuit pattern microscopic local feature variance; The value obtained by multiplying the variance of the microscopic local feature of the circuit pattern by a constant of two and the mean value of the microscopic local feature of the circuit pattern are added to the hyperparameter to obtain a statistical modulation value of the microscopic local feature of the circuit pattern; The circuit pattern microscopic local feature difference value is divided by the circuit pattern microscopic local feature statistical modulation value to obtain a circuit pattern microscopic local energy significance description factor corresponding to the circuit pattern microscopic local feature map.

4. The process for producing ultra-fine circuits on a chip according to claim 3, characterized in that: The set of circuit pattern microscopic local energy significance description factors is input into a local feature adaptive selector based on a gating function to obtain a set of circuit pattern microscopic local significance modulation weights, including: Calculating an exponential function with the natural constant e as the base and the negative number of each circuit pattern microscopic local energy significance description factor in the set of circuit pattern microscopic local energy significance description factors as the exponent to obtain a set of circuit pattern microscopic local energy significance description exponential factors; Calculating the reciprocal of the sum of each circuit pattern microscopic local energy significance description index factor in the set of circuit pattern microscopic local energy significance description index factors and a constant of one to obtain a set of normalized circuit pattern microscopic local energy significance description factors; Each normalized circuit pattern microscopic local energy significance description factor in the set of normalized circuit pattern microscopic local energy significance description factors is input into a gating function for masking processing to obtain a set of circuit pattern microscopic local significance modulation weights.

5. The process for producing ultra-fine circuits on a chip according to claim 4, characterized in that: Inputting the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map into an inter-sequence matching network based on energy-intensive interaction distribution to obtain an inter-sequence semantic matching coefficient, including: Expanding the circuit pattern microscopic optimization feature map and the circuit pattern design optimization feature map to obtain a sequence of circuit pattern microscopic optimization feature vectors and a sequence of circuit pattern design optimization feature vectors; Performing feature selection on the sequence of circuit pattern micro-optimization feature vectors and the sequence of circuit pattern design optimization feature vectors to obtain a sequence of selected circuit pattern micro-optimization feature vectors and a sequence of selected circuit pattern design optimization feature vectors; Calculating the energy synergy response value between any pair of selected circuit pattern micro-optimization feature vectors and selected circuit pattern design optimization feature vectors in the sequence of selected circuit pattern micro-optimization feature vectors and the sequence of selected circuit pattern design optimization feature vectors to obtain a circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution matrix; Performing dilated convolution coding on the circuit pattern microscopic-pattern design optimization feature collaborative energy fine-grained global distribution matrix to obtain a circuit pattern microscopic-pattern design optimization feature collaborative energy fine-grained global distribution feature matrix; The circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution feature matrix is ​​input into the sequence matching degree measurement network to obtain the sequence semantic matching coefficient.

6. The process for producing ultra-fine circuits on a chip according to claim 5, characterized in that: Performing feature selection on the sequence of circuit pattern micro-optimization feature vectors and the sequence of circuit pattern design optimization feature vectors to obtain a sequence of selected circuit pattern micro-optimization feature vectors and a sequence of selected circuit pattern design optimization feature vectors, comprising: Calculating the circuit pattern micro-optimization importance factor of each circuit pattern micro-optimization feature vector in the sequence of circuit pattern micro-optimization feature vectors using a first importance metric function; Based on the comparison between each of the circuit pattern micro-optimization importance factors and a first preset threshold, feature selection is performed on the sequence of circuit pattern micro-optimization feature vectors to obtain the sequence of selected circuit pattern micro-optimization feature vectors; calculating a circuit pattern design optimization importance factor of each circuit pattern design optimization feature vector in the sequence of circuit pattern design optimization feature vectors using a second importance metric function; Based on the comparison between each of the circuit pattern design optimization importance factors and a second preset threshold, feature selection is performed on the sequence of circuit pattern design optimization feature vectors to obtain the sequence of selected circuit pattern design optimization feature vectors.

7. The process for producing ultra-fine circuits on a chip according to claim 6, characterized in that: Calculating the energy synergy response value between any pair of selected circuit pattern micro-optimization feature vectors and selected circuit pattern design optimization feature vectors in the sequence of the selected circuit pattern micro-optimization feature vectors and the sequence of the selected circuit pattern design optimization feature vectors to obtain a circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution matrix, including: Calculating the position-by-position division between the selected circuit pattern microscopic optimization feature vector and the selected circuit pattern design optimization feature vector to obtain a selected circuit pattern microscopic-design local area matching feature vector; Extracting the maximum value of the selected circuit pattern microscopic-designed local area matching feature vector to obtain the selected circuit pattern microscopic-designed local area matching feature maximum value; Respectively calculating the mean and variance of the selected circuit pattern microscopic-designed local area matching feature vector to obtain the selected circuit pattern microscopic-designed local area matching feature mean and the selected circuit pattern microscopic-designed local area matching feature variance; The value obtained by adding the selected circuit pattern microscopic-designed local area matching feature variance and the bias term is multiplied by four to obtain the selected circuit pattern microscopic-designed local area matching feature first energy synergy response value; Calculating the square of the difference between the maximum value of the selected circuit pattern microscopic-designed local area matching feature and the mean value of the selected circuit pattern microscopic-designed local area matching feature to obtain a selected circuit pattern microscopic-designed local area feature difference value; The second energy synergy response value of the selected circuit pattern microscopic-designed local area matching feature is obtained by adding the modulated selected circuit pattern microscopic-designed local area matching feature variance obtained by multiplying the selected circuit pattern microscopic-designed local area matching feature variance by two, the value obtained by multiplying the bias term by two, and the selected circuit pattern microscopic-designed local area feature difference value; The energy synergy response value between the selected circuit pattern microscopic-designed local area matching feature vector and the selected circuit pattern design optimized feature vector is obtained by dividing the first energy synergy response value of the selected circuit pattern microscopic-designed local area matching feature vector by the second energy synergy response value of the selected circuit pattern microscopic-designed local area matching feature vector.

8. The process for producing ultra-fine circuits on a chip according to claim 7, characterized in that: Generating the defect detection result based on the semantic matching coefficient between sequences includes: generating the defect detection result based on a comparison between the semantic matching coefficient between sequences and a preset threshold.

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