Dynamic adjustment of threshold voltage offset for word line groups

Abstract

The invention relates to dynamic adjustment of threshold voltage offset for word line groups. A system includes a memory device; and a processing device operably coupled with the memory device to perform operations including: receiving a request to perform a read operation on a set of memory cells of the memory device; identifying a group of word lines coupled to the set of memory cells of the memory device; identifying a threshold voltage offset bin associated with the set of memory cells; determining a current temperature associated with the set of memory cells; determining a read mask identifier associated with the set of memory cells based on the threshold voltage offset bin and the current temperature; determining a set of threshold voltage offsets associated with the set of memory cells based on the read mask identifier and the word line group; and performing the read operation using the set of threshold voltage offsets.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to dynamic adjustment of threshold voltage offsets for groups of word lines. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a system comprising: a memory device; and a processing device operably coupled to the memory device to perform operations comprising: receiving a request to perform a read operation on a group of memory cells of the memory device; identifying a word line group coupled to the group of memory cells of the memory device; identifying a threshold voltage offset bin associated with the group of memory cells; determining a current temperature associated with the group of memory cells; determining a read mask identifier associated with the group of memory cells based on the threshold voltage offset bin and the current temperature; determining a set of threshold voltage offsets associated with the group of memory cells based on the read mask identifier and the word line group; and performing the read operation using the set of threshold voltage offsets.

[0004] In another aspect, the present disclosure provides a method comprising: receiving, by a processing device, a request to perform a read operation on a group of memory cells of a memory device; identifying a word line group coupled to the group of memory cells of the memory device; identifying a threshold voltage offset bin associated with the group of memory cells; determining a current temperature associated with the group of memory cells; determining a set of threshold voltage offsets associated with the group of memory cells based on the threshold voltage offset bin, the current temperature, and the word line group; and performing the read operation using the set of threshold voltage offsets.

[0005] In another aspect, the present disclosure provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to perform a read operation on a group of memory cells of a memory device; identifying a word line group coupled to the group of memory cells of the memory device; identifying a threshold voltage offset bin associated with the group of memory cells; determining a current temperature associated with the group of memory cells; determining a read mask identifier associated with the group of memory cells based on the threshold voltage offset bin and the current temperature; determining a set of threshold voltage offsets associated with the group of memory cells based on the read mask identifier and the word line group; and performing the read operation using the set of threshold voltage offsets. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more completely understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2A Schematically illustrates a temporal voltage shift caused by a slow charge loss exhibited by a three-level memory cell according to some embodiments of the present disclosure.

[0009] Figure 2B A set of predefined threshold voltage offset bins according to an embodiment of the present disclosure is schematically illustrated.

[0010] Figure 3 is an example of a set of threshold voltage offset bins determined according to some embodiments of the present disclosure.

[0011] Figure 4 is a flow chart of an example method for updating a read level voltage offset of a word line group according to some embodiments of the present disclosure.

[0012] Figures 5 to 6 is an example of a data structure for updating a read level voltage offset of a word line group according to some embodiments of the present disclosure.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to dynamic adjustment of threshold voltage offsets of word line groups. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0015] The memory subsystem may utilize one or more memory devices (including any combination of different types of nonvolatile memory devices and / or volatile memory devices) to store data provided by the host system. One example of a nonvolatile memory device is a NAND memory device. Other examples of nonvolatile memory devices are described below in conjunction with Figure 1 A nonvolatile memory device is a package of one or more dies. Each die includes one or more planes. For some types of nonvolatile memory devices (such as NAND devices), each plane includes a set of physical blocks. Each block consists of a set of pages. Each page includes a set of memory cells. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary information bits and have various logical states related to the number of bits stored. The logical state can be represented by a binary value such as "0" and "1" or a combination of such values.

[0016] A memory device may consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells of a memory device, which together with one or more bit lines are used to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. A block refers hereinafter to a unit of a memory device for storing data and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form separate partitions (e.g., planes) of a memory device in order to allow concurrent operations to occur on each plane.

[0017] The memory device includes a plurality of memory cells capable of storing one or more bits of information depending on the memory cell type. One type of cell is a single-level cell (SLC), which stores 1 bit per cell and defines a plurality of memory cells that correspond to respective V T Another type of cell is the multi-level cell (MLC), which stores 2 bits per cell and defines two logical states (“states”) corresponding to the respective V T The 4 states of the voltage level (“11” or “L0”, “10” or “L1”, “01” or “L2” and “00” or “L3”) are defined. Another type of cell is a triple-level cell (TLC), which stores 3 bits per cell and defines the corresponding VT 8 states of the level ("111" or "L0", "110" or "L1", "101" or "L2", "100" or "L3", "011" or "L4", "010" or "L5", "001" or "L6", and "000" or "L7"). Another type of cell is a quad-level cell (QLC), which stores 4 bits per cell and defines 16 states L0 to L15, where L0 corresponds to "1111" and L15 corresponds to "0000". Another type of cell is a penta-level cell (PLC), which stores 5 bits per cell and defines 32 states. Other types of cells are also contemplated. Thus, an n-level cell may use 2 n The memory device may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, etc., or any combination thereof. For example, the memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of cells.

[0018] Various data operations (such as writing, reading, erasing, etc.) can be performed by the memory subsystem. The data operation can be a host-initiated operation. For example, the host system can initiate a data operation (such as writing, reading, erasing, etc.) on the memory subsystem. The host system can send an access request (such as a write command, a read command) to the memory subsystem to, for example, store data on a memory device at the memory subsystem and read data from a memory device on the memory subsystem. The data to be read or written specified by the host request is referred to as "host data" hereinafter. The host request may include logical address information (such as a logical block address (LBA), a namespace) of the host data, which is the location associated with the host data by the host system. The logical address information (such as an LBA, a namespace) may be part of the metadata of the host data. The metadata may also include error handling data (such as error correction code (ECC) codeword parity data), data version (such as for distinguishing the age of written data), valid bitmap (which LBA or logical transfer unit contains valid data), etc.

[0019] A memory cell can be programmed (written) by applying a specific voltage to the cell, which causes a charge to be retained by the cell. For example, a voltage signal V CG A control electrode may be applied to the cell to turn on the cell to allow current to flow across the cell between the source electrode and the drain electrode. More specifically, for each individual cell (on which a charge Q is stored), there may be a threshold control gate voltage V T (also called the “threshold voltage”), which causes the source-drain current to flow at a controlled gate voltage (V CG ) is lower than the threshold voltage (V CG <V T). The current is lower when the control gate voltage exceeds the threshold voltage (V CG >V T ) and then increases significantly. Because the actual geometry of the electrodes and gates varies from cell to cell, the threshold voltage may be different even for cells implemented on the same die. Therefore, a cell can be characterized by a distribution of threshold voltages, P(Q, V T )=dW / dV T , where dW represents the threshold voltage of any given cell when a charge Q is placed on the cell in the interval [V T ,V T +dV T ]. A valley may be located between pairs of adjacent programming distributions. A valley may refer to a region or area between a pair of adjacent programming distributions. The relative width of a valley may be approximated by a valley margin. A valley margin may refer to a relative width or relative margin between pairs of adjacent programming distributions. A valley margin may refer to an absolute measurement in volts, such as millivolts (mV), between two adjacent programming distributions.

[0020] The valley margin can also be called the read window. For example, in an SLC cell, there is a T As another example, in an MLC cell, there are 4 V T As another example, in a TLC cell, there are 3 read windows for 8 V T The read window budget (RWB) refers to the cumulative value of the read windows.

[0021] A memory device may exhibit a threshold voltage distribution P(Q, V) that is narrower than the operating range of control voltages tolerated by the device's cells. T ). Therefore, multiple non-overlapping distributions P(Q k ,V T ) (“valley”) can fit within the operating range, allowing the charge Q to be stored and reliably detected k , k=1, 2, 3, ... The distribution (valleys) are interspersed with voltage intervals ("valley margins") where cells of the device have none (or very few) of their threshold voltages. Thus, such valley margins can be used to separate various charge states Q k , the logical state of a cell can be determined by detecting the cell's corresponding threshold voltage V during a read operation. T Specifically, a read operation can be performed by comparing the measured threshold voltage V exhibited by the memory cell toT This is performed with one or more reference voltage levels ("read level thresholds") corresponding to known valley margins (eg, the center of the margin) of the memory device.

[0022] Due to a phenomenon called slow charge loss (SCL), the threshold voltage V T Can change over time as the charge of the cell decreases, a process sometimes called "time voltage shift" (TVS). TVS can include different components, such as intrinsic charge loss, system charge loss, fast charge loss, etc. TVS generally increases with the number of program erase cycles (PEC), temperature, and programming voltage. TVS can show significant die-to-die variation and word line group (WGR)-to-word line group (WGR) variation. Since a typical cell stores negatively charged particles (electrons), the loss of electrons causes the threshold voltage to move along the voltage axis toward a lower threshold voltage, V T The threshold voltage may change rapidly first (immediately after programming of the memory cell) and then in an approximately log-linear or power-law fashion (ΔV T (t)=–C*t b ) slows down over a longer period of time.

[0023] In some memory subsystems, a TVS can be used to generate a voltage drop by tracking the time elapsed since a programming event and the environmental conditions (e.g., temperature) of a particular memory partition (block, plane, etc.) and offsetting the per-valley voltage used during a read operation by ΔV. T associated to mitigate, where the standard “reference read level” threshold voltage V T Modified by voltage offset: V T →V T +ΔV T , where ΔV T is negative. “Base read level” refers to the initial threshold voltage level exhibited by a memory cell immediately after programming. Although TVS is a continuous process and compensates for ΔV T (t) may be a continuous time function, but in some embodiments, sufficient offset accuracy may be achieved by a discrete number of threshold voltage offset "bins." For example, the voltage offset associated with each threshold voltage offset bin minimizes the error rate when applied to a reference read level, i.e., there are no other threshold voltage offsets set for a particular bin that result in a lower error rate.

[0024] In some embodiments, the memory subsystem may employ a block family based error avoidance strategy, in which the TVS of the programming blocks grouped by block families are selectively tracked, and an appropriate voltage offset based on the block affiliation with a particular block family is applied to the reference read level in order to perform a read operation. A "block family" refers to a group of blocks that have been programmed within a specified time window and a specified temperature window. Since the time and temperature that have passed after programming are the main factors affecting the TVS, it is assumed that all blocks and / or partitions within a single block family exhibit similar threshold voltage distributions in the memory cells and therefore require the same voltage offset to be applied to the reference read level for read operations. Block families may be created asynchronously with respect to block programming events. In an illustrative example, a new block family may be created whenever a specified period (e.g., a predetermined number of minutes) has passed since the creation of the last block family or the reference temperature of the memory cell has changed by more than a specified threshold. The memory subsystem controller may maintain identifiers of valid block families, which are associated with the one or more blocks when they are programmed.

[0025] In order to implement a block-family-based error avoidance strategy, the memory subsystem controller may periodically perform a calibration process ("calibration scan") in order to evaluate data state metrics (e.g., bit error rates) in order to associate each block family with one of the predefined threshold voltage offset bins, which in turn are associated with the voltage offset applied for read operations. The associations of blocks to block families and block families to threshold voltage offset bins may be stored in corresponding metadata tables maintained by the memory subsystem controller. The calibration scan may be periodically performed with respect to blocks of the memory device to determine if the read levels of the blocks are offset and to update the bin associations accordingly. For example, the memory subsystem controller may perform a calibration scan with respect to a set of pages that may be addressed by a selected set of word lines of the block (e.g., a randomly selected set of word lines) and to update the threshold voltage offset bins associated with the selected set of word lines of the block accordingly. However, updating the threshold voltage offset bins is typically applied not only to the selected set of word lines of the block, but also to the remaining word lines in the block. In the presence of large inter-WGR variations, applying such threshold voltage offset bins to all word lines in the block will result in large read position loss (RPL), resulting in degraded read performance.

[0026] Aspects of the present disclosure address the above and other shortcomings by implementing a memory subsystem that updates a threshold voltage offset associated with a word line group of a memory device. A memory subsystem controller may receive a read command to perform a read operation on a memory device. The read command specifies a logical address that can be used to identify a group of memory cells (e.g., a block) of the memory device.

[0027] The memory subsystem controller may identify one or more word line groups associated with the group of memory cells specified by the read command. In some implementations, the word lines of the memory device may be grouped based on their respective physical locations. For example, a word line group may be formed to include all word lines within a specific distance between the first and last word lines in the word line group. The memory subsystem controller may use the logical address specified in the read command, for example, via a page map, to identify the word line and then identify the word line group corresponding to the identified word line. A page map is a data structure that maps logical pages (e.g., logical addresses) to physical blocks (e.g., word lines).

[0028] The memory subsystem controller may identify the threshold voltage offset bins assigned to the block family associated with the group of memory cells specified by the read command. In some embodiments, the memory subsystem controller may identify the threshold voltage offset bins assigned to the block family associated with the read command via a metadata table. The metadata table associates blocks with their respective block families and further associates block families and dies with their respective threshold voltage offset bins. The memory subsystem controller may identify the block family associated with the memory partition identified by the logical address specified in the read command and identify the current threshold voltage offset bin associated with the identified family through the metadata table.

[0029] The memory subsystem controller may determine the characteristic temperature associated with a group of memory cells (e.g., a block) to be read as the current temperature of the die on which the block resides or as the crossover temperature of the group of memory cells (i.e., the difference between the current temperature of the die and the temperature of the die recorded when the most recent programming operation was performed with respect to the group of memory cells).

[0030] Based on the identified word line group, the identified threshold voltage offset bin, and the determined temperature, the memory subsystem controller may determine a set of threshold voltage offsets that may be applied to the word line group during a read operation to improve the bit error rate exhibited by the memory subsystem. Specifically, the memory subsystem controller may determine the set of threshold voltage offsets in two steps. The memory subsystem controller may first obtain a read mask identifier from a first lookup table based on the threshold voltage offset bin and the temperature, wherein the first lookup table provides a plurality of entries, each entry providing a corresponding parameter including a threshold voltage offset bin, a temperature, or other relevant metric to the read mask identifier. The memory subsystem controller may then determine the set of threshold voltage offsets based on the read mask identifier and the word line group, the set of threshold voltage offsets from a second lookup table, wherein the second lookup table provides a plurality of entries, each entry providing a set of threshold voltage offsets for the word line group having the corresponding read mask identifier.

[0031] The read mask identifier is a value used to identify a set of threshold voltage offsets corresponding to a given word line group (e.g., a word line group specific to a scenario, such as high temperature write operation to low temperature read operation, low temperature write operation to high temperature read operation, SCL occurs in a short duration, high temperature data retention, potential read disturbance, underfill, etc.). Thus, each read mask identifier references a set of threshold voltage offsets applied to various word line groups (e.g., in the second lookup table), and a group of memory cells used to perform a read operation can be associated with one of the read mask identifiers (e.g., in the first lookup table) based on the identified threshold voltage offset bin and the determined temperature. The first and second lookup tables can start with manufacturing default values, and tests can be run so that different scenarios for all word line groups in the memory system can be pre-characterized (e.g., high temperature write operation to low temperature read operation, low temperature write operation to high temperature read operation, SCL occurs in a short duration, high temperature data retention, potential read disturbance, underfill, etc.).

[0032] In some embodiments, in addition to the identified threshold voltage offset bins and the determined temperature, the program erase cycle count associated with the memory cell group can also be used to determine the read mask identifier. In some embodiments, the memory cell group used to perform the read operation can be associated with a read mask identifier sequence, and the read mask identifier sequence represents the order for applying the read mask identifiers, and thus applying the threshold voltage offset groups, during the read error handling process. The read mask identifier sequence can be determined from a first lookup table based on the identified threshold voltage offset bins and the determined temperature (and / or program erase cycle). During the read error handling process, the memory subsystem controller can determine a set of threshold voltage offsets corresponding to each read mask identifier from the second lookup table in the order listed in the read mask identifier sequence and sequentially apply the threshold voltage offset groups for read error handling.

[0033] The present disclosure provides a technical improvement over conventional block family error avoidance performed on all word lines of a memory device without adaptive adjustment and without accounting for WGR-to-WGR variations, differences in data retention behavior between program-erase cycles, and / or crossover temperature differences between programming and reading. The present disclosure also provides a technical improvement over existing methods of determining threshold voltage offsets, which result in suboptimal behavior on certain dies that are outliers to begin with and do not account for inconsistent relationship variations between WGRs.

[0034] Advantages of the present disclosure include, but are not limited to, reducing the bit error rate exhibited by the memory subsystem, reducing the time required to decode the corresponding codeword, and improving the overall quality of service (QoS) caused by the mismatch between the offset and the memory device. Custom offsets can reduce error rates and free up error recovery related resources for other operations, thereby reducing latency and improving system performance.

[0035] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or a combination thereof.

[0036] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0037] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (such as an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0038] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0039] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0040] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0041] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0042] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device that is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can perform bit storage based on body resistance changes in combination with a stackable cross-gate data access array. Therefore, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0043] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0044] Although non-volatile memory components such as a 3D cross-point array of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory or electrically erasable programmable read-only memory (EEPROM).

[0045] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0046] The memory subsystem controller 115 may include a processing device, including one or more processors, such as the processor 117, configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0047] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0048] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0049] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0050] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local media controller 135) located on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0051] The memory subsystem 110 includes an offset update component 113 that can update a threshold voltage offset associated with a word line group of memory devices 130, 140. In some embodiments, the memory subsystem controller 115 includes at least a portion of the offset update component 113. In some embodiments, the offset update component 113 is part of the host system 120, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the offset update component 113 and is configured to perform the functionality described herein. More details on the operation of the offset update component 113 are described in detail in the accompanying drawings. Figures 2A to 7 Give a description.

[0052] Figure 2A Schematically illustrates the temporal voltage shift caused by the slow charge loss exhibited by a three-level memory cell according to some embodiments of the present disclosure. Figure 2A The illustrative example of utilizes a triple level cell, but the same observations can be made and the same remedial measures applied accordingly to compensate for slow charge loss for single level cells and multi-level cells, as well as any other fractional or integer number of bits per cell (eg, 3.5 bits per cell, etc.).

[0053] Each of the graphs 210 and 230 illustrates a programming voltage distribution 220A-220N (also referred to herein as a "programming distribution" or "voltage distribution" or "distribution" or "level") for memory cells that encode a corresponding logic level ("000" to "111" in the case of TLC) programmed by a respective write level (which may be assumed to be at the midpoint of the programming distribution). The programming distributions 220A-220N may illustrate a range of threshold voltages (e.g., a normal distribution of threshold voltages) for memory cells that are programmed at the respective write level. To distinguish adjacent programming distributions (corresponding to two different logic levels), a read threshold voltage level (shown by a vertical dashed line) is defined such that any measured voltage that drops below the read threshold level is associated with one programming distribution in an adjacent pair of programming distributions, while any measured voltage that is greater than or equal to the read threshold level is associated with the other programming distribution in the adjacent pair of distributions.

[0054] In chart 210, eight states of the memory cell are shown below the corresponding programming distribution (except for the state labeled ER, which is the erased state, for which the distribution is not shown). Each state corresponds to a logic level. The read threshold voltage levels are labeled Va through Vh. As shown, any measured voltage below Va is associated with the ER state. The states labeled P1, P2, P3, P4, P5, P6, and P7 correspond to distributions 220A through 220N, respectively.

[0055] Time after programming (TAP) shall refer to the time since the cell was written in this article and is the main driver of TVS (time voltage shift) and temperature. TVS captures SCL and other charge loss mechanisms. TAP can be estimated (e.g., inferred from data state metrics) or directly measured (e.g., from a controller clock). A cell, block, page, block family, etc. is younger (or relatively younger) when it has a (relatively) small TAP and older (or relatively older) when it has a (relatively) large TAP. A time slice is the duration between two TAP points during which measurements can be made (e.g., a reference calibration is performed in X to Y minutes or hours after programming). A time slice can be referenced by its center point.

[0056] As can be seen from comparing example graphs 210 and 230 reflecting 0 time after programming (TAP) (immediately after programming) and T hours (where T is the number of hours) TAP, respectively, the programming distribution changes over time primarily due to slow charge loss. In order to reduce the read bit error rate, the corresponding read threshold voltage needs to be adjusted to compensate for the programming distribution shift, which is shown by the vertical dashed line. In various embodiments of the present disclosure, the temporal voltage shift of the die group is selectively tracked based on measurements performed at one or more representative dies in the die group. Based on the measurements of the temporal voltage shift and operating temperature of the die in the die group that are characterized by the representative die in the die group, the threshold voltage offset for reading the memory cells of the die in the die group is updated and applied to the base read threshold level to perform the read operation.

[0057] Figure 2B A set of threshold voltage offset bins (bin 0 to bin 9) according to an embodiment of the present disclosure is schematically illustrated. Figure 2B Schematically, the threshold voltage shift map can be subdivided into a plurality of threshold voltage shift bins, such that each bin corresponds to a threshold voltage shift range. Figure 2B The illustrative example of defines 10 bins, but in other embodiments, various other numbers of bins (eg, 64 bins) may be employed.

[0058] The memory subsystem controller may associate a segment of memory devices (e.g., a group of dies of a block family) with a threshold voltage offset bin based on a calibration process that is performed periodically. The calibration process selects a threshold voltage offset group that is applied to a reference voltage read level in order to perform a read operation. The calibration process involves performing a read operation with different threshold voltage offset groups with respect to a specified number of selected pages or blocks being calibrated and selecting a threshold voltage offset group that results in a defined error rate (e.g., a bit error rate) for the read operation. The defined error rate may be a minimum error rate, or it may be an error rate that falls within a specific range. The threshold voltage offset bins may be determined using different techniques, such as block family error avoidance (BFEA), dynamic pass-through voltage (VpassR), digital fail byte count (CFByte), or charge bucket classifier (CBC) indexing. That is, a segment of memory devices (e.g., a cell, page, block, plane, die, etc.) may be grouped using different techniques to be associated with one or more of the threshold voltage offset bins.

[0059] In one embodiment, the threshold voltage offset bins may be determined by a block family error avoidance (BFEA) technique or the like. According to BFEA, a block family (or any other memory partition) programmed within a specified time window and / or under similar environmental (e.g., temperature) conditions may be associated with one of the threshold voltage offset bins. Given that wear leveling maintains programming within similar program erase cycles (PECs), the time elapsed since programming and temperature conditions are one of the main factors affecting the amount of TVS, it may be assumed that different partitions within a single block family exhibit similar threshold voltage distributions of their memory cells, and therefore require the same voltage offset to be applied to the reference read level for read operations.

[0060] Block families can be created asynchronously with respect to block programming events. "Block" shall refer to a group of continuous or non-continuous memory pages in this article. An example of a "block" is an "erasable block", which is the smallest erasable memory unit, and a "page" is the smallest writable memory unit. Each page includes a group of memory cells. "Block family" shall refer to a group of possible non-continuous memory cells (which may reside in one or more complete and / or partial blocks, the latter being referred to as "partitions" in this article) that have been programmed within a specified time window and a specified temperature window and are therefore expected to exhibit similar or related changes in their corresponding data state metrics according to time voltage shifts. Block families can be generated at any granularity, containing only entire codewords, entire pages, entire super pages, or entire super blocks, or any combination of these.

[0061] Block family creation is the process of opening a block family, maintaining the block family open for a duration, and then closing the block family. In an illustrative example, a new block family may be created ("opened") whenever a specified period of time Δt (e.g., a predetermined number of minutes) has elapsed since the last block family creation or whenever the reference temperature of the memory cells has changed by more than a specified threshold ΔΘ (e.g., 10C, 20C, or any other value). Similarly, a family may be closed (and a new family may be created) after a time Δt has elapsed since the family was created or when the reference temperature has changed (in either direction) by more than ΔΘ. The memory subsystem controller may maintain identifiers of valid block families that are associated with the one or more blocks as they are programmed.

[0062] The memory subsystem controller may periodically perform a calibration process in order to associate each family of partitions with one of the threshold voltage offset bins. Each threshold voltage offset bin may in turn be associated with a set of voltage offsets applied for a read operation. Upon receiving a read command, the memory subsystem controller may: (1) identify the family associated with the memory partition identified by the logical address specified in the read command; (2) identify the current threshold voltage offset bin associated with the identified family; (3) determine a set of read offsets for the identified threshold voltage offset bin; (4) calculate a new read voltage by applying the read offset associated with the identified threshold voltage offset bin to a reference read level; and (5) perform a read operation using the new read voltage, as described in more detail below.

[0063] The calibration process may evaluate the data state metric (e.g., voltage shift or bit error rate) of each die of each block family with one of a set of predefined threshold voltage offset bins, for example, by measuring the data state metric values ​​of the blocks (of the block family) stored on the die for each die of each block family. The calibration process may then update the bin pointers associated with the die and block family to point to the threshold voltage offset bin corresponding to the measured value of the data state metric. Each threshold voltage offset bin is in turn associated with a voltage offset applied for a read operation; for a TLC with 8 distributions (levels), there are 7 valleys, and one for each valley for a given threshold voltage offset bin that includes 7 offsets. For example, a bin pointer may remain the same when the data state metric is within a range associated with an existing bin pointer or may be changed to point to an older bin when the data state metric is within a range associated with an older bin.

[0064] In general, the temporal voltage shift of younger block families (i.e., most recently created block families) is more pronounced than the temporal voltage shift of older block families (i.e., block families created in the past). The memory subsystem controller may periodically perform a calibration process for each block family based on the age of the block family corresponding to the threshold voltage offset bin associated with the block family. For example, in an 8-threshold voltage offset bin architecture, a newly created block family may be associated with threshold voltage offset bin 0, while the oldest (i.e., earliest created) block family is associated with threshold voltage offset bin 7. The memory subsystem controller performs the calibration process for the block families in threshold voltage offset bin 0 more frequently than the block families in threshold voltage offset bin 7 based on the age of the block families associated with threshold voltage offset bin 0 (e.g., based on the log-linear property of SCL). The association of blocks to block families and block families and dies to threshold voltage offset bins may be stored in respective metadata tables maintained by the memory subsystem controller.

[0065] Figure 3is a set of example read level voltage offsets determined according to some embodiments of the present disclosure. The bin offset calibration process determines a set of read level voltage offsets that result in a suboptimal error rate that does not exceed a maximum allowable error rate, thereby extending the period during which a given block family is associated with a particular threshold voltage offset bin. Figure 3 An example group N 301 of read level voltage offsets is illustrated. This example group of read level voltage offsets is for a triple level cell (TLC) and therefore has 7 valleys 305. Note that a group of single level cells (SLC) would have 1 valley, a group of multi-level cells (MLC) would have 3 valleys, a group of quad level cells (QLC) would have 15 valleys, etc. In addition, Figure 3 In the example illustrated in FIG. 3 , the group has 8 bins 303. Letters a to z represent read level voltage offsets. Note that letters a to z are examples; the read level voltage offsets may be the same in some valleys and bins, or they may be different across the bins. Figure 3 More or fewer different read level voltage offsets described in Figure 3 26 a to z values ​​described in ).

[0066] In this example, the memory subsystem controller has determined that: read level voltage offset a, when applied to valley 1 of the TLC associated with bin 0, causes a suboptimal error rate to not exceed a maximum allowable error rate; read level voltage offset b, when applied to valley 2 of the TLC associated with bin 0, causes a suboptimal error rate to not exceed a maximum allowable error rate; read level voltage offset d, when applied to valley 3 of the TLC associated with bin 0, causes a suboptimal error rate to not exceed a maximum allowable error rate; and so on. Thus, associating a block family with group N 301 can extend the period during which the block family will be in bin 0, thereby reducing the frequency of the calibration process and improving overall system performance. Group N 301 of read level voltage offsets is updated in accordance with an embodiment of the present disclosure. More details about the update process are described in detail in detail in the accompanying drawings. Figure 4 supply.

[0067] Figure 4 4 is a flow chart of an example method 400 for updating a read level voltage offset of a word line group according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The offset update component 113 is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0068] At operation 410, processing logic may receive a request to perform a read operation ("read command") on a memory device. For example, the request may specify a logical address that may be used to identify a group of cells of the memory device. The group of cells of the memory device may include one or more cells (e.g., a group of memory cells, a group of word lines, a word line, or an individual memory cell) of a memory array of a memory device (e.g., memory device 130). In one embodiment, the request may be sent to a memory subsystem controller (e.g., Figure 1 The processing logic may initiate a read operation with respect to a group of target cells in response to receiving the request. In one example, the processing logic may initiate an operation to update a read level voltage offset of a word line group with respect to a group of target cells in response to receiving a request to perform a correction read in response to detecting a read error. The request may be initiated as an option in an error handling process. The read error may be detected in response to performing a host-initiated read operation or performing a calibration operation.

[0069] At operation 420, processing logic may identify a word line group coupled to a group of memory cells of the memory device. For example, when a read operation is performed on a group of cells of the memory device, the group of cells may correspond to one or more word lines, one or more individual cells, or unconnected memory segments (e.g., not physically connected or organized, such as a particular word line from two or more groups of word lines, etc.), and processing logic may identify one or more word line groups from the group of cells associated with the read operation.

[0070] In some implementations, processing logic may identify one or more word line groups associated with a read operation through a page map. A page map maps logical pages to physical blocks. For each cell of a memory device, a page map provides bit information stored in the cell and logical page information and physical location information of the cell (e.g., word line, sub-block, block). After receiving a read command, processing logic may identify a word line through a page map using a logical address specified in the read command. In some implementations, the identified word line may correspond to one or more word line groups.

[0071] At operation 430, processing logic may identify the threshold voltage offset bins assigned to the block family associated with the memory cell group of the memory device. In some implementations, processing logic may identify the threshold voltage offset bins assigned to the block family through a metadata table. The metadata table provides associations of blocks to block families and block families to dies to threshold voltage offset bins. As described above, upon receiving a read command, processing logic may identify the block family associated with the memory partition identified by the logical address specified in the read command and identify the current threshold voltage offset bin associated with the identified family through the metadata table.

[0072] In some embodiments, processing logic may identify segments of a memory device associated with a threshold voltage offset bin. Segments of a memory device (e.g., cells, pages, blocks, planes, dies, etc.) may be grouped using the different techniques described above to be associated with one of the threshold voltage offset bins. In one implementation, a segment of a memory device may be one or more of a family of blocks (or any other memory partition) that are programmed within a specified time window and / or under similar environmental (e.g., temperature) conditions (e.g., BFEA techniques or the like).

[0073] In one embodiment, a threshold voltage offset bin may be associated with a segment of a memory device when processing logic determines and / or selects a set of read level voltage offsets from a plurality of sets of read level voltage offsets to result in a suboptimal error rate that does not exceed a maximum tolerable error rate when applied to a reference read level threshold voltage associated with the segment of the memory device. The read level voltage offset sets may be generated when the memory subsystem is manufactured or during use of the memory subsystem. In one embodiment, the threshold voltage offset bin may be associated with a segment of the memory device at the time of programming. In another embodiment, processing logic may associate a block family with a threshold voltage offset bin by updating block family metadata associated with the memory device. The block family metadata may include a data structure storing records, such as a table, and each record in the table associates a block with a block family.

[0074] At operation 440, processing logic may determine the characteristic temperature associated with the group of memory cells to be read (e.g., a block) as the current temperature of the die on which the block resides or the crossover temperature of the group of memory cells (i.e., the difference between the current temperature of the die and the temperature of the die recorded when the most recent programming operation was performed with respect to the group of memory cells).

[0075] In some embodiments, the processing logic may determine a temperature measured as a crossover temperature. The processing logic may obtain the temperature measured as the crossover temperature by: determining a write temperature when a request to perform a program operation is received; determining a read temperature when a request to perform a read operation is received; and calculating the write temperature (T write ) is higher than the reading temperature (T read ) value (difference): Difference = T write -Tread The processing logic may determine the value (difference) to be the temperature measured as the crossover temperature.

[0076] In some embodiments, processing logic may determine the temperature measured as the read temperature, ie, use the read temperature to represent the crossover temperature in situations where the write temperature is not available. Processing logic may determine the temperature by using the temperature read from the temperature sensor when a read command is received.

[0077] In one embodiment, processing logic may obtain temperature measurements from a temperature sensor on memory device 130, such as a temperature sensor (i.e., an on-die temperature sensor). Depending on the embodiment, processing logic may query the temperature sensor for new temperature measurements in response to receiving a request (e.g., the request at operation 410) or may use the most recently measured temperature value (e.g., when temperature measurements are routinely made at periodic intervals on memory device 130). In another embodiment, control logic may receive temperature measurements from a temperature sensor external to the memory device, such as a sensor located elsewhere in memory subsystem 110.

[0078] A group of target cells may be defined to have the same temperature variation. In one embodiment, the memory subsystem controller 115 tracks temperature at a particular level of granularity (e.g., by segment, by memory die, by memory device, etc.). Thus, the offset update component 113 may retrieve, for example, a temperature associated with a segment of the memory device that includes the target cell from a data structure maintained in the local memory 119 or elsewhere on the memory device 130. For example, the processing logic may determine the read temperature when a request to perform a read operation is received. Depending on the embodiment, the processing logic may determine the current temperature by querying a temperature sensor for a new temperature measurement in response to receiving a request (e.g., a read request) or using the most recently measured temperature value (e.g., when temperature measurements are routinely performed on the memory device 130 at periodic intervals). Thus, the processing logic may determine the temperature associated with the word line group as the temperature associated with the read command.

[0079] In some implementations, processing logic may determine a program erase cycle (PEC) count associated with a group of cells of a memory device. In some embodiments, processing logic may determine a PEC count for a group of target cells. A group of target cells may be defined to have the same PEC count. In one embodiment, the memory subsystem controller 115 tracks the PEC count at a particular level of granularity, such as by segment, by memory die, by word line group, by memory device, etc. Thus, processing logic may retrieve, for example, a PEC count associated with a segment of a memory device that includes a word line group from a data structure maintained in local memory 119 or elsewhere on memory device 130.

[0080] At operation 450, based on the identified word line groups, the identified threshold voltage offset bins, and the determined temperature, processing logic may determine a set of threshold voltage offsets associated with the group of memory cells, and the set of threshold voltage offsets may be applied to the word line groups during read operations to improve the bit error rate exhibited by the memory subsystem.

[0081] In some implementations, processing logic may determine the threshold voltage offset group by obtaining a read mask identifier based on the threshold voltage offset bin and temperature from a first lookup table (e.g., table 500A), wherein the first lookup table provides a plurality of entries, each entry providing a corresponding parameter including the threshold voltage offset bin, temperature, or other relevant metric (e.g., PEC count) to the read mask identifier. The memory subsystem controller may then determine the threshold voltage offset group based on the read mask identifier and the word line group, the threshold voltage offset group from a second lookup table (e.g., table 500B), wherein the second lookup table provides a plurality of entries, each entry providing a set of threshold voltage offsets for the word line group having the corresponding read mask identifier. The read mask identifier is a value used to identify a set of threshold voltage offsets corresponding to a given word line group (e.g., a word line group specific to a situation, such as high temperature write operation to low temperature read operation, low temperature write operation to high temperature read operation, SCL occurs in a short duration, high temperature data retention, potential read disturbance, underfill, etc.). Thus, each read mask identifier references a set of threshold voltage offsets applied to various word line groups, as shown in the second lookup table (e.g., table 500B), and the group of memory cells used to perform a read operation can be associated with one of the read mask identifiers based on the identified threshold voltage offset bins and the determined temperature, as shown in the first lookup table (e.g., table 500A). The first and second lookup tables can start with manufacturing default values, and tests can be run so that different scenarios for all word line groups in the memory system can be pre-characterized (e.g., high temperature write operation to low temperature read operation, low temperature write operation to high temperature read operation, SCL occurs in short duration, high temperature data retention, potential read disturbance, underfill, etc.).

[0082] refer to Figure 5 , an example of the first lookup table 500A includes a bin field, a temperature field, a read mask ID field, and a read mask ID sequence field. The bin field refers to the threshold voltage offset bin (represented by a bin number or bin index). The temperature field refers to the temperature offset value based on the write temperature and the read temperature (represented by T or difference). The read mask ID refers to the above-mentioned read mask identifier and can be represented by a number or an index. The read mask ID sequence refers to the sequence of the above-mentioned read mask identifiers and can be represented by a sequence of numbers or indices.

[0083] For example, when the bin number is less than or equal to B1 and the temperature is less than T11, the processing logic may determine the read mask ID as X1, which may correspond to updating the threshold voltage offset of the word line group for the situation of high temperature write operation to low temperature read operation. The processing logic may determine the read mask ID sequence as X1, X4, X2, X3, Y1, each of which will be used to identify a set of threshold voltage offsets to be applied to the word line group in sequence for read error handling. In another example, when the bin number is less than or equal to B1 and the temperature is greater than or equal to T11 and less than or equal to T12, the processing logic may determine the read mask ID as X2, which may correspond to updating the threshold voltage offset of the word line group for the situation where SCL occurs in a short duration. The processing logic may determine the read mask ID sequence as X2, X3, X4, X1, Y2, each of which will be used to identify a set of threshold voltage offsets to be applied to the word line group in sequence for read error handling.

[0084] In one embodiment, processing logic may compare the bin number to a threshold value (e.g., B2) or a range of values. In one embodiment, processing logic may determine that the bin number is greater than or equal to the threshold value (e.g., B#>=B2). In another embodiment, processing logic may determine that the bin number falls within a range.

[0085] In one embodiment, processing logic may compare the temperature to a threshold value (e.g., T21) or a range of values. In one implementation, processing logic may determine that the temperature is less than or equal to the threshold value (e.g., T<=T21). In another implementation, processing logic may determine that the temperature falls within a range.

[0086] In some implementations, other performance metrics such as program-erase cycles (PEC) may be included in Table 500A (not shown) and used with the bin and temperature to determine the read mask ID and read mask ID sequence. For example, when the count of program-erase cycles is greater than or equal to a value, the bin number is less than or equal to B1, and the temperature is less than T11, the processing logic may determine the read mask ID to be X1. In another example, when the count of program-erase cycles is within a range of values, the bin number is less than or equal to B1, and the temperature is greater than or equal to T11 and less than or equal to T12, the processing logic may determine the read mask ID to be X2.

[0087] In one embodiment, processing logic may compare the PEC count to a threshold or value range. In one embodiment, processing logic may determine that the temperature is less than or equal to the threshold. In another embodiment, processing logic may determine that the temperature falls within a range.

[0088] refer to Figure 5, an example of the second lookup table 500B includes a read mask ID field and a plurality of word line group fields (WGR0, WGR1, ... WGRn). Each word line group field refers to a set of threshold voltage offsets applied to a word line group for a read operation, and the threshold voltage offset set may be represented by a set of voltage values ​​or a number (e.g., a bin number) that may be used to refer to the set of voltage values. For example, when the read mask ID is X1 and the word line group is WGR0, the threshold voltage offset set is O1, which may be a bin number that may be used to identify a set of voltage values ​​or may be an offset value that may be applied to a bin number used to identify a set of voltage values.

[0089] refer to Figure 6 , in some implementations, processing logic may determine the threshold voltage offset group by obtaining the threshold voltage offset group from a third lookup table (e.g., table 600) based on the threshold voltage offset bin, temperature, program-erase cycle, and word line group. That is, identifying the read mask ID may be omitted, and the threshold voltage offset group may be directly identified. For example, when the bin number is B1, the temperature is T11, the PEC count is P1, and the word line group is WGR0, processing logic may determine the threshold voltage offset group to be O1. It should be noted that each entry of the variables (e.g., bin, temperature, PEC) used to determine the read mask ID in tables 500A and 600 may include one value, multiple discrete values, or a range of values.

[0090] Return to reference Figure 4 At operation 460, the processing logic may perform a read operation by applying the threshold voltage offset group. For example, when a read operation is requested, the processing device may identify a segment of the memory device associated with the logical address specified in the request based on metadata associated with the memory device. The processing device may calculate a modified threshold voltage by applying the threshold voltage offset to a reference read level voltage associated with the memory device. The reference read level voltage may be stored in a metadata area of ​​the memory device. The processing device may utilize the calculated modified threshold voltage to perform the requested read operation.

[0091] Figure 7 An example machine illustrating a computer system 700 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110) or can be used to perform operations of the controller (for example, to execute an operating system to execute a corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0092] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0093] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 718, which communicate with each other via a bus 730.

[0094] The processing device 702 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 702 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 to communicate over a network 720.

[0095] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside completely or at least partially within the main memory 704 and / or the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0096] In one embodiment, instructions 726 include instructions for implementing a component corresponding to an offset bin update component (e.g. Figure 1 The term "machine-readable storage medium" should be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be taken to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0097] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally conceived here to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0098] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0099] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0100] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0101] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0102] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory device; and A processing device operatively coupled to the memory device to perform operations comprising: receiving a request to perform a read operation on a group of memory cells of the memory device; identifying a group of word lines coupled to the set of memory cells of the memory device; identifying a threshold voltage offset bin associated with the group of memory cells; determining a current temperature associated with the set of memory cells; determining a read mask identifier associated with the group of memory cells based on the threshold voltage offset bins and the current temperature; determining a set of threshold voltage offsets associated with the set of memory cells based on the read mask identifier and the word line group; and The read operation is performed using the set of threshold voltage shifts.

2. The system of claim 1, wherein the word line group is identified from a data structure comprising a plurality of records, wherein each record of the plurality of records maps an identifier of a group of memory cells to a corresponding word line group.

3. The system of claim 1 , wherein the read mask identifier is determined based on a first lookup table comprising a first plurality of records, wherein each record in the first plurality of records maps a threshold voltage offset bin and a current temperature to a corresponding read mask identifier, and wherein the set of threshold voltage offsets is determined based on a second lookup table comprising a second plurality of records, wherein each record in the second plurality of records maps a read mask identifier and a word line group to a set of corresponding threshold voltage offsets.

4. The system of claim 1, wherein the current temperature is a crossover temperature associated with the group of memory cells. 5 . The system of claim 1 , wherein determining the read mask identifier is further based on a program-erase cycle count associated with the group of memory cells.

6. The system of claim 1, wherein the operations further comprise: determining a sequence of read mask identifiers associated with the group of memory cells based on the threshold voltage offset bins and the current temperature, The read mask identifier sequence is used in read error handling.

7. The system of claim 6, wherein the read mask identifier sequence is determined based on a third lookup table comprising a third plurality of records, wherein each record of the third plurality of records maps a threshold voltage offset bin and a current temperature to a corresponding read mask identifier sequence.

8. A method comprising: receiving, by a processing device, a request to perform a read operation on a group of memory cells of a memory device; identifying a group of word lines coupled to the set of memory cells of the memory device; identifying a threshold voltage offset bin associated with the group of memory cells; determining a current temperature associated with the set of memory cells; determining a set of threshold voltage offsets associated with the set of memory cells based on the threshold voltage offset bins, the current temperature, and the word line groups; and The read operation is performed using the set of threshold voltage shifts.

9. The method of claim 8, wherein determining the set of threshold voltage shifts further comprises: determining a read mask identifier associated with the group of memory cells based on the threshold voltage offset bins and the current temperature; and The set of threshold voltage offsets associated with the set of memory cells is determined based on the read mask identifier and the word line group.

10. The method of claim 8, wherein the word line group is identified from a data structure comprising a plurality of records, wherein each record of the plurality of records maps an identifier of a group of memory cells to a corresponding word line group.

11. The method of claim 8, wherein the set of threshold voltage offsets is determined based on a lookup table comprising a plurality of records, wherein each record of the plurality of records maps a threshold voltage offset bin, a current temperature, and a word line group to a corresponding set of threshold voltage offsets.

12. The method of claim 8, wherein the current temperature is a crossover temperature associated with the group of memory cells.

13. The method of claim 8, wherein determining the set of threshold voltage shifts is further based on a program-erase cycle count associated with the set of memory cells.

14. The method according to claim 8, further comprising: determining a sequence of read mask identifiers associated with the group of memory cells based on the threshold voltage offset bins and the current temperature, The read mask identifier sequence is used in read error handling.

15. The method of claim 14, wherein the read mask identifier sequence is determined based on a lookup table comprising a plurality of records, wherein each record of the plurality of records maps a threshold voltage offset bin and a current temperature to a corresponding read mask identifier sequence.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to perform a read operation on a group of memory cells of a memory device; identifying a group of word lines coupled to the set of memory cells of the memory device; identifying a threshold voltage offset bin associated with the group of memory cells; determining a current temperature associated with the set of memory cells; determining a read mask identifier associated with the group of memory cells based on the threshold voltage offset bins and the current temperature; determining a set of threshold voltage offsets associated with the set of memory cells based on the read mask identifier and the word line group; and The read operation is performed using the set of threshold voltage shifts.

17. The non-transitory computer-readable storage medium of claim 16, wherein determining the read mask identifier is further based on a program-erase cycle count associated with the group of memory cells.

18. The non-transitory computer-readable storage medium of claim 16, wherein the operations further comprise: determining a sequence of read mask identifiers associated with the group of memory cells based on the threshold voltage offset bins and the current temperature, The read mask identifier sequence is used in read error handling.

19. The non-transitory computer-readable storage medium of claim 16, wherein the word line group is identified from a data structure comprising a plurality of records, wherein each record of the plurality of records maps an identifier of a group of memory cells to a corresponding word line group.

20. The non-transitory computer-readable storage medium of claim 16, wherein the read mask identifier is determined based on a first lookup table comprising a first plurality of records, wherein each record in the first plurality of records maps a threshold voltage offset bin and a current temperature to a corresponding read mask identifier, and wherein the set of threshold voltage offsets is determined based on a second lookup table comprising a second plurality of records, wherein each record in the second plurality of records maps a read mask identifier and a word line group to a set of corresponding threshold voltage offsets.

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