Memory, operating method thereof, memory system, and electronic device

Abstract

The embodiment of the invention discloses a memory and an operation method thereof, a memory system and an electronic device, the memory comprises a memory cell array and a page buffer, the page buffer is arranged corresponding to a bit line of the memory cell array, and the page buffer comprises a pre-charge-discharge circuit, a first charge-discharge circuit and a second charge-discharge circuit, the pre-charge / discharge circuit is coupled to a bit line through a sensing node of a page buffer, and includes: a first type transistor; a plurality of latches respectively coupled to the sensing nodes; wherein at least one of the latches comprises a second type of transistor, and the characteristic size of the second type of transistor is smaller than that of the first type of transistor.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to semiconductor technology, and relate to but are not limited to a memory and an operating method thereof, a memory system, and an electronic device. Background Art

[0002] Semiconductor memories can be roughly divided into two categories, depending on whether they retain stored data when power is off; these two categories of semiconductor memories are: volatile memory, which loses stored data when power is off, and non-volatile memory, which retains stored data when power is off. In non-volatile memory, the memory cells are connected to the bit line and the word line respectively, so they have good random access time characteristics.

[0003] As the integration of memories increases, the area occupied by page buffers in peripheral circuits of memories is limited and there is a demand to reduce the area of ​​page buffers. Therefore, how to reduce the area of ​​page buffers has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory and an operating method thereof, a memory system, and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, the memory comprising a memory cell array and a page buffer, the page buffer being arranged corresponding to a bit line of the memory cell array, the page buffer comprising:

[0006] A pre-charge and discharge circuit, the pre-charge and discharge circuit is coupled to the bit line through a sensing node of the page buffer, comprising: a first type of transistor;

[0007] A plurality of latches are respectively coupled to the sensing nodes; wherein at least one of the plurality of latches comprises a second type of transistor, and a characteristic size of the second type of transistor is smaller than a characteristic size of the first type of transistor.

[0008] In a second aspect, an embodiment of the present disclosure further provides an operating method of a memory, wherein the memory comprises a memory cell array and a page buffer, wherein the page buffer is arranged corresponding to a bit line of the memory cell array; the page buffer comprises a pre-charge and discharge circuit and a plurality of latches; the pre-charge and discharge circuit is coupled to the bit line through a sensing node of the page buffer, and the plurality of latches are respectively coupled to the sensing node; the operating method comprises:

[0009] Applying a first voltage to a control terminal of a first type of transistor in the pre-charge and discharge circuit to perform a pre-charge operation on the bit line;

[0010] After performing the precharge operation, a second voltage is applied to the control terminal of the second type of transistor in at least one of the latches to perform a programming operation or a reading operation on the memory cell array through the latch; wherein the characteristic size of the second type of transistor is smaller than the characteristic size of the first type of transistor; and the second voltage is different from the first voltage.

[0011] In a third aspect, an embodiment of the present disclosure further provides a memory system, the memory system comprising:

[0012] One or more memories as described in any of the above embodiments;

[0013] A memory controller is coupled to the memory and configured to control the memory.

[0014] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, comprising the memory system as described in the above embodiment.

[0015] In the embodiment of the present disclosure, by setting at least one of the multiple latches to include a second type of transistor, and the characteristic size of the second type of transistor is smaller than the characteristic size of the first type of transistor, the area of ​​at least one latch in the page buffer can be reduced, thereby reducing the area of ​​the page buffer in the peripheral circuit, which is beneficial to reducing the area of ​​the peripheral circuit in the memory, thereby realizing the miniaturization of the memory.

[0016] Furthermore, at least one latch in the disclosed embodiment uses a second type of transistor with a smaller characteristic size. Accordingly, the voltage required for the operation of the second type of transistor is smaller, which is beneficial to reducing the power consumption of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0018] Figure 1A A schematic diagram of the structure of an exemplary system provided for an embodiment of the present disclosure;

[0019] Figure 1B A schematic diagram of the structure of a memory card provided by an embodiment of the present disclosure;

[0020] Figure 1C A schematic diagram of the structure of a solid state disk (SSD) provided in accordance with an embodiment of the present disclosure;

[0021] Figure 1D and Figure 1EA schematic diagram of the structure of a memory including a memory cell array and a peripheral circuit provided in one embodiment of the present disclosure;

[0022] Figure 1F A schematic diagram of the structure of a memory including a page buffer provided in an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of a page buffer provided in an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of a latch provided in an embodiment of the present disclosure;

[0026] Figure 5 A flowchart of a method for operating a memory provided by an embodiment of the present disclosure;

[0027] Figure 6a and Figure 6b A timing diagram of a memory operation method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0030] like Figure 1AAs shown, the embodiment of the present disclosure shows an exemplary system 10, which may include a host 20 and a memory system 30. The exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34; the host 20 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device.

[0031] In an embodiment of the present disclosure, the host 20 may be configured to send data to or receive data from the memory system 30. Here, the memory system 30 may include a memory controller 32 and one or more memories 34. The memory 34 may include, but is not limited to, NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0032] In an embodiment of the present disclosure, a memory controller 32 may be coupled to a memory 34 and a host 20, and used to control the memory 34. Exemplarily, the memory controller 32 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 32 may also be designed to operate in a high duty cycle environment, such as an SSD or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as an enterprise storage array.

[0033] Further, the memory controller 32 can manage the data in the memory 34 and communicate with the host. The memory controller 32 can be configured to control operations such as reading, erasing, and programming the memory 34; it can also be configured to manage various functions related to the data stored or to be stored in the memory 34, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.; it can also be configured to process error correction codes (Error Checking and Correction, ECC) on data read from or written to the memory 34. In addition, the memory controller 32 can also perform any other suitable functions, such as formatting the memory 34, or communicating with external devices (e.g., Figure 1AThe memory controller 32 can communicate with the external host 20. Exemplarily, the memory controller 32 can communicate with the external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc.

[0034] In an embodiment of the present disclosure, the memory controller 32 and one or more memories 34 may be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 30 may be implemented and packaged into different types of terminal electronic products. Figure 1B As shown, the memory controller 32 and the single memory 34 can be integrated together to form a memory card 40. The memory card 40 may include a PC card (Personal Computer Memory Card), a CF (Compact Flash) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 40 may also include a memory card 40 that connects the memory card 40 to a host (e.g., Figure 1A The memory card connector 42 is coupled to the host 20 in the embodiment. Figure 1C In another embodiment shown in FIG. 5 , the memory controller 32 and the plurality of memories 34 may be integrated together to form an SSD 50. The SSD 50 may also include a processor that connects the SSD 50 to a host (eg, Figure 1AIn some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0035] It should be noted that the memory involved in an embodiment of the present disclosure may be a semiconductor memory, which is a solid-state electronic device for storing data information made using semiconductor integrated circuit technology. For example, Figure 1D FIG. 6 is a schematic diagram of an optional memory 60 in an embodiment of the present disclosure. The memory 60 may be Figures 1A to 1C The memory 34 in the. Figure 1D As shown, the memory 60 may include a memory cell array 62 and a peripheral circuit 64 coupled to the memory cell array 62, etc. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 66, and each NAND memory string 66 extends vertically above the substrate. In some embodiments, each NAND memory string 66 may include a plurality of memory cells coupled in series and stacked vertically. Wherein, each memory cell is to maintain a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the memory cell area. In addition, each memory cell in the above-mentioned memory cell array 62 may be a floating gate type memory cell including a floating gate transistor, or a charge capture type memory cell including a charge capture transistor.

[0036] In one embodiment of the present disclosure, the above-mentioned memory cell may be a single-level memory cell (SLC) having two possible storage states and thus can store one bit of data. For example, the first storage state "0" may correspond to a first threshold voltage range, and the second storage state "1" may correspond to a second threshold voltage range. In other embodiments, each memory cell may be a multi-level memory cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC may be programmed to program the memory cell from an erased state to one of three possible programming levels by writing one of three possible nominal storage values ​​to the memory cell. Among them, the fourth nominal storage value may be used for the erased state.

[0037] In the embodiment of the present disclosure, the above-mentioned peripheral circuit can be coupled to the memory cell array through the bit line (Bit Line, BL), the word line (Word Line, WL), the source (Source Line, SL), the source select gate (Source Select Gate, SSG) and the drain select gate (Drain Select Gate, DSG). Here, the peripheral circuit may include any suitable analog, digital and mixed signal circuits for facilitating the relevant operation of the memory cell array by applying a voltage signal and / or a current signal to each target memory cell via a bit line, a word line, a source, an SSG or a DSG, etc. and sensing a voltage signal and / or a current signal from each target memory cell. In addition, the peripheral circuit may also include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology. For example, as Figure 1E As shown. The peripheral circuit 70 may include a page buffer (PB) / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77 and a data bus 78. It should be understood that the above peripheral circuit 70 may be connected to Figure 1D The peripheral circuit 64 is the same as in FIG. 1 , and in some other embodiments, the peripheral circuit 70 may also include Figure 1E Additional peripheral circuits not shown.

[0038] like Figure 1F As shown, a page buffer group 90 is shown in one embodiment of the present disclosure. The page buffer group 90 can be coupled to the memory cell array 80 via a plurality of bit lines BL1 to BLk. The page buffer group 90 can include page buffer 1 (PB1) to page buffer k (PBk), each of which is coupled to the memory cell array via a bit line. For example, the page buffers PB1 to PBk can be coupled to the memory cell array via corresponding bit lines BL1 to BLk, respectively.

[0039] As the number of stacked film layers in the memory increases, the peripheral circuit will limit the size of the memory to be further reduced, and currently the page buffer 91 occupies the largest share of the peripheral circuit. Therefore, in the context of the increasingly miniaturized memory, how to reduce the area of ​​the page buffer 91 has become a technical problem that needs to be solved urgently.

[0040] In view of this, embodiments of the present disclosure provide a memory and an operating method thereof, a memory system, and an electronic device.

[0041] Figure 2 A schematic diagram of a memory 100 provided in an embodiment of the present disclosure is shown in FIG. Figure 3A circuit diagram of a page buffer 120 provided in an embodiment of the present disclosure is shown in FIG. Figure 4 A schematic diagram of a latch 122 provided in an embodiment of the present disclosure is shown below in conjunction with Figures 2 to 4 The memory 100 , the page buffer 120 , and the latch 122 provided in the embodiment of the present disclosure are further described.

[0042] Reference Figure 2 and Figure 3 As shown, the memory 100 includes a memory cell array 110 and a page buffer 120. The page buffer 120 is arranged corresponding to the bit line BL of the memory cell array 110. The page buffer 120 includes:

[0043] The pre-charge and discharge circuit 121 is coupled to the bit line BL through the sensing node SO of the page buffer 120 and includes: a first type of transistor;

[0044] A plurality of latches 122 are respectively coupled to the sensing node SO; wherein at least one of the plurality of latches 122 comprises a second type of transistor, and a characteristic size of the second type of transistor is smaller than a characteristic size of the first type of transistor.

[0045] The memory 100 includes a memory cell array 110 and a peripheral circuit, wherein the peripheral circuit includes a page buffer 120, and the page buffer 120 is coupled to the memory cell array 110 through a bit line BL. The number of the page buffers 120 in the memory 100 may be one or more. Figure 2 Only one page buffer 120 is shown.

[0046] The pre-charge and discharge circuit 121 is coupled to the power supply terminal and the sensing node SO respectively, and is used to adjust the voltage of the bit line BL during the execution of a logic (e.g., programming, reading, or writing) operation. For example, a voltage is applied to the bit line BL to pre-charge the bit line BL; or the voltage of the bit line BL is pulled down to the ground voltage to discharge the bit line BL.

[0047] In some embodiments, during the process of performing a programming operation on a memory cell, a programming inhibiting bit line voltage (e.g., ) or a normal programming bit line voltage (e.g., VSS) may be applied to the bit line BL connected to the memory cell through the pre-charge and discharge circuit 121. Exemplarily, a high level is applied to the bit line BL through the charging function of the pre-charge and discharge circuit 121 to achieve the effect of inhibiting programming, or the bit line BL is discharged through the discharging function of the pre-charge and discharge circuit 121, so that the voltage of the bit line BL is pulled down to the ground voltage to achieve the effect of allowing programming.

[0048] The page buffer 120 includes a plurality of latches, for example, latches 122-1, 122-2, 122-3, 122-4, and 122-5. The latches may latch data, for example, latch data "0" or "1", according to a sensing voltage of the sensing node SO. For ease of illustration, Figure 3 Five latches are shown in FIG. 1 , but the number of latches in the page buffer 120 is not limited thereto and can be set according to actual devices.

[0049] The first type of transistor and the second type of transistor can be a collection of one or more transistors. The transistors framed by dashed lines in the pre-charge and discharge circuit 121 are transistors of the first type, and the transistors not framed by dashed lines in the latch are transistors of the second type. Figure 3 As shown. Taking the first type of transistor including multiple transistors as an example, the conductivity type, and / or the characteristic size, and / or the doping concentration of the active region of any two transistors in the first type of transistor can be the same or different. Here, the conductivity type includes P type or N type, and the characteristic size can be represented by at least one of the length and / or width of the channel of the transistor, the length and / or width of the gate of the transistor, and the length and / or width of the gate dielectric layer of the transistor.

[0050] In some embodiments, the first type of transistors includes high voltage transistors (high voltage MOS, HV MOS), and the second type of transistors includes low voltage transistors (low voltage MOS, LV MOS) and / or ultra low voltage transistors (low low voltage, LLV MOS). In other embodiments, the first type of transistors includes low voltage transistors, and the second type of transistors includes ultra low voltage transistors. In some other embodiments, the first type of transistors includes high voltage transistors and low voltage transistors, and the second type of transistors includes ultra low voltage transistors.

[0051] It should be noted that high voltage, low voltage and ultra-low voltage are relative concepts. Transistors can be divided into high voltage transistors, low voltage transistors and ultra-low voltage transistors according to the size of the operating voltage (i.e., the gate conduction voltage); among which, the operating voltages of high voltage transistors, low voltage transistors and ultra-low voltage transistors decrease in sequence, and the thicknesses of the gate dielectric layers of high voltage transistors, low voltage transistors and ultra-low voltage transistors decrease in sequence.

[0052] In some embodiments, the absolute value of the threshold voltage of the second type of transistor is less than the absolute value of the threshold voltage of the first type of transistor. The threshold voltage refers to the voltage applied when the transistor starts to conduct, and the operating voltage refers to the maximum voltage provided to the source, drain and gate during the operation of the transistor. Generally, the larger the threshold voltage of the transistor, the larger its corresponding operating voltage.

[0053] In some embodiments, the thickness of the gate dielectric layer of the second type of transistor is less than the thickness of the gate dielectric layer of the first type of transistor; in a specific embodiment, the thickness of the gate dielectric layer of the first type of transistor is 30 angstroms ( to For example, the thickness of the gate dielectric layer of the first type of transistor is or When the first type of transistors includes a plurality of different transistors, the thickness of the largest gate dielectric layer in the second type of transistors is smaller than the thickness of the smallest gate dielectric layer in the first type of transistors.

[0054] In some embodiments, the length of the channel of the second type of transistor is less than the length of the channel of the first type of transistor.

[0055] In the embodiment of the present disclosure, by setting at least one of the multiple latches to include a second type of transistor, and the characteristic size of the second type of transistor is smaller than the characteristic size of the first type of transistor, the area of ​​at least one latch in the page buffer can be reduced, thereby reducing the area of ​​the page buffer in the peripheral circuit, which is beneficial to reducing the area of ​​the peripheral circuit in the memory, thereby realizing the miniaturization of the memory.

[0056] Furthermore, at least one latch in the disclosed embodiment uses a second type of transistor with a smaller characteristic size. Accordingly, the voltage required for the operation of the second type of transistor is smaller, which is beneficial to reducing the power consumption of the memory.

[0057] In some embodiments, the memory includes a plurality of bit lines, the peripheral circuit includes a page buffer group; the page buffer group includes a plurality of page buffers; the plurality of page buffers are respectively coupled to the memory cell array via a plurality of bit lines; wherein the latch of at least one of the plurality of page buffers includes a second type of transistor. In a specific embodiment, the latches of the plurality of page buffers all include the second type of transistor, thereby reducing the area of ​​the page buffer group in the peripheral circuit, which is more conducive to the miniaturization of the memory.

[0058] In some embodiments, in combination Figure 2 and Figure 3 As shown, the page buffer 120 also includes: a bit line voltage setting circuit 123, which is respectively coupled to the precharge circuit, the sensing node SO and the bit line BL, and includes: a third type of transistor; wherein the characteristic size of the second type of transistor is smaller than the characteristic size of the third type of transistor.

[0059] The pre-charge and discharge circuit 121 is configured to provide a power supply voltage VDD from a power supply terminal to the bit line voltage setting circuit 123 and / or the sensing node SO; the bit line voltage setting circuit 123 is configured to provide a bit line forced voltage to the bit line BL based on the power supply voltage VDD provided by the pre-charge and discharge circuit 121; wherein the normal programming bit line voltage < the bit line forced voltage < the prohibited programming bit line voltage. The bit line voltage setting circuit 123 may include a plurality of bit line voltage setting components, and different bit line forced voltages may be generated based on different bit line voltage setting components. For example, the first bit line forced voltage, the second bit line forced voltage. And the normal programming bit line voltage < the first bit line forced voltage < the second bit line forced voltage < the prohibited programming bit line voltage.

[0060] The bit line voltage setting component may be an NMOS transistor, a PMOS transistor, or a combination of multiple NMOS transistors and / or multiple PMOS transistors. The bit line voltage setting component may also be other components that can be used to clamp or adjust the voltage, such as a Zener diode, a transient voltage suppressor, a varistor, etc.

[0061] By using the bit line voltage setting circuit 123 and applying different bit line forced voltages to the bit line BL based on the pre-charge and discharge circuit 121, fine programming of the memory cell can be achieved, so that the target threshold voltage distribution is narrower, the reading window between memory cells in different programming states is increased, and accurate data reading is ensured.

[0062] The third type of transistor may be a collection of one or more transistors. The transistors framed by dotted lines in the bit line voltage setting circuit 123 are the third type of transistors. Figure 3 The conductivity type, and / or the characteristic size, and / or the doping concentration of the active region of any two transistors in the third type of transistors may be the same or different.

[0063] In some embodiments, the third type of transistors includes high voltage transistors, and the second type of transistors includes low voltage transistors and / or ultra low voltage transistors. In other embodiments, the third type of transistors includes low voltage transistors, and the second type of transistors includes ultra low voltage transistors. In still other embodiments, the third type of transistors includes high voltage transistors and low voltage transistors, and the second type of transistors includes ultra low voltage transistors. Here, the threshold voltage of the transistors in the third type of transistors and the threshold voltage of the transistors in the first type of transistors may be the same or different, and the present disclosure has no particular restrictions on this.

[0064] In some embodiments, the absolute value of the threshold voltage of the second type of transistor is smaller than the absolute value of the threshold voltage of the third type of transistor; the thickness of the gate dielectric layer of the second type of transistor is smaller than the thickness of the gate dielectric layer of the third type of transistor; the length of the channel of the second type of transistor is smaller than the length of the channel of the third type of transistor. In a specific embodiment, the thickness of the gate dielectric layer of the third type of transistor is The maximum gate dielectric thickness of the second type of transistor is less than

[0065] It should be noted that the pre-charge and discharge circuit and the bit line voltage setting circuit in the page buffer usually need to perform corresponding analog operations in response to analog signals. Replacing some transistors in the pre-charge and discharge circuit and the bit line voltage setting circuit with smaller transistors will affect the normal function of the page buffer.

[0066] In the disclosed embodiment, by replacing at least part of the transistors of the latch in the page buffer with the second type of transistors with smaller feature sizes, the area of ​​the page buffer can be reduced while ensuring that the normal function of the page buffer is not affected.

[0067] In some embodiments, in combination Figure 3 and Figure 4 As shown, the page buffer 120 further includes: at least one read path; the read path includes:

[0068] A first transistor 131, wherein a first terminal of the first transistor 131 is coupled to the sensing node SO, a second terminal of the first transistor 131 is coupled to the ground terminal, and a control terminal of the first transistor 131 is coupled to the output terminal of the latch 122; wherein a characteristic size of the first transistor 131 is smaller than a characteristic size of the first type of transistor;

[0069] The second transistor 132, the first end of the second transistor 132 is coupled to the sensing node SO, the second end of the second transistor 132 is coupled to the first end of the first transistor 131, and the control end of the second transistor 132 is configured to receive a bias voltage; wherein the characteristic size of the second transistor 132 is greater than the characteristic size of the first transistor 131.

[0070] Reference Figure 3As shown, the page buffer 120 includes a plurality of read paths, for example, a read path 124-1, a read path 124-2, a read path 124-3, a read path 124-4, and a read path 124-5. The read paths are configured to sense data latched in a correspondingly set latch. For example, depending on whether a high level at a sensing node SO is discharged to a low level, the data latched in the corresponding latch can be sensed. For example, if a high level at a sensing node SO is discharged to a low level, the data latched in the latch is "1"; if the sensing node SO maintains a high level, the data latched in the latch is "0".

[0071] The read path can also be configured to transmit data between different latches. For example, the data in the latch 122-1 is sensed by the read path 124-1, and a sensing result is obtained. The sensing result can be reflected in the voltage change or the final voltage value of the sensing node SO, and then according to this sensing result, data can be set for other latches, thereby realizing the function of data transmission between different latches. Specifically, when the sensing result indicates that the data latched in the latch 122-1 is "1", the sensing result obtained can be used to set the other latches to "1", that is, the data latched in the latch 122-1 is transmitted to other latches.

[0072] In some embodiments, a plurality of latches are respectively provided with a plurality of read paths.

[0073] In other embodiments, at least two latches of the plurality of latches share a common read path. On the one hand, at least two latches sharing a common read path can reduce the number of read paths in the page buffer, thereby reducing the area of ​​the page buffer in the peripheral circuit; on the other hand, when the area occupied by the page buffer remains unchanged, a larger number of latches can be provided to meet the needs of a memory with higher bit data, thereby being able to store more bits of data information, which is beneficial to improving the bit density of the memory.

[0074] In some embodiments, the second transistor 132 includes a high voltage transistor and / or a low voltage transistor, and the first transistor 131 includes an ultra-low voltage transistor. The first transistor 131 and the second transistor 132 include but are not limited to a P-type transistor or an N-type transistor. In the embodiments of the present disclosure, the first transistor 131 and the second transistor 132 are N-type transistors as an example for description.

[0075] For example, when the data latched in the latch 122 is "1", the first transistor 131 is turned on, and a bias voltage V is applied to the control terminal of the second transistor 132. RD, the second transistor 132 is turned on, and the high level at the sensing node SO is discharged to a low level through the read path 124. For another example, when the data latched in the latch 122 is "0", the first transistor 131 is turned off, and a bias voltage V is applied to the control terminal of the second transistor 132. RD , the second transistor 132 is turned on, and the sensing node SO maintains a high level.

[0076] In some embodiments, the absolute value of the threshold voltage of the second transistor 132 is greater than the absolute value of the threshold voltage of the first transistor 131; the thickness of the gate dielectric layer of the second transistor 132 is greater than the thickness of the gate dielectric layer of the first transistor 131; the length of the channel of the second transistor 132 is greater than the length of the channel of the first transistor 131. In a specific embodiment, the thickness of the gate dielectric layer of the second transistor 132 is The thickness of the gate dielectric layer of the first transistor 131 is less than

[0077] In some embodiments, the bias voltage V RD is less than the sensing voltage V of the sensing node SO SO In this way, the voltage at the first end of the first transistor 131 can be clamped to prevent the first transistor 131 from being broken down.

[0078] In the disclosed embodiment, by setting the characteristic size of the first transistor in the read path to be smaller than the characteristic size of the first type of transistor, the area of ​​the read path in the page buffer can be reduced, and the area of ​​the page buffer can be further reduced.

[0079] In some embodiments, reference Figure 3 As shown, the first type of transistor includes: a third transistor 133 and a fourth transistor 134, the first end of the third transistor 133 is coupled to the power supply terminal, and the second end of the third transistor 133 is coupled to the sensing node SO; the first end of the fourth transistor 134 is coupled to the control end of the third transistor 133, the second end of the fourth transistor 134 is coupled to the ground end, and the control end of the fourth transistor 134 is configured to receive the first control signal Prech_charge_all.

[0080] The third transistor 133 and the fourth transistor 134 include but are not limited to P-type transistors or N-type transistors. In the embodiment of the present disclosure, the third transistor 133 is a P-type transistor and the fourth transistor 134 is an N-type transistor.

[0081] The process of the pre-charge and discharge circuit 121 charging the bit line BL includes: the first control signal Prech_charge_all is enabled, the fourth transistor 134 is turned on, the ground voltage from the ground terminal is provided to the control terminal of the third transistor 133, the third transistor 133 is turned on, and the sensing node SO is pre-charged to a high level.

[0082] The process of the pre-charge and discharge circuit 121 discharging the bit line BL includes: the first control signal Prech_charge_all is not enabled, the fourth transistor 134 is turned off, and in response to the high level of the sensing latch, the third transistor 133 is turned off, and the sensing node SO is grounded and discharged to a low level through the pre-charge and discharge circuit 121.

[0083] It should be noted that, during the execution of the programming operation, it is necessary to determine whether to charge the bit line according to the programming verification result (e.g., the level of the sensing latch). For example, when the programming verification result indicates that the memory cell has reached the target threshold voltage, the bit line coupled to the memory cell needs to be charged to a programming inhibiting bit line voltage (e.g., VDD) to inhibit programming; when the programming verification result indicates that the memory cell has not reached the target threshold voltage, the bit line coupled to the memory cell needs to be adjusted to a normal programming bit line voltage (e.g., VSS) or a bit line forced voltage (greater than VSS and less than VDD) to continue programming.

[0084] In some embodiments, reference Figure 3 As shown, multiple latches include: a sensing latch 122-1, the sensing latch 122-1 includes a second type of transistor; the first type of transistor also includes: a fifth transistor 135 and a sixth transistor 136, the first end of the fifth transistor 135 is coupled to the power supply end, the second end of the fifth transistor 135 is coupled to the control end of the third transistor 133, and the control end of the fifth transistor 135 is configured to receive a second control signal Prech_charge_dis; the sixth transistor 136, wherein the second control signal Prech_charge_dis is different from the first control signal Prech_charge_all; the third control signal Sa_iso is different from the second control signal Prech_charge_dis.

[0085] The sense latch 122 - 1 is configured to store inhibit information and verify information from a verify operation.

[0086] The fifth transistor 135 and the sixth transistor 136 include but are not limited to P-type transistors or N-type transistors. In the embodiment of the present disclosure, the fifth transistor 135 is a P-type transistor and the sixth transistor 136 is an N-type transistor.

[0087] It should be noted that after the transistor in the sensing latch 122-1 is replaced with a second type of transistor with a smaller feature size, the pre-charge and discharge circuit in the related art will have difficulty controlling whether to charge the bit line. For example, the threshold voltage of the second type of transistor becomes smaller, and the voltage of the sensing latch 122-1 decreases accordingly, and the third transistor 133 cannot be turned off.

[0088] In the disclosed embodiment, before precharging the bit line BL, the second control signal Prech_charge_dis is enabled, the fifth transistor 135 is turned on, and the power supply voltage VDD from the power supply terminal is provided to the control terminal of the third transistor 133, and the third transistor 133 is turned off; the third control signal Sa_iso is not enabled, and the sixth transistor 136 is turned off. In this way, even if the voltage of the sensing latch 122-1 decreases, the third transistor 133 can be turned off to ensure the normal operation of the page buffer.

[0089] In other embodiments, when the sensing latch 122-1 does not include the second type of transistor, the pre-charge and discharge circuit in the related art can be used, that is, the fifth transistor and the sixth transistor are omitted. Those skilled in the art can make a selection according to actual needs, and the present disclosure does not limit this.

[0090] In some embodiments, reference Figure 4 As shown, the latch 122 includes: a first inverter 141, a second inverter 142, a seventh transistor 145, an eighth transistor 146 and a ninth transistor 147; the output end of the first inverter 141 is coupled to the input end of the second inverter 142; the input end of the first inverter 141 is coupled to the output end of the second inverter 142; the first end of the seventh transistor 145 is coupled to the first node 143; the first end of the eighth transistor 146 is coupled to the second node 144; the second end of the seventh transistor 145 and the second end of the eighth transistor 146 are coupled to the third node 148; the first end of the ninth transistor 147 is coupled to the third node 148, and the second end of the ninth transistor 147 is coupled to the ground end.

[0091] In some embodiments, the seventh transistor 145 is a reset transistor or a set transistor, and the eighth transistor 146 is a set transistor or a reset transistor. The seventh transistor 145, the eighth transistor 146, and the ninth transistor 147 include but are not limited to P-type transistors or N-type transistors. The second type of transistor includes at least one of the seventh transistor 145, the eighth transistor 146, and the ninth transistor 147.

[0092] When the seventh transistor 145 and the ninth transistor 147 are turned on, the ground voltage of the ground terminal can be transmitted to the first node 143 ; when the eighth transistor 146 and the ninth transistor 147 are turned on, the ground voltage of the ground terminal can be transmitted to the second node 144 .

[0093] In some embodiments, the data actually latched by the latch 122 can be determined by the level information at the first node 143 of the latch 122. For example, if the first node 143 of the latch 122 is at a low level, the latch 122 latches data "0"; if the first node 143 of the latch 122 is at a high level, the latch 122 latches data "1". Here, the first node 143 is coupled to the control terminal of the first transistor 131.

[0094] In some embodiments, the plurality of latches further include a low voltage latch 122-2, a data latch (e.g., a D1 latch 122-3 and a D2 latch 122-4), and a cache latch 122-5. The low voltage latch 122-2 is configured to store prohibition information and adjusted verification information from a verification operation, the data latch is configured to store physical page (e.g., low page LP, middle page MP, high page UP, or extra page XP) information, and the cache latch 122-5 is configured to exchange data with the outside, for example, first transferring external data to the cache latch 122-5, and then transferring it to the sense latch 122-1 through the cache latch 122-5. For another example, the data in the sense latch 122-1 is transferred to the cache latch 122-5, and then transferred to the outside through the cache latch 122-5. The outside may be a memory controller or a host, etc.

[0095] Based on the above memory, an embodiment of the present disclosure further provides a method for operating the memory.

[0096] Figure 5 A flowchart of a memory operation method provided by an embodiment of the present disclosure. The memory includes a memory cell array and a page buffer, the page buffer is set corresponding to the bit line of the memory cell array; the page buffer includes a pre-charge and discharge circuit and a plurality of latches; the pre-charge and discharge circuit is coupled to the bit line through the sensing node of the page buffer, and the plurality of latches are respectively coupled to the sensing node; the operation method includes at least the following steps:

[0097] S210: applying a first voltage to a control terminal of a first type of transistor in a pre-charge and discharge circuit to perform a pre-charge operation on a bit line;

[0098] S220: After performing a precharge operation, applying a second voltage to a control terminal of a second type of transistor in at least one latch to perform a programming operation or a reading operation on a memory cell array through the latch; wherein a characteristic size of the second type of transistor is smaller than a characteristic size of the first type of transistor; and the second voltage is different from the first voltage.

[0099] It should be noted that Figure 5 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 5The steps shown in the figure can be adjusted in sequence according to actual needs.

[0100] Combine the following Figure 6a and Figure 6b The timing diagram and Figure 3 The page buffer 120 in Figure 5 The steps in are described in detail.

[0101] In step S210, a first voltage is applied to a control terminal of a first type of transistor in a pre-charge and discharge circuit to perform a pre-charge operation on a bit line.

[0102] Reference Figure 6b As shown, at time T4 (i.e., the fourth time), the fourth transistor 134 is turned on in response to the enable ground signal Prech_charge_all, and the ground voltage from the ground terminal is provided to the control terminal 133-gate of the third transistor, and the third transistor 133 is turned on, thereby performing a precharge operation on the sensing node SO. Here, Prech_charge_all is a signal applied to the control terminal of the fourth transistor 134, and the first voltage is a high level corresponding to when the signal Prech_charge_all is enabled. It can be understood that the first type of transistor includes the fourth transistor 134.

[0103] In step S220, after performing a precharge operation, a second voltage is applied to a control terminal of a second type of transistor in at least one latch to perform a programming operation or a reading operation on a memory cell array through the latch; wherein the characteristic size of the second type of transistor is smaller than the characteristic size of the first type of transistor; and the second voltage is different from the first voltage.

[0104] Taking the programming operation as an example, after the T4 moment, the programming verification result is sensed by the sensing latch 122-1, and the bit line voltage is adjusted based on the programming verification result. For example, when the programming verification result indicates that the memory cell has reached the target threshold voltage, the eighth transistor 146 and the ninth transistor 147 are turned on, the second node 144 is at a low level, and the control terminal 133-gate of the third transistor is turned on in response to the low level at the second node 144 to charge the bit line to the programming inhibiting bit line voltage VDD; when the programming verification result indicates that the memory cell has not reached the target threshold voltage, the seventh transistor 145 and the ninth transistor 147 are turned on, the second node 144 is at a high level, and the control terminal 133-gate of the third transistor is turned off in response to the high level at the second node 144 to adjust the bit line to the normal programming bit line voltage or the bit line forced voltage.

[0105] Taking the read operation as an example, after time T4, the bit line voltage is sensed by the sense latch 122-1, and the data in the storage cell is latched into the sense latch 122-1. For example, when the data in the storage cell is "1", the eighth transistor 146 and the ninth transistor 147 are turned on, the first node 143 is at a high level, and the latch 122 latches the data "1"; when the data in the storage cell is "0", the seventh transistor 145 and the ninth transistor 147 are turned on, the first node 143 is at a low level, and the latch 122 latches the data "0".

[0106] It can be understood that the second type of transistor includes at least one of the seventh transistor 145 , the eighth transistor 146 and the ninth transistor 147 .

[0107] The second voltage is different from the first voltage including: the second voltage is greater than the first voltage, or the second voltage is less than the first voltage. For example, when the first type of transistor and the second type of transistor are transistors of the same conductivity type (for example, both are N-type transistors), the second voltage is less than the first voltage; for another example, when the first type of transistor is a P-type transistor and the second type of transistor is an N-type transistor, the second voltage is greater than the first voltage. Here, the magnitude of the second voltage and the first voltage depends on the conductivity type of the transistor in the actual device and the characteristic size of the channel.

[0108] In some embodiments, before executing step S210, the operating method further includes: at a first moment, turning on the fifth transistor, and turning off the fourth transistor and the sixth transistor.

[0109] In some embodiments, at the first moment, the fifth transistor is turned on and the fourth transistor and the sixth transistor are turned off, including: applying a first control signal to the control end of the fourth transistor; applying a second control signal to the control end of the fifth transistor; wherein the second control signal is different from the first control signal; applying a third control signal to the control end of the sixth transistor; wherein the third control signal is different from the second control signal.

[0110] Reference Figure 6a As shown, from T1 (i.e., the first moment) to T2, the fifth transistor 135 is turned on in response to the enable ground signal Prech_charge_dis (e.g., low level), and provides the power supply voltage VDD from the power supply terminal to the control terminal of the third transistor 133, and the third transistor 133 is turned off; the fourth transistor 134 and the sixth transistor 136 are turned off in response to the disable ground signal Prech_charge_all (e.g., low level) and the disable ground signal sa_iso (e.g., low level), respectively.

[0111] Here, the enabled signal Prech_charge_dis is the second control signal applied to the control terminal of the fifth transistor 135; the disabled signal Prech_charge_all is the first control signal applied to the control terminal of the fourth transistor 134; and the disabled signal sa_iso is the third control signal applied to the control terminal of the sixth transistor 136.

[0112] In the disclosed embodiment, by turning on the fifth transistor and turning off the fourth transistor and the sixth transistor before precharging, even if the sensing latch includes a second type of transistor with a smaller threshold voltage, the third transistor can be turned off to ensure the normal operation of the page buffer.

[0113] In some embodiments, the above operation method further includes: at a second moment after the first moment, turning off the fifth transistor; and at a third moment after the second moment, turning on the sixth transistor.

[0114] Reference Figure 6a As shown, at time T2 (ie, the second time), the fifth transistor 135 is turned off in response to the disabled ground signal Prech_charge_dis (eg, high level), the fourth transistor 134 and the sixth transistor 136 continue to be turned off, and the third transistor 133 is in a floating state.

[0115] Reference Figure 6a As shown, at time T3 (i.e., the third time), the sixth transistor 136 is turned on in response to the enable ground signal sa_iso (e.g., high level), the fourth transistor 134 and the fifth transistor 135 continue to be turned off, and the third transistor 133 is turned on or off based on the data latched by the sense latch 122-1. Figure 3 and Figure 4 Provide explanation.

[0116] For example, when the sensing latch 122-1 latches data "0" (i.e., the first node 143 is at a low level), the second node 144 is at a high level, and the control terminal 133-gate of the third transistor 133 is turned off in response to the high level at the second node 144. Figure 6a Indicated by the dashed line;

[0117] For another example, when the sensing latch 122 - 1 latches data “1” (ie, the first node 143 is at a high level), the second node 144 is at a low level, and the control terminal 133 -gate of the third transistor 133 is turned on in response to the low level at the second node 144 .

[0118] In the embodiment of the present disclosure, by turning on the fifth transistor and turning off the fourth transistor and the sixth transistor at a first moment; turning off the fifth transistor, the fourth transistor and the sixth transistor at a second moment; and turning on the sixth transistor and turning off the fourth transistor and the fifth transistor at a third moment, the data latched in the sensing latch can be accurately transmitted to the pre-charge and discharge circuit, so that the pre-charge and discharge circuit adjusts the bit line voltage based on the data latched in the sensing latch.

[0119] In some embodiments, the above step S210 includes: at a fourth moment after the first moment, turning off the fifth transistor and the sixth transistor, applying a first voltage to the control terminal of the fourth transistor, and turning on the fourth transistor.

[0120] Reference Figure 6b As shown, at time T4, the fifth transistor 135 is turned off in response to the disabled ground signal Prech_charge_dis (e.g., high level), the sixth transistor 136 is turned off in response to the disabled ground signal sa_iso (e.g., high level), and the fourth transistor 134 is turned on in response to the enabled ground signal Prech_charge_all (e.g., high level), thereby performing a precharge operation on the sensing node SO. It can be understood that by adding the fifth transistor and the sixth transistor to the precharge and discharge circuit, the third transistor can be turned off before precharging. Therefore, during precharging, the fifth transistor and the sixth transistor need to be turned off to avoid affecting the precharge operation. Here, T4 is located after T3.

[0121] In some embodiments, the above operating method further includes: after the first moment and before the fourth moment, turning off the fourth transistor, the fifth transistor and the sixth transistor.

[0122] Reference Figure 6b As shown, at time T5, the fourth transistor 134, the fifth transistor 135 and the sixth transistor 136 are each turned off in response to the disabled ground signal Prech_charge_all, the disabled ground signal Prech_charge_dis and the disabled ground signal sa_iso. Here, T5 is located between T3 and T4.

[0123] In some embodiments, the above operation method further includes: applying a bias voltage to the control terminal of the second transistor after performing the precharge operation; wherein the characteristic size of the second transistor is greater than the characteristic size of the first transistor; and the bias voltage is less than the sensing voltage of the sensing node. Here, after performing the precharge operation, applying a bias voltage to the control terminal of the second transistor can sense the data latched in the corresponding latch through the read path.

[0124] For example, when the data latched in the latch 122 is "1", the first transistor 131 is turned on, and a bias voltage V is applied to the control terminal of the second transistor 132. RD , the second transistor 132 is turned on, and the high level at the sensing node SO is discharged to a low level through the read path 124. For another example, when the data latched in the latch 122 is "0", the first transistor 131 is turned off, and a bias voltage V is applied to the control terminal of the second transistor 132. RD , the second transistor 132 is turned on, and the sensing node SO maintains a high level.

[0125] The present disclosure also provides a memory system. Figure 1A As shown, the memory system 30 includes:

[0126] One or more memories 100 according to any of the above embodiments;

[0127] The memory controller 32 is coupled to the memory 100 and is configured to control the memory 100 .

[0128] The present disclosure also provides an electronic device, such as Figure 1A As shown, it includes a memory system 30 as described in the above embodiment.

[0129] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0130] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0131] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: The memory includes a memory cell array and a page buffer, wherein the page buffer is arranged corresponding to a bit line of the memory cell array, and the page buffer includes: A pre-charge and discharge circuit, the pre-charge and discharge circuit is coupled to the bit line through a sensing node of the page buffer, comprising: a first type of transistor; A plurality of latches are respectively coupled to the sensing nodes; wherein at least one of the plurality of latches comprises a second type of transistor, and a characteristic size of the second type of transistor is smaller than a characteristic size of the first type of transistor.

2. The memory according to claim 1, characterized in that: The page buffer further comprises: at least one read path; the read path comprises: A first transistor, wherein a first end of the first transistor is coupled to the sensing node, a second end of the first transistor is coupled to a ground terminal, and a control end of the first transistor is coupled to an output end of the latch; wherein a characteristic size of the first transistor is smaller than a characteristic size of the first type of transistor.

3. The memory according to claim 2, characterized in that: The read path further comprises: A second transistor, wherein a first terminal of the second transistor is coupled to the sensing node, a second terminal of the second transistor is coupled to the first terminal of the first transistor, and a control terminal of the second transistor is configured to receive a bias voltage; wherein a characteristic size of the second transistor is greater than a characteristic size of the first transistor.

4. The memory according to claim 3, characterized in that: The bias voltage is lower than a sensing voltage of the sensing node.

5. The memory according to claim 1, characterized in that: The first type of transistors includes: a third transistor, wherein a first terminal of the third transistor is coupled to the power supply terminal, and a second terminal of the third transistor is coupled to the sensing node; A fourth transistor, wherein a first terminal of the fourth transistor is coupled to the control terminal of the third transistor, a second terminal of the fourth transistor is coupled to the ground terminal, and the control terminal of the fourth transistor is configured to receive a first control signal.

6. The memory according to claim 5, characterized in that: The plurality of latches include: a sensing latch, the sensing latch including the second type of transistor; the first type of transistor also includes: a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the power terminal, a second terminal of the fifth transistor is coupled to the control terminal of the third transistor, and the control terminal of the fifth transistor is configured to receive a second control signal; wherein the second control signal is different from the first control signal; A sixth transistor, wherein a first end of the sixth transistor is coupled to the control end of the third transistor, a second end of the sixth transistor is coupled to the sensing latch, and the control end of the sixth transistor is configured to receive a third control signal; wherein the third control signal is different from the second control signal.

7. The memory according to claim 6, characterized in that: The third transistor and the fifth transistor include: a P-type transistor; The fourth transistor and the sixth transistor include: N-type transistors.

8. The memory according to claim 1, characterized in that: The page buffer further includes: The bit line voltage setting circuit is respectively coupled to the precharge circuit, the sensing node and the bit line, and comprises: a third type of transistor; wherein the characteristic size of the second type of transistor is smaller than the characteristic size of the third type of transistor.

9. The memory according to claim 1, characterized in that: An absolute value of a threshold voltage of the second type of transistor is smaller than an absolute value of a threshold voltage of the first type of transistor.

10. The memory according to claim 1, characterized in that: The thickness of the gate dielectric layer of the second type of transistor is smaller than the thickness of the gate dielectric layer of the first type of transistor; The length of the channel of the second type of transistor is smaller than the length of the channel of the first type of transistor.

11. A method for operating a memory, characterized in that: The memory includes a memory cell array and a page buffer, wherein the page buffer is arranged corresponding to the bit line of the memory cell array; the page buffer includes a pre-charge and discharge circuit and a plurality of latches; The pre-charge and discharge circuit is coupled to the bit line through a sensing node of the page buffer, and the plurality of latches are respectively coupled to the sensing node; the operation method comprises: Applying a first voltage to a control terminal of a first type of transistor in the pre-charge and discharge circuit to perform a pre-charge operation on the bit line; After performing the precharge operation, a second voltage is applied to the control terminal of the second type of transistor in at least one of the latches to perform a programming operation or a reading operation on the memory cell array through the latch; wherein the characteristic size of the second type of transistor is smaller than the characteristic size of the first type of transistor; and the second voltage is different from the first voltage.

12. The operating method according to claim 11, characterized in that: The page buffer further comprises: at least one read path, the read path comprising a first transistor and a second transistor; a first end of the first transistor is coupled to a second end of the second transistor, the second end of the first transistor is coupled to a ground end, a control end of the first transistor is coupled to an output end of the latch; a first end of the second transistor is coupled to the sensing node; The operation method also includes: After performing the precharge operation, a bias voltage is applied to the control terminal of the second transistor; wherein the characteristic size of the second transistor is greater than the characteristic size of the first transistor; and the bias voltage is less than the sensing voltage of the sensing node.

13. The operating method according to claim 11, characterized in that: The plurality of latches include a sense latch including the second type of transistors; the first type of transistors include a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The first end of the third transistor is coupled to the power supply terminal, and the second end of the third transistor is coupled to the sensing node; the first end of the fourth transistor is coupled to the control terminal of the third transistor, and the second end of the fourth transistor is coupled to the ground terminal; the first end of the fifth transistor is coupled to the power supply terminal, and the second end of the fifth transistor is coupled to the control terminal of the third transistor; the first end of the sixth transistor is coupled to the control terminal of the third transistor, and the second end of the sixth transistor is coupled to the sensing latch; Before applying the first voltage to the control terminal of the first type of transistor in the pre-charge and discharge circuit, the operating method further includes: At a first moment, the fifth transistor is turned on, and the fourth transistor and the sixth transistor are turned off.

14. The operating method according to claim 13, characterized in that: The operation method also includes: At a second moment after the first moment, turning off the fifth transistor; At a third moment after the second moment, the sixth transistor is turned on.

15. The operating method according to claim 13, characterized in that: The step of turning on the fifth transistor and turning off the fourth transistor and the sixth transistor at the first moment comprises: Applying a first control signal to a control terminal of the fourth transistor; Applying a second control signal to the control terminal of the fifth transistor; wherein the second control signal is different from the first control signal; A third control signal is applied to the control terminal of the sixth transistor; wherein the third control signal is different from the second control signal.

16. The operating method according to claim 13, characterized in that: The step of applying a first voltage to a control terminal of a first type of transistor in the pre-charge and discharge circuit comprises: At a fourth moment after the first moment, the fifth transistor and the sixth transistor are turned off, the first voltage is applied to the control terminal of the fourth transistor, and the fourth transistor is turned on.

17. The operating method according to claim 16, characterized in that: The operation method also includes: After the first time and before the fourth time, the fourth transistor, the fifth transistor and the sixth transistor are turned off.

18. The operating method according to claim 11, characterized in that: The thickness of the gate dielectric layer of the second type of transistor is smaller than the thickness of the gate dielectric layer of the first type of transistor; The length of the channel of the second type of transistor is smaller than the length of the channel of the first type of transistor.

19. A memory system, characterized in that: include: One or more memories as claimed in any one of claims 1 to 10; A memory controller is coupled to the memory and is configured to control the memory.

20. An electronic device, characterized in that: Comprising the memory system of claim 19.

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