Semiconductor memory and electronic devices

Abstract

The present invention relates to a semiconductor memory and electronic device. The semiconductor memory includes: a plurality of memory blocks; at least one column strobe control circuit, each of the column strobe control circuits being coupled to at least two of the plurality of memory blocks; each of the memory blocks being coupled to one column strobe control circuit, and each of the memory blocks coupled to the same column strobe control circuit sharing the same column strobe control circuit; the column strobe control circuit being configured to receive selection signals from each of the memory blocks coupled thereto and to generate corresponding memory block control signals based on the selection signals of each of the memory blocks; and the memory blocks being configured to receive corresponding memory block control signals and to perform read / write operations in response to the memory block control signals. The present invention can reduce the area occupied by the column select control circuit in the semiconductor memory.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor memory and electronic equipment. Background Art

[0002] Low-power double-data-rate synchronous dynamic random access memory (LPDDR) is a low-power memory communication standard developed by the Joint Electron Device Engineering Council (JEDEC) for portable electronic devices. It can be roughly divided into five generations: LPDDR, LPDDR2, LPDDR3, LPDDR4 (including LPDDR4X), and LPDDR5. LPDDR5 has twice the number of memory blocks, resulting in twice the number of related circuits, which significantly increases the area required. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor memory and electronic device that can save occupied area.

[0004] In a first aspect, a semiconductor memory is provided, comprising:

[0005] Multiple storage blocks;

[0006] at least one column strobe control circuit, each of the column strobe control circuits being coupled to at least two of the plurality of memory blocks, each of the memory blocks being coupled to one column strobe control circuit, and each of the memory blocks coupled to the same column strobe control circuit sharing one column strobe control circuit;

[0007] The column strobe control circuit is configured to receive selection signals of the respective storage blocks coupled thereto, and generate corresponding storage block control signals based on the selection signals of the respective storage blocks;

[0008] The storage block is used to receive the corresponding storage block control signal and perform a read / write operation in response to the storage block control signal.

[0009] In one embodiment, the column gating control circuit includes:

[0010] a merging circuit, configured to receive the selection signals of the respective storage blocks coupled to the column strobe control circuit, and merge the received selection signals of the respective storage blocks to generate a total selection signal;

[0011] a delay control circuit connected to the combining circuit, and configured to generate a total control signal based on the received total selection signal;

[0012] an identification generating circuit, configured to receive selection signals of the respective storage blocks coupled to the column gating control circuit, and generate a storage block identification signal based on the received selection signals of the respective storage blocks;

[0013] A separation circuit is connected to the delay control circuit and the identification generation circuit respectively, and is used to generate storage block control signals corresponding to each of the storage blocks coupled to the column selection control circuit based on the received total control signal and the storage block identification signal.

[0014] In one embodiment, each of the column enable control circuits is arranged adjacent to each of the coupled storage blocks; the storage blocks coupled to the same column enable control circuit are arranged adjacent to each other in the first direction and / or the second direction, so that the control signal transmission distance between the column enable control circuit and each of the coupled storage blocks is the same, and the first direction and the second direction intersect.

[0015] In one embodiment, the memory blocks coupled to each column strobe control circuit include a first memory block and a second memory block, and the column strobe control circuit is located between the coupled first memory block and the second memory block.

[0016] In one embodiment, the first storage block, the column strobe control circuit coupled to the first storage block, and the second storage block coupled to the column strobe control circuit are sequentially spaced apart along the first direction.

[0017] In one embodiment, the semiconductor memory includes a plurality of the column selection control circuits, and the first storage blocks and the second storage blocks to which the plurality of the column selection control circuits are respectively coupled, the plurality of the column selection control circuits are arranged in sequence along the second direction, the first storage blocks to which the plurality of the column selection control circuits are respectively coupled are arranged in sequence along the second direction, and the second storage blocks to which the plurality of the column selection control circuits are respectively coupled are arranged in sequence along the second direction.

[0018] In one embodiment, the first direction is a row direction, and the second direction is a column direction.

[0019] In one embodiment, the merging circuit includes:

[0020] An OR gate, wherein the first input end of the OR gate is used to receive the selection signal of the first storage block, the second input end of the OR gate is used to receive the selection signal of the second storage block, and the output end of the OR gate is used to output the total selection signal.

[0021] In one embodiment, the identification generating circuit includes:

[0022] An RS latch, wherein the first input end of the RS latch is used to receive the selection signal of the first storage block, the second input end of the RS latch is used to receive the selection signal of the second storage block, and the positive output end and / or the negative output end of the RS latch is used to output the storage block identification signal.

[0023] In one embodiment, the overall control signal includes a plurality of overall control sub-signals, and the storage block control signal corresponding to each storage block also includes a plurality of storage block control sub-signals; the separation circuit includes a plurality of separation sub-circuits, and the plurality of separation sub-circuits respectively correspond one-to-one to the plurality of overall control sub-signals and the plurality of storage block control sub-signals;

[0024] Each of the separation sub-circuits is connected to the delay control circuit and the identification generation circuit respectively, and is configured to generate a corresponding storage block control sub-signal based on the received storage block identification signal and a corresponding overall control sub-signal.

[0025] In one embodiment, each of the separation sub-circuits comprises:

[0026] a NOT gate, wherein an input end of the NOT gate receives the storage block identification signal;

[0027] a first AND gate, wherein a first input terminal of the first AND gate is connected to the output terminal of the NOT gate, a second input terminal of the first AND gate is used to receive a corresponding one of the general control sub-signals, and an output terminal of the first AND gate is used to output a storage block control sub-signal corresponding to the first storage block;

[0028] A second AND gate, wherein the first input terminal of the second AND gate is connected to the input terminal of the NOT gate, the second input terminal of the second AND gate is used to receive a corresponding one of the total control sub-signals, and the output terminal of the second AND gate is used to output a storage block control sub-signal corresponding to the second storage block.

[0029] In one embodiment, the separation circuit includes:

[0030] a third AND gate, wherein a first input terminal of the third AND gate is connected to the inverting output terminal of the RS latch, a second input terminal of the third AND gate is connected to the delay control circuit, and an output terminal of the third AND gate is used to output a control signal of the first storage block;

[0031] A fourth AND gate, wherein the first input end of the fourth AND gate is connected to the non-inverting output end of the RS latch, the second input end of the fourth AND gate is connected to the delay control circuit, and the output end of the fourth AND gate is used to output the control signal of the second storage block.

[0032] In one embodiment, the storage block includes a storage cell array and an error correction and detection circuit; the multiple general control sub-signals include multiple array general control sub-signals and multiple ECC general control sub-signals, and the multiple storage block control sub-signals include multiple array control sub-signals and multiple ECC control sub-signals; the storage cell array performs read / write data operations based on the array control sub-signals, and the error correction and detection circuit performs error correction and detection operations on the read / write data based on the ECC control sub-signals.

[0033] In one embodiment, the storage block control sub-signal includes an enable signal of a data reading circuit in the storage cell array, an enable signal of a data writing circuit in the storage cell array, and an enable signal of the error correction and detection circuit.

[0034] In a second aspect, an electronic device is provided, comprising the semiconductor memory provided in the first aspect.

[0035] In the semiconductor memory and electronic device described above, since the column gating control circuit is coupled to at least two memory blocks among the plurality of memory blocks, and each memory block is coupled to a column gating control circuit, each memory block coupled to the same column gating control circuit shares a common column gating control circuit. This reduces the number of column gating control circuits and saves space compared to using a different column gating control circuit for each memory block. Furthermore, the column gating control circuit receives selection signals from each memory block coupled thereto and generates corresponding memory block control signals based on the selection signals from each memory block. The memory blocks receive the corresponding memory block control signals and perform read / write operations in response to the memory block control signals, achieving the same effect as using a different column gating control circuit for each memory block. Thus, the semiconductor memory and electronic device described above reduce the number of column gating control circuits and save space while achieving separate control of each memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1A schematic diagram of the structure of a semiconductor memory in the related art;

[0038] Figure 2 is a schematic structural diagram of a semiconductor memory according to an embodiment;

[0039] Figure 3 is a structural block diagram of a column selection control circuit according to an embodiment;

[0040] Figure 4 A timing diagram of various signals in a column selection control circuit according to an embodiment;

[0041] Figure 5 is a structural diagram of a merging circuit according to an embodiment;

[0042] Figure 6 1 is a schematic structural diagram of an RS latch according to an embodiment;

[0043] Figure 7 1 is a schematic structural diagram of an RS latch according to another embodiment;

[0044] Figure 8 1 is a schematic structural diagram of a separation circuit according to an embodiment;

[0045] Figure 9 is a schematic structural diagram of a separation circuit according to another embodiment;

[0046] Figure 10 FIG. 1 is a structural diagram of a column selection control circuit according to an embodiment.

[0047] Description of reference numerals:

[0048] 101. Storage block, 102. Column strobe control circuit;

[0049] 201, storage block, 202, column strobe control circuit;

[0050] 10. Merging circuit, 11. OR gate;

[0051] 20. Delay control circuit;

[0052] 30. Identity generation circuit, 31. First NOR gate, 32. Second NOR gate, 33. First NAND gate, 34. Second NAND gate;

[0053] 40. Separation circuit, 41. NOT gate, 42. First AND gate, 43. Second AND gate, 44. Third AND gate, 45. Fourth AND gate. DETAILED DESCRIPTION

[0054] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0056] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0057] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0058] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0059] JEDEC requires LPDDR5 to have 16 memory blocks, twice as many as LPDDR4. Figure 1 Schematic diagram of the structure of semiconductor memory in related technology, such as Figure 1 As shown, each memory block 101 is independently provided with a column strobe control circuit 102 for coupling, and 16 memory blocks 101 are provided with 16 column strobe control circuits 102 in total. The 16 column strobe control circuits 102 occupy a lot of area.

[0060] Based on the above situation, the present application provides a semiconductor memory and electronic device, in which a column selection control circuit is coupled to at least two storage blocks among multiple storage blocks, and each memory coupled to the same column selection control circuit shares a column selection control circuit, thereby reducing the number of column selection control circuits and saving occupied area.

[0061] Figure 2 FIG. 1 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present invention. Figure 2 As shown, the semiconductor memory circuit includes a plurality of memory blocks 201 and at least one column strobe control circuit 202. Each column strobe control circuit 202 is coupled to at least two memory blocks 201 among the plurality of memory blocks 201. Each memory block 201 is coupled to one column strobe control circuit 202, and each memory block 201 coupled to the same column strobe control circuit 202 shares one column strobe control circuit 202. The column strobe control circuit 202 is configured to receive selection signals from the memory blocks 201 coupled thereto and generate corresponding memory block control signals based on the selection signals from the memory blocks 201. The memory blocks 201 are configured to receive corresponding memory block control signals and perform read / write operations in response to the memory block control signals.

[0062] The column strobe control circuit 202 in the semiconductor memory device is coupled to at least two of the multiple memory blocks, with each memory block coupled to a column strobe control circuit. Each memory block coupled to the same column strobe control circuit shares a common column strobe control circuit. This reduces the number of column strobe control circuits and saves space compared to using a different column strobe control circuit for each memory block. Furthermore, the column strobe control circuit receives selection signals from each memory block coupled thereto and generates corresponding memory block control signals based on the selection signals from each memory block. The memory blocks receive the corresponding memory block control signals and perform read / write operations in response to the memory block control signals, achieving the same effect as using a different column strobe control circuit for each memory block. Thus, the semiconductor memory device reduces the number of column strobe control circuits and saves space while achieving separate control of each memory block.

[0063] by Figure 2 For example, the semiconductor memory circuit includes 16 memory blocks 201 and 8 column strobe control circuits 202. Each column strobe control circuit 202 is coupled to two memory blocks 201, and each memory block 201 is coupled to one column strobe control circuit 202. Two memory blocks 201 coupled to the same column strobe control circuit 202 share one column strobe control circuit 202. In this way, a total of 8 column strobe control circuits 202 are provided for the 16 memory blocks 201. Figure 1 A total of 16 column gating control circuits 102 are provided in the 16 storage blocks 101, and the number of column gating control circuits is reduced by half, and the occupied area is also reduced by half.

[0064] Alternatively, as Figure 2As shown, each column gating control circuit is disposed adjacent to each memory block coupled thereto. Memory blocks coupled to the same column gating control circuit are disposed adjacent to each other in the first direction and / or the second direction, such that the control signal transmission distances between the column gating control circuit and each memory block coupled thereto are the same, and the first direction and the second direction intersect.

[0065] In the above embodiment, the storage blocks coupled to the same column selection control circuit are arranged adjacent to each other in the first direction and / or the second direction, so that the control signal transmission distance between the column selection control circuit and each storage block coupled thereto is the same. This can ensure that the multiple storage blocks sharing the same column selection control circuit have the same path to the column selection control circuit, avoiding different transmission delays of the storage block control signals due to different paths, thereby ensuring the stability of signal transmission when sharing the same column selection control circuit.

[0066] Or Figure 2 For example, the two memory blocks 201 coupled to each column strobe control circuit 202 are respectively a first memory block and a second memory block, and the column strobe control circuit 202 is located between the coupled first memory block and the second memory block.

[0067] In the above embodiment, each column enable control circuit is coupled to two storage blocks and is located between the two storage blocks, which facilitates the realization of the same control signal transmission distance between the column enable control circuit and the two storage blocks coupled thereto, thereby ensuring the stability of signal transmission when sharing the same column enable control circuit.

[0068] Accordingly, the semiconductor memory includes a plurality of column strobe control circuits 202 , and a first memory block and a second memory block to which the plurality of column strobe control circuits 202 are respectively coupled.

[0069] For example, Figure 2 As shown, the first storage block, the column strobe control circuit 202 coupled to the first storage block, and the second storage block coupled to the column strobe control circuit 202 are sequentially arranged along a first direction A. The first direction A may be a row direction.

[0070] The plurality of column strobe control circuits 202 are sequentially spaced apart along a second direction B. The first memory blocks to which the plurality of column strobe control circuits 202 are respectively coupled are sequentially spaced apart along the second direction B. The second memory blocks to which the plurality of column strobe control circuits 202 are respectively coupled are sequentially spaced apart along the second direction B. The second direction B may be a column direction.

[0071] In the above embodiment, multiple column selection control circuits, multiple first storage blocks, and multiple second storage blocks are respectively arranged in sequence along one direction, and each column selection control circuit and the first storage block and the second storage block coupled thereto are arranged in sequence along another direction, so as to facilitate the realization of the same control signal transmission distance between the column selection control circuit and the two storage blocks coupled thereto, thereby ensuring the stability of signal transmission when sharing the same column selection control circuit.

[0072] Figure 3 FIG. 1 is a structural block diagram of a column selection control circuit according to an embodiment of the present invention. Figure 3 As shown, in one embodiment, the column strobe control circuit 202 includes a merging circuit 10, a delay control circuit 20, an identification generation circuit 30, and a separation circuit 40. The merging circuit 10 is configured to receive the selection signals of the respective memory blocks 201 coupled to the column strobe control circuit 202 and to merge the received selection signals of the respective memory blocks 201 to generate a total selection signal. The delay control circuit 20 is connected to the merging circuit 10 and is configured to generate a total control signal based on the received total selection signal. The identification generation circuit 30 is configured to receive the selection signals of the respective memory blocks 201 coupled to the column strobe control circuit 202 and to generate a memory block identification signal based on the received selection signals of the respective memory blocks 201. The separation circuit 40 is connected to the delay control circuit 20 and the identification generation circuit 30, respectively, and is configured to generate a memory block control signal corresponding to each memory block 201 coupled to the column strobe control circuit 202 based on the received total control signal and the memory block identification signal.

[0073] In the above embodiment, the merging circuit first merges the selection signals of the respective memory blocks coupled to the column strobe control circuit into a total selection signal, then the delay control circuit generates a total control signal based on the total selection signal, and finally the separation circuit separates the total control signal into memory block control signals corresponding to the respective memory blocks coupled to the column strobe control circuit. Compared with the case where the selection signals of the respective memory blocks coupled to the column strobe control circuit each generate a corresponding memory block control signal, the number of delay control circuits is reduced from multiple to one, which can effectively save the occupied area of ​​the entire circuit. In addition, the identification generation circuit receives the selection signals of the respective memory blocks coupled to the column strobe control circuit and generates a memory block identification signal based on the received selection signals of the respective memory blocks. In this way, when the separation circuit separates the total control signal into the memory block control signals corresponding to the respective memory blocks coupled to the column strobe control signal, the memory block identification signal can be used for identification, and the memory block control signals corresponding to the respective memory blocks coupled to the column strobe control signal can be accurately determined from the total control signal.

[0074] Or Figure 2 For example, the two storage blocks 201 coupled to each column strobe control circuit 202 are respectively a first storage block and a second storage block. Figure 4As shown, the merging circuit 10 merges the selection signal CAC0 of the first storage block and the selection signal CAC1 of the second storage block into a total selection signal CAC01. At the same time, the flag generation circuit 30 generates a storage block identification signal BankFlag based on the selection signal CAC0 of the first storage block and the selection signal CAC1 of the second storage block. The delay control circuit 20 generates a total control signal YsaEn01 based on the total selection signal CAC01. The separation circuit 40 separates the total control signal YsaEn01 into a storage block control signal YsaEn0 corresponding to the first storage block and a storage block control signal YsaEn1 corresponding to the second storage block according to the storage block identification signal BankFlag.

[0075] Figure 5 FIG. 1 is a structural diagram of a merging circuit according to an embodiment of the present invention. Figure 5 As shown, optionally, the merging circuit 10 includes an OR gate 11. A first input terminal of the OR gate 11 is used to receive a selection signal CAC0 of the first storage block, a second input terminal of the OR gate 11 is used to receive a selection signal CAC1 of the second storage block, and an output terminal of the OR gate 11 is used to output a total selection signal CAC01 to the delay control circuit 20, so that the delay control circuit 20 generates a total control signal YsaEn01 based on the total selection signal CAC01.

[0076] In the above embodiment, the merging circuit includes an OR gate, each input end of the OR gate can receive selection signals of different storage blocks respectively, and merge the selection signals of at least two storage blocks to generate a total selection signal output.

[0077] In one implementation, the flag generation circuit 30 includes an RS latch. A first input terminal of the RS latch is used to receive a selection signal CAC0 of the first storage block, a second input terminal of the RS latch is used to receive a selection signal CAC1 of the second storage block, and a positive output terminal and / or a negative output terminal of the RS latch is used to output the storage block flag signal BankFlag.

[0078] For example, Figure 6 As shown, the RS latch includes a first NOR gate 31 and a second NOR gate 32. The first input of the first NOR gate 31 is used to receive the selection signal CAC0 of the first storage block, and the second input of the first NOR gate 31 is connected to the output of the second NOR gate 32. The output of the first NOR gate 31 serves as the non-inverting output of the RS latch. The first input of the second NOR gate 32 is connected to the output of the first NOR gate 31. The second input of the second NOR gate 32 is used to receive the selection signal CAC1 of the second storage block, and the output of the second NOR gate 32 serves as the inverting output of the RS latch.

[0079] like Figure 7As shown, the RS latch includes a first NAND gate 33 and a second NAND gate 34. The first input of the first NAND gate 33 is used to receive the selection signal CAC0 for the first storage block, and the second input of the first NAND gate 33 is connected to the output of the second NAND gate 34. The output of the first NAND gate 33 serves as the non-inverting output of the RS latch. The first input of the second NAND gate 34 is connected to the output of the first NAND gate 33. The second input of the second NAND gate 34 is used to receive the selection signal CAC1 for the second storage block, and the output of the second NAND gate 34 serves as the inverting output of the RS latch.

[0080] In another implementation, the identifier generation circuit 30 includes an encoder. Multiple input terminals of the encoder are used to receive selection signals of different storage blocks, for example, the first input terminal of the encoder is used to receive the selection signal CAC0 of the first storage block, and the second input terminal of the encoder is used to receive the selection signal CAC1 of the second storage block. The output terminal of the encoder is used to output the storage block identification signal BankFlag. <n:0>, n+1 is the number of memory blocks. For example, when each column selection control circuit 202 is coupled to two memory blocks 201 , the output terminal of the encoder outputs the memory block identification signal BankFlag<1:0>.

[0081] Optionally, the overall control signal includes multiple overall control sub-signals, and the storage block control signal corresponding to each storage block 202 also includes multiple storage block control sub-signals. The separation circuit 40 includes multiple separation sub-circuits, each corresponding one-to-one to the multiple overall control sub-signals and the multiple storage block control sub-signals. Each separation sub-circuit is connected to the delay control circuit 20 and the identifier generation circuit 30, respectively, and is configured to generate a corresponding storage block control sub-signal based on a received storage block identifier signal and a corresponding overall control sub-signal.

[0082] In one implementation, Figure 8 As shown, each separation sub-circuit includes a NOT gate 41, a first AND gate 42, and a second AND gate 43. The input of NOT gate 41 receives the memory block identification signal BankFlag. The first input of first AND gate 42 is connected to the output of NOT gate 41, the second input of first AND gate 42 is used to receive a corresponding master control sub-signal, and the output of first AND gate 42 is used to output a memory block control sub-signal corresponding to the first memory block. The first input of second AND gate 43 is connected to the input of NOT gate 41, the second input of second AND gate 43 is used to receive a corresponding master control sub-signal, and the output of second AND gate 43 is used to output a memory block control sub-signal corresponding to the second memory block.

[0083] by Figure 4 For example, the flag generation circuit 30 generates a memory block flag signal BankFlag based on the first memory block selection signal CAC0 and the second memory block selection signal CAC1. The input of the NOT gate 41 receives the memory block flag signal BankFlag and outputs it to the first input of the first AND gate 42. The second input of the first AND gate 42 receives the total selection signal CAC01, and the output of the first AND gate 42 outputs the memory block control signal YsaEn0 corresponding to the first memory block. The first input of the second AND gate 43 receives the memory block flag signal BankFlag, the second input of the second AND gate 43 receives the total selection signal CAC01, and the output of the second AND gate 43 outputs the memory block control signal YsaEn1 corresponding to the second memory block.

[0084] In another implementation, Figure 9 As shown, the separation circuit 40 includes a third AND gate 44 and a fourth AND gate 45. A first input of the third AND gate 44 is connected to the inverting output of the RS latch, a second input of the third AND gate 44 is connected to the delay control circuit 20, and an output of the third AND gate 44 is used to output a control signal for the first storage block. A first input of the fourth AND gate 45 is connected to the non-inverting output of the RS latch, a second input of the fourth AND gate 44 is connected to the delay control circuit 20, and an output of the fourth AND gate 44 is used to output a control signal for the second storage block.

[0085] In one embodiment, Figure 10 As shown, the column strobe control circuit 202 includes a merging circuit 10 , a delay control circuit 20 , a flag generating circuit 30 and a separating circuit 40 .

[0086] The merging circuit 10 includes an OR gate 11. A first input terminal of the OR gate 11 is used to receive a selection signal CAC0 of the first storage block, a second input terminal of the OR gate 11 is used to receive a selection signal CAC1 of the second storage block, and an output terminal of the OR gate 11 is used to output a total selection signal CAC01 to the delay control circuit 20, so that the delay control circuit 20 generates a total control signal YsaEn01 based on the total selection signal CAC01.

[0087] The flag generation circuit 30 includes an RS latch. A first input terminal of the RS latch is used to receive a selection signal CAC0 for the first storage block, a second input terminal of the RS latch is used to receive a selection signal CAC1 for the second storage block, and a positive output terminal and / or negative output terminal of the RS latch is used to output a storage block flag signal BankFlag.

[0088] Separation circuit 40 includes a NOT gate 41, a first AND gate 42, and a second AND gate 43. The input of NOT gate 41 receives the memory block identification signal BankFlag. A first input of first AND gate 42 is connected to the output of NOT gate 41, a second input of first AND gate 42 is used to receive the master control signal YsaEn01, and an output of first AND gate 42 is used to output the memory block control signal YsaEn0 corresponding to the first memory block. A first input of second AND gate 43 is connected to the input of NOT gate 41, a second input of second AND gate 43 is used to receive the master control signal YsaEn01, and an output of second AND gate 43 is used to output the memory block control signal YsaEn1 corresponding to the second memory block.

[0089] In practical applications, the delay control circuit 20 is typically implemented using analog circuits, which occupies a very large area. In the present application, two memory blocks (i.e., the first memory block and the second memory block) share a single delay control circuit 20, and corresponding memory block control signals can be generated based on their respective corresponding selection signals, effectively reducing the area occupied by the analog circuits.

[0090] In one embodiment, a memory block includes a memory cell array and an error checking and correcting (ECC) circuit. Multiple general control sub-signals include multiple array general control sub-signals and multiple ECC general control sub-signals. The array general control sub-signals are used to control the memory cell array, and the ECC general control sub-signals are used to control the ECC circuit. Multiple memory block control sub-signals include multiple array control sub-signals and multiple ECC control sub-signals. The memory cell array performs read / write data operations based on the array control sub-signals, and the error checking and correcting circuit performs error checking and correcting operations on the read / write data based on the ECC control sub-signals.

[0091] Optionally, the storage block control sub-signal includes an enable signal of a data read circuit (such as a read amplifier) ​​in the storage cell array, an enable signal of a data write circuit (such as a write driver) in the storage cell array, and an enable signal of an error correction and detection circuit.

[0092] Exemplarily, the read / write operation includes controlling an amplifier in a data read circuit to process read data, or controlling a driver in a data write circuit to drive data to be written.

[0093] Based on the same inventive concept, the present application also provides an electronic device, which includes the semiconductor memory provided by any of the above embodiments.

[0094] The electronic device includes a semiconductor memory, wherein a column strobe control circuit in the semiconductor memory is coupled to at least two memory blocks among a plurality of memory blocks, each memory block being coupled to a column strobe control circuit. Each memory block coupled to the same column strobe control circuit shares the same column strobe control circuit. Compared to using a different column strobe control circuit for each memory block, the number of column strobe control circuits can be reduced, saving occupied area. Furthermore, the column strobe control circuit receives selection signals from each memory block coupled thereto and generates corresponding memory block control signals based on the selection signals of each memory block. The memory blocks receive the corresponding memory block control signals and perform read / write operations in response to the memory block control signals, achieving the same effect as using a different column strobe control circuit for each memory block. Thus, the electronic device reduces the number of column strobe control circuits and saves occupied area while achieving separate control of each memory block.

[0095] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of these terms do not necessarily refer to the same embodiment or example.

[0096] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A semiconductor memory, characterized in that: The semiconductor memory comprises: Multiple storage blocks; at least one column strobe control circuit, each of the column strobe control circuits being coupled to at least two of the plurality of memory blocks, each of the memory blocks being coupled to one column strobe control circuit, and each of the memory blocks coupled to the same column strobe control circuit sharing one column strobe control circuit; The column strobe control circuit is configured to receive selection signals of the respective memory blocks coupled thereto, and generate corresponding memory block control signals based on the selection signals of the respective memory blocks; The storage block is configured to receive a corresponding storage block control signal and perform a read / write operation in response to the storage block control signal; The column strobe control circuit comprises: a merging circuit, configured to receive the selection signals of the respective storage blocks coupled to the column strobe control circuit, and merge the received selection signals of the respective storage blocks to generate a total selection signal; The column strobe control circuit generates storage block control signals corresponding to the respective storage blocks coupled thereto based on the overall selection signal.

2. The semiconductor memory according to claim 1, wherein The column strobe control circuit further includes: a delay control circuit connected to the combining circuit, and configured to generate a total control signal based on the received total selection signal; an identification generating circuit, configured to receive selection signals of the respective storage blocks coupled to the column gating control circuit, and generate a storage block identification signal based on the received selection signals of the respective storage blocks; A separation circuit is connected to the delay control circuit and the identification generation circuit respectively, and is used to generate storage block control signals corresponding to each of the storage blocks coupled to the column selection control circuit based on the received total control signal and the storage block identification signal.

3. The semiconductor memory according to claim 2, wherein: Each of the column enable control circuits is arranged adjacent to the coupled storage blocks; the storage blocks coupled to the same column enable control circuit are arranged adjacent to each other in the first direction and / or the second direction, so that the control signal transmission distance between the column enable control circuit and the coupled storage blocks is the same, and the first direction and the second direction intersect.

4. The semiconductor memory according to claim 3, wherein The memory blocks coupled to each column strobe control circuit include a first memory block and a second memory block, and the column strobe control circuit is located between the coupled first memory block and the second memory block.

5. The semiconductor memory according to claim 4, wherein The first storage block, the column strobe control circuit coupled to the first storage block, and the second storage block coupled to the column strobe control circuit are sequentially spaced apart along the first direction.

6. The semiconductor memory according to claim 5, wherein The semiconductor memory includes a plurality of column selection control circuits, and the first storage blocks and the second storage blocks to which the plurality of column selection control circuits are respectively coupled. The plurality of column selection control circuits are arranged in sequence at intervals along the second direction, the first storage blocks to which the plurality of column selection control circuits are respectively coupled are arranged in sequence at intervals along the second direction, and the second storage blocks to which the plurality of column selection control circuits are respectively coupled are arranged in sequence at intervals along the second direction.

7. The semiconductor memory according to claim 6, wherein: The first direction is a row direction, and the second direction is a column direction.

8. The semiconductor memory according to any one of claims 4 to 7, wherein: The merging circuit includes: An OR gate, wherein the first input end of the OR gate is used to receive the selection signal of the first storage block, the second input end of the OR gate is used to receive the selection signal of the second storage block, and the output end of the OR gate is used to output the total selection signal.

9. The semiconductor memory according to any one of claims 4 to 7, wherein: The identification generating circuit includes: An RS latch, wherein the first input end of the RS latch is used to receive the selection signal of the first storage block, the second input end of the RS latch is used to receive the selection signal of the second storage block, and the positive output end and / or the negative output end of the RS latch is used to output the storage block identification signal.

10. The semiconductor memory according to claim 9, wherein The overall control signal includes a plurality of overall control sub-signals, and the storage block control signal corresponding to each storage block also includes a plurality of storage block control sub-signals; the separation circuit includes a plurality of separation sub-circuits, and the plurality of separation sub-circuits respectively correspond one-to-one to the plurality of overall control sub-signals and the plurality of storage block control sub-signals; Each of the separation sub-circuits is connected to the delay control circuit and the identification generation circuit respectively, and is configured to generate a corresponding storage block control sub-signal based on the received storage block identification signal and a corresponding overall control sub-signal.

11. The semiconductor memory according to claim 10, wherein: Each of the separation sub-circuits comprises: a NOT gate, wherein an input end of the NOT gate receives the storage block identification signal; a first AND gate, wherein a first input terminal of the first AND gate is connected to the output terminal of the NOT gate, a second input terminal of the first AND gate is used to receive a corresponding one of the general control sub-signals, and an output terminal of the first AND gate is used to output a storage block control sub-signal corresponding to the first storage block; A second AND gate, wherein the first input terminal of the second AND gate is connected to the input terminal of the NOT gate, the second input terminal of the second AND gate is used to receive a corresponding one of the total control sub-signals, and the output terminal of the second AND gate is used to output a storage block control sub-signal corresponding to the second storage block.

12. The semiconductor memory according to claim 10, wherein: The separation circuit includes: a third AND gate, wherein a first input terminal of the third AND gate is connected to the inverting output terminal of the RS latch, a second input terminal of the third AND gate is connected to the delay control circuit, and an output terminal of the third AND gate is used to output a control signal of the first storage block; A fourth AND gate, wherein the first input end of the fourth AND gate is connected to the non-inverting output end of the RS latch, the second input end of the fourth AND gate is connected to the delay control circuit, and the output end of the fourth AND gate is used to output the control signal of the second storage block.

13. The semiconductor memory according to claim 10, wherein: The storage block includes a storage cell array and an error correction and detection circuit; the plurality of general control sub-signals include a plurality of array general control sub-signals and a plurality of ECC general control sub-signals, and the plurality of storage block control sub-signals include a plurality of array control sub-signals and a plurality of ECC control sub-signals; The memory cell array performs a read / write data operation based on the array control sub-signal, and the error correction and detection circuit performs an error correction and detection operation on the read / write data based on the ECC control sub-signal.

14. The semiconductor memory according to claim 13, wherein: The storage block control sub-signals include an enable signal for a data reading circuit in the storage cell array, an enable signal for a data writing circuit in the storage cell array, and an enable signal for the error correction and detection circuit.

15. A semiconductor memory, characterized in that: The semiconductor memory comprises: Multiple storage blocks; at least one column strobe control circuit, each of the column strobe control circuits being coupled to at least two of the plurality of memory blocks, each of the memory blocks being coupled to one column strobe control circuit, and each of the memory blocks coupled to the same column strobe control circuit sharing one column strobe control circuit; The column strobe control circuit is configured to receive selection signals of the respective memory blocks coupled thereto, and generate corresponding memory block control signals based on the selection signals of the respective memory blocks; The storage block is configured to receive a corresponding storage block control signal and perform a read / write operation in response to the storage block control signal; Each of the column enable control circuits is arranged adjacent to the coupled storage blocks; the storage blocks coupled to the same column enable control circuit are arranged adjacent to each other in the first direction and / or the second direction, so that the control signal transmission distance between the column enable control circuit and the coupled storage blocks is the same, and the first direction and the second direction intersect.

16. An electronic device, characterized in that: The electronic device comprises the semiconductor memory according to any one of claims 1 to 15.

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