Semiconductor system for performing read-modify-write operations

Abstract

The invention relates to a semiconductor system for performing read-modify-write operations. The semiconductor system includes: a controller outputting a clock, a chip selection signal, a command address, and data; and a semiconductor device that performs an automatic refresh operation when a chip selection signal and a command address input in synchronization with a clock have a combination for performing the automatic refresh operation, when an automatic refresh operation is performed a first set number of times, errors of internal data stored therein are corrected by performing a read-modify-write operation instead of the automatic refresh operation and the corrected internal data are stored, when a chip selection signal and a command address input in synchronization with a clock have a combination for performing a self-refresh operation, the self-refresh operation is performed, and correcting an error of the internal data stored therein and storing the corrected internal data by performing a read-modify-write operation instead of the self-refresh operation when the self-refresh operation is performed a second set number of times.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0078542 filed in the Korean Intellectual Property Office on June 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor system for correcting an error of internal data by performing a read-modify-write operation when each of an auto refresh operation and a self refresh operation is performed a set number of times. Background Art

[0004] Recently, in order to increase the operating speed of semiconductor devices, a method of inputting and outputting multiple bits of data per clock cycle has been used, such as DDR2, DDR3, DDR4, or DDR5. If the input / output speed of data reaches a certain speed, a separate device and method for ensuring the reliability of data transmission are additionally required because the probability of an error occurring during the process of transmitting data also increases.

[0005] A method is being used to ensure the reliability of data transmission by generating an error check code and transmitting the error check code together with the data, the error check code being able to check whether an error occurs whenever data is transmitted. The error check code includes an error detection code (EDC) that is able to detect whether an error has occurred and an error correction code (ECC) that is able to automatically correct the error when an error occurs. Summary of the invention

[0006] In one embodiment, a semiconductor system may include: a controller configured to output a clock, a chip select signal and a command address, and configured to output data; and a semiconductor device configured to perform an automatic refresh operation when a chip select signal and a command address input synchronously with the clock have a combination for performing an automatic refresh operation, configured to correct errors of internal data stored in the semiconductor device by performing a read-modify-write operation instead of an automatic refresh operation when the automatic refresh operation is performed a first set number of times and store the corrected internal data, configured to perform a self-refresh operation when a chip select signal and a command address input synchronously with the clock have a combination for performing a self-refresh operation, and configured to correct errors of internal data stored in the semiconductor device by performing a read-modify-write operation instead of a self-refresh operation when the self-refresh operation is performed a second set number of times and store the corrected internal data.

[0007] In one embodiment, a semiconductor device may include: a read-modify-write control circuit configured to generate a power control signal when a self-refresh operation is performed a set number of times, and configured to sequentially generate an internal read signal and an internal write signal; a power supply circuit configured to supply a power supply voltage to a column control circuit during an interval in which the power control signal is enabled; and a column control circuit configured to operate by being supplied with the power supply voltage, configured to generate read data and a read parity by receiving the internal data and the internal parity when an internal read signal is input, and configured to output the read data as internal data by correcting an error of the read data based on the read parity and the write parity when an internal write signal is input. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a configuration of a semiconductor system according to an embodiment of the present disclosure.

[0009] Figure 2 The diagram is based on the Figure 1 0014 is a block diagram of a configuration of one embodiment of a semiconductor device in a semiconductor system illustrated in FIG.

[0010] Figure 3 The diagram is based on the Figure 2 0014 is a block diagram of a configuration of one embodiment of a command generation circuit in a semiconductor device illustrated in FIG.

[0011] Figure 4 The diagram is based on the Figure 2 0 is a block diagram of a configuration of one embodiment of a row address generation circuit in a semiconductor device illustrated in FIG.

[0012] Figure 5 The diagram is based on the Figure 2 0014 is a block diagram of a configuration of one embodiment of a refresh control circuit in a semiconductor device illustrated in FIG.

[0013] Figure 6 The diagram is based on the Figure 2 0014 is a block diagram of the construction of one embodiment of a read-modify-write control circuit in a semiconductor device illustrated in FIG.

[0014] Figure 7 The diagram is based on the Figure 6 A diagram of the construction of one embodiment of an internal activity signal generating circuit in a read-modify-write control circuit illustrated in FIG.

[0015] Figure 8 The diagram is based on the Figure 6 0 is a block diagram of the construction of one embodiment of a read / write control circuit in the read-modify-write control circuit illustrated in FIG.

[0016] Fig. 9 The diagram is based on the Figure 6 A diagram of the construction of one embodiment of a power control signal generating circuit in a read-modify-write control circuit illustrated in FIG.

[0017] Fig.10 The diagram is based on the Figure 2 A diagram of the configuration of one embodiment of a memory circuit in a semiconductor device is illustrated in FIG.

[0018] Fig.11 The diagram is based on the Figure 2 0 is a block diagram of a configuration of one embodiment of a column control circuit in a semiconductor device illustrated in FIG.

[0019] Fig.12 is a diagram for describing an auto refresh operation of a semiconductor device according to an embodiment of the present disclosure.

[0020] Fig.13 is a diagram for describing a self-refresh operation of a semiconductor device according to an embodiment of the present disclosure.

[0021] Fig.14 is a diagram illustrating a configuration according to one embodiment of an electronic system, Figure 1 and Fig.13 The semiconductor system illustrated in FIG. 1 has been applied to the electronic system. DETAILED DESCRIPTION

[0022] In the description of the following embodiments, the term "preset" indicates that when a parameter is used in a process or algorithm, the value of the parameter is predetermined. According to one embodiment, the value of the parameter can be set at the beginning of the process or algorithm or while the process or algorithm is being executed.

[0023] Terms such as "first" and "second" used to distinguish between various components are not limited to the components. For example, a first component may be referred to as a second component, and vice versa.

[0024] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the components may be directly coupled or connected to each other, or coupled or connected to each other with another component interposed therebetween. In contrast, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that the components are directly coupled or connected to each other without another component interposed therebetween.

[0025] "Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal with a "logical high level" is different from a signal with a "logical low level". For example, when a signal with a first voltage corresponds to a signal with a "logical high level", a signal with a second voltage may correspond to a signal with a "logical low level". According to one embodiment, the "logical high level" may be set to a voltage higher than the "logical low level". According to one embodiment, the logic level of a signal may be set to a different logic level or an opposite logic level. For example, in some embodiments, a signal with a logical high level may be set to have a logical low level, and in some embodiments, a signal with a logical low level may be set to have a logical high level.

[0026] Hereinafter, the present disclosure will be described in more detail by way of examples. The examples are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0027] An embodiment of the present disclosure provides a semiconductor system for correcting an error of internal data by performing a read-modify-write operation when each of an auto refresh operation and a self refresh operation is performed a set number of times.

[0028] According to an embodiment of the present disclosure, since errors in internal data are corrected by performing a read-modify-write operation when each of an auto-refresh operation and a self-refresh operation is performed a set number of times, efficient operations can be performed without adding commands for performing the read-modify-write operation.

[0029] Furthermore, according to the embodiments of the present disclosure, since an error of internal data is corrected by performing a read-modify-write operation when each of an auto refresh operation and a self refresh operation is performed a set number of times, an error of internal data can be prevented.

[0030] Furthermore, according to an embodiment of the present disclosure, power consumption can be reduced by supplying a power supply voltage to a column control circuit only during an interval in which a read-modify-write operation is performed when each of an auto refresh operation and a self refresh operation is performed a set number of times.

[0031] like Figure 1 As shown, the semiconductor system 1 may include a controller 10 and a semiconductor device 20. The semiconductor device 20 may include a refresh control circuit (REF CTR) 230, a read-modify-write control circuit (RMW CTR) 240, a power supply circuit (VDDSUP) 270, and a column control circuit (COL CTR) 280.

[0032] The controller 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, and a fourth control pin 11_4. The semiconductor device 20 may include a first device pin 21_1, a second device pin 21_2, a third device pin 21_3, and a fourth device pin 21_4. The first transmission line L11 may be connected between the first control pin 11_1 and the first device pin 21_1. The second transmission line L12 may be connected between the second control pin 11_2 and the second device pin 21_2. The third transmission line L13 may be connected between the third control pin 11_3 and the third device pin 21_3. The fourth transmission line L14 may be connected between the fourth control pin 11_4 and the fourth device pin 21_4.

[0033] The controller 10 may transmit a clock CLK for controlling the semiconductor device 20 to the semiconductor device 20 through a first transmission line L11. The controller 10 may transmit a chip select signal CS for controlling the semiconductor device 20 to the semiconductor device 20 through a second transmission line L12. The controller 10 may transmit a command address CA for controlling the semiconductor device 20 to the semiconductor device 20 through a third transmission line L13. The controller 10 may transmit data DATA to the semiconductor device 20 through a fourth transmission line L14. The controller 10 may receive data DATA from the semiconductor device 20 through the fourth transmission line L14. The clock CLK may be set as a signal that switches periodically so as to synchronize the operation of the controller 10 with the operation of the semiconductor device 20. The chip select signal CS may be set as a signal for activating the semiconductor device 20. The command address CA may include a plurality of bits, and may be set as a signal including a command and an address for controlling the operation of the semiconductor device 20. The data DATA may be set as data including a plurality of bits.

[0034] The controller 10 may output a chip selection signal CS and a command address CA to the semiconductor device 20 in synchronization with the clock CLK for performing an auto refresh operation and a self refresh operation.

[0035] When an auto refresh command is input after the auto refresh operation starts ( Figure 2 When the refresh control circuit 230 generates an internal refresh signal ( Figure 2 When an automatic refresh command is input after the smart refresh operation starts ( Figure 2 When the refresh control circuit 230 blocks the internal refresh signal ( Figure 2 When a self-refresh command ( Figure 2 When SREF in the refresh control circuit 230 is used, the refresh control circuit 230 may generate an internal refresh signal ( Figure 2 in IREF).

[0036] When the auto-refresh operation is performed a first set number of times, the read-modify-write control circuit 240 may generate a power control signal ( Figure 2 When the auto-refresh operation is performed a first set number of times, the read-modify-write control circuit 240 may sequentially generate an internal read signal ( PG_RMW) for performing the read-modify-write operation. Figure 2 RD_RMW) and the internal write signal ( Figure 2 When the self-refresh operation is performed a second set number of times, the read-modify-write control circuit 240 may generate a power control signal ( Figure 2 When the self-refresh operation is performed a second set number of times, the read-modify-write control circuit 240 may sequentially generate an internal read signal ( PG_RMW) for performing the read-modify-write operation. Figure 2 RD_RMW) and the internal write signal ( Figure 2 WT_RMW in .

[0037] The power circuit 270 can be enabled by the power control signal ( Figure 2 During the interval of PG_RMW in Figure 2 The power supply circuit 270 may block the power supply voltage (VDD) after the read-modify-write operation is completed. Figure 2 VDD) supply.

[0038] The column control circuit 280 can be supplied with a power supply voltage ( Figure 2 When the internal read signal ( Figure 2 RD_RMW in the column control circuit 280 can receive internal data ( Fig.11 ID<1:8>) and internal parity ( Fig.11 The column control circuit 280 can obtain the internal data ( Fig.11 ID<1:8>) and internal parity ( Fig.11 IP<1:3> in the READ_DATABASE_ ... Fig.11 RD<1:8>) and read parity ( Fig.11 When the internal write signal ( Figure 2 WT_RMW in, the column control circuit 280 can be based on the read parity ( Fig.11 RP<1:3> in the Fig.11Write parity generated by RD<1:8> in Fig.11 WP<1:3> in the correct read data ( Fig.11 RD<1:8>) error to output the read data ( Fig.11 RD<1:8> in the Fig.11 ID<1:8> in .

[0039] When the chip selection signal CS and the command address CA input in synchronization with the clock CLK have a combination for performing the self-refresh operation, the semiconductor device 20 can perform the self-refresh operation. When the chip selection signal CS and the command address CA input in synchronization with the clock CLK have a combination for performing the self-refresh operation, the semiconductor device 20 can perform the self-refresh operation. When the self-refresh operation has been performed a first set number of times, the semiconductor device 20 can correct the internal data ( Fig.11 ID<1:8>) in the error, and can store the internal data of the corrected error ( Fig.11 When the self-refresh operation has been performed a second set number of times, the semiconductor device 20 can correct the internal data ( Fig.11 ID<1:8>) in the error, and can store the internal data of the corrected error ( Fig.11 When each of the auto-refresh operation and the self-refresh operation is performed a set number of times, the semiconductor device 20 may supply the power supply voltage to the column control circuit 280 only during the intervals in which the read-modify-write operation is performed ( Figure 2 After starting the read-modify-write operation, the semiconductor device 20 can perform a read-modify-write operation based on the read parity ( Fig.11 RP<1:3> in the Fig.11 Write parity generated by RD<1:8> in Fig.11 WP<1:3> in the correct read data ( Fig.11 RD<1:8>) error to store the read data ( Fig.11 RD<1:8> in .

[0040] like Figure 2As shown, the semiconductor device 20 may include a command generation circuit (CMD GEN) 210, a row address generation circuit (RADD GEN) 220, a refresh control circuit (REF CTR) 230, a read-modify-write control circuit (RMW CTR) 240, a row control circuit (ROW CTR) 250, a memory circuit (MEM CT) 260, a power supply circuit 270 and a column control circuit (COL CTR) 280.

[0041] The command generation circuit 210 may generate an auto refresh command AREF, a self refresh command SREF, an active command ACT, and the first to Lth internal command addresses ICAR<1:L> based on the chip selection signal CS and the first to Lth command addresses CA<1:L> input synchronously with the clock CLK. When the chip selection signal CS and the first to Lth command addresses CA<1:L> input synchronously with the clock CLK have a combination for performing an auto refresh operation, the command generation circuit 210 may generate the auto refresh command AREF. When the chip selection signal CS and the first to Lth command addresses CA<1:L> input synchronously with the clock CLK have a combination for performing a self refresh operation, the command generation circuit 210 may generate the self refresh command SREF. When the chip selection signal CS and the first to Lth command addresses CA<1:L> input synchronously with the clock CLK have a combination for performing an active operation, the command generation circuit 210 may generate the active command ACT. The command generation circuit 210 may generate first to Lth internal command addresses ICAR<1:L> based on first to Lth command addresses CA<1:L> input in synchronization with the rising edge of the clock CLK.

[0042] When the active command ACT is input and the refresh enable signal REN is disabled, the row address generation circuit 220 may generate first to M-th row addresses RADD<1:M> for selecting word lines adjacent to word lines repeatedly activated by the first to L-th internal command addresses ICAR<1:L>. The row address generation circuit 220 may store the first to L-th internal command addresses ICAR<1:L> whenever the active command ACT is input, and may generate first to M-th target addresses ( RADD<1:M>) from the first to L-th internal command addresses ICAR<1:L> when the stored first to L-th internal command addresses ICAR<1:L> have the same logic level combination. Figure 4 When performing a smart refresh operation of an auto refresh operation, the row address generation circuit 220 can generate a row address from the first to the Mth target addresses ( Figure 4 SM_ADD<1:M> in the SM_ADD<1:M>) generates the first to Mth row addresses RADD<1:M>. The first to Mth target addresses ( Figure 4SM_ADD<1:M> in SM_ADD<1:M> may be set to an address for activating a word line adjacent to the repeatedly activated word line. The first to Mth target addresses ( Figure 4 SM_ADD<1:M> in SM_ADD<1:M> can be generated by latching the first to Lth internal command addresses ICAR<1:L> that are frequently input. Whenever the first to Lth internal command addresses ICAR<1:L> are input, the first to Mth target addresses ( Figure 4 SM_ADD<1:M> in SM_ADD<1:M>) can be counted, and when the first to Mth target addresses ( Figure 4 When SM_ADD<1:M> in SM_ADD<1:M> is counted many times (for example, more than 10 times), the first to Mth target addresses ( Figure 4 SM_ADD<1:M> in FIG. 21 ). When the auto refresh command AREF is input and the refresh enable signal REN is enabled, the row address generation circuit 220 may generate the first to Mth row addresses RADD<1:M> that are counted sequentially. When the self refresh command SREF is input and the refresh enable signal REN is enabled, the row address generation circuit 220 may generate the first to Mth row addresses RADD<1:M> that are counted sequentially.

[0043] The refresh control circuit 230 may generate an internal refresh signal IREF including a pulse generated when the automatic refresh command AREF is input. When the automatic refresh command AREF is input after the smart refresh operation starts, the refresh control circuit 230 may block the generation of the internal refresh signal IREF. The refresh control circuit 230 may generate an internal refresh signal IREF including a pulse periodically generated when the self-refresh command SREF is input. When the data stored in the memory cell ( Fig.10 When the logic level of the data in the MC in the input (MC in the input) transitions, the internal refresh signal IREF may be generated to include pulses periodically generated in a time period shorter than the hold time. When the automatic refresh command AREF is input and the automatic refresh operation is performed, the refresh control circuit 230 may generate an enabled refresh enable signal REN. When the automatic refresh command AREF is input and the smart refresh operation is performed, the refresh control circuit 230 may generate a disabled refresh enable signal REN. When the self-refresh command SREF is input and the self-refresh operation is performed, the refresh control circuit 230 may generate an enabled refresh enable signal REN.

[0044] The read-modify-write control circuit 240 may generate the power control signal PG_RMW when the auto refresh command AREF and the self refresh command SREF are input. The read-modify-write control circuit 240 may generate the enabled power control signal PG_RMW when either the auto refresh command AREF and the self refresh command SREF are input.

[0045] A first setting number may be set in the read-modify-write control circuit 240 in response to the automatic test mode signal ATM. When the automatic refresh command AREF is input the first setting number of times, the read-modify-write control circuit 240 may generate an internal activity signal ACT_RMW. By delaying the internal activity signal ACT_RMW, the read-modify-write control circuit 240 may generate: an internal read signal RD_RMW, an internal write signal WT_RMW, and an internal precharge signal PCG_RMW that are sequentially enabled. The first setting number may vary according to the embodiment. For example, when the first setting number is set to five, when the automatic refresh command AREF is input five times, the read-modify-write control circuit 240 may generate an internal activity signal ACT_RMW.

[0046] A second setting number may be set in the read-modify-write control circuit 240 in response to the self-test mode signal STM. When the self-refresh command SREF is input the second setting number of times, the read-modify-write control circuit 240 may generate an internal activity signal ACT_RMW. By delaying the internal activity signal ACT_RMW, the read-modify-write control circuit 240 may generate sequentially enabled: an internal read signal RD_RMW, an internal write signal WT_RMW, and an internal precharge signal PCG_RMW. The second setting number may vary according to the embodiment. For example, when the second setting number is set to seven, when the self-refresh command SREF is input seven times, the read-modify-write control circuit 240 may generate an internal activity signal ACT_RMW.

[0047] When the internal active signal ACT_RMW and the internal refresh signal IREF are input, the row control circuit 250 may activate a plurality of word lines ( Fig.10 Any one of WL1 to WLj in the word line. Fig.10 The case where any one of WL1 to WLj in the word line is activated can be set as an operation to activate the word line in the common active operation, the auto refresh operation, and the self refresh operation. Fig.10The case where any one of WL1 to WLj in the row address RADD<1:M> is activated may mean that the word line selected based on the first to M-th row addresses RADD<1:M> is driven to a high voltage level. When the internal precharge signal PCG_RMW is input, the row control circuit 250 may enable the plurality of word lines (WL1 to WLj) based on the first to M-th row addresses RADD<1:M> Fig.10 Any one of WL1 to WLj in the word line is precharged. Fig.10 The case where any one of the word lines WL1 to WLj in the word line is precharged may mean the case where the word line is driven to the precharge voltage level in the precharge operation after the common activity operation. Fig.10 The case where any one of WL1 to WLj in the M-th row address RADD<1:M> is precharged may mean a case where a word line selected based on the first to M-th row addresses RADD<1:M> is driven to a precharge voltage level.

[0048] After the auto-refresh operation starts, the multiple word lines ( Fig.10 1:M>. After the smart refresh operation starts, the memory circuit 260 may activate word lines adjacent to the word lines repeatedly activated by the first to Mth row addresses RADD<1:M> generated from the first to Mth target addresses SM_ADD<1:M>. For example, after the smart refresh operation starts, when the first to Mth row addresses RADD<1:M> have a value for activating the second word line ( Fig.10 When the logic level combination of WL2 in the memory circuit 260 is realized, the memory circuit 260 can activate the first word line ( Fig.10 WL1 in the Fig.10 After the self-refresh operation starts, the memory circuit 260 may sequentially activate the plurality of word lines WL1 to WLj based on the first to Mth row addresses RADD<1:M>. After the read-modify-write operation starts, the memory circuit 260 may output the internal data ( Fig.11 ID<1:8> in the memory cell MC is connected to a plurality of word lines ( Fig.10 The activated word lines and multiple column lines (WL1 to WLj in Fig.10 The memory circuit 260 can output information including information about the internal data ( Fig.11 The internal parity check of the error information of ID<1:8> in Fig.11 After starting the read-modify-write operation, the memory circuit 260 can store the corrected error internal data ( Fig.11ID<1:8> in FIG. 1 is stored in a memory cell MC connected to a plurality of word lines ( Fig.10 The activated word lines and multiple column lines (WL1 to WLj in Fig.10 After the write operation starts, the memory circuit 260 can store the first to eighth data DATA<1:8> in the columns connected to the plurality of word lines ( Fig.10 The activated word lines and multiple column lines (WL1 to WLj in Fig.10 After the read operation starts, the memory circuit 260 can output the first to eighth data DATA<1:8> stored in the memory cells MC connected to the plurality of word lines ( Fig.10 The activated word lines and multiple column lines (WL1 to WLj in Fig.10 The activated column lines among Yi1 to Yik).

[0049] The power supply circuit 270 may include an inverter 271 <1> and switch 271 <2> . Inverter 271 <1> The power control signal PG_RMW can be inverted and output. <2> This can be achieved by using a PMOS transistor. Switch 271 <2> Can be used as an inverter 271 <1> The power supply circuit 270 is turned on when the output signal of has a logic low level, and can supply the power supply voltage VDD to the column control circuit 280. The power supply circuit 270 can supply the power supply voltage VDD to the column control circuit 280 during an interval in which the power control signal PG_RMW is enabled to a logic high level. After the read-modify-write operation is ended, the power supply circuit 270 can block the supply of the power supply voltage VDD during an interval in which the power control signal PG_RMW is disabled to a logic low level.

[0050] The column control circuit 280 may be operated by being supplied with the power supply voltage VDD. When the internal read signal RD_RMW is input, the column control circuit 280 may receive the internal data ( Fig.11 ID<1:8>) and internal parity ( Fig.11 When the internal read signal RD_RMW is input, the column control circuit 280 can read the internal data ( Fig.11 ID<1:8>) and internal parity ( Fig.11 IP<1:3> in the READ_DATABASE_ ... Fig.11 RD<1:8>) and read parity ( Fig.11 When the internal write signal WT_RMW is input, the column control circuit 280 can read the data from the Fig.11 Write parity generated by RD<1:8> in Fig.11 WP<1:3> in ) and read parity ( Fig.11 RP<1:3> in the correct read data ( Fig.11 RD<1:8>) error to generate internal data ( Fig.11 The column control circuit 280 can correct the error of the internal data ( Fig.11 ID<1:8> in ) is output to the memory circuit 260.

[0051] When the chip selection signal CS and the first to Lth command addresses CA<1:L> input synchronously with the clock CLK have a combination for performing an auto-refresh operation, the semiconductor device 20 may perform an auto-refresh operation. When the auto-refresh operation is performed a first set number of times, the semiconductor device 20 may supply the power supply voltage VDD to the column control circuit 280. When the auto-refresh operation is performed a first set number of times, the semiconductor device 20 may correct the internal data ( Fig.11 ID<1:8>) in the error, and can store the internal data of the corrected error ( Fig.11 When the chip selection signal CS and the first to Lth command addresses CA<1:L> input synchronously with the clock CLK have a combination for performing a self-refresh operation, the semiconductor device 20 may perform a self-refresh operation. When the self-refresh operation is performed a second set number of times, the semiconductor device 20 may supply the power supply voltage VDD to the column control circuit 280. When the self-refresh operation is performed a second set number of times, the semiconductor device 20 may correct the internal data ( Fig.11 ID<1:8>) in the error, and can store the internal data of the corrected error ( Fig.11 By performing the smart refresh operation of the auto refresh operation, the semiconductor device 20 may activate a word line adjacent to a word line that corresponds to a target address for selecting a word line and is repeatedly activated.

[0052] Figure 3 2 is a block diagram illustrating a configuration according to one embodiment of a command generation circuit 210 included in the semiconductor device 20. The command generation circuit 210 may include a buffer circuit (BUF CT) 211 and a command decoder (CMD DEC) 212.

[0053] The buffer circuit 211 can generate the internal chip select signal ICSR by latching the chip select signal CS synchronized with the rising edge of the clock CLK. The buffer circuit 211 can generate the first to Lth internal command addresses ICAR<1:L> by latching the first to Lth command addresses CA<1:L> synchronized with the rising edge of the clock CLK.

[0054] The command decoder 212 may generate an auto refresh command AREF, a self refresh command SREF, and an active command ACT by decoding the internal chip select signal ICSR and the first to L th internal command addresses ICAR<1:L>. When the internal chip select signal ICSR and the first to L th internal command addresses ICAR<1:L> have a combination for performing an auto refresh operation, the command decoder 212 may generate an enabled auto refresh command AREF. When the internal chip select signal ICSR and the first to L th internal command addresses ICAR<1:L> have a combination for performing a self refresh operation, the command decoder 212 may generate an enabled self refresh command SREF. When the internal chip select signal ICSR and the first to L th internal command addresses ICAR<1:L> have a combination for performing an active operation, the command decoder 212 may generate an enabled active command ACT.

[0055] Figure 4 is a block diagram illustrating a configuration according to one embodiment of a row address generation circuit 220 included in the semiconductor device 20. The row address generation circuit 220 may include a target address generation circuit (SM ADD GEN) 221, a refresh address generation circuit (REFADD GEN) 222, and an address selection circuit (ADD SEL) 223.

[0056] The target address generation circuit 221 may latch the first to Lth internal command addresses ICAR<1:L> whenever the active command ACT is input. When the latched first to Lth internal command addresses ICAR<1:L> have a logic level combination that is frequently input, the target address generation circuit 221 may generate the first to Mth target addresses SM_ADD<1:M> from the first to Lth internal command addresses ICAR<1:L>. The target address generation circuit 221 may count the first to Lth internal command addresses ICAR<1:L> whenever the first to Lth internal command addresses ICAR<1:L> are input, and may generate the first to Mth target addresses SM_ADD<1:M> from the first to Lth internal command addresses ICAR<1:L> when the first to Lth internal command addresses ICAR<1:L> having the same logic level combination are counted many times (for example, more than 10 times). The first to Mth target addresses SM_ADD<1:M> may be set as addresses for activating word lines that are repeatedly activated. The first to Mth target addresses ( Figure 4 The target address generation circuit 221 may generate the first to Lth internal command addresses ICAR<1:L> by latching the first to Lth internal command addresses ICAR<1:L> that are frequently input. The target address generation circuit 221 may count the first to Lth internal command addresses ICAR<1:L> whenever the first to Lth internal command addresses ICAR<1:L> are input, and may generate the first to Mth target addresses ( SM_ADD<1:M> in FIG. 2 ) from the first to Lth internal command addresses ICAR<1:L> when the first to Lth internal command addresses ICAR<1:L> having the same logic level combination are counted many times (for example, more than 10 times). Figure 4 SM_ADD<1:M> in the .

[0057] When the auto refresh command AREF is input, the refresh address generation circuit 222 may generate sequentially counted first to Mth refresh addresses REF_ADD<1:M>. When the self refresh command SREF is input, the refresh address generation circuit 222 may generate sequentially counted first to Mth refresh addresses REF_ADD<1:M>.

[0058] When the refresh enable signal REN is disabled, the address selection circuit 223 may generate the first to Mth row addresses RADD<1:M> from the first to Mth target addresses SM_ADD<1:M>. When the refresh enable signal REN is enabled, the address selection circuit 223 may generate the first to Mth row addresses RADD<1:M> from the first to Mth refresh addresses REF_ADD<1:M>.

[0059] Figure 5 2 is a block diagram illustrating a configuration according to one embodiment of a refresh control circuit 230 included in the semiconductor device 20. The refresh control circuit 230 may include a temperature sensor (TEMP SENSOR) 231, a self-refresh pulse generating circuit (SELF REF PUL GEN) 232, an automatic refresh pulse generating circuit (AUTO REF PUL GEN) 233, and an internal refresh signal generating circuit (IREF GEN) 234.

[0060] The temperature sensor 231 may detect the internal temperature of the semiconductor device 20. The temperature sensor 231 may generate temperature information TINF including information about the internal temperature of the semiconductor device 20. The temperature sensor 231 may generate temperature information TINF including high temperature information and low temperature information of the semiconductor device 20.

[0061] When the self-refresh command SREF is input, the self-refresh pulse generation circuit 232 may generate a self-refresh pulse SRP, and the generation period of the self-refresh pulse SRP is adjusted based on the temperature information TINF. When the self-refresh command SREF is input and the temperature information TINF includes high temperature information, the self-refresh pulse generation circuit 232 may generate a self-refresh pulse SRP whose generation period becomes relatively fast. When the self-refresh command SREF is input and the temperature information TINF includes low temperature information, the self-refresh pulse generation circuit 232 may generate a self-refresh pulse SRP whose generation period becomes relatively slow.

[0062] When the automatic refresh command AREF is input, the automatic refresh pulse generation circuit 233 may generate the automatic refresh pulse ARP based on the temperature information TINF. When the automatic refresh command AREF is input, if the smart refresh operation is performed based on the temperature information TINF, the automatic refresh pulse generation circuit 233 may block the generation of the automatic refresh pulse ARP. When the automatic refresh command AREF is input and the automatic refresh operation is performed, the automatic refresh pulse generation circuit 233 may generate an enabled refresh enable signal REN. When the automatic refresh command AREF is input and the smart refresh operation is performed, the automatic refresh pulse generation circuit 233 may generate a disabled refresh enable signal REN. The smart refresh operation may be performed during the automatic refresh operation. For example, a smart refresh operation may be performed once after the automatic refresh operation has been performed three times.

[0063] The internal refresh signal generating circuit 234 may generate the internal refresh signal IREF by synthesizing the self refresh pulse SRP and the automatic refresh pulse ARP. The internal refresh signal generating circuit 234 may generate the internal refresh signal IREF from any one of the self refresh pulse SRP and the automatic refresh pulse ARP. The internal refresh signal generating circuit 234 may generate the internal refresh signal IREF including a pulse generated when a pulse of the self refresh pulse SRP and a pulse of the automatic refresh pulse ARP are generated.

[0064] Figure 6 2 is a block diagram illustrating a configuration according to one embodiment of a read-modify-write control circuit 240 included in the semiconductor device 20. The read-modify-write control circuit 240 may include an internal activity signal generating circuit (ACTRMW GEN) 241, a read / write control circuit (R / W CTR) 242, and a power control signal generating circuit (PG RMW GEN) 243.

[0065] The internal activity signal generating circuit 241 may generate an internal activity signal ACT_RMW based on the automatic refresh command AREF and the automatic test mode signal ATM. The internal activity signal generating circuit 241 may set a first setting number in response to the automatic test mode signal ATM. When the automatic refresh command AREF is input the first setting number of times, the internal activity signal generating circuit 241 may generate the internal activity signal ACT_RMW. For example, if the first setting number is set to five, when the automatic refresh command AREF is input five times, the internal activity signal generating circuit 241 may generate the internal activity signal ACT_RMW. The internal activity signal generating circuit 241 may generate the internal activity signal ACT_RMW based on the self refresh command SREF and the self test mode signal STM. The internal activity signal generating circuit 241 may set a second setting number in response to the self test mode signal STM. When the self refresh command SREF is input the second setting number of times, the internal activity signal generating circuit 241 may generate the internal activity signal ACT_RMW. For example, if the second set number is set to seven times, when the self refresh command SREF is input seven times, the internal active signal generation circuit 241 may generate the internal active signal ACT_RMW.

[0066] By delaying the internal active signal ACT_RMW, the read / write control circuit 242 can generate the internal read signal RD_RMW, the internal write signal WT_RMW, and the internal precharge signal PCG_RMW that are sequentially enabled. When the internal active signal ACT_RMW is input, the read / write control circuit 242 can generate the first to Nth column addresses CADD<1:N> that are sequentially counted.

[0067] The power control signal generating circuit 243 may generate the power control signal PG_RMW based on the self-refresh command SREF, the internal active signal ACT_RMW, and the internal precharge signal PCG_RMW. When the internal active signal ACT_RMW is input during the interval in which the self-refresh command SREF is enabled, the power control signal generating circuit 243 may generate the enabled power control signal PG_RMW. When the internal precharge signal PCG_RMW is input, the power control signal generating circuit 243 may generate the disabled power control signal PG_RMW.

[0068] Figure 7 is a diagram illustrating a configuration according to one embodiment of an internal activity signal generation circuit 241 included in a read-modify-write control circuit 240. The internal activity signal generation circuit 241 may include an auto refresh control signal generation circuit 310, a self refresh control signal generation circuit 320, and a logic circuit 330.

[0069] The auto refresh control signal generating circuit 310 may include a first counter ( CNT1 ) 311 and an auto refresh control signal output circuit 312 .

[0070] The first counter 311 may set a first set number in response to the automatic test mode signal ATM. When the automatic refresh command AREF is input the first set number of times, the first counter 311 may generate a first detection signal DET1 enabled to a logic high level. For example, the first counter 311 may set the first set number to five in response to the automatic test mode signal ATM. In this case, when the automatic refresh command AREF is input five times, the first counter 311 may generate a first detection signal DET1 enabled to a logic high level.

[0071] The automatic refresh control signal output circuit 312 can be realized by using a NAND gate 312 <1> and inverter 312 <2> When the first detection signal DET1 is disabled to a logic low level, the auto-refresh control signal output circuit 312 may generate an auto-refresh control signal AR_CTR disabled to a logic low level. When the first detection signal DET1 is enabled to a logic high level, the auto-refresh control signal output circuit 312 may generate an auto-refresh control signal AR_CTR enabled to a logic high level by buffering the auto-refresh command AREF.

[0072] The auto refresh control signal generating circuit 310 may set a first set number in response to the automatic test mode signal ATM. When the auto refresh command AREF is input the first set number of times, the auto refresh control signal generating circuit 310 may generate the auto refresh control signal AR_CTR enabled to a logic high level.

[0073] The self-refresh control signal generating circuit 320 may include a second counter ( CNT2 ) 321 and a self-refresh control signal output circuit 322 .

[0074] The second counter 321 may set a second set number in response to the self-test mode signal STM. When the self-refresh command SREF is input the second set number of times, the second counter 321 may generate a second detection signal DET2 enabled to a logic high level. For example, the second counter 321 may set the second set number to seven in response to the self-test mode signal STM. In this case, when the self-refresh command SREF is input seven times, the second counter 321 may generate a second detection signal DET2 enabled to a logic high level.

[0075] The self-refresh control signal output circuit 322 can be realized by using a NAND gate 322 <1> and inverter 322 <2> When the second detection signal DET2 is disabled to a logic low level, the self-refresh control signal output circuit 322 may generate a self-refresh control signal SR_CTR disabled to a logic low level. When the second detection signal DET2 is enabled to a logic high level, the self-refresh control signal output circuit 322 may generate a self-refresh control signal SR_CTR enabled to a logic high level by buffering the self-refresh command SREF.

[0076] The self refresh control signal generation circuit 320 may set a second set number in response to the self test mode signal STM. When the self refresh command SREF is input the second set number of times, the self refresh control signal generation circuit 320 may generate a self refresh control signal SR_CTR enabled to a logic high level.

[0077] The logic circuit 330 can be realized by using a NOR gate 331 <1> and inverter 331 <2> The logic circuit 330 may generate an internal active signal ACT_RMW based on the auto refresh control signal AR_CTR and the self refresh control signal SR_CTR. When either of the auto refresh control signal AR_CTR and the self refresh control signal SR_CTR is enabled to a logic high level, the logic circuit 330 may generate an internal active signal ACT_RMW enabled to a logic high level.

[0078] Figure 8 is a block diagram illustrating a configuration according to one embodiment of a read / write control circuit 242 included in a read-modify-write control circuit 240. The read / write control circuit 242 may include a first delay circuit (DLY1) 410, a second delay circuit (DLY2) 420, a third delay circuit (DLY3) 430, and a column address generation circuit (CADD GEN) 440.

[0079] The first delay circuit 410 can generate an internal read signal RD_RMW by delaying the internal active signal ACT_RMW. The delay amount of the first delay circuit 410 can be set to be consistent with the internal data ( Fig.11 The delay amount corresponding to the time of ID<1:8> in .

[0080] The second delay circuit 420 can generate the internal write signal WT_RMW by delaying the internal read signal RD_RMW. The delay amount of the second delay circuit 420 can be set to be consistent with the internal data ( Fig.11 The delay amount corresponding to the error time of ID<1:8> in the .

[0081] The third delay circuit 430 can generate the internal precharge signal PCG_RMW by delaying the internal write signal WT_RMW. The delay length of the third delay circuit 430 can correspond to the internal data ( Fig.11 The time it takes for ID<1:8> in ) to be stored in the memory circuit 260.

[0082] The column address generation circuit 440 may generate first to Nth column addresses CADD<1:N> counting sequentially when the internal active signal ACT_RMW is input. The column address generation circuit 440 may generate first to Nth column addresses CADD<1:N> counting up and down whenever the internal active signal ACT_RMW is input.

[0083] Fig. 9 is a diagram illustrating a configuration according to one embodiment of a power control signal generation circuit 243 included in the read-modify-write control circuit 240. The power control signal generation circuit 243 may include an internal control signal generation circuit 510 (RMW CTR GEN) and a power control signal output circuit 520.

[0084] The internal control signal generating circuit 510 may generate the internal control signal RMW_CTR based on the internal activity signal ACT_RMW and the internal precharge signal PCG_RMW. When the internal activity signal ACT_RMW is enabled to a logic high level, the internal control signal generating circuit 510 may generate the internal control signal RMW_CTR having a logic high level. When the internal precharge signal PCG_RMW is enabled to a logic high level, the internal control signal generating circuit 510 may generate the internal control signal RMW_CTR having a logic low level.

[0085] The power control signal output circuit 520 can be realized by using an inverter 520 <1> , NOR gate 520 <2> and inverter 520 <3> To achieve. The power control signal output circuit 520 can generate a power control signal PG_RMW based on the self-refresh command SREF and the internal control signal RMW_CTR. When the internal control signal RMW_CTR is enabled to a logic high level, the power control signal output circuit 520 can generate a power control signal PG_RMW enabled to a logic high level. When the internal control signal RMW_CTR is disabled to a logic low level during an interval in which the self-refresh command SREF is enabled to a logic high level, the power control signal output circuit 520 can generate a power control signal PG_RMW disabled to a logic low level.

[0086] Fig.10is a diagram illustrating a configuration according to one embodiment of a memory circuit 260 included in the semiconductor device 20. The memory circuit 260 may include a plurality of word lines WL1 to WLj, a plurality of column lines Yi1 to Yik, and a plurality of memory cells MC.

[0087] A plurality of memory cells MC included in the memory circuit 260 may be connected to locations where a plurality of word lines WL1 to WLj intersect with a plurality of column lines Yi1 to Yik. After the auto-refresh operation starts, the memory circuit 260 may sequentially activate the plurality of word lines WL1 to WLj based on the first to M-th row addresses RADD<1:M>. After the smart refresh operation starts, the memory circuit 260 may activate a word line adjacent to a repeatedly activated word line among the plurality of word lines WL1 to WLj based on the first to M-th row addresses RADD<1:M> generated from the first to M-th target addresses SM_ADD<1:M>. After the self-refresh operation starts, the memory circuit 260 may sequentially activate the plurality of word lines WL1 to WLj based on the first to M-th row addresses RADD<1:M>. After the read-modify-write operation starts, the memory circuit 260 may output the internal data ( Fig.11 ID<1:8> in the memory cell MC), the memory cell MC is connected to an activated word line among a plurality of word lines WL1 to WLj and an activated column line among a plurality of column lines Yi1 to Yik. The memory circuit 260 can output information including information about the internal data ( Fig.11 The internal parity check of the error information of ID<1:8> in Fig.11 After starting the read-modify-write operation, the memory circuit 260 can store the corrected error internal data ( Fig.11 8) are stored in memory cells MC connected to an activated word line among a plurality of word lines WL1 to WLj and an activated column line among a plurality of column lines Yi1 to Yik.

[0088] Fig.11 is a block diagram illustrating a configuration according to one embodiment of a column control circuit 280 included in the semiconductor device 20. The column control circuit 280 may include a data input and output circuit (DATA IN OUT) 610, a write parity generation circuit (WP GEN) 620, a syndrome generation circuit (SYN GEN) 630, an error correction signal generation circuit (CR GEN) 640, and a correction data generation circuit (CD GEN) 650.

[0089] The data input and output circuit 610 may be driven by being supplied with a power supply voltage VDD. When the internal read signal RD_RMW is input, the data input and output circuit 610 may receive the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3>. When the internal read signal RD_RMW is input, the data input and output circuit 610 may generate the first to eighth read data RD<1:8> and the first to third read parity PR<1:3> from the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3>. When the internal write signal WT_RMW is input, the data input and output circuit 610 may receive the first to eighth corrected data CD<1:8>. When the internal write signal WT_RMW is input, the data input and output circuit 610 may output the first to eighth corrected data CD<1:8> as the first to eighth internal data ID<1:8>.

[0090] The write parity generation circuit 620 may be driven by being supplied with a power supply voltage VDD. When the internal write signal WT_RM is input, the write parity generation circuit 620 may receive the first to eighth read data RD<1:8>. The write parity generation circuit 620 may generate the first to third write parities WP<1:3> by performing an error correction code (ECC) encoding operation on the first to eighth read data RD<1:8>. By using the ECC, the write parity generation circuit 620 may generate the first to third write parities WP<1:3> including error information included in the first to eighth read data RD<1:8>.

[0091] The syndrome generation circuit 630 may be driven by being supplied with the power supply voltage VDD. The syndrome generation circuit 630 may generate first to third syndromes SYN<1:3> by comparing the first to third write parities WP<1:3> and the first to third read parities RP<1:3>.

[0092] The error correction signal generation circuit 640 may generate first to eighth error correction signals CR<1:8> by performing an ECC decoding operation on the first to third syndromes SYN<1:3>. By using ECC, the error correction signal generation circuit 640 may generate first to eighth error correction signals CR<1:8> for correcting errors included in the first to eighth read data RD<1:8> based on the first to third syndromes SYN<1:3>.

[0093] Based on the first to eighth error correction signals CR<1:8>, the correction data generation circuit 650 may generate the first to eighth correction data CD<1:8> by correcting errors included in the first to eighth read data RD<1:8>. <1> When the correction data generation circuit 650 makes the first read data RD <1> The logic level is inverted to generate the first correction data CD <1> , and the second to eighth corrected data CD<2:8> can be generated by buffering the second to eighth read data RD<2:8>. That is, the corrected data generating circuit 650 can correct the first read data RD <1> The first to eighth correction data CD<1:8> are generated based on the errors.

[0094] Fig.12 is a diagram for describing an automatic refresh operation of a semiconductor device according to an embodiment of the present disclosure. Fig.12 , the case where the first set number is set to five (first set number=AREF 5) for the auto refresh operation is described as follows.

[0095] The command generation circuit 210 may generate the auto refresh command AREF five times based on the chip selection signal CS and the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK.

[0096] When the auto refresh command AREF is input three times and the refresh enable signal REN is enabled, the row address generation circuit 220 may generate first to Mth row addresses RADD<1:M> that are counted sequentially.

[0097] The refresh control circuit 230 may generate an internal refresh signal IREF three times, the internal refresh signal IREF including a pulse generated when the auto refresh command AREF is input.

[0098] The memory circuit 260 may perform the auto refresh operation AR based on sequentially activating the plurality of word lines WL1 to WLj by the first to Mth row addresses RADD<1:M> after the auto refresh operation starts.

[0099] When the auto refresh command AREF is input four times and the refresh enable signal REN is disabled, the row address generation circuit 220 may generate first to Mth row addresses RADD<1:M> from the first to Mth target addresses SM_ADD<1:M>.

[0100] The memory circuit 260 may perform the smart refresh operation ST based on activation of a word line adjacent to the repeatedly activated word line among the plurality of word lines WL1 to WLj by the first to Mth row addresses RADD<1:M> after the auto refresh operation starts.

[0101] When the auto refresh command AREF is input five times, the read-modify-write control circuit 240 may generate the internal activity signal ACT_RMW. When the internal activity signal ACT_RMW is input, the read-modify-write control circuit 240 may generate the enabled power control signal PG_RMW.

[0102] The power supply circuit 270 may supply the power supply voltage VDD to the column control circuit 280 during an interval in which the power control signal PG_RMW is enabled to a logic high level.

[0103] The read-modify-write control circuit 240 may generate the internal read signal RD_RMW by delaying the internal activity signal ACT_RMW.

[0104] When the internal read signal RD_RMW is input, the column control circuit 280 may receive the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> from the memory circuit 260. When the internal read signal RD_RMW is input, the column control circuit 280 may generate the first to eighth read data RD<1:8> and the first to third read parity RP<1:3> from the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3>.

[0105] The read-modify-write control circuit 240 may generate the internal write signal WT_RMW by delaying the internal read signal RD_RMW.

[0106] When the internal write signal WT_RMW is input, the column control circuit 280 can generate the first to eighth internal data ID<1:8> by correcting errors of the first to eighth read data RD<1:8> based on the first to third write parities WP<1:3> and the first to third read parities RP<1:3> generated from the first to eighth read data RD<1:8>.

[0107] The memory circuit 260 can perform a read-modify-write operation RMW to store the first to eighth internal data ID<1:8> in a memory cell MC, which is connected to a word line activated by the first to Mth row address RADD<1:M> among a plurality of word lines WL1 to WLj and a column line activated by the first to Nth column address CADD<1:N> among a plurality of column lines Yi1 to Yik.

[0108] The read-modify-write control circuit 240 may generate the internal precharge signal PCG_RMW by delaying the internal write signal WT_RMW.

[0109] When the internal precharge signal PCG_RMW is input, the read-modify-write control circuit 240 may generate the power control signal PG_RMW which is disabled.

[0110] When the power control signal PG_RMW is disabled to a logic low level, the power circuit 270 may block the supply of the power voltage VDD.

[0111] As described above, since the word line adjacent to the word line corresponding to the target address for selecting the word line and repeatedly activated is activated by performing the smart refresh operation of the automatic refresh operation, the semiconductor system 1 can prevent the occurrence of an error of the internal data ID<1:8>. Because the error of the internal data ID<1:8> is corrected by performing the read-modify-write operation when the automatic refresh operation is performed a set number of times, the semiconductor system 1 can perform efficient operations without adding a command for performing the read-modify-write operation. When the automatic refresh operation is performed a set number of times, the semiconductor system 1 can prevent the error of the internal data ID<1:8> by correcting the error of the internal data ID<1:8> by performing the read-modify-write operation. The semiconductor system 1 can reduce power consumption by supplying the power supply voltage VDD to the column control circuit 280 only during the interval of performing the read-modify-write operation when the automatic refresh operation is performed a set number of times.

[0112] Fig.13 is a diagram for describing a self-refresh operation of a semiconductor device according to an embodiment of the present disclosure. Fig.13 , the case where the second set number is set to seven (second set number=SREF 7) for the self refresh operation is described as follows.

[0113] The command generation circuit 210 may generate a self refresh command SREF seven times based on the chip selection signal CS and the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK.

[0114] When the self refresh command SREF is input seven times and the refresh enable signal REN is enabled, the row address generation circuit 220 may generate first to Mth row addresses RADD<1:M> that are counted sequentially.

[0115] The refresh control circuit 230 may generate the internal refresh signal IREF six times, the internal refresh signal IREF including a pulse periodically generated when the self refresh command SREF is input.

[0116] The memory circuit 260 may perform the self refresh operation SR based on sequentially activating the plurality of word lines WL1 to WLj by the first to Mth row addresses RADD<1:M> after the self refresh operation starts.

[0117] When the self refresh command SREF is input seven times, the read-modify-write control circuit 240 may generate the internal active signal ACT_RMW. When the internal active signal ACT_RMW is input, the read-modify-write control circuit 240 may generate the enabled power control signal PG_RMW.

[0118] The power supply circuit 270 may supply the power supply voltage VDD to the column control circuit 280 during an interval in which the power control signal PG_RMW is enabled to a logic high level.

[0119] The read-modify-write control circuit 240 may generate the internal read signal RD_RMW by delaying the internal activity signal ACT_RMW.

[0120] When the internal read signal RD_RMW is input, the column control circuit 280 may receive the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> from the memory circuit 260. When the internal read signal RD_RMW is input, the column control circuit 280 may generate the first to eighth read data RD<1:8> and the first to third read parity RP<1:3> from the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3>.

[0121] The read-modify-write control circuit 240 may generate the internal write signal WT_RMW by delaying the internal read signal RD_RMW.

[0122] When the internal write signal WT_RMW is input, the column control circuit 280 can generate the first to eighth internal data ID<1:8> by correcting errors of the first to eighth read data RD<1:8> based on the first to third write parities WP<1:3> and the first to third read parities RP<1:3> generated from the first to eighth read data RD<1:8>.

[0123] The memory circuit 260 can perform a read-modify-write operation RMW to store the first to eighth internal data ID<1:8> in a memory cell MC, which is connected to a word line activated by the first to Mth row address RADD<1:M> among a plurality of word lines WL1 to WLj and a column line activated by the first to Nth column address CADD<1:N> among a plurality of column lines Yi1 to Yik.

[0124] The read-modify-write control circuit 240 may generate the internal precharge signal PCG_RMW by delaying the internal write signal WT_RMW.

[0125] The read-modify-write control circuit 240 may generate the power control signal PG_RMW which is disabled when the internal precharge signal PCG_RMW is input.

[0126] When the power control signal PG_RMW is disabled to a logic low level, the power circuit 270 may block the supply of the power voltage VDD.

[0127] As described above, since the error of the internal data ID<1:8> is corrected by performing the read-modify-write operation when the self-refresh operation is performed a set number of times, the semiconductor system 1 according to the embodiment of the present disclosure can perform efficient operation without adding a command for performing the read-modify-write operation. When the self-refresh operation is performed a set number of times, by correcting the error of the internal data ID<1:8> by performing the read-modify-write operation, the semiconductor system 1 can prevent the error of the internal data ID<1:8>. The semiconductor system 1 can reduce power consumption by supplying the power supply voltage VDD to the column control circuit 280 only during the interval of performing the read-modify-write operation when the self-refresh operation is performed a set number of times.

[0128] According to one embodiment of the present disclosure, Fig.14 1 is a block diagram illustrating a configuration according to one embodiment of an electronic system 1000. Fig.14 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

[0129] The host 1100 and the semiconductor system 1200 may transmit signals to each other by using an interface protocol. The interface protocol used between the host 1100 and the semiconductor system 1200 may include a multimedia card (MMC), an enhanced mini disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB).

[0130] The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400 (K: 1). The controller 1300 may control the semiconductor device 1400 (K: 1) so that the semiconductor device 1400 (K: 1) performs an active operation, an automatic refresh operation, and a self-refresh operation. Since a word line adjacent to a word line corresponding to a target address for selecting a word line and repeatedly activated is activated by performing a smart refresh operation of an automatic refresh operation, each semiconductor device in the semiconductor device 1400 (K: 1) may prevent the occurrence of an error of the internal data ID<1: 8>. Because an error of the internal data ID<1: 8> is corrected by performing a read-modify-write operation when each of the automatic refresh operation and the self-refresh operation is performed a set number of times, each semiconductor device in the semiconductor device 1400 (K: 1) may perform an efficient operation without adding a command for performing a read-modify-write operation. Each of the semiconductor devices 1400(K:1) can prevent an error of the internal data ID<1:8> by correcting the error of the internal data ID<1:8> by performing a read-modify-write operation when each of the auto refresh operation and the self refresh operation is performed a set number of times. Each of the semiconductor devices 1400(K:1) can reduce power consumption by supplying the power supply voltage VDD to the column control circuit 280 only during an interval in which the read-modify-write operation is performed when each of the auto refresh operation and the self refresh operation is performed a set number of times.

[0131] The controller 1300 may be implemented as Figure 1 Each semiconductor device in the semiconductor device 1400 (K:1) may be implemented as Figure 1 and Figure 2 1. The semiconductor device 20 shown in FIG. Each of the semiconductor devices 1400 (K:1) according to an embodiment may be implemented as one of a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

Claims

1. A semiconductor system comprising: A controller configured to output a clock, a chip select signal and a command address, and configured to output data; as well as A semiconductor device, configured to perform an automatic refresh operation when the chip selection signal and the command address input synchronously with the clock have a combination for performing the automatic refresh operation, configured to correct errors of internal data stored in the semiconductor device by performing a read-modify-write operation instead of the automatic refresh operation when the automatic refresh operation is performed a first set number of times and store the corrected internal data, configured to perform the self-refresh operation when the chip selection signal and the command address input synchronously with the clock have a combination for performing the self-refresh operation, and configured to correct errors of the internal data stored in the semiconductor device by performing a read-modify-write operation instead of the self-refresh operation when the self-refresh operation is performed a second set number of times and store the corrected internal data. 2 . The semiconductor system according to claim 1 , wherein the semiconductor device is configured to perform an operation of activating a word line adjacent to a word line corresponding to a target address by performing a smart refresh operation of the auto refresh operation.

3. The semiconductor system according to claim 1, wherein the semiconductor device comprises: a command generation circuit configured to generate an auto refresh command, a self refresh command, an active command, and an internal command address based on the chip select signal and the command address input in synchronization with the clock; a row control circuit configured to: activate a plurality of word lines based on sequentially counted row addresses when an internal refresh signal generated based on the auto refresh command and the self refresh command is input; a read-modify-write control circuit configured to set the first set number and the second set number in response to an auto-test mode signal and a self-test mode signal, configured to generate a power control signal when the auto-refresh command and the self-refresh command are input, configured to generate an internal activity signal, an internal read signal, an internal write signal, and an internal precharge signal that are sequentially enabled, and configured to generate a column address that is sequentially counted; a power supply circuit configured to supply a power supply voltage to the column control circuit during an interval in which the power control signal is enabled; as well as The column control circuit is configured to operate by being supplied with the power supply voltage, is configured to generate read data and read parity when the internal read signal is input, and is configured to output the read data as internal data by correcting an error of the read data based on the read parity and the write parity when the internal write signal is input. 4 . The semiconductor system according to claim 3 , wherein the row control circuit is configured to activate the plurality of word lines based on the row address when the internal activity signal and the internal refresh signal are input. 5 . The semiconductor system according to claim 3 , wherein the power supply circuit comprises a switch which is turned on during the interval in which the power control signal is enabled and is configured to supply the power supply voltage to the column control circuit.

6. The semiconductor system of claim 3, wherein the read-modify-write control circuit comprises: an internal active signal generating circuit configured to set the first setting number and the second setting number in response to the automatic test mode signal and the self-test mode signal, and configured to generate the internal active signal when the automatic refresh command is input the first setting number of times or the self-refresh command is input the second setting number of times; a read / write control circuit configured to generate the internal read signal, the internal write signal, and the internal precharge signal that are sequentially enabled by delaying the internal active signal, and configured to generate the column address that is sequentially counted; as well as A power control signal generating circuit is configured to generate the power control signal, the power control signal being enabled when the internal activity signal is input, and the power control signal being disabled when the internal precharge signal is input during an interval in which the self-refresh command is enabled.

7. The semiconductor system of claim 6, wherein the internal activity signal generating circuit comprises: an automatic refresh control signal generating circuit configured to set the first set number in response to the automatic test mode signal, and configured to generate an automatic refresh control signal when the automatic refresh command is input the first set number of times; a self-refresh control signal generating circuit configured to set the second set number in response to the self-test mode signal, and configured to generate a self-refresh control signal when the self-refresh command is input the second set number of times; as well as A logic circuit is configured to generate the internal activity signal from any one of the auto-refresh control signal and the self-refresh control signal.

8. The semiconductor system according to claim 6, wherein the read / write control circuit comprises: a first delay circuit configured to generate the internal read signal by delaying the internal activity signal; a second delay circuit configured to generate the internal write signal by delaying the internal read signal; a third delay circuit configured to generate the internal precharge signal by delaying the internal write signal; as well as The column address generation circuit is configured to generate the column addresses that are counted sequentially when the internal activity signal is input.

9. The semiconductor system according to claim 6, wherein the power control signal generating circuit comprises: an internal control signal generating circuit configured to generate an internal control signal, the internal control signal being enabled when the internal active signal is input and the internal control signal being disabled when the internal precharge signal is input; as well as A power control signal output circuit is configured to generate the power control signal by buffering the internal control signal during the interval in which the self-refresh command is enabled.

10. The semiconductor system according to claim 3, wherein the column control circuit is configured to: generating the read data and the read parity by receiving the internal data and the internal parity output by the memory circuit based on the column address when the internal read signal is input, When the internal write signal is input, the internal data is generated by correcting an error of the read data based on the read parity and the write parity, and The internal data is output to the memory circuit based on the column address.

11. The semiconductor system of claim 3, wherein the column control circuit comprises: a data input and output circuit driven by being supplied with the power supply voltage, configured to generate the read data and the read parity by receiving internal data and internal parity when the internal read signal is input, configured to receive correction data when the internal write signal is input, and configured to output the correction data as the internal data; a write parity generation circuit driven by being supplied with the power supply voltage, configured to receive the read data when the internal write signal is input, and configured to generate the write parity by performing an error correction code (ECC) encoding operation on the read data; a syndrome generation circuit driven by being supplied with the power supply voltage and configured to generate a syndrome by comparing the write parity and the read parity; an error correction signal generating circuit configured to generate an error correction signal by performing an ECC decoding operation on the syndrome; as well as A correction data generation circuit is configured to generate the correction data by correcting an error included in the read data in response to the error correction signal.

12. A semiconductor device comprising: a read-modify-write control circuit configured to generate a power control signal when a self-refresh operation is performed a set number of times, and configured to sequentially generate an internal read signal and an internal write signal; a power supply circuit configured to supply a power supply voltage to the column control circuit during an interval in which the power control signal is enabled; as well as The column control circuit is configured to operate by being supplied with the power supply voltage, is configured to generate read data and read parity by receiving internal data and internal parity when the internal read signal is input, and is configured to output the read data as the internal data by correcting an error of the read data based on the read parity and write parity when the internal write signal is input.

13. The semiconductor device according to claim 12, wherein the power supply circuit is configured as: supplying the power supply voltage to the column control circuit after a read-modify-write operation in the self-refresh operation starts, and The supply of the power supply voltage is blocked after the read-modify-write operation is finished.

14. The semiconductor device of claim 12, wherein the read-modify-write control circuit comprises: an internal active signal generating circuit configured to set the set number in response to a self-test mode signal, and configured to generate the internal active signal when a self-refresh command is input the set number of times; a read / write control circuit configured to generate an internal read signal, an internal write signal, and an internal precharge signal that are sequentially enabled by delaying the internal activity signal, and configured to generate a sequentially counted column address; as well as A power control signal generating circuit is configured to generate the power control signal, the power control signal being enabled when the internal activity signal is input, and the power control signal being disabled when the internal precharge signal is input during an interval in which the self-refresh command is enabled.

15. The semiconductor device according to claim 14, wherein the internal activity signal generating circuit comprises: a self-refresh control signal generating circuit configured to set the set number in response to the self-test mode signal, and configured to generate a self-refresh control signal when the self-refresh command is input the set number of times; as well as A logic circuit is configured to generate the internal activity signal from the self-refresh control signal.

16. The semiconductor device according to claim 14, wherein the read / write control circuit comprises: a first delay circuit configured to generate the internal read signal by delaying the internal activity signal; a second delay circuit configured to generate the internal write signal by delaying the internal read signal; a third delay circuit configured to generate the internal precharge signal by delaying the internal write signal; as well as The column address generation circuit is configured to generate the column addresses that are counted sequentially when the internal activity signal is input.

17. The semiconductor device according to claim 14, wherein the power control signal generating circuit comprises: an internal control signal generating circuit configured to generate an internal control signal, the internal control signal being enabled when the internal active signal is input and the internal control signal being disabled when the internal precharge signal is input; as well as A power control signal output circuit is configured to generate the power control signal by buffering the internal control signal during the interval in which the self-refresh command is enabled.

18. The semiconductor device according to claim 12, wherein the column control circuit comprises: a data input and output circuit driven by being supplied with the power supply voltage, configured to generate the read data and the read parity by receiving internal data and internal parity when the internal read signal is input, configured to receive correction data when the internal write signal is input, and configured to output the correction data as the internal data; a write parity generation circuit driven by being supplied with the power supply voltage, configured to receive the read data when the internal write signal is input, and configured to generate the write parity by performing an error correction code (ECC) encoding operation on the read data; a syndrome generation circuit driven by being supplied with the power supply voltage and configured to generate a syndrome by comparing the write parity and the read parity; an error correction signal generating circuit configured to generate an error correction signal by performing an ECC decoding operation on the syndrome; as well as A correction data generation circuit is configured to generate the correction data by correcting an error included in the read data in response to the error correction signal.

19. The semiconductor device according to claim 12, further comprising: a command generation circuit configured to generate a self-refresh command for performing the self-refresh operation based on a chip selection signal and a command address input in synchronization with a clock; a row address generation circuit configured to generate row addresses that are counted sequentially when the self-refresh command is input; a refresh control circuit configured to generate an internal refresh signal including a pulse periodically generated when the self-refresh command is input; as well as A row control circuit is configured to sequentially activate a plurality of word lines based on the row address when the internal refresh signal is input.

20. The semiconductor device according to claim 19, wherein the command generation circuit comprises: a buffer circuit configured to generate an internal chip select signal by latching the chip select signal in synchronization with a rising edge of the clock, and configured to generate an internal command address by latching the command address in synchronization with a rising edge of the clock; as well as A command decoder is configured to generate the self-refresh command, and the self-refresh command is enabled when the internal chip selection signal and the internal command address have a combination for performing the self-refresh operation.

21. The semiconductor device according to claim 19, wherein the row address generation circuit comprises: a refresh address generation circuit configured to generate refresh addresses that are counted sequentially when the self-refresh command is input; as well as The address selection circuit is configured to output any one of a target address and the refresh address as the row address based on a refresh enable signal, the target address being used to select a repeatedly activated word line among a plurality of word lines.

22. The semiconductor device according to claim 19, wherein the refresh control circuit comprises: A self-refresh pulse generating circuit configured to generate a self-refresh pulse when the self-refresh command is input, wherein a generation period of the self-refresh pulse is adjusted based on temperature information; as well as The internal refresh signal generating circuit is configured to generate the internal refresh signal by synthesizing the self refresh pulse and an auto refresh pulse generated after the auto refresh operation starts.

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