Memory circuit comprising electronic unit and control circuit

Abstract

The invention relates to a memory circuit comprising an electronic unit and a control circuit. A memory circuit includes a memory array formed of electronic units. Each electronic unit includes an integrated stack continuously having a first electrode, an intermediate layer formed of a bidirectional threshold switch layer, and a resistor connected to the intermediate layer. The control circuit is connected to the electronics unit. The control circuit is constructed and configured to apply a first voltage pulse of a first polarity between the first electrode and the resistor to set a first logic state of the electronic unit, and to apply a second voltage pulse of a second polarity opposite the first polarity to set a second logic state of the electronic unit.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French Patent Application No. 2306306, filed on June 19, 2023, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more specifically, to integrated electronic units arranged in an array. The present disclosure relates specifically to electronic devices including cycloidal threshold switch (OTS) materials. Background Art

[0004] Among chalcogenide materials, two categories are currently being studied for use in electronic devices, more specifically for the manufacture of switching devices and memories. In particular, a distinction is made between cyclotron (OTS) materials and phase change (PC) materials. Both materials can be used in thin films in electronic integrated devices.

[0005] The bidirectional threshold switch material switches between "on" and "off" states depending on the amount of voltage potential applied across the electronic unit. When the voltage across the bidirectional threshold switch exceeds the threshold voltage, the state of the bidirectional threshold switch changes. Once the threshold voltage is reached, the "on" state is triggered and the bidirectional threshold switch is in a substantially conductive state. If the current or voltage potential drops below the threshold, the bidirectional threshold switch returns to the "off" state.

[0006] Phase change materials can switch between a crystalline phase and an amorphous phase under the action of heat. Since the resistance of amorphous materials is significantly greater than that of crystalline materials, this phenomenon can be used to define two memory states distinguished by the resistance measured using the phase change material. The most common phase change material used in phase change memory is based on germanium-antimony-tellurium (GST).

[0007] Figure 1A and Figure 1B Two simplified cross-sectional views of an example of a known memory cell illustrated in U.S. Patent Application Publication No. 2022 / 0238603 (corresponding to French Patent Application No. 2100747, the disclosure of which is incorporated by reference) are illustrated.

[0008] The electronic unit 100 comprises a resistor 102 or a resistive element having a fixed resistance value, a first electrode 105, also referred to as a first electrode, and an additional layer 106. The electronic unit 100 further comprises an intermediate layer 104', the intermediate layer 104' comprising a bidirectional threshold switch (OTS) layer 104, a memory layer 108, and a barrier layer 110. The intermediate layer 104' is, for example, located between the resistor 102 and the first electrode 105, wherein the OTS layer 104 is, for example, in contact with the resistor 102. The additional layer 106 is, for example, connected to the first electrode 105. The memory layer 108 is, for example, located above the OTS layer 104 and between the OTS layer 104 and the first electrode 105. The barrier layer 110 is arranged between the memory layer 108 and the OTS layer 104.

[0009] When a voltage applied to the electronic cell is higher than the threshold voltage of the OTS layer 104, current may flow through the OTS layer 104 and the memory layer 108 in the electronic cell 100 and may cause a change in the resistivity of the layer 108. This change may change the memory state of the layer 108, thus changing the electrical characteristics of the electronic cell 100.

[0010] The high resistance state may be associated with a “reset” state or a logical “0” value, while the low resistance state may be associated with a “set” state or a logical “1” value.

[0011] There is a need to improve existing integrated electronic units containing bidirectional threshold switches.

[0012] There is a need in the art to address the problem of making an electronic unit to be used in a (memory) array having a simplified structure but at the same time being able to operate efficiently and / or correctly and / or having desired overall characteristics. Summary of the invention

[0013] To solve the above-mentioned problems, a memory circuit according to one or more of the following embodiments is proposed.

[0014] One embodiment provides a memory circuit, which includes: a memory array, the memory array including a plurality of electronic cells, wherein at least one electronic cell includes an integrated stack, the integrated stack continuously having: i) a first electrode; ii) an intermediate layer including a bidirectional threshold switching layer; and iii) a resistor connected to the intermediate layer; and a control circuit, the control circuit being connected to the at least one electronic cell, wherein the control circuit is constructed and configured to apply a first voltage pulse of a first polarity between the first electrode and the resistor to set a first logic state of the electronic cell, and to apply a second voltage pulse of a second polarity opposite to the first polarity to set a second logic state of the electronic cell.

[0015] According to one embodiment, the bidirectional threshold switch layer is made of a chalcogenide material.

[0016] According to one embodiment, the at least one electronic unit comprises only the intermediate layer between the first electrode and the resistor, and wherein the intermediate layer comprises only the bidirectional threshold switch layer.

[0017] According to one embodiment, the bidirectional threshold switch layer has a thickness between 15 nm and 50 nm.

[0018] According to one embodiment, the control circuit comprises a plurality of bit lines and a plurality of word lines, and the at least one electronic unit is connected to the respective bit line via its resistor and to the respective word line via its first electrode.

[0019] According to an embodiment, the integrated stack further comprises a transistor connected to the resistor at an opposite side with respect to the intermediate layer.

[0020] According to an embodiment, the transistor is a MOSFET transistor.

[0021] According to an embodiment, the transistor is a FinFET transistor.

[0022] According to one embodiment, the bidirectional threshold switch layer has a thickness between 5 nm and 10 nm.

[0023] According to one embodiment, the control circuit comprises a plurality of bit lines and a plurality of word lines, and the at least one electronic unit is connected to the respective word line via its transistor and to the respective bit line via its first electrode.

[0024] According to one embodiment, the transistor comprises a drain and a gate, and it is connected to the resistor via its drain and to the corresponding word line via its gate.

[0025] According to one embodiment, the control circuit comprises a respective inverter for each pair of bit line and word line, the respective inverter comprising a respective p-MOS transistor and a respective n-MOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above features and advantages and others will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0027] Figure 1A and Figure 1B Two simplified cross-sectional views of a known electronic unit are illustrated;

[0028] Figure 2A and Figure 2Billustrates two simplified cross-sectional views of an electronic unit according to a first embodiment;

[0029] Figure 3 Picture shows Figure 2A and Figure 2B Voltage-current characteristics of the electronic unit;

[0030] Figure 4 illustrates a simplified schematic diagram of a memory circuit according to a first embodiment of the present embodiment;

[0031] Figure 5 illustrates a simplified cross-sectional view of an electronic unit according to a second embodiment; and

[0032] Figure 6 A simplified schematic diagram of a memory circuit according to a second embodiment of the present embodiment is illustrated. DETAILED DESCRIPTION

[0033] In the various drawings, similar features have been designated by similar reference symbols. In particular, common structural and / or functional features between the various embodiments may have the same reference symbols and may have the same structure, dimensions, and material properties.

[0034] For clarity, only operations and elements useful for understanding the embodiments described herein are illustrated and described in detail. Specifically, the electrical connections between electronic units organized in an array and selection circuits are not described in detail, and the disclosed embodiments are compatible with existing switch arrays and corresponding control circuits.

[0035] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0036] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers such as terms "front", "back", "top", "bottom", "left", "right", or relative position qualifiers such as terms "above", "below", "higher", "lower", or orientation qualifiers such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figure.

[0037] Unless otherwise specified, the terms "about," "substantially," and "approximately" mean within + / - 10%, and preferably within + / - 5%.

[0038] In the context of this specification, "logic state" means a "set" state of an intermediate layer (or a bidirectional threshold switch layer) characterized by a first threshold voltage or a "reset" state of an intermediate layer (or a bidirectional threshold switch layer) characterized by a second threshold voltage. Typically, for voltage values ​​between the first threshold voltage and the second threshold voltage, the intermediate layer (or a bidirectional threshold switch layer) in the set state is conductive, and for voltage values ​​between the first threshold and the second threshold, the intermediate layer (or a bidirectional threshold switch layer) in the reset state is resistive.

[0039] In the context of this specification, a "conductive" element means an element (e.g., an intermediate layer or a bidirectional threshold switching layer) that allows a current of less than or equal to 5 mA (preferably less than or equal to 2 mA) to pass (this current is limited by the presence of a resistor having a resistance value of typically about 5-10 kΩ) by applying an electric field strength greater than or equal to 2 MV / cm and less than or equal to 4 MV / cm (a voltage difference is applied along the thickness direction of the element, which is typically nanometer-scale).

[0040] In the context of this specification, a "resistive" (or non-conductive) element means an element (e.g., an intermediate layer or a bidirectional threshold switching layer) that allows a current less than or equal to 50 μA, preferably less than or equal to 25 μA, and more preferably less than or equal to 10 μA to pass through by applying an electric field strength greater than 4 MV / cm and less than or equal to 10 m MV / cm.

[0041] Advantageously, the control circuit allows a bipolar operation of the intermediate layer. In particular, it has been experimentally verified (through a large test campaign) that in this way, the intermediate layer including the OTS layer can be used both as a memory element (i.e. an element that can be programmed in a logic state and can maintain the assigned logic state) and as a selector drain element (i.e. an element that can allow / block the passage of current through the electronic unit).

[0042] Figure 2A and Figure 2B The electronic unit 200 according to the first embodiment is shown. Note that Figure 2A and Figure 2B Only one electronic cell 200 is shown, but typically the electronic cell is part of a memory array including a large number of integrated electronic cells fabricated using thin film layers of chalcogenide materials, semiconductor materials, resistive materials, insulating materials, conductive materials, and the like.

[0043] For the sake of simplicity, reference is made to the layers to designate the corresponding elements of the stack forming the electronic unit. However, it should be understood that in practice the corresponding layers correspond to thin films that are deposited and etched to form individual switching elements separated by insulating trenches and arranged, for example, in an array. The terminals or electrodes of each electronic unit can be interconnected, for example, in rows and columns, through the corresponding layers of the stack.

[0044] The electronic unit 200 includes a resistor 202 exemplarily having a fixed resistance value (eg, independent of the crystal state).

[0045] The electronic unit 200 includes a first electrode 205 .

[0046] The electronic unit 200 includes an intermediate layer 204 ′ exemplarily interposed between the resistor 202 and the first electrode 205 to be in direct contact therewith.

[0047] Exemplarily, the intermediate layer 204' comprises only an OTS layer 204. In this way, the structure of the electronic unit is simplified, resulting in advantages in terms of cost and / or production time, and / or reduced obstruction of the electronic unit, thereby reducing the overall size of the memory circuit (i.e., saving silicon area and associated costs).

[0048] For example, the electronic unit 200 further includes an additional layer 206 connected to the first electrode 205 at the opposite side relative to the OTS layer 204 (in other words, the first electrode is interposed between the additional layer and the intermediate layer). Preferably, the additional layer is made of a material having an electrical conductivity greater than or equal to 20 S / μm, more preferably greater than or equal to 40 S / μm.

[0049] For example, in Figure 2A and Figure 2B In the embodiment of the present invention, the first electrode 205 forms an electrode of the electronic unit 200 , and the resistor 202 forms another electrode of the electronic unit 200 .

[0050] The resistor 202 has, for example, an L-shaped cross section, i.e., the resistor 202 has a horizontal portion 2020 and a vertical portion 2022. The resistor 202 is, for example, surrounded by an insulating layer not shown. The thickness of the insulating layer is such that the upper surface of the vertical portion 2022 of the resistor 202 is coplanar with the upper surface of the insulating layer. Although illustrated in an L-shaped cross section, the shape of the resistor 202 can be easily adapted to a square cross section or any other shape (not shown). The resistor 202 is connected to the OTS layer 204, for example, in contact with the OTS layer 204.

[0051] Figure 2A , Figure 2B and Figures 4 to 6The electronic unit is shown in space following an orthogonal spatial system XYZ in which the axis Z is orthogonal to the top surface of the additional layer 206 of electronic units.

[0052] exist Figure 2A and Figure 2B In the embodiment of FIG. 2 , the top additional layer 206 extends horizontally along the direction X. Figure 2A In the example of , the vertical portion 2022 of the resistor 202 is preferably centered relative to the electronic unit 200 and extends vertically along the direction Y. Figure 2B In the example of FIG. 2 , the vertical portion 2022 of the resistor 202 is preferably centered relative to the electronic unit 200 and extends vertically along the direction X.

[0053] therefore, Figure 2A and Figure 2B The difference between the views shown in is the orientation of the L-shaped resistor. Figure 2A The view in is referred to as a "self-aligned wall" cell architecture, in which the width of the resistor 202 is equal to the width of the additional layer 206. Figure 2A In the view of FIG. 2 , the resistor 202 and the additional layer 206 are formed, for example, using the same shielding layer and in the same direction.

[0054] Figure 2B The view of corresponds to using the "self-aligned wall technique" in a different way, where the width of the resistor 202 is not equal to the width of the additional layer 206. Figure 2B , the resistor 202 , the OTS layer 204 and the first electrode 205 are formed, for example, using the same shielding layer as used to form the additional layer 206 , but are oriented in a perpendicular direction compared to the direction of the additional layer 206 . Figure 2B The electronic cell architecture allows the integration of resistor 202 into the OTS device without area penalty, at the expense of one non-critical additional mask and few additional process steps.

[0055] exist Figure 2A and Figure 2B In both views of FIG. 2 , the interconnections (not shown) of the portion 2020 of the resistor 202 are perpendicular to the interconnections of the additional layer 206. In other words, if the additional layer 206 is organized in columns, the bottom electrodes are organized in rows.

[0056] exist Figure 2A and Figure 2B In the embodiment of the present invention, the vertical portion 2022 of the resistor 202 is preferably centered relative to the electronic unit 200 and extends vertically along the direction X. Alternatively, the vertical portion 2022 of the resistor 202 is preferably centered relative to the electronic unit 200 and extends vertically along the direction Y.

[0057] The first electrode 205 and the resistor 202 are made of, for example, the same metal material (e.g., tungsten). Alternatively, the first electrode 205 and the resistor 202 may be made of two different metal materials. For example, the resistor and / or the first electrode are made of a (refractory) metal material preferably selected from the following group: carbon (C), carbon nitride ((CN)n), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (W2N, WN, WN2), tungsten carbon nitride, tungsten silicon nitride, tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride, tantalum tungsten, or any combination or alloy of these materials.

[0058] The first electrode 205 is connected to the additional layer 206. For example, the first electrode 205 is in direct contact with the additional layer 206. The additional layer 206 is connected to the first electrode 205, for example, by a conductive path that is smaller than the first electrode 205, and is made of tungsten, for example.

[0059] The additional layer 206 has, for example, a width that is the same as one of the dimensions of the first electrode 205 or a width that is greater than one of the dimensions of the first electrode 205 .

[0060] For example, the additional layer 206 is made of copper.

[0061] When the voltage applied between the additional layer 206 and the resistor 202 exceeds the threshold voltage V TH The OTS layer 204 has the characteristic of a significant decrease in resistivity when the voltage is applied between the top and bottom of the layer. This decrease (or increase), triggered by a voltage applied between the top and bottom of the layer, allows the layer to be considered as forming a switch between an "off" state and an "on" state. If the voltage applied to the OTS layer 204 is below the threshold V TH , the OTS layer 204 remains in an "off" or high resistance state. In this state, only leakage current flows through the electronic unit 200. If a voltage above the threshold V TH The OTS layer 204 switches to the "on" state and operates in a relatively low resistance state. In the "on" state, current flows through the electronic unit 200. The threshold voltage V TH For example, between 0.5V and 5V (including the end values).

[0062] The OTS layer 204 is made of, for example, a chalcogenide material such as germanium. Alternatively, the OTS layer is made of, for example, any other chalcogenide material selected from the following group: germanium (Ge), tellurium (Te), selenium (Se), arsenic (As), or any combination or alloy of these materials. For example, the OTS layer may also be preferably doped with antimony (Sb), indium (In), or silicon (Si).

[0063] Other examples of bidirectional materials suitable for forming the OTS layer 204 can be found in US Pat. No. 8,148,707 (corresponding to European Patent No. 2204851), the contents of which are incorporated herein by reference to the extent permitted by law.

[0064] Typically, the chalcogenide material of the OTS layer is not a phase change material, that is, the OTS layer is independently made of an amorphous material by applying energy. In other words, the chalcogenide material is always an amorphous material. This means that the intermediate layer 204' does not contain any phase change material.

[0065] The OTS layer 204 has a thickness of, for example, 30 nm. More typically, the OTS layer may have a thickness greater than or equal to 10 nm, more preferably greater than or equal to 15 nm, even more preferably greater than or equal to 25 nm, and / or less than or equal to 100 nm, more preferably less than or equal to 50 nm, even more preferably less than or equal to 40 nm.

[0066] The OTS layer 204 and the first electrode 205 of each electronic unit are separated from the corresponding OTS layer 204 and the first electrode 205 of the adjacent unit by an insulating layer not shown. In other words, the OTS layer 204 is "fully constrained". For example, the OTS layer 204 and the first electrode 205 have a parallelepiped shape, for example, with the same width and the same length for both layers.

[0067] Figure 3 is a graph illustrating the evolution of the current as the voltage applied to the electrodes of the electronic unit 200 varies.

[0068] In bipolar operation, when the voltage applied to the electronic unit exceeds the first threshold voltage V in the positive polarity or the first polarity TH 0, the OTS layer 204 becomes conductive in the "on" state and is programmed to the "0" state or the first logic state, and then becomes resistive again in the "off" state as the applied voltage decreases. Similarly, when the absolute value of the voltage applied to the electronic unit exceeds the threshold voltage V in the negative polarity or the second polarity, TH 1, the OTS layer 204 becomes conductive in the "on" state and is programmed to the "1" state or the second logic state, and then becomes resistive again in the "off" state as the applied voltage decreases.

[0069] When an electronic cell is programmed to "1" twice in a row (twice in a row), the threshold voltage V is lower than when the electronic cell is programmed to "0" and then to "1". TH The absolute value of 1 is less important. In other words, if the same electronic cell is programmed to "1" and then it is reprogrammed to "1" (without being programmed to "0" in between), the threshold voltage V TH1 is equal to V TH SAME 1, whereas if the same electronic cell is programmed to “0” and then it is programmed to “1”, the threshold voltage V TH 1 is equal to V TH OPPO 1. V TH OPPO The absolute value of 1 is greater than V TH SAME 1. As an example, the voltage V TH SAME The absolute value of 1 is roughly equal to the voltage V TH 0.

[0070] To exploit this memory effect, it is recommended to use a TH SAME 1 and V TH OPPO 1 corresponds to a negative voltage V READ The electronic cell 200 is read. With such a read voltage, if the measurement of the current flowing in the electronic cell determines that the OTS layer 204 is conductive, this is because the threshold voltage V TH 1 corresponds to V being exceeded TH SAME 1 and the electronic cell has just been programmed to “1”. In contrast, if the measurement of the current flowing in the electronic cell determines that the OTS layer 204 is resistive, this means that the threshold voltage V TH 1 corresponds to V not being exceeded TH OPPO 1 and the electronic unit has just been programmed to "0".

[0071] It should be noted that the electronic cell read does not overwrite the programming, because reading the programming as 1 includes reprogramming to "1", and reading the programming as "0" includes not reprogramming the electronic cell.

[0072] Figure 4 A simplified schematic diagram of an array of electronic units 200 is illustrated.

[0073] The array of cells 200 illustratively includes Figure 2A and Figure 2B . The array is for example associated with a control circuit 405 (CTRL) configured to apply a voltage on each electronic unit between two electrodes (more precisely, between the resistor 202 and the first electrode 205).

[0074] exist Figure 4 In FIG. 4 , the electronic unit 200 is arranged between a plurality of bit lines 401 and word lines 403. Figure 4, bit lines 401 are illustrated with vertical lines and word lines 403 are illustrated with horizontal lines.

[0075] Exemplarily, the control circuit T405 includes (not shown) a corresponding inverter for each pair of bit lines 401 and word lines 403 (i.e., one inverter connected to the pair of bit lines and another inverter connected to the pair of word lines). Preferably, each inverter includes a corresponding p-MOS transistor and a corresponding n-MOS transistor. In this way, the control circuit is simple in structure and / or has relatively high performance.

[0076] Preferably, the control circuit 405 (also refer to Figure 6 , as will be disclosed below) is constructed and configured to apply a read voltage pulse (of a first or second polarity) having a voltage value between a first voltage threshold and a second voltage threshold between a first electrode and a resistor to determine a current logic state of the electronic unit.

[0077] Exemplarily, each electronic unit 200 is connected to a corresponding word line 403 via a first electrode 205 and to a corresponding bit line 401 via a resistor 202. Alternatively, at least one electronic unit is connected to a corresponding bit line via its first electrode and to a corresponding word line via its resistor. The described connection is called a "crossbar scheme". It is noted that the electronic unit of an embodiment in a crossbar scheme allows the selector element to be placed outside the silicon substrate, thereby allowing additional circuits and / or logic components to be advantageously introduced into the silicon substrate. In addition, the crossbar scheme allows improved modularity of the memory circuit, with advantages for embedded applications (e.g., automotive).

[0078] In order to be programmed, the electronic cell 200 must see a voltage difference between its two electrodes respectively connected to the bit line 401 and the word line 403. In practice, in order to program the electronic cell 200 to a “0”, its bit line 401 is placed at a voltage corresponding to a value of −V / 2 and its word line 403 is placed at a voltage corresponding to a value of +V / 2, so that the electronic cell under consideration sees a voltage of V. Similarly, in order to program the electronic cell 200 to a “1”, its bit line 401 is placed at a voltage corresponding to a value of +V / 2 and its word line 403 is placed at a voltage corresponding to a value of −V / 2, so that the electronic cell under consideration sees a voltage of −V.

[0079] For one or the other procedure, the other electronic units see a voltage of 0, V / 2 or -V / 2. By choosing the value of V so that its absolute value is greater than V TH OPPO 1 and the absolute value of V / 2 is less than V TH SAME 1 and V TH0, the electronic unit that sees 0, V / 2, or -V / 2 is not programmed.

[0080] As an example, the operating voltage is comprised between 4V and 6V.

[0081] Figure 5 A simplified cross-sectional view of an electronic unit 500 according to a second embodiment is illustrated.

[0082] Figure 5 The electronic unit 500 shown in FIG. Figure 2A and Figure 2B , except that the electronic unit 500 further includes a transistor 502. Exemplarily, the transistor 502 is connected to the resistor 202 at the opposite side relative to the intermediate layer 204'. In this way, the operating voltage of the overall electronic unit can be reduced, and there is an advantage in power consumption. In addition, the transistor can act as a selector element, thereby enabling the OTS layer to perform only memory functions. In this way, an OTS layer with a relatively low thickness can be used.

[0083] Alternatively, the transistor may be connected to the first electrode at an opposite side relative to the intermediate layer.

[0084] Exemplarily, transistor 502 is an n-MOS FinFET transistor. It has been shown that n-MOS FinFET transistors can be easily driven, thus simplifying the overall operation of the memory circuit. Typically, transistor 502 is a MOSFET transistor, preferably of the FinFET type. It has been shown that MOSFET transistors (especially FinFET transistors) have high performance in terms of low size (i.e., low burden on the electronic unit) and / or high frequency range. This is conducive to using the electronic unit for embedded applications, such as automotive applications.

[0085] Exemplarily, in the electronic unit 500 , the OTS layer 204 ″ has a thickness of 8 nm.

[0086] More generally, when the electronic unit includes a transistor, the OTS layer 204″ may have a thickness greater than or equal to 2 nm, preferably greater than or equal to 5 nm, and / or less than or equal to 15 nm, preferably less than or equal to 10 nm. As described above, transistors allow the use of relatively low thickness OTS layers, thereby increasing the applicability of memory circuits due to their easier integration in various devices.

[0087] If you can Figure 6 As schematically seen in FIG. 5 , transistor 502 is connected to a word line (WL) via its gate 502g.

[0088] In this example, the drain 502d of the transistor 502 is connected to the resistor 202 and more specifically to the horizontal portion 2020 of the resistor 202. In this example, the source 502s of the transistor 502 is connected to ground.

[0089] Figure 6 A simplified schematic diagram of an array of electronic units 500 (having a plurality of electronic units 500 ) is illustrated.

[0090] exist Figure 6 In the embodiment, the electronic unit 500 is disposed between a plurality of bit lines 401 and word lines 403 .

[0091] Exemplarily, each electronic unit 500 is connected to a bit line 401 via its first electrode 205 and to a word line 403 via the gate 502 g of its transistor 502 .

[0092] For example, a memory array is associated with control circuit 405 .

[0093] In order to be programmed, the electronic cell 500 must have a non-zero voltage across it. In order to program the electronic cell 500 to a "0", its bit line 401 is placed at a voltage corresponding to a +V value and its word line 403 is placed at a voltage corresponding exemplarily to a 0V value, so that the transistor 502 is turned on and the electronic cell under consideration sees a voltage V. In order to program the electronic cell 500 to a "1", its bit line 401 is placed at a voltage corresponding to a -V value and its word line 403 is placed at a voltage corresponding exemplarily to a 0V value, so that the transistor 502 is turned on and the electronic cell under consideration sees a voltage -V.

[0094] For one or the other of the programs, the other electronic units of the memory circuit either have their corresponding transistors 502 switched on and see a voltage of exemplarily 0 V, or have their transistors 502 switched off. These electronic units are therefore not programmed.

[0095] In one embodiment, the control circuit includes respective inverters for each pair of bit line 401 and word line 403 (ie, one inverter connected to the pair of bit lines and another inverter connected to the pair of word lines), for example, including p-MOS transistors and n-MOS transistors.

[0096] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations.

[0097] Finally, based on the functional description provided above, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A memory circuit, comprising: A memory array comprising a plurality of electronic units, wherein at least one electronic unit comprises an integrated stack having in series: i) a first electrode; ii) an intermediate layer including a bidirectional threshold switching layer; and iii) a resistor connected to said intermediate layer; and A control circuit is connected to the at least one electronic unit, wherein the control circuit is configured to apply a first voltage pulse of a first polarity between the first electrode and the resistor to set a first logic state of the electronic unit, and to apply a second voltage pulse of a second polarity opposite to the first polarity to set a second logic state of the electronic unit different from the first logic state.

2. The memory circuit according to claim 1, wherein: The bidirectional threshold switch layer is made of chalcogenide material.

3. The memory circuit according to claim 1, wherein: Only the intermediate layer is located between the first electrode and the resistor of the at least one electronic unit, and wherein the intermediate layer is only the bidirectional threshold switch layer.

4. The memory circuit according to claim 3, wherein: The bidirectional threshold switch layer has a thickness between 15 nm and 50 nm.

5. The memory circuit according to claim 1, wherein: The control circuit includes a plurality of bit lines and a plurality of word lines, wherein the at least one electronic unit is connected to a corresponding bit line through the resistor, and wherein the at least one electronic unit is connected to a corresponding word line through the first electrode.

6. The memory circuit according to claim 1, wherein: The integrated stack also includes a transistor connected to the resistor at an opposite side relative to the intermediate layer.

7. The memory circuit according to claim 6, wherein: The transistor is a MOSFET transistor.

8. The memory circuit according to claim 6, wherein: The transistor is a FinFET transistor.

9. The memory circuit according to claim 6, wherein: The bidirectional threshold switch layer has a thickness between 5 nm and 10 nm.

10. The memory circuit according to claim 6, wherein: The control circuit includes a plurality of bit lines and a plurality of word lines, wherein the at least one electronic unit is connected to a corresponding word line through the transistor, and wherein the at least one electronic unit is connected to a corresponding bit line through the first electrode.

11. The memory circuit according to claim 10, wherein: The transistor includes a drain and a gate, and wherein the drain is connected to the resistor, and wherein the gate is connected to a corresponding word line.

12. The memory circuit according to claim 10, wherein: The control circuit includes, for each pair of bit line and word line, a respective inverter including a respective p-MOS transistor and a respective n-MOS transistor.

13. A circuit comprising: a bidirectional threshold switch memory cell formed by an integrated stack including a first electrode, a resistor, and a bidirectional threshold switch layer having a first surface in contact with the first electrode and a second surface in contact with the resistor; and A control circuit is electrically connected to the bidirectional threshold switch memory cell and is configured to set a first logic state by applying a first voltage pulse of a first polarity between the first electrode and the resistor, and to set a second logic state different from the first logic state by applying a second voltage pulse of a second polarity opposite to the first polarity between the first electrode and the resistor.

14. The circuit according to claim 13, wherein: The bidirectional threshold switch layer is made of chalcogenide material.

15. The circuit of claim 13, wherein: The bidirectional threshold switch layer has a thickness between 15 nm and 50 nm.

16. The circuit of claim 13, further comprising a transistor having a conduction terminal connected to the resistor and a control terminal connected to a word line.

17. The circuit of claim 16, wherein: The transistor is a MOSFET transistor, the conduction terminal is the drain and the control terminal is the gate.

18. The circuit of claim 16, wherein: The transistor is a FinFET transistor, the conduction terminal is a drain and the control terminal is a gate.

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