Preparation method of charge trapping layer and nonvolatile memory device

Abstract

The invention provides a preparation method of a charge trapping layer and a nonvolatile memory device. The preparation method of the charge trapping layer comprises the following steps: depositing the charge trapping layer; performing fluorine-based plasma treatment on the charge trapping layer by using fluorine-based gas; the charge trapping layer is thermally treated. According to the electric preparation method, fluorine-based plasma treatment is carried out on the charge trapping layer by using fluorine-based gas so as to reduce the interface state and increase charge trapping sites, and then heat treatment is carried out so as to promote crystallization of the charge trapping layer and increase shallow and deep charge trapping sites; when the preparation method disclosed by the invention is applied to preparation of the nonvolatile memory device, the storage window, programming and erasing efficiency of the nonvolatile memory device can be improved; meanwhile, when the charge trapping layer adopts an aluminum-doped hafnium oxide layer, the isolation layer can adopt a tunnel layer (Al2O3)-active channel layer (IGZO)-protective layer (Al2O3) structure, so that the performance of the nonvolatile memory device is further optimized.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to a method for preparing a charge trapping layer and a non-volatile memory device. Background Art

[0002] Flash memory (Flash Memory) is an electronic non-volatile memory (NVM) that can retain data after power failure. Flash memory is the main means of achieving low-cost, high-density data storage required by all major end-user devices (smartphones, personal computers, USBs, medical devices, video games, etc.), and is widely used in various electronic devices. The working principle of flash memory is based on the combination of floating gates and control gates. The Fowler-Nordheim (FN) tunneling effect is used to change the position of electrons in the floating gate to achieve data storage and erasure.

[0003] Ideally, the information stored in a flash memory device should be preserved for a long time after the power is turned off. The dominant technology of flash memory is the floating gate (FG) memory cell. With the ever-increasing demand for the amount of stored data, the size of the floating gate cell has shrunk dramatically, resulting in some inherent limitations of the floating gate technology being reached, such as: (1) the thickness scaling of the tunnel oxide and polysilicon dielectric layer impairs reliability; (2) as the floating gate size decreases, the number of electrons accumulated in the floating gate decreases significantly; (3) it is difficult to maintain a high capacitive coupling coefficient between the control gate and the floating gate; (4) the parasitic capacitance between adjacent cells causes data interference to become important, etc.

[0004] Charge trap flash CTF-NVM is considered a promising alternative technology to conventional floating gate memory due to its superior operating characteristics, such as improved retention, endurance, lower power consumption and higher programming / erasing speed, as well as the ability to support vertical stacking. The most important part of charge trap memory is the charge trap stack structure. The charge trap layer consists of three layers, in which the charges are stored in its traps, and the charge trap layer is stacked between the tunnel oxide and the blocking oxide. The tunnel oxide (TO) is used to more efficiently inject charges from the substrate channel into the charge trap layer to prevent the trapped charges from tunneling back to the substrate and improve the retention characteristics. On the other hand, in order to form a barrier to prevent the undesirable movement of charges (holes / electrons) in and out of the gate, a sufficiently thick blocking oxide (BO) should be introduced, and its band offset with the charge trap layer should have a sufficient height. In order to improve the reliability of non-volatile memory devices, it is therefore necessary to generate stable trap sites to effectively enhance the charge trapping / de-trapping events originating from Fowler-Nordheim tunneling through defect sites located in the band gap.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a method for preparing a charge trapping layer and a non-volatile memory device. The method for preparing the charge trapping layer adds fluorine-based plasma treatment and subsequent high-temperature annealing treatment, which can increase the charge trapping sites of the charge trapping layer, thereby improving the charge retention ability of the charge trapping layer and improving the performance of the memory device.

[0007] Specifically, the first aspect of the present invention provides a method for preparing a charge trapping layer, characterized in that the preparation method comprises the following steps:

[0008] depositing a charge trapping layer;

[0009] performing a fluorine-based plasma treatment on the charge trapping layer using a fluorine-based gas;

[0010] The charge-trapping layer is heat-treated.

[0011] According to the first aspect of the present invention, the fluorine-based gas is CF 4 , SF 6 , CHF 3 , CH 2 F 2 , CH 3 F.C 2 F 6 , C 3 F 8 and NF 3 A combination of one or more of .

[0012] According to the first aspect of the present invention, the process parameters of the plasma treatment are:

[0013] Electrode power is 150-200W;

[0014] The fluorine-based gas flow rate is 40 to 60 sccm;

[0015] The chamber pressure is 10-50 mTorr;

[0016] The temperature is 10 to 40°C; and

[0017] The processing time is 1 to 10 minutes.

[0018] According to the first aspect of the present invention, the charge trapping layer is heat treated at a temperature of 500-800° C. for a time of 0.5-3 h.

[0019] According to the first aspect of the present invention, the charge trapping layer is an aluminum-doped hafnium oxide layer.

[0020] According to the first aspect of the present invention, the doping amount of aluminum in the aluminum-doped hafnium oxide layer is 4-6 mol %.

[0021] A second aspect of the present invention provides a nonvolatile memory device, comprising a substrate, a source region and a drain region on a separation region of the substrate, a tunneling oxide layer on the substrate in contact with the source region and the drain region, and a charge trapping layer, an isolation layer and a control gate sequentially stacked on the tunneling oxide layer;

[0022] The charge trapping layer is obtained by adopting the preparation method of the charge trapping layer.

[0023] According to a second aspect of the present invention, the isolation layer includes a tunnel layer, an active channel layer and a protection layer stacked in sequence.

[0024] According to the second aspect of the present invention, the protective layer is an aluminum oxide layer with a thickness of 3nm to 5nm;

[0025] The active channel layer is an indium gallium zinc oxide layer with a thickness of 15nm to 25nm; and / or

[0026] The tunnel layer is an aluminum oxide layer with a thickness of 8nm to 10nm.

[0027] According to a second aspect of the present invention, the tunneling oxide layer is a silicon dioxide layer, and the non-volatile memory device further includes an isolation layer;

[0028] The isolation layer is disposed between the tunneling oxide layer and the charge trapping layer.

[0029] In the electrical preparation method of the present invention, a fluorine-based gas is used to perform a fluorine-based plasma treatment on the charge trapping layer to reduce the interface state and increase the charge trapping sites, and then a heat treatment is performed to promote the crystallization of the charge trapping layer to increase the shallow and deep charge trapping sites; when the preparation method of the present invention is applied to the preparation of a non-volatile memory device, the storage window and programming and erasing efficiency of the non-volatile memory device can be improved; at the same time, when the charge trapping layer adopts an aluminum-doped hafnium oxide layer, the isolation layer can select a tunnel layer (Al 2 O 3 )-Active channel layer (IGZO)-Protective layer (Al 2 O 3 ) structure, thereby further optimizing the performance of the non-volatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0031] Figure 1 A flow chart of a method for preparing a charge trapping layer according to an embodiment of the present invention; and

[0032] Figure 2 FIG. 4 is a schematic structural diagram of a nonvolatile memory device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0034] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0035] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0036] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0037] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0038] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0039] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0040] As used herein, a "layer" may refer to a layer formed on a material (e.g., a substrate) and / or a layer formed on a previously deposited layer using, for example, a variety of deposition, masking, processing, and thermal techniques described herein. The term "layer" is meant to include layers specific to the semiconductor industry, such as "barrier layers," "dielectric layers," and "conductive layers," as well as other types of layers. The term "layer" is intended to be synonymous with the term "film," as used in the semiconductor industry. As used herein, "forming" a material is intended to include depositing a material (e.g., as a layer) using appropriate deposition techniques used in the semiconductor industry. As used herein, a "material" is intended to include a variety of chemical elements and / or combinations of a variety of chemical elements, as well as various quantities of each chemical element (e.g., to form compounds), which can be used to form a material (e.g., by depositing the material as a layer).

[0041] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to concretize specific characteristics, areas, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, areas, integers, steps, operations, elements and / or components. Although not defined differently, including the technical terms and scientific terms used herein, all terms have the same meaning as the meaning generally understood by technicians in the technical field to which the present invention belongs. The terms defined in the commonly used dictionary are additionally interpreted as having a meaning consistent with the relevant technical literature and the content of the current prompt, and as long as they are not defined, they shall not be overly interpreted as ideal or very formal meanings.

[0042] In order to overcome the above technical problems, the present invention provides a method for preparing a charge trapping layer and a non-volatile memory device, wherein the method for preparing the charge trapping layer comprises the following steps: depositing a charge trapping layer; subjecting the charge trapping layer to a fluorine-based plasma treatment using a fluorine-based gas; and heat treating the charge trapping layer. In the electrical preparation method of the present invention, a fluorine-based gas is used to subject the charge trapping layer to a fluorine-based plasma treatment to reduce interface states and increase charge trapping sites, and then a heat treatment is performed to promote crystallization of the charge trapping layer to increase shallow and deep charge trapping sites; when the preparation method of the present invention is applied to the preparation of a non-volatile memory device, the storage window and programming and erasing efficiency of the non-volatile memory device can be improved; at the same time, when the charge trapping layer uses an aluminum-doped hafnium oxide layer, the isolation layer can use a tunnel layer (Al 2 O 3 )-Active channel layer (IGZO)-Protective layer (Al 2 O 3 ) structure, thereby further optimizing the performance of the non-volatile memory device.

[0043] The method for preparing the charge trapping layer and the nonvolatile memory device of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0044] Figure 1 The present invention is a flow chart of a method for preparing a charge trapping layer according to an embodiment of the present invention. Specifically, the preparation method comprises the following steps:

[0045] Step S100: depositing a charge trapping layer. Of course, when the preparation method is used to prepare the source region S and the drain region D of the non-volatile memory device, a tunneling oxide layer is formed between the source region S and the drain region D to contact the source region S and the drain region D, and the charge trapping layer is deposited on the tunneling oxide layer. In some embodiments, the charge trapping layer and the tunneling oxide layer are provided with a blocking layer, etc.

[0046] In one embodiment, the charge trapping layer is an aluminum-doped hafnium oxide layer (Al:HfO 2 ), hafnium oxide is a material with a high dielectric constant. The hafnium oxide layer is used as the main area for storing charges. Al doping helps to increase the density of trap sites and improve storage efficiency. The density and distribution of trap sites can be controlled by controlling the doping amount of aluminum. Preferably, the doping amount of aluminum in the aluminum-doped hafnium oxide layer can be between 4 mol% and 6 mol%.

[0047] For example, the charge trapping layer is a hafnium oxide layer doped with 5 mol% aluminum. The charge trapping layer can be obtained by atomic layer deposition (ALD). Atomic layer deposition uses chemical reactions to deposit atoms or molecules layer by layer on the surface of the substrate to form a uniform and dense film. Since atomic layer deposition can grow thin films at the atomic level layer by layer, the thickness of the charge trapping layer can be precisely controlled. Usually, the thickness of the charge trapping layer is between 10nm and 40nm, such as 20nm. In practice, the material of the charge trapping layer and the thickness of the charge trapping layer can be further selected according to the structure of the target non-volatile memory device and the performance to be obtained.

[0048] After the charge trapping layer is obtained, step S200 is performed: using a fluorine-based gas to perform a fluorine-based plasma treatment on the charge trapping layer. The fluorine-based gas may be carbon tetrafluoride CF4, sulfur hexafluoride SF6, trifluoromethane CHF 3 、DifluoromethaneCH 2 F 2 , fluoromethane CH 3 F. Hexafluoroethane C 2 F 6 、Octafluoropropane C 3 F 8 and nitrogen trifluoride NF3 A combination of one or more of .

[0049] In one embodiment, the fluorine-based gas is selected from CF 4 The plasma treatment process parameters are: electrode power of 150-200W; fluorine-based gas flow rate of 40-60sccm; chamber pressure of 10-50mTorr; temperature of 10-40°C; and treatment time of 1-10min. During the plasma treatment process, the fluorine-based gas generates ions and free radicals, and the plasma collides with the exposed surface of the charge trapping layer. This process can reduce the interface state of the charge trapping layer and introduce fluorine ions (F - ) can form deep advanced sites in the charge trapping layer, thereby increasing the charge trapping sites in the charge trapping layer, improving the charge retention ability of the charge trapping layer and improving the performance of the memory device.

[0050] Step S300: heat-treating the charge trapping layer. The temperature of the heat-treating the charge trapping layer may be 500-800° C., such as 500° C., 600° C., 650° C. or 700° C. The gas during the heat treatment may include nitrogen (N 2 ) and inert gases, but are not limited thereto. Wherein, the inert gas may include but is not limited to helium (He), argon (Ar), etc. The heat treatment time may be 0.5 to 3 hours. For example, the heat treatment time for the charge trapping layer may be 0.5 hours, 1 hour, 2 hours, or 3 hours. Step S300 is a high-temperature annealing process, which can effectively repair the damage caused by the plasma, while promoting the crystallization of the aluminum-doped hafnium oxide layer and increasing the shallow and deep charge trapping sites in the charge trapping layer. Too short a heat treatment time may lead to insufficient repair and affect the performance of the charge trapping layer, while too long a heat treatment time may lead to degradation of material properties. By regulating the effect of heat treatment by regulating gas flow, chamber pressure, temperature, and time during the heat treatment process, the distribution and stability of the trap sites in the charge trapping layer can be further improved, thereby improving the storage window and programming and erasing efficiency of the storage device.

[0051] The present invention also provides a nonvolatile memory device, Figure 2The nonvolatile memory device of one embodiment of the present invention is a schematic diagram of the structure of a charge-trap-type memory thin film transistor CTM-TFT (charge-trap-type memory thin film transistors). Specifically, the nonvolatile memory device includes a substrate 1, a source region S and a drain region D on a separation region of the substrate, a tunneling oxide layer 2 on the substrate 1 in contact with the source region S and the drain region D, and a charge trapping layer 3, an isolation layer 4 and a control gate 5 sequentially stacked on the tunneling oxide layer 2. The thickness of the isolation layer 4, the thickness of the charge trapping layer 3 and the thickness of the tunneling oxide layer 2 can be reduced in sequence.

[0052] The isolation layer 4 may include a tunneling layer 41 (Tunneling Layer, TL), an active channel layer 42 (Active Channel Layer, ACT) and a protection layer 43 (Protection Layer, PL) stacked in sequence on the charge trapping layer 3. The tunneling layer 41 is relatively thin, and serves as an interface between the charge trapping layer 3 and the active channel layer 42, allowing charges to move between the charge trapping layer 3 and the active channel through the tunneling effect. The active channel layer 42 is usually an oxide semiconductor material to form an active channel, and the conductivity of the active channel layer 42 is controlled by the voltage of the control gate. The protection layer 43 can protect the active channel layer 42 from damage by subsequent wet etching processes, etc.

[0053] In some embodiments, a blocking layer 21 may be further disposed between the tunneling oxide layer 2 and the charge trapping layer 3 to prevent charges from directly penetrating from the substrate 1 into the charge trapping layer 3 .

[0054] The substrate 1 of the non-volatile memory device can be made of semiconductor material, insulating material, conductive material or any combination of these material types, and can be a single-layer structure or a multi-layer structure. Taking the substrate 1 as a p-type silicon substrate as an example, the source region S and the drain region D can be formed on the surface of the substrate 1 with n-type doping regions. The tunneling oxide layer 2 contacts the source region S and the drain region D, and can be formed between the source region S and the drain region D on the substrate 1. The tunneling oxide layer 2 can be a silicon dioxide layer SiO 2 .

[0055] When the tunnel oxide 2 layer is a silicon dioxide layer SiO 2 When the storage device is in operation, it is also the support layer of the storage device. The barrier layer 21 can be an aluminum oxide layer, and a 50nm Al2O3 layer can be prepared by an atomic layer deposition process. 2 O 3The aluminum oxide layer can also reduce the interface state of the charge trapping layer 3. The tunnel layer 41 can be an aluminum oxide layer. Preferably, the thickness of the tunnel layer 41 is 3nm to 5nm, such as 4nm. The active channel layer 42 is an indium gallium zinc oxide layer (In-Ga-Zn-O, IGZO) with a thickness of 15nm to 25nm. Preferably, the thickness of the indium gallium zinc oxide layer is 20nm. The protective layer can be an aluminum oxide layer with a thickness of 8nm to 10nm. The control gate 5 can be gold, aluminum, ruthenium or their alloys.

[0056] The electron trapping layer treated by fluorine-based plasma and subsequent thermal annealing can significantly affect the performance of the non-volatile memory device of the charge trap type storage thin film transistor structure. The test structure shows that the non-volatile memory device of the present invention has the characteristic of long-term data retention durability. The non-volatile memory device can be used in integrated circuits such as embedded storage devices and system-on-chip (SoC).

[0057] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0058] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a charge trapping layer, characterized in that: The preparation method comprises the following steps: depositing a charge trapping layer; performing a fluorine-based plasma treatment on the charge trapping layer using a fluorine-based gas; The charge-trapping layer is heat-treated.

2. The method for preparing a charge trapping layer according to claim 1, characterized in that: The fluorine-based gas is a combination of one or more of CF4, SF6, CHF3, CH2F2, CH3F, C2F6, C3F8 and NF3.

3. The method for preparing a charge trapping layer according to claim 1, characterized in that: The process parameters of the plasma treatment are: Electrode power is 150-200W; The fluorine-based gas flow rate is 40 to 60 sccm; The chamber pressure is 10-50 mTorr; The temperature is 10 to 40°C; and The processing time is 1 to 10 minutes.

4. The method for preparing a charge trapping layer according to claim 1, characterized in that: The charge trapping layer is heat treated at a temperature of 500 to 800° C. for a time of 0.5 to 3 hours.

5. The method for preparing a charge trapping layer according to claim 1, characterized in that: The charge trapping layer is an aluminum-doped hafnium oxide layer.

6. The method for preparing a charge trapping layer according to claim 5, characterized in that: The aluminum doping amount of the aluminum-doped hafnium oxide layer is 4 to 6 mol %.

7. A non-volatile memory device, characterized in that: The invention comprises a substrate, a source region and a drain region on a separation area of ​​the substrate, a tunneling oxide layer on the substrate in contact with the source region and the drain region, and a charge trapping layer, an isolation layer and a control gate sequentially stacked on the tunneling oxide layer; The charge-trapping layer is obtained by using the method for preparing a charge-trapping layer according to any one of claims 1 to 6.

8. The nonvolatile memory device according to claim 7, wherein: The isolation layer includes a tunnel layer, an active channel layer and a protection layer which are stacked in sequence.

9. The nonvolatile memory device according to claim 8, wherein: The protective layer is an aluminum oxide layer with a thickness of 3nm to 5nm; The active channel layer is an indium gallium zinc oxide layer with a thickness of 15nm to 25nm; and / or The tunnel layer is an aluminum oxide layer with a thickness of 8nm to 10nm.

10. The nonvolatile memory device according to claim 7, wherein: The tunneling oxide layer is a silicon dioxide layer, and the non-volatile memory device further includes an isolation layer; The isolation layer is disposed between the tunneling oxide layer and the charge trapping layer.

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