Method for forming semiconductor device structure

Abstract

Methods of forming semiconductor device structures are described. In some embodiments, the method includes forming a gate electrode; forming a mask structure over the gate electrode; patterning the mask structure to form an opening; and performing a first etching process on the gate electrode by applying a first supply power having a first pulse scheme and a first bias supply. The first bias power supply has a first frequency to control etching in a lateral direction. The method further includes performing a second etching process on the mask structure exposed in the opening by applying a second supply power having a second pulse scheme and a second bias supply, the second bias supply having a second frequency to control etching in a vertical direction, the first frequency and the second frequency being substantially different.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to methods for forming semiconductor device structures. Background Art

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation. Over the history of integrated circuit development, functional density (i.e., the number of devices interconnected per chip area) has increased while geometry size (i.e., the smallest component or circuit produced during the manufacturing process) has decreased. This process of miniaturization of component size provides the benefits of increased production efficiency and reduced associated costs. This miniaturization of component size has also increased the complexity of processing and manufacturing integrated circuits.

[0003] Therefore, there is a need for improvements in the processing and manufacture of integrated circuits. Summary of the invention

[0004] In some embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a gate electrode; forming a mask structure above the gate electrode; patterning the mask structure to form an opening; performing a first etching process on the gate electrode by applying a first power supply having a first pulse scheme and a first bias power supply, wherein the first bias power supply has a first frequency to control etching in a lateral direction; and performing a second etching process on the mask structure exposed in the opening by applying a second power supply having a second pulse scheme and a second bias power supply, wherein the second bias power supply has a second frequency to control etching in a vertical direction, wherein the first frequency and the second frequency are substantially different.

[0005] In some embodiments, a method for forming a semiconductor device structure is provided, the method comprising performing a first etching process on a gate electrode, wherein the first etching process comprises a plasma etching process, the plasma etching process having: a first power supply power having an 80% duty cycle at a power level in a range of about 1500 W to about 2500 W; and a first bias power supply having a 30% duty cycle at a voltage level in a range of about 150 V to about 250 V and a 50% duty cycle after the 30% duty cycle at a voltage level in a range of about 5 V to about 100 V; and performing a second etching process on a mask structure disposed on the gate electrode, wherein the second etching process comprises a plasma etching process, the plasma etching process having: a second power supply power having a 100% duty cycle at a power level in a range of about 10 W to about 200 W; and a second bias power supply having a 50% duty cycle at a voltage level in a range of about 200 V to about 800 V.

[0006] In some other embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a plurality of fins from a semiconductor substrate; forming an isolation region surrounding each of the plurality of fins; depositing a gate electrode above the plurality of fins; forming a mask structure above the gate electrode; forming an opening in the mask structure; extending the opening through the gate electrode by a first plasma etching process having a first bias power supply with a frequency to control lateral etching of the gate electrode; extending the opening through the isolation region; etching the sidewalls of the mask structure in the opening by a second plasma etching process having a second bias power supply with a frequency to control vertical etching of the mask structure and remove sharp corners in the sidewalls of the mask structure exposed to the opening; and filling the opening with a dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the present invention can be better understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the drawings are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0008] Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C Various schematic diagrams of intermediate stages and corresponding intermediate structures of an example process for forming a semiconductor device structure including one or more FinFETs according to some embodiments.

[0009] Fig. 9 A pulse scheme used in an etching process is shown according to some embodiments.

[0010] Fig.10 , Fig.11 , Fig.12 According to some embodiments, corresponding Figure 4D Schematic diagram of the cross-section AA of each processing example.

[0011] Fig.13 A pulse scheme used in an etching process is shown according to some embodiments.

[0012] Fig.14 , Fig.15 , Fig.16 , Fig.17 According to some embodiments, corresponding Figure 4D Schematic diagram of the cross-section AA of each processing example.

[0013] The reference numerals are described as follows:

[0014] 20: Semiconductor substrate

[0015] 22: Stress semiconductor layer

[0016] 24: Fins

[0017] 26: Quarantine

[0018] 28: Interface dielectric

[0019] 30: Dummy gate

[0020] 32: Mask

[0021] 34: Gate spacer

[0022] 36: Epitaxial source / drain region

[0023] 38: Contact Etch Stop Layer

[0024] 40: Interlayer dielectric

[0025] 42: Notch

[0026] 44: Gate dielectric layer

[0027] 46: Compliance layer

[0028] 48: Gate electrode

[0029] 52: Mask structure

[0030] 54, 56, 58: Layer

[0031] 59: Hard Mask Layer

[0032] 60: Opening

[0033] 60b: Bottom

[0034] 60m: Middle section

[0035] 60t: Top

[0036] 61: Sidewall

[0037] 61a: roughly straight section

[0038] 61b: Sloped part

[0039] 64: Dielectric materials

[0040] 66: Gap

[0041] a: top critical size

[0042] b: intermediate critical size

[0043] A, B: Angle DETAILED DESCRIPTION

[0044] It is to be understood that the following disclosure provides many different embodiments or examples to implement different parts of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, the size of the component is not limited to the scope or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the component. In addition, in the subsequent description, the first component formed above or on the second component includes an embodiment in which the first and second components are formed to be in direct contact, and may also include an additional component that can be formed between the first and second components so that the first and second components may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the appearance structure.

[0045] Furthermore, to facilitate description of the relationship of one element or component to another (plural) element or (plural) component in the drawings, spatially relative terms, such as "under", "below", "lower", "over", "above", "on", "top", "upper" and similar terms, may be used. Spatially relative terms also encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description of the spatially relative terms used would be interpreted accordingly.

[0046] Embodiments of the present invention relate to semiconductor devices and manufacturing methods, and in particular to the use of a cut metal gate (CMG) process to manufacture semiconductor devices. The cut metal gate process represents a manufacturing process in which, after a gate electrode (e.g., a metal gate) replaces a dummy gate structure (e.g., polysilicon), the gate electrode is cut (e.g., by an etching process) to separate the gate electrode into two or more parts. Each part is used as a gate electrode for a separate transistor. Thereafter, an isolation material is filled in the opening between adjacent parts of the gate electrode. In order to minimize the voids formed in the isolation material, a main etching step and a final penetration etching step are performed to form an opening.

[0047] In some examples, in the embodiments described, various deteriorations (e.g., height) may occur to the structures shown during processing. Such deteriorations may not be explicitly shown in the drawings or described herein, but one of ordinary skill in the art will readily understand how such deteriorations occur. Such deterioration may occur as a result of planarization processes such as chemical mechanical polishing (CMP), etching processes such as when the structures achieving the deterioration are not the primary target of the etching, and other processes.

[0048] Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C Various schematic diagrams of corresponding intermediate structures during intermediate stages of an example process for forming a semiconductor device structure including one or more FinFETs in accordance with some embodiments. Figure 1 In the cross-sectional schematic diagram, a semiconductor substrate 20 is shown having a stressed semiconductor layer 22 formed thereon. The semiconductor substrate 20 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, and the semiconductor substrate 20 may be doped (e.g., doped with p-type or n-type dopants) or undoped. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include an elemental semiconductor (e.g., silicon (Si), germanium (Ge)), a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide), an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP), or a combination of the foregoing.

[0049] The stressed semiconductor layer 22 may have compressive stress or tensile stress. In some examples, the stress of the stressed semiconductor layer 22 comes from heteroepitaxial growth on the semiconductor substrate 20. For example, heteroepitaxial growth generally includes epitaxial growth of a natural lattice constant that is different from the lattice constant of the substrate material at the surface on which the growth material is epitaxially grown. Pseudomorphically growing a material on a substrate material will cause the grown material to have stress. If the natural lattice constant of the growing material is greater than the lattice constant of the substrate material, the stress in the growing material is compressive stress, and if the natural lattice constant of the growing material is less than the lattice constant of the substrate material, the stress in the growing material is tensile stress. For example, pseudomorphically growing silicon germanium on bulk silicon will cause silicon germanium to have compressive stress, and pseudomorphically growing silicon carbide on bulk silicon will cause silicon carbide to have tensile stress.

[0050] The stressed semiconductor layer 22 may be or include silicon, silicon germanium (Si1-xGex, where x may be between about 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V semiconductor compound, a II-VI semiconductor compound, or the like. For example, materials used to form the III-V semiconductor compound include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, or the like. Furthermore, the stressed semiconductor layer 22 may be epitaxially grown on the semiconductor substrate 20 using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. The thickness of the stressed semiconductor layer 22 may be in the range of about 30 nm to about 50 nm.

[0051] Figure 2A schematic cross-sectional view of forming a fin 24 in a stressed semiconductor layer 22 or semiconductor substrate 20 is shown. In some examples, a mask (e.g., a hard mask) is used to form the fin 24. For example, one or more mask layers are deposited over the stressed semiconductor layer 22, and then the one or more mask layers are patterned into a mask. In some examples, the one or more mask layers may include or be silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition techniques. The one or more mask layers may be patterned by using photolithography. For example, a photoresist may be formed on the one or more mask layers, such as by spin coating, and then the photoresist may be exposed to light using a suitable mask to pattern the photoresist. Then, depending on whether a positive or negative photoresist is used, the exposed or unexposed portions of the photoresist may be removed. The photoresist pattern may then be transferred to one or more mask layers, for example, by using a suitable etching process to form a mask. The etching process may include reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, the like, or a combination thereof. The etching process may be anisotropic. The photoresist is then removed, for example, in an ashing or wet stripping process.

[0052] By using a mask, the stressed semiconductor layer 22 and / or the semiconductor substrate 20 can be etched to form grooves between adjacent pairs of fins 24 and to cause the fins 24 to protrude from the semiconductor substrate 20. In some embodiments, each fin 24 has a height in the range of about 115 nm to about 120 nm. The etching process can include reactive ion etching, neutron beam etching, inductively coupled plasma etching, the like, or a combination of the foregoing. The etching process can be anisotropic. The depth of the grooves can be formed in the range of about 80 nm to about 150 nm measured from the top surface of the stressed semiconductor layer 22. In some embodiments, the grooves between a pair of fins 24 can be substantially shallower than the grooves between adjacent pairs of fins 24, such as Figure 2 In some embodiments where the grooves have different depths, the different depths may not be explicitly shown.

[0053] Although the examples described herein are for stress engineering of the fin 24 (e.g., the fin 24 includes a corresponding portion of the stressed semiconductor layer 22), other examples may not perform such stress engineering. For example, the fin 24 may be formed from a bulk semiconductor substrate (e.g., the semiconductor substrate 20) without a stressed semiconductor layer. Furthermore, for the sake of clarity of the drawings, the stressed semiconductor layer 22 may be omitted from subsequent drawings. In some embodiments, even if not explicitly shown, the stressed semiconductor layer may be used for stress engineering, and the stressed semiconductor layer 22 may be a part of the fin 24. In some embodiments, the stressed semiconductor layer is not used for stress engineering, and the fin 24 may be formed from the semiconductor substrate 20.

[0054] Figure 3A and Figure 3B Schematic cross-sectional views and top views of each isolation region 26 formed in a corresponding trench are shown, respectively. Isolation region 26 may include or be an insulating material, such as an oxide (e.g., silicon oxide), a nitride, the like, or a combination thereof, and the insulating material may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (depositing a material based on chemical vapor deposition using a remote plasma system and then hardening the material to convert it into another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any suitable process may be used. In the embodiment shown, isolation region 26 includes silicon oxide formed by a flowable chemical vapor deposition process. A planarization process (e.g., chemical mechanical polishing) may remove any excess insulating material and any remaining mask (e.g., used to form trenches and fins 24) to form a coplanar top surface of the insulating material and fins 24. The insulating material may then be recessed to form isolation region 26. The insulating material is recessed so that the fins 24 may protrude from between adjacent isolation regions 26, which may at least partially characterize the fins 24 as channel regions on the semiconductor substrate 20. The insulating material may be recessed using an acceptable suitable dry or wet etching process, such as an etching process that is selective to the material of the insulating material. Furthermore, the top surface of the isolation region 26 has a flat surface as shown, a convex surface, a concave surface (e.g., a dish shape), or a combination of the foregoing, which may result from the etching process. As shown in the top view of FIG. 3B, the fins 24 extend longitudinally across the semiconductor substrate 20. The fins 24 may have a height in the range of about 30 nm to about 50 nm measured from the top surface of the corresponding adjacent isolation region 26. For example, the interface between the stressed semiconductor layer 22 and the semiconductor substrate 20 corresponding to each fin 24 may be below the top surface of the isolation region 26.

[0055] Those with ordinary knowledge in the art will readily understand that Figures 1 to 3A , Figure 3BThe process described is merely an example of how to form the fin 24. In other embodiments, a dielectric layer may be formed over the top surface of the semiconductor substrate 20, trenches may be etched through the dielectric layer, a homoepitaxial structure may be epitaxially grown in the trenches (e.g., without stress engineering), and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. In other embodiments, a heteroepitaxial structure may be used for the fin. For example, the fin 24 may be recessed (e.g., after planarizing the insulating material of the isolation region 26 and before recessing the insulating material), and a material different from the fin may be epitaxially grown in the location of the fin. In another embodiment, a dielectric layer may be formed over the top surface of the semiconductor substrate 20, trenches may be etched through the dielectric layer, a heteroepitaxial structure may be epitaxially grown in the trenches using a material different from the semiconductor substrate 20 (e.g., with stress engineering), and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin. In some embodiments of epitaxially grown homoepitaxial or heteroepitaxial structures, the grown material may be doped in situ during growth, which may obviate prior implantation of fins, although in situ and implanted doping may be used together. Furthermore, it may be advantageous to epitaxially grow n-type devices of different material than p-type devices.

[0056] Figure 4A , Figure 4B , Figure 4C and Figure 4D A dummy gate stack is shown formed on the fin 24 . Figure 4A and Figure 4B Display cross-sectional schematics; Figure 4C Display the top view; Figure 4D Displays a perspective view. Figure 4D Display section AA and section BB. Figure 1 , Figure 2 , Figure 3A , Figure 4A The subsequent figures ending with A show cross-sectional schematic diagrams corresponding to the cross-sectional view AA in various examples of the process. Figure 4B The subsequent figures ending with B show cross-sectional schematic diagrams corresponding to the cross section BB in various examples of the process. In some figures, the reference symbols of some components or parts may be omitted, which can avoid confusing other components or parts and facilitate the description of the figures.

[0057] The dummy gate stacks are above the fins 24 and extend laterally perpendicular to the fins 24. Each dummy gate stack (or gate structure in general) includes one or more interfacial dielectrics 28, a dummy gate 30, and a mask 32. The interfacial dielectrics 28, dummy gates 30, and masks 32 for the dummy gate stacks may be formed by sequentially forming corresponding layers and then patterning the layers into the dummy gate stacks. For example, the layer for the one or more interfacial dielectrics 28 may include or be silicon oxide, silicon nitride, the like, or multiple layers of the foregoing, and may be thermally and / or chemically grown (as shown) or conformally deposited on the fins 24, for example, by plasma assisted chemical vapor deposition (PECVD), atomic layer deposition, or other deposition techniques. The layer for the dummy gate 30 may include or be silicon (e.g., polysilicon) or other material deposited by chemical vapor deposition, physical vapor deposition, or other deposition techniques. The layer for the mask 32 may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, the like, or a combination thereof, deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other deposition techniques. The mask 32, the dummy gate 30, and the one or more interface dielectrics 28 are then patterned, for example, using the above-described photolithography and one or more etching processes to form the mask 32, the dummy gate 30, and the one or more interface dielectrics 28 for each dummy gate stack.

[0058] In some embodiments, after forming the dummy gate stack, a lightly doped drain (LDD) region (not specifically shown) may be formed in the fin 24. For example, the dummy gate stack may be used as a mask to implant dopants into the fin 24. Example dopants for the lightly doped drain region may include or be, for example, boron for p-type devices and phosphorus or arsenic for n-type devices, although other dopants may be used. The lightly doped drain region may have a dopant concentration of about 10 15 cm -3 to about 10 17 cm -3 in the range.

[0059] Section AA extends along the gate stack, and subsequent figures and descriptions will be sections through section AA. Section BB extends along the fin 24 (eg, along the channel direction in the fin 24), and subsequent figures and descriptions will be sections through section BB. Sections AA and BB are perpendicular to each other.

[0060] Figure 5A , Figure 5B and Figure 5CThe formation of gate spacers 34 is shown. Gate spacers 34 are formed along the sidewalls of the dummy gate stack (e.g., the sidewalls of one or more interfacial dielectrics 28, dummy gates 30, and mask 32) and over the fins 24. In addition, the remaining gate spacers 34 may be formed along the exposed sidewalls of the fins 24, as shown. For example, gate spacers 34 may be formed by conformally depositing one or more layers of gate spacers 34 and anisotropically etching the one or more layers. The one or more layers for gate spacers 34 may include or be silicon nitride, silicon carbon nitride, silicon oxycarbide, the like, multiple layers of the foregoing, or combinations thereof, and the etching process may include reactive ion etching, neutron beam etching, or other etching processes.

[0061] Next, epitaxial source / drain regions 36 are formed in the fins 24. Recesses for the epitaxial source / drain regions 36 are formed in the fins 24 on both sides of the dummy gate stack. The recesses may be formed by an etching process. The etching process may be isotropic or anisotropic, or selective to one or more crystal planes of the stressed semiconductor layer 22 and / or the semiconductor substrate 20. Thus, the recesses may have various cross-sectional profiles depending on the etching process performed. The etching process may be a dry etching process (e.g., reactive ion etching, neutron beam etching, or the like) or a wet etching process (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or other etchants). The recesses may extend from the corresponding top surfaces of the fins 24 into the fins 24 to a depth in the range of about 0 nm to about 80 nm. For example, in some examples, the recess may not extend below the level of the top surface of the adjacent isolation region 26 and / or below the interface between the stressed semiconductor layer 22 and the semiconductor substrate 20, but in other examples, the recess may extend below the level of the top surface of the adjacent isolation region 26 and / or below the interface.

[0062] Epitaxial source / drain regions 36 are formed in the recesses in the fins 24. The epitaxial source / drain regions 36 may include or be silicon germanium (Si 1-x Ge x, where x may be between about 0 and 1), silicon carbide, silicon phosphorus, silicon carbon phosphorus, pure or substantially pure germanium, Group III-V semiconductor compounds, Group II-VI semiconductor compounds, or the like. For example, materials used to form Group III-V semiconductor compounds include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. The epitaxial source / drain regions 36 may be formed by epitaxially growing a material in the recess, for example, by metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, the like, or a combination of the foregoing. Depending on the depth of the recess in which the epitaxial source / drain regions 36 are formed, the epitaxial source / drain regions 36 may first grow vertically in the recess due to the blocking of the isolation regions 26 and / or the remaining gate spacers 34, during which the epitaxial source / drain regions 36 do not grow horizontally. After completely filling the isolation regions 26 and / or the recesses in the remaining gate spacers 34, the epitaxial source / drain regions 36 may grow vertically and horizontally to form facets that may correspond to the crystal planes of the semiconductor substrate 20. The epitaxial source / drain regions 36 may be elevated relative to the fins 24, such as Figure 5B . In some examples, different materials are used for the epitaxial source / drain regions of p-type devices and n-type devices. Recessing or appropriate masking during epitaxial growth can allow different materials to be used in different devices. In this article, source region and drain region are used interchangeably, and the structure of source region and drain region is generally the same. Furthermore, depending on the context, source / drain region can represent source or drain alone or collectively.

[0063] Fig. 6A , Figure 6B and Figure 6CThe formation of a contact etch stop layer (CESL) 38 and an interlayer dielectric (ILD) 40 is shown. The CESL 38 may be conformally deposited over the fins 24, the dummy gate stack, the gate spacers 34, and the isolation regions 26. The CESL 38 may include or be silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition, plasma assisted chemical vapor deposition, atomic layer deposition, or other deposition techniques. The interlayer dielectric 40 is deposited over the CESL 38. The interlayer dielectric 40 may include or be silicon dioxide, a low dielectric constant dielectric material (e.g., a material having a lower dielectric constant than silicon dioxide), such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), SiO x C y , spin-on glass, spin-on polymer, silicon carbon material, a compound thereof, a composite layer thereof, the like, or a combination thereof. The interlayer dielectric 40 may be deposited by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, or other deposition techniques.

[0064] The contact etch stop layer 38 and the interlayer dielectric 40 are formed to have a top surface coplanar with the top surface of the dummy gate 30. A planarization process (e.g., chemical mechanical polishing) may be performed to make the top surfaces of the contact etch stop layer 38 and the interlayer dielectric 40 flush with the top surface of the dummy gate 30. The chemical mechanical polishing may also remove the mask 32 on the dummy gate 30 (and in some examples, also remove the upper portion of the gate spacer 34). Therefore, the top surface of the dummy gate 30 is exposed through the contact etch stop layer 38 and the interlayer dielectric 40.

[0065] Fig. 7A , Figure 7B and Figure 7CThe removal of the dummy gate stack is shown. The dummy gate 30 and one or more interface dielectrics 28 are removed, for example, by one or more etching processes. The dummy gate 30 can be removed by an etching process that is selective to the dummy gate 30, wherein the one or more interface dielectrics 28 are used as an etch stop layer, and then the one or more interface dielectrics 28 can be removed by a different etching process that is selective to the one or more interface dielectrics 28. The etching process can be, for example, reactive ion etching, neutron beam etching, a wet etching process, or other etching process. Recesses 42 are formed between the gate spacers 34 (where the dummy gate stack is removed), and the channel region of the fin 24 is exposed through the recesses 42. In some embodiments, the interface dielectric 28 is not removed.

[0066] Fig. 8A , Figure 8B and Figure 8C Replacement gate structures are shown formed in recesses 42. The replacement gate structures each include a gate dielectric layer 44, one or more selective compliant layers 46, and a gate electrode 48.

[0067] The gate dielectric layer 44 is conformally deposited in the recess 42 (e.g., on the top surface of the isolation region 26, on the sidewalls and top surface of the fin 24 along the channel region (or the sidewalls of the interfacial dielectric 28 and the gate spacer 34 if not removed) and the top surface of the gate spacer 34, the contact etch stop layer 38, and the top surface of the interlayer dielectric 40. The gate dielectric layer 44 can be or include silicon oxide, silicon nitride, a high-k dielectric material, multiple layers of the foregoing, or other dielectric materials. The high-k dielectric material can have a dielectric constant value greater than about 7.0 and can include metal oxides or metal silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), multiple layers of the foregoing, or combinations of the foregoing. The gate dielectric layer 44 can be deposited by atomic layer deposition, plasma-assisted chemical vapor deposition, molecular beam epitaxy, or other deposition techniques.

[0068] Next, one or more selective compliant layers 46 may be conformally (and if more than one, sequentially) deposited on the gate dielectric layer 44. The one or more selective compliant layers 46 may include one or more work function adjusting layers. The one or more work function adjusting layers may include or be titanium and / or tantalum nitrides, silicon nitride, carbon nitride, aluminum nitride, aluminum oxide and / or aluminum carbide, tungsten carbide, cobalt, platinum, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma assisted chemical vapor deposition, molecular beam epitaxy, or other deposition techniques.

[0069] A layer for gate electrode 48 is formed over gate dielectric layer 44 and one or more selective compliant layers 46, if used. The layer for gate electrode 48 may fill the remaining recess 42 formed by removing the dummy gate stack. The layer for gate electrode 48 may be or include a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multiple layers of the foregoing, combinations of the foregoing, or the like. The layer for gate electrode 48 may be deposited by atomic layer deposition, plasma assisted chemical vapor deposition, molecular beam epitaxy, physical vapor deposition, or other deposition techniques.

[0070] The layer for gate electrode 48, one or more selective compliant layers 46, and portions of gate dielectric layer 44 above the top surfaces of interlayer dielectric 40, contact etch stop layer 38, and gate spacers 34 are removed. For example, a planarization process (e.g., chemical mechanical polishing) may remove portions of the layer for gate electrode 48, one or more selective compliant layers 46, and portions of gate dielectric layer 44 above the top surfaces of interlayer dielectric 40, contact etch stop layer 38, and gate spacers 34. Each replacement gate structure including gate electrode 48, one or more selective compliant layers 46, and gate dielectric layer 44 may then be formed, such as FIG. 8A to FIG. 8C shown.

[0071] Fig. 9 A pulse scheme for a process of etching gate electrode 48 is shown according to some embodiments, and Figure 10 to Figure 12 According to some embodiments, corresponding Figure 4D Schematic diagram of the cross section AA in each processing example. Fig.10 In the embodiment, mask structure 52 is formed on gate electrode 48. Mask structure 52 may also be formed on interlayer dielectric 40. Mask structure 52 includes one or more layers (layers 54, 56, 58). In some embodiments, layer 54 includes SiN, layer 56 includes amorphous silicon, and layer 58 includes SiN. Mask structure 52 may include more or fewer layers. Mask structure 52 is patterned to have one or more openings 60 to expose a portion of gate electrode 48. In some embodiments, as shown in FIG. Fig.10 As shown, a hard mask layer 59 (eg, a SiN layer) is conformally formed on the exposed surface of the gate electrode 48 and the sidewalls of the mask structure 52 exposed in the opening 60 .

[0072] An etching process is performed to remove the gate electrode 48 in the opening 60. The hard mask layer 59 and a portion of the mask structure 52 may also be removed by the etching process. Fig.11As shown, the etching process extends the opening 60 to the bottom of the remaining gate electrode 48 or slightly below the bottom of the remaining gate electrode 48. The profile of the middle portion 60m of the opening 60 may affect subsequent processes. For example, if the middle portion 60m has a bowling ball profile, large voids may exist in the refill material subsequently formed in the opening 60. The presence of large voids in the refill material may cause some portions of the refill material to be as thin as weak points. These weak points not only lead to poor isolation between metal gates, but may also be broken down, resulting in the loss of metal gates in the subsequent continuous oxide definition edge cut metal (cut-metal on oxide definition edge, CMODE) process. Poor isolation and loss of metal gates may reduce device performance and result in low yield.

[0073] According to some embodiments, a main etching step and a breakthrough (BT) etching step are provided to etch the gate electrode with a desired profile that minimizes the size of voids (if any) in the dielectric layer that refills the opening. The main etching step can be performed using a mixture of etching gases including SiCl4, BCl3, N2, Cl2 and He, with a processing pressure of about 20mTorr. The processing pressure can be adjusted to a value in the range of about -20mTorr to about 20mTorr. A plasma source (e.g., transformer coupled plasma (TCP)) can be used to generate ions from the gas mixture. The power of the transformer coupled plasma can be controlled in the range of about 1500W to about 2500W. In some embodiments, the power of the transformer coupled plasma can be controlled at about 2000W. A bias power supply is also applied to pull the ions toward the gate electrode 48. It has been observed that the etching angle relative to the vertical line depends on the frequency of the bias power supply. That is, by selecting a suitable frequency, the ratio of lateral etching to vertical etching can be controlled so that a predetermined profile extending through the middle portion 60m of the gate electrode 48 can be obtained. According to some embodiments, a bias power supply with a frequency of about 1 MHz is applied to control the lateral etching on the gate electrode 48, such as Fig.11 As indicated by the horizontal arrow.

[0074] Fig. 9A pulse scheme of transformer coupled plasma power and bias power for the main etching step of etching gate electrode 48 is shown according to some embodiments. The transformer coupled plasma power has an 80% duty cycle (DC) at a power level of about 2000 W. That is, the transformer coupled plasma power is controlled at a power level of about 2000 W for 80% of each cycle and is off (0 W) for the remaining time (i.e., 20% of each cycle). According to some embodiments, the power level can be adjusted to a value in the range of about +500 W to about -500 W. The bias power also has an 80% duty cycle. That is, the bias power is on for 80% of each cycle and off for 20% of each cycle. However, the voltage level of the bias power is controlled at about 200 V for the first 30% of each cycle, and the voltage level of the bias power is reduced to about 50 V for the next 50% of each cycle. Each voltage level can be adjusted to a voltage value in the range of about +50 V to about -50 V. In some embodiments, the voltage for the next 50% of each cycle is in the range of about 5V to about 100V. The 30% duty cycle can be adjusted in percentages in the range of about +30% to about -30%, and the 50% duty cycle can be adjusted in percentages in the range of about +40% to about -40%. The off period can also be adjusted in percentages in the range of about +20% to about -20%. The parameters of the plasma etching process for etching the gate electrode 48 are listed in Table 1 below.

[0075]

[0076] Table 1

[0077] Fig. 9 The main etching steps with pulse schemes shown and the etching conditions shown in Table 1 provide control of the lateral etching, such as Fig.11 The etched gate electrode 48 has a tapered profile with a cross-section that gradually decreases from the top to the bottom.

[0078] exist Fig.12 In the embodiment of the present invention, the opening 60 is further extended by etching through the isolation region 26 and the top of the semiconductor substrate 20. The bottom 60b extending through the isolation region 26 and the top of the semiconductor substrate 20 can be formed by an etching process using a gas mixture of C4F6, O2 and N2 at a pressure of about 20mTorr±20mTorr. The power of the power supply can be controlled at a power level of about 100W, and a 1000V bias power supply with a frequency of about 13.5MHz can also be applied.

[0079] exist Fig.12, the sidewall 61 of the mask structure 52 exposed at the top 60t of the opening 60 may have a substantially straight portion 61a and an inclined portion 61b. In some embodiments, the side surface of the layer 54 exposed at the top 60t of the opening 60 forms an angle A with the bottom surface of the layer 54 disposed on the gate electrode 48, and the angle A is in the range of about 80 degrees to about 90 degrees. In some embodiments, the side surface of the layer 58 exposed at the top 60t of the opening 60 forms an angle B with the top surface of the layer 58, and the angle B is in the range of about 100 degrees to about 120 degrees. Sharp corners may be formed where the substantially straight portion 61a and the inclined portion 61b intersect. Sharp corners may hinder the flow of the material that subsequently refills the opening 60. In addition, the sharp corners may cause the refill material to merge at the top 60t before the middle portion 60m and the bottom 60b are completely filled. Similar to the bowling ball profile of the middle portion 60m, the sharp corners may cause large voids to form or further expand in the refill material. Therefore, according to some embodiments, an additional etching step is performed after the opening 60 has been extended into the substrate 20. The additional etching step may be referred to as a final breakdown (BT) etching step for fine-tuning the profile of the opening 60.

[0080] Fig.13 A pulse scheme for performing a final breakdown etch step according to some embodiments is shown, and Figure 14 to Figure 17 According to some embodiments, corresponding Figure 4D Schematic diagram of the cross section AA in each processing example. The final breakdown etching step may be a plasma etching process with a power level of about 100W with the power source always turned on. That is, the power source has a 100% duty cycle at a power level of about 100W. The power level can be adjusted to a value in the range of about +100W to about -100W. In some embodiments, the power level is in the range of about 10W to about 200W. According to some embodiments, the bias power source has a frequency of about 13.5MHz and has a 50% duty cycle at a power level of about 500V. That is, the bias power source is turned on to a voltage level of about 500V for 50% of each cycle and is turned off for 50% of each cycle. The power level can be adjusted to a value in the range of about +300V to about -300V. In some embodiments, the power level is in the range from about 200V to about 800V. The etching gas may include a gas mixture of C4F6, O2 and Ar. The applied pressure may be about 20 mTorr ± 20 mTorr. The etching parameters may be controlled according to Table 2 below.

[0081] As shown in Table 2, the transformer coupled plasma power is controlled at a power level of about 100 W, and the frequency of the bias power supply is about 13.5 MHz. It is expected that the ions can stay at the top 60t of the opening 60 and etch the sidewalls of the mask structure 52 in a substantially vertical direction, such as Fig.14. The parameters shown in Table 2 allow the ions generated by the transformer coupled plasma power to be located at the top 60t to widen and smooth the sidewalls of the mask structure 52 in the top 60t of the opening 60 without further etching the gate electrode 48 and the isolation region 26 laterally. Therefore, the sharp corners of the sidewall 61 can be removed, and a substantially linear inclined sidewall 61 of the mask structure 52 exposed to the top 60t is formed. The substantially linear sidewall 61 provides an overall funnel profile of the opening 60. In some embodiments, the angle A is substantially reduced by the final breakdown etching step, and the angle B is substantially expanded by the final breakdown etching step. In some embodiments, the angle A after the final breakdown etching step is in the range of about 30 degrees to about 60 degrees, and the angle B after the final breakdown etching step is in the range of about 140 degrees to about 170 degrees. The final breakdown etching step changes the profile of the mask structure 52 without substantially affecting the gate electrode 48. After the bottom 60b of the opening 60 is formed, the final breakdown etching step is performed to protect the gate electrode 48. If a final breakdown etching step is performed before the etching process used to form the bottom 60b of the opening 60, the etching process used to form the bottom 60b of the opening 60 may remove a portion of the mask structure 52, causing the mask structure 52 to become thinner due to the final breakdown etching step and damaging the gate electrode 48 and / or unnecessarily expanding the critical dimension of the opening 60 in the gate electrode 48.

[0082]

[0083] Table 2

[0084] like Fig.15 As shown, the combination of the main etching step and the final breakdown etching step for removing the gate electrode 48 forms a funnel profile of the opening 60. The top critical dimension (TCD) a at the top of the metal gate (i.e., the patterned gate electrode 48) is greater than the middle critical dimension (MCD) b at the top level of the fin 24. In some embodiments, the difference between the top critical dimension a and the middle critical dimension b (i.e., ab) is calculated by using Fig. 9 The main etching process with the pulse scheme and etching conditions listed in Table 1 can be improved from the range of -4nm to -1nm to the range of -1nm to 1nm. In combination with the final breakdown etching step, the difference can be further improved to the range of 1nm to 4nm.

[0085] like Fig.16As shown, dielectric material 64 is formed in opening 60. Dielectric material 64 may be any suitable material, such as SiN. The gap filling capability of dielectric material 64 is poor in high aspect ratio opening 60, and voids 66 may be formed in dielectric material 64. In some embodiments, voids 66 have a size greater than about 1 nm. As described above, the funnel profile of opening 60 formed by the main etching step and the final breakdown etching step of gate electrode 48 improves the refilling of dielectric material 64, thereby minimizing the size of voids 66. For example, according to some embodiments, the width of voids 66 can be reduced to less than 1 nm.

[0086] Fig.17 The device is shown after performing the metallization process on the oxide defined edge. With the size of the gap 66 minimized, the dielectric material 64 has sufficient thickness to provide good isolation between the metal gates. There are no weak points to be broken through by the metallization process on the oxide defined edge. Thus, loss of metal gates is prevented. Therefore, higher yield and improved device performance can be expected.

[0087] Embodiments of the present invention provide for forming an opening 60 in a mask structure 52 and a gate electrode 48. In some embodiments, the method includes a main etching step and a final breakdown etching step. Some embodiments can achieve some advantages. For example, the process conditions of the main etching step prevent the opening 60 in the gate electrode 48 from forming a bowling ball profile, while the final breakdown etching step enlarges the portion of the opening 60 in the mask structure 52. Therefore, the dielectric material 64 formed in the opening 60 includes a void 66 with a reduced size.

[0088] One embodiment of the present invention is a method, the method comprising forming a gate electrode; forming a mask structure above the gate electrode; patterning the mask structure to form an opening; and performing a first etching process on the gate electrode by applying a first power source having a first pulse scheme and a first bias power source. The first bias power source has a first frequency to control etching in a lateral direction. The method further comprises performing a second etching process on the mask structure exposed in the opening by applying a second power source having a second pulse scheme and a second bias power source, and the second bias power source has a second frequency to control etching in a vertical direction, and the first frequency and the second frequency are substantially different.

[0089] In some other embodiments, the first pulse scheme includes an 80% duty cycle for both the first supply power and the first bias power.

[0090] In some other embodiments, the first pulse scheme includes: controlling the power level of the first power supply to be approximately 2000W in an 80% duty cycle; controlling the voltage level of the first bias power supply to be approximately 200V in the first 30% of the 80% duty cycle; and controlling the voltage level of the first bias power supply to be approximately 50V in the last 50% of the 80% duty cycle.

[0091] In some other embodiments, the second pulse scheme includes a 100% duty cycle of the second power supply and a 50% duty cycle of the second bias power supply.

[0092] In some other embodiments, the second pulse scheme includes controlling the second power supply to have a power level of about 100 W in a 100% duty cycle; and controlling the second bias power supply to have a voltage level of about 500 V in a 50% duty cycle.

[0093] In some other embodiments, the first frequency is about 1 MHz and the second frequency is about 13.5 MHz.

[0094] In some other embodiments, the method further includes performing a third etching process before performing the second etching process to extend the opening through the isolation region under the gate electrode and a portion of the substrate under the isolation region.

[0095] In some other embodiments, the method further comprises forming a compliant hard mask layer after patterning the mask structure.

[0096] In some other embodiments, the method further includes controlling the second power supply at a power level and the second bias power supply at a voltage level such that the second etching process provides a fine-tuning effect on the sidewall of the mask structure.

[0097] Another embodiment of the present invention is a method, which includes performing a first etching process on a gate electrode, the first etching process including a plasma etching process, the plasma etching process having: a first power supply having an 80% duty cycle at a power level in a range of about 1500 W to about 2500 W; and a first bias power supply having a 30% duty cycle at a voltage level in a range of about 150 V to about 250 V and a 50% duty cycle after the 30% duty cycle at a voltage level in a range of about 5 V to about 100 V. The method further includes performing a second etching process on a mask structure disposed on the gate electrode, the second etching process including a plasma etching process, the plasma etching process having: a second power supply having a 100% duty cycle at a power level in a range of about 10 W to about 200 W; and a second bias power supply having a 50% duty cycle at a voltage level in a range of about 200 V to about 800 V.

[0098] In some other embodiments, the first bias power source has a first frequency to control lateral etching of the gate electrode, and the second bias power source has a second frequency to control vertical etching of the mask structure.

[0099] In some other embodiments, the first frequency is 1 MHz and the second frequency is 13.5 MHz.

[0100] In some other embodiments, the second etching process is performed after the first etching process.

[0101] Another embodiment of the present invention is a method, which includes forming a plurality of fins from a semiconductor substrate; forming an isolation region surrounding each of the plurality of fins; depositing a gate electrode above the plurality of fins; forming a mask structure above the gate electrode; forming an opening in the mask structure; extending the opening through the gate electrode by a first plasma etching process having a first bias power supply with a frequency to control lateral etching of the gate electrode; extending the opening through the isolation region; etching the sidewalls of the mask structure in the opening by a second plasma etching process having a second bias power supply with a frequency to control vertical etching of the mask structure and remove sharp corners in the sidewalls of the mask structure exposed to the opening; and filling the opening with a dielectric layer.

[0102] In some other embodiments, the step of forming the mask structure includes: forming a first layer; forming a second layer on the first layer; and forming a third layer on the second layer.

[0103] In some other embodiments, the side surface of the first layer exposed to the opening forms a first angle with the bottom surface of the first layer, and the side surface of the third layer exposed to the opening forms a second angle with the top surface of the third layer.

[0104] In some other embodiments, the first angle is in a range of about 80 degrees to about 90 degrees, and the second angle is in a range of about 100 degrees to about 120 degrees.

[0105] In some other embodiments, the first angle decreases after the second plasma etching process.

[0106] In some other embodiments, the second angle increases after the second plasma etching process.

[0107] In some other embodiments, the first angle is in a range of about 30 degrees to about 60 degrees after the second plasma etching process, and the second angle is in a range of about 140 degrees to about 170 degrees after the second plasma etching process.

[0108] The foregoing text summarizes the features of many embodiments, so that those with ordinary knowledge in the art can better understand the embodiments of the present invention from various aspects. Those with ordinary knowledge in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the embodiments of the present invention. Various changes, substitutions or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the invention of the embodiments of the present invention.

Claims

1. A method for forming a semiconductor device structure, comprising: forming a gate electrode; forming a mask structure above the gate electrode; patterning the mask structure to form an opening; Performing a first etching process on the gate electrode by applying a first power source having a first pulse scheme and a first bias power source, wherein the first bias power source has a first frequency to control etching in a lateral direction; as well as A second etching process is performed on the mask structure exposed in the opening by applying a second power supply having a second pulse scheme and a second bias power supply, wherein the second bias power supply has a second frequency to control etching along a vertical direction, wherein the first frequency and the second frequency are substantially different.

2. The method for forming a semiconductor device structure as claimed in claim 1, wherein the first pulse scheme comprises an 80% duty cycle for both the first power supply and the first bias power supply.

3. The method for forming a semiconductor device structure according to claim 1, further comprising: Before performing the second etching process, a third etching process is performed to extend the opening through an isolation region under the gate electrode and a portion of a substrate under the isolation region.

4. The method for forming a semiconductor device structure according to claim 1, further comprising: The second power source is controlled at a power level and the second bias power source is controlled at a voltage level so that the second etching process provides a fine-tuning effect on the sidewall of the mask structure.

5. A method for forming a semiconductor device structure, comprising: A first etching process is performed on a gate electrode, wherein the first etching process comprises a plasma etching process, and the plasma etching process has: a first power source having an 80% duty cycle at a power level in a range of about 1500 W to about 2500 W; and a first bias power supply having a 30% duty cycle at a voltage level in the range of about 150V to about 250V and a 50% duty cycle after the 30% duty cycle at a voltage level in the range of about 5V to about 100V; and A second etching process is performed on a mask structure disposed on the gate electrode, wherein the second etching process comprises a plasma etching process, and the plasma etching process has: a second power source having a 100% duty cycle at power levels in the range of about 10 W to about 200 W; and A second bias power supply has a 50% duty cycle at a voltage level in the range of about 200V to about 800V.

6. A method for forming a semiconductor device structure, comprising: forming a plurality of fins from a semiconductor substrate; forming an isolation region around each of the plurality of fins; depositing a gate electrode over the plurality of fins; forming a mask structure above the gate electrode; forming an opening in the mask structure; Extending the opening through the gate electrode by a first plasma etching process with a first bias power supply having a frequency to control a lateral etching of the gate electrode; extending the opening through the isolation region; Etching a side wall of the mask structure in the opening by a second plasma etching process with a second bias power supply having a frequency to control a vertical etching of the mask structure and remove a sharp corner of the side wall of the mask structure exposed to the opening; as well as The opening is filled with a dielectric layer.

7. The method for forming a semiconductor device structure as claimed in claim 6, wherein the step of forming the mask structure comprises: forming a first layer; forming a second layer on the first layer; as well as A third layer is formed on the second layer.

8. The method for forming a semiconductor device structure as described in claim 7, wherein the side surface of the first layer exposed to the opening forms a first angle with the bottom surface of the first layer, and the side surface of the third layer exposed to the opening forms a second angle with the top surface of the third layer. 9 . The method for forming a semiconductor device structure as claimed in claim 8 , wherein after the second plasma etching process, the first angle is reduced. 10 . The method for forming a semiconductor device structure as claimed in claim 9 , wherein after the second plasma etching process, the second angle increases.

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