Method for improving warping of silicon carbide wafer in N2 atmosphere and semiconductor device

Abstract

The invention provides a method for improving warping of a silicon carbide wafer in N2 atmosphere and a semiconductor device, the method for improving warping of the silicon carbide wafer comprises the following steps: providing a silicon carbide substrate, one side of the silicon carbide substrate comprising at least one ion implantation area; depositing a silicon dioxide layer on the surface of at least one ion implantation region of the silicon carbide substrate; and annealing the silicon carbide substrate by adopting an annealing process, wherein the reaction gas of the annealing process is nitrogen. According to the method for improving the warping of the silicon carbide wafer in the N2 atmosphere, the silicon dioxide layer is deposited on the surface of the silicon carbide substrate after ion implantation, and annealing heat treatment is carried out in pure nitrogen under the protection of the surface silicon dioxide layer, so that the surface nitridation of the substrate is avoided, and meanwhile, the lattice damage defect of the silicon carbide substrate caused by ion implantation is eliminated; the warping degree of the silicon carbide substrate in heat treatment is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to a method for improving warping of a silicon carbide wafer in a N2 atmosphere and a semiconductor device. Background Art

[0002] With the development of semiconductor technology, the characteristic size of semiconductor devices is getting smaller and smaller. Especially after the semiconductor process enters the deep submicron stage, in order to achieve highly integrated and high-performance devices, different types of substrates are used in the device manufacturing process.

[0003] Compared with silicon, silicon carbide (SiC) has a wider bandgap, higher thermal conductivity, and extremely low intrinsic carriers under isothermal conditions, making it suitable for working under higher voltage, high current and high temperature conditions. Taking into account various excellent properties, silicon carbide substrates have great value and great potential in various fields. Silicon carbide substrates have many excellent properties. Silicon carbide wafers of different sizes can be processed into various circuit element structures of different numbers. However, due to the relatively thin thickness of silicon carbide wafers (usually 150μ~350μm), some high-temperature processes in the existing silicon carbide MOSFET device processing, such as high-temperature ion implantation, will cause silicon carbide wafers to deform easily, and the warpage of the wafer will increase. Wafer warpage will cause trouble for many semiconductor processes, thereby affecting the stability of the performance of the semiconductor devices prepared subsequently and the product yield. Therefore, how to reduce the warpage caused by high-temperature ion implantation is a technical problem that needs to be solved in the field of silicon carbide device processing.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a method for improving the warping of silicon carbide wafers under N2 atmosphere and a semiconductor device. The ion implantation method can effectively reduce the degree of warping of the silicon carbide substrate during the ion implantation activation process.

[0006] Specifically, the first aspect of the present invention provides a method for improving the warpage of a silicon carbide wafer under a N2 atmosphere, the method for improving the warpage of a silicon carbide wafer comprising the following steps:

[0007] Providing a silicon carbide substrate, wherein one side of the silicon carbide substrate includes at least one ion implantation region;

[0008] Depositing a silicon dioxide layer on a surface of at least one ion implantation region of the silicon carbide substrate;

[0009] The silicon carbide substrate is annealed by an annealing process, and the reaction gas of the annealing process is nitrogen.

[0010] According to a first aspect of the present invention, the silicon dioxide layer is deposited using low pressure tetraethylorthosilicate.

[0011] According to the first aspect of the present invention, the thickness of the silicon dioxide layer is

[0012] According to the first aspect of the present invention, the flow rate of the reaction gas in the annealing process is 8 L / min to 12 L / min.

[0013] According to the first aspect of the present invention, the annealing temperature of the annealing process is 1000°C to 1200°C.

[0014] According to the first aspect of the present invention, the annealing time of the annealing process is 1.5 to 2.0 hours.

[0015] According to the first aspect of the present invention, the annealing process is performed under normal pressure.

[0016] According to the first aspect of the present invention, the temperature of the ion implantation is greater than or equal to 500°C.

[0017] According to the first aspect of the present invention, the ion implantation method further comprises the following steps:

[0018] The silicon dioxide layer is removed.

[0019] A second aspect of the present invention provides a semiconductor device, comprising a silicon carbide substrate and an ion implantation region located on the silicon carbide substrate, wherein the ion implantation region is prepared by using the method for improving the warpage of a silicon carbide wafer under a N2 atmosphere.

[0020] Compared with the prior art, the method for improving the warpage of silicon carbide wafers under N2 atmosphere of the present invention deposits a silicon dioxide layer on the surface of the silicon carbide substrate after ion implantation, and performs annealing heat treatment in pure nitrogen under the protection of the surface silicon dioxide layer, thereby avoiding nitridation of the substrate surface and eliminating lattice damage defects of the silicon carbide substrate caused by ion implantation, thereby effectively reducing the degree of warpage of the silicon carbide substrate during heat treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0022] Figure 1 A flow chart of a method for improving warpage of a silicon carbide wafer in a N2 atmosphere according to an embodiment of the present invention; and

[0023] Figure 2 1 and 2 are warpage repair value curves respectively showing a conventional silicon carbide wafer warpage repair method and a method for improving silicon carbide wafer warpage in a N2 atmosphere according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0025] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0026] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0027] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0028] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0029] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0030] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0031] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0032] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0033] In order to overcome the technical problem of warpage caused by the existing high-temperature ion implantation process, the present invention provides a method for improving the warpage of silicon carbide wafers under N2 atmosphere and a semiconductor device, the method for improving the warpage of silicon carbide wafers comprises the following steps: providing a silicon carbide substrate, one side of the silicon carbide substrate includes at least one ion implantation region; depositing a silicon dioxide layer on the surface of at least one ion implantation region of the silicon carbide substrate; annealing the silicon carbide substrate by an annealing process, wherein the reaction gas of the annealing process is nitrogen. The method for improving the warpage of silicon carbide wafers under N2 atmosphere of the present invention deposits a silicon dioxide layer on the surface of the silicon carbide substrate after ion implantation, and performs annealing heat treatment in pure nitrogen under the protection of the surface silicon dioxide layer, thereby avoiding nitridation of the substrate surface and eliminating the lattice damage defects of the silicon carbide substrate caused by ion implantation, and effectively reducing the degree of warpage of the silicon carbide substrate during heat treatment.

[0034] The following further describes a method for improving warpage of a silicon carbide wafer under a N2 atmosphere and a semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. It can be understood that the various specific embodiments are not intended to limit the scope of protection of the present invention.

[0035] Figure 1 The present invention is a flowchart of a method for improving the warpage of a silicon carbide wafer in a N2 atmosphere according to an embodiment of the present invention. Specifically, the method for improving the warpage of a silicon carbide wafer comprises the following steps:

[0036] Step S100: providing a silicon carbide substrate, wherein one side of the silicon carbide substrate includes at least one ion implantation region; in a specific embodiment, step S100 may include the following steps:

[0037] Step S10: depositing a hard mask layer on the surface of the silicon carbide substrate; the silicon carbide substrate may be a single crystal silicon carbide substrate, or a silicon carbide substrate with an epitaxial layer, such as an n-type 4H-SiC substrate with an n-type epitaxial growth layer. The hard mask layer may be a single layer or a multilayer, such as a hard mask layer may include a silicon dioxide layer and a silicon nitride layer, or include a silicon dioxide layer and a titanium nitride layer.

[0038] Step S11: patterning the hard mask layer; the most commonly used method for this step is to coat a photoresist layer on the surface of the hard mask layer and expose and develop the photoresist layer to obtain a patterned photoresist layer, and use the patterned photoresist layer as a mask to etch the hard mask layer using an etching process. The etching process can be a dry etching process, such as reactive ion etching (RIE) process or plasma etching (PE) process, that is, the hard mask layer is patterned (Pattern Formation) to define the area where ion implantation is required, and the photoresist layer is removed to obtain the patterned hard mask layer.

[0039] Step S12: Using the hard mask layer as an implantation mask, ion implantation is performed to form an ion implantation area. Ion implantation of silicon carbide substrates is used to introduce specific impurity atoms into silicon carbide materials, thereby forming different conductivity types in the ion implantation area. Ion implantation usually uses a high-energy ion beam to implant the required dopants into the silicon carbide substrate. In the doping process of silicon carbide power devices, commonly used N-type doping elements are nitrogen and phosphorus, and P-type doping elements are aluminum and boron. In step S12, the type of implanted ions, the concentration and depth of the implanted ions, etc. can be determined according to the type of silicon carbide device to be obtained and the performance to be achieved. At the same time, the acceleration voltage of the ion beam is adjusted according to the concentration and depth of the implanted ions to be achieved, that is, the concentration and depth of the ion implantation can be accurately controlled by controlling the parameters of the ion implantation process. Unlike the ion implantation process of silicon substrates, the temperature of ion implantation of silicon carbide substrates is generally high temperature. Usually, the temperature of ion implantation is greater than or equal to 500°C.

[0040] The ion implantation process in step S12 is to ionize and accelerate the doped ions in an electric field to form an ion beam of single energy. After focusing the ion beam, it is injected into the substrate. When the ion beam passes through the surface of the substrate, the ions will be decelerated and stop in the substrate. The kinetic energy of the colliding ions is consumed in the substrate through two collision modes: collision with the lattice atoms of the substrate and the generation of some lattice defects in the substrate and the blocking of the electron shell of the lattice atoms (electron deceleration). The higher the implantation energy of the implanted ions, the more lattice defects are generated in the ion implantation area of ​​the silicon carbide substrate. The high temperature of step S12 and the lattice defects generated during ion implantation cause a certain degree of warping of the entire wafer.

[0041] Step S13: remove the hard mask layer; after this step, a silicon carbide substrate including an ion implantation region on one side can be obtained. It should be noted that in a silicon carbide device, there may be ion implantation regions with different conductivities, that is, one side of the silicon carbide substrate may include multiple ion regions. At this time, it can be achieved by repeating steps S10 to S13. The difference is that due to the different conductivity types, ion implantation concentrations or depths of the ion implantation regions to be obtained, the parameters of the ion implantation process in step S12 and the implanted ion elements are different.

[0042] After the ion implantation of all regions of the silicon carbide substrate is completed, step S200 is performed: a silicon dioxide layer is deposited on the surface of at least one ion implantation region of the silicon carbide substrate; in this step, low-pressure tetraethyl orthosilicate (LPTEOS) can be used to deposit the silicon dioxide layer. The LPTEOS process utilizes the thermal decomposition of TEOS (tetraethyl orthosilicate, chemical formula SI(OC2H5)4) to generate an oxide layer, and the process temperature is between 600°C and 700°C. In one embodiment, the temperature in the LPTEOS process is 650°C, the deposition time is between 15min and 20min, and the thickness of the obtained silicon dioxide layer is between 100 and 1500°C. The obtained silicon dioxide layer has the advantage of good uniformity. The function of depositing the silicon dioxide layer on the silicon carbide substrate with the ion implantation region in step S200 is to protect the surface of the substrate to prevent it from being nitrided in step S300, thereby changing the conductive properties of the silicon carbide substrate.

[0043] Step S300: annealing the silicon carbide substrate using an annealing process, wherein the reaction gas of the annealing process is nitrogen N2. In one embodiment, the annealing process is performed under normal pressure, the flow rate of the reaction gas N2 of the annealing process is 8L / min-12L / min, the annealing temperature is 1000°C-1200°C, and the annealing time is 1.5-2.0 hours.

[0044] In some embodiments, the ion implantation method further comprises the following step S400: removing the silicon dioxide layer. It should be noted that in some semiconductor devices with oxide layers, polysilicon layers, and oxide-polysilicon-oxide (OPO) structures, the silicon dioxide layer deposited in step S300 can replace the silicon dioxide layer deposited by plasma enhanced tetraethyl orthosilicate deposition (PE-TEOS) process, which can be retained as a subsequent doping barrier layer.

[0045] Figure 2It is the warpage repair value of the existing silicon carbide wafer warpage repair method and the method for improving the warpage of the silicon carbide wafer under the N2 atmosphere of one embodiment of the present invention. Among them, curve A is the warpage repair value of the existing silicon carbide wafer warpage repaired by Ar annealing, and curve B is the warpage repair value of the method for improving the warpage of the silicon carbide wafer under the N2 atmosphere of the present application. Among them, the ordinate is μm, and the size of the silicon carbide substrate is 150mm. The warpage repair value is the difference between the warpage of the silicon carbide wafer before repair and the warpage of the silicon carbide wafer after repair, and the warpage is the difference between the maximum height of the upper edge arch of the silicon carbide wafer and the maximum height of the center of the silicon carbide wafer. It can be seen that the warpage repair value of the method of the present invention is ~69.43μm, and the warpage repair value of Ar annealing is 70.67μm, and the two are basically consistent, that is, the warpage of the silicon carbide wafer improved by the method of the present invention is equivalent to the warpage improved by the existing repair method, and it is achieved that when the silicon carbide wafer is heat-treated in a N2 atmosphere, the nitridation of the substrate surface is avoided while eliminating the lattice damage defects of the silicon carbide substrate caused by ion implantation, and the degree of warpage of the silicon carbide substrate during heat treatment is effectively reduced, thereby improving the yield of devices prepared on the wafer and reducing the manufacturing cost of silicon carbide devices.

[0046] Of course, in actual use, the ion implantation method may further include step S500: treating the silicon carbide substrate with an ion implantation activation process. The high-temperature ion activation process temperature of the silicon carbide device may be 1500°C to 1900°C, and the process duration may be 10min to 30min. The high-temperature process activates the implanted ions in each ion implantation area of ​​the silicon carbide substrate to improve the uniformity of ion dispersion. The specific parameters of the ion activation process may be further determined according to the type of implanted ions, which will not be described in detail here.

[0047] The second aspect of the present invention provides a semiconductor device, the semiconductor device includes a silicon carbide substrate, and the silicon carbide substrate is prepared by the method for improving the warpage of silicon carbide wafers under N2 atmosphere. Silicon carbide substrates are considered to be excellent materials for power switching elements due to their wide energy gap (such as the Eg of 4H-SiC can reach 3.26eV), high critical breakdown electric field strength (2.2MV / cm) and high thermal conductivity (4.9W / cm-K). Silicon carbide is also the only compound semiconductor that can form an oxide layer by thermal oxidation, so it can be suitable for making metal oxide semiconductor field effect transistors (Metaloxide semiconductor field effect transistor, referred to as MOSFET) and insulated gate bipolar transistors (Insulated gate bipolar transistor, referred to as IGBT) and other metal oxide semiconductor controlled switch elements (MOS controlled switches). Experiments show that the method for improving the warpage of silicon carbide wafers under N2 atmosphere of the present invention is used to obtain silicon carbide MOSFET devices, and its gate-source leakage current Igss, threshold voltage Vth and on-resistance Rdson and other performances meet product requirements. At the same time, the above-mentioned measurement was performed on the silicon carbide MOSFET device obtained by directly heat-treating the silicon carbide wafer in N2 atmosphere (i.e., without performing step S200 of the present invention) after ion implantation. The measurement results show that, without the protection of the surface silicon dioxide layer, heat-treating the silicon carbide wafer in N2 atmosphere will cause the parameters of the silicon carbide MOSFET device to shift, thereby affecting the yield of the silicon carbide MOSFET device. In addition, the nitrogen annealing process of step S300 of the present invention can be carried out in a special annealing equipment, such as a BDAN machine. Compared with the original warpage repair process equipment under Ar atmosphere, such as the BDHTC01 machine, the nitrogen annealing equipment can accommodate more wafers at a time, that is, the process of the present invention not only improves the warpage of the wafer, but also increases the output of batch generation, thereby improving production efficiency and reducing production costs.

[0048] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0049] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for improving the warpage of a silicon carbide wafer in a N2 atmosphere, characterized in that: The method for improving the warpage of a silicon carbide wafer comprises the following steps: Providing a silicon carbide substrate, wherein one side of the silicon carbide substrate includes at least one ion implantation region; Depositing a silicon dioxide layer on a surface of at least one ion implantation region of the silicon carbide substrate; The silicon carbide substrate is annealed by an annealing process, and the reaction gas of the annealing process is nitrogen.

2. The method for improving warpage of silicon carbide wafers under N2 atmosphere according to claim 1, characterized in that: The silicon dioxide layer was deposited using low pressure tetraethylorthosilicate.

3. The method for improving the warpage of a silicon carbide wafer under a N2 atmosphere according to claim 1, characterized in that: The thickness of the silicon dioxide layer is 4. The method for improving warpage of silicon carbide wafers in N2 atmosphere according to claim 1, characterized in that: The flow rate of the reaction gas in the annealing process is 8 L / min to 12 L / min.

5. The method for improving warpage of silicon carbide wafers in N2 atmosphere according to claim 1, characterized in that: The annealing temperature of the annealing process is 1000°C to 1200°C.

6. The method for improving warpage of silicon carbide wafers in N2 atmosphere according to claim 1, characterized in that: The annealing time of the annealing process is 1.5 to 2.0 hours.

7. The method for improving warpage of silicon carbide wafers in N2 atmosphere according to claim 1, characterized in that: The annealing process is performed under normal pressure.

8. The method for improving warpage of a silicon carbide wafer in a N2 atmosphere according to claim 1, characterized in that: The ion implantation temperature is greater than or equal to 500°C.

9. The method for improving warpage of silicon carbide wafers in N2 atmosphere according to claim 1, characterized in that: The ion implantation method further comprises the following steps: The silicon dioxide layer is removed.

10. A semiconductor device, characterized in that: The semiconductor device includes a silicon carbide substrate and an ion implantation region located on the silicon carbide substrate, wherein the ion implantation region is obtained by using the method for improving the warpage of a silicon carbide wafer under a N2 atmosphere as described in any one of claims 1 to 9.

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