Wafer test result processing method and device, equipment and storage medium

Abstract

The invention discloses a wafer test result processing method and device, equipment and a storage medium. The method comprises the steps that a first test result graph is generated according to a wafer test result, and the first test result graph comprises a plurality of first chips and a plurality of second chips; wherein the first chip is a chip passing the wafer test, and the second chip is a chip not passing the wafer test; marking the first chip as a third chip according to the position relationship between the second chip and the first chip; wherein the third chip is a failed chip; marking the first chip as a third chip according to the position relationship between the third chip and the first chip; and generating a second test result graph according to the marking result. The method has the technical effects that the potential risk chips are removed thoroughly according to the wafer test result, the accuracy is good, and the efficiency is high.

Description

Technical Field

[0001] The present application relates to the field of wafer testing technology, and in particular to a wafer testing result processing method, device, equipment and storage medium. Background Art

[0002] Wafer testing (Circuit Probe test, or CP test) refers to the process of testing the electrical performance of chips during the wafer manufacturing process. In the CP test, the chip on the wafer is connected to the test equipment through a contact probe. The test equipment will test and analyze the parameters of devices such as transistors, capacitors, and resistors through test signals to determine whether the electrical performance of the chip meets the requirements. The CP test of the wafer is usually carried out in the later manufacturing stage of the wafer and is one of the very important links in the wafer manufacturing process. Through the CP test, electrical problems in the chip such as short circuit, open circuit, leakage, etc. can be discovered in time, so that the chip can be subsequently repaired or eliminated to ensure the quality and reliability of the wafer. After the CP test, a wafer test result map (CPMap: Circuit Probe Map) showing the distribution of wafer test results will be obtained. In the wafer test result map, the chips that pass the test and the chips that fail the test will be marked separately. In the subsequent production process, the user will perform packaging, testing, and output steps according to the test result map. However, in the process of chip manufacturing, there are often process or physical effects, which cause certain failure areas to appear on the wafer test result map, and the qualified chips around the unqualified chips also have potential failure risks. In this case, the qualified chips around the unqualified chips are usually marked accordingly and discarded to improve the reliability of the overall wafer in the subsequent production process. Summary of the invention

[0003] In view of this, the present application provides a wafer test result processing method, device, equipment and storage medium, in order to solve the technical problem of low reliability of some chips in the wafer test results.

[0004] Specifically, the technical solution of this application is as follows:

[0005] A wafer test result processing method comprises the steps of:

[0006] Generate a first test result graph according to the wafer test result, the first test result graph including: a plurality of first chips and a plurality of second chips;

[0007] The first chip is a chip that has passed the wafer test, and the second chip is a chip that has not passed the wafer test;

[0008] According to the positional relationship between the second chip and the first chip, marking the first chip as the third chip;

[0009] The third chip is a failed chip;

[0010] According to the positional relationship between the third chip and the first chip, marking the first chip as the third chip;

[0011] A second test result graph is generated according to the marking result.

[0012] In some implementations, marking the first chip as the third chip according to the positional relationship between the second chip and the first chip specifically includes:

[0013] Setting a region where a plurality of first chips are connected as a first continuous region;

[0014] Setting a region where a plurality of second chips are connected as a second continuous region;

[0015] The first chip adjacent to the first continuous region and the second continuous region is marked as the third chip.

[0016] In some implementations, marking the first chip as the third chip according to the positional relationship between the second chip and the first chip further includes:

[0017] Taking the second chip as a punctuation point, setting a first preset number of chips around the second chip as a first area;

[0018] In the first area, the first chips having a number greater than or equal to a second preset number are marked as third chips.

[0019] In some implementations, marking the first chip as the third chip according to the positional relationship between the third chip and the first chip specifically includes:

[0020] Setting a closed area formed by connecting a plurality of third chips as a second area;

[0021] In the second area, the first chip is marked as the third chip.

[0022] In some implementations, setting an area formed by connecting a plurality of third chips as the second area further includes:

[0023] Setting a region formed by connecting a plurality of third chips that meet the first ratio threshold as a second region;

[0024] In the second region, a plurality of first chips satisfying a second ratio threshold are marked as third chips.

[0025] Based on the same technical concept, the present application also provides a computer device / equipment / system, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the wafer test result processing method in any of the above implementations.

[0026] Based on the same technical concept, the present application also provides a computer-readable storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the wafer test result processing method in any of the above implementations are implemented.

[0027] Based on the same technical concept, the present application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the wafer test result processing method in any of the above implementations.

[0028] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0029] 1. This application generates a first test result graph based on the wafer test results. Based on the first test result graph, firstly, according to the positional relationship between the second chip that failed the wafer test and the first chip that passed the wafer test, the first chip that has a certain degree of risk of failing the wafer test is marked and set as the third chip of the failed chip. On this basis, the positional relationship between the third chip and the first chip is judged again, and the first chip surrounded by the third chip that may have risks is marked as the third chip, so that the overall wafer test results are more reliable.

[0030] 2. In the process of marking the first chip as the third chip based on the positional relationship between the second chip and the first chip, the present application adopts the marking method of adjacent positions between continuous regions, and first marks the first chip that may be at risk at a macro level. Then, further marking is performed on the first chip that is less continuous or not continuous but has a certain risk, so that the first chip at risk is marked as the third chip to the greatest extent at a macro level, thereby improving the efficiency of the wafer test result processing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0032] Figure 1 A flowchart of a wafer test result processing method provided by the present application is shown;

[0033] Figure 2 A flow chart of a method for marking a first chip as a third chip according to a positional relationship between a second chip and a first chip provided by the present application is shown;

[0034] Figure 3 A flow chart showing another method provided by the present application for marking a first chip as a third chip according to the positional relationship between the second chip and the first chip;

[0035] Figure 4 A first test result diagram provided by the present application is shown;

[0036] Figure 5 A test result graph provided by the present application is shown, which is generated based on the dot division of the first test result graph;

[0037] Figure 6 A second test result diagram provided by the present application is shown. DETAILED DESCRIPTION

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0039] In order to simplify the drawings, only the parts related to the application are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0040] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0041] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0043] Wafer testing (Chip Probing) is to use finer probes (Probes) to establish connections with testers (Testers) for extremely tiny pins among tens of thousands of unpackaged chips after the wafer (Wafer) is manufactured, and the exposed chips are tested between the tester and the electrical characteristics, functions and performance of the chips on the wafer are directly contacted through the probes. This testing method helps to detect potential manufacturing defects or problems early. The general process of wafer testing includes: preparing wafers, installing test benches, positioning chips, testing probe contacts, electrical and functional testing, data processing, problem location and result analysis. This application mainly analyzes and applies the wafer test result graphs generated by data processing during wafer testing.

[0044] After completing the wafer test, users will select chips based on the wafer test result map for subsequent packaging, testing and shipment. However, during the production and manufacturing of chips, they are often affected by the manufacturing process, and some unqualified chip areas will appear on the wafer test result map. In some cases, qualified chips around unqualified chips may also have potential risks. In this case, qualified chips with potential risks need to be marked and set as failed chips.

[0045] As explained above, in wafer testing, there are tens of thousands of chips that need to be tested, and the distribution of unqualified chips and qualified chips in risk areas on the wafer test result map varies. The traditional approach can only be done by manual analysis and marking on the wafer test result map, which is very unfavorable for chip mass production. At the same time, the marking method for qualified chips with potential risks in the prior art is also insufficient, and it is difficult to completely mark all qualified chips with risks. For this reason, the present application provides a wafer test result processing method, device, equipment and storage medium to solve the above problems.

[0046] In one embodiment, the reference specification Figure 1 The present application provides a wafer test result processing method, comprising the steps of:

[0047] S110, generating a first test result graph according to the wafer test result, the first test result graph including: a plurality of first chips and a plurality of second chips;

[0048] The first chip is a chip that has passed the wafer test, and the second chip is a chip that has not passed the wafer test.

[0049] Specifically, the first test result graph generated according to the wafer test result is a graph that graphically presents the test results of each chip on the wafer, referring to Figure 4A first test result graph is provided. The generation process includes the following steps: Test data collection: During the wafer test process, the test system measures and records information such as electrical characteristics, functions and performance of each chip, which covers parameters such as current, voltage, power, and the results of functional tests, obtained according to specific test items. Then the test data is mapped to the corresponding position on the wafer according to the position of each chip. Each chip has a unique coordinate position on the wafer, usually represented by polar coordinates or Cartesian coordinates. When generating the first test result graph, a variety of colors, graphics, encodings, etc. can be used to represent the test results of each chip. The color is associated with a certain performance level or test threshold. For example, green indicates qualified, and red indicates unqualified, that is, in this application, the first chip is a qualified chip that has passed the wafer test, and the second chip is an unqualified chip that has not passed the wafer test. The final image is presented by using graphics software or data visualization tools, and the mapped test data is presented in the form of a graphic on the image of the wafer, which can be a picture of the entire wafer or an enlarged picture of a specific area. In addition, for the visualization of the image, descriptions may also be added to the legend, such as marking the legend to explain the meaning of colors and marking symbols so that users can understand the meaning of the test results.

[0050] The first test result graph helps manufacturing personnel quickly understand the test status of the chips on the entire wafer, locate unqualified areas, and take necessary measures to process the content contained in the first test result graph. This visual approach is more efficient in identifying and solving problems that arise during wafer testing.

[0051] S120, marking the first chip as a third chip according to the positional relationship between the second chip and the first chip;

[0052] The third chip is a failed chip;

[0053] Specifically, during the wafer testing process, the chips around the unqualified chips usually have certain potential risks. The main reason for these potential risks is firstly the proximity effect. Some problems in the manufacturing or testing process may cause the performance of the surrounding chips to be affected. For example, the adjacent chips may be affected by the electromagnetic interference or thermal effects of the adjacent chips, which may have a potential negative impact on their performance. Or process variation, the variability of the wafer during the manufacturing process may cause slight differences between adjacent chips on the wafer, which may cause potential risks to the performance of some chips in marginal cases. For example, there may be signal crosstalk between adjacent chips on the wafer, causing the test results of some chips to be affected by the signals of adjacent chips and be mistakenly considered qualified. At the same time, defects in the manufacturing process may propagate between adjacent chips. Although some of these chips may be judged as qualified in the test, their adjacent chips may potentially be affected by manufacturing defects and also be judged as qualified, but these chips all have certain risks. Local process problems will also affect the performance of adjacent chips. Such problems are usually temporary or difficult to detect directly in the testing stage. Therefore, the qualified chips adjacent to the qualified chips and the unqualified chips have certain potential risks and need to be identified, and these potential risk chips are closely related to the positional relationship between the qualified chips and the unqualified chips. In this case, although the qualified chip itself may pass the test, there are potential risk factors around it, which may cause problems in the subsequent production process. Therefore, the manufacturer needs to remove these risky chips to eliminate potential problems in the subsequent production process and ensure the overall production quality. Figure 5 A test result graph generated based on the point division of the first test result graph is shown. Through the positional relationship between the second chip and the first chip, some qualified chips (first chips) that are in direct or indirect contact (but relatively close to the unqualified chips) between the qualified chip and the unqualified chip are marked as third chips to eliminate the above potential risks. Of course, in the first test result graph, there are usually a large number of first chips connected to each other to form a large qualified area. In these qualified areas, there are usually some unqualified second chips scattered around. Some of the scattered second chips are only one or very few. The first chips in the areas where the first chip and the second chip are in contact with each other may not be marked, but they need to be selected and marked according to the test requirements. If the test requirements are high, they can also be marked. In the wafer testing process, the boundary between the two relatively large areas formed by the continuous first chip and the continuous second chip, the first chips included in the area involved in this boundary have a greater potential risk. Therefore, marking a certain number of first chips on the boundary side as third chips can eliminate the above potential risks as much as possible.

[0054] S130, marking the first chip as the third chip according to the positional relationship between the third chip and the first chip;

[0055] Specifically, after part of the first chip adjacent to the second chip is marked as the third chip in step S120, there is a high probability that part of the first chip is surrounded by the third chip. Although these first chips are identified or marked as qualified chips, since the first chips around them are all identified as third chips, naturally these surrounded first chips are also unreliable. Therefore, it is also necessary to identify these first chips as failed and unreliable chips, i.e., third chips, based on the positional relationship between the third chip and the first chip.

[0056] S140, generating a second test result graph according to the marking result.

[0057] Specifically, after the marking in step S120 and step S130, the first chip that meets the above requirements and conditions has been marked as the third chip. There are two presentation modes in the second test result graph. One is the second test result graph obtained by the first chip, the second chip and the third chip. In this image, the technician can analyze the specific problem. Since it presents the entire marking process, the position marked as the third chip can be specifically analyzed during the analysis, so as to obtain the corresponding conclusion and decide whether to completely identify it as an unqualified chip. Figure 6 The second test result graph provided. Or in the subsequent second round of testing, focus on the test results of these positions to improve the accuracy of wafer testing. Another way is to directly define these third chips as second chips, and only present two types of chips in the second test result graph, namely the first chip that passed the wafer test and the second chip that did not pass the wafer test, and directly present the final test results. This test result can be presented in the test process with higher test level requirements.

[0058] In one implementation, reference Figure 2 , which shows a flow chart of marking the first chip as the third chip according to the positional relationship between the second chip and the first chip, and specifically includes:

[0059] S210, setting a region where a plurality of first chips are connected as a first continuous region;

[0060] S220, setting a region where a plurality of second chips are connected as a second continuous region;

[0061] S230 , marking a first chip adjacent to the first continuous region and the second continuous region as a third chip.

[0062] The first chip and the second chip shown in the first test result diagram are often connected in pieces. Multiple qualified first chips that have passed the wafer test are adjacent to each other, forming one or more continuous complete areas, which are set as the first continuous area; multiple unqualified second chips that have not passed the wafer test are adjacent to each other, forming one or more continuous complete areas, which are set as the second continuous area. Since there are only two types of chips in this step in the first test result diagram, there must be parts where the first continuous area and the second continuous area are connected to each other. These parts are where qualified chips and unqualified chips are adjacent to each other. Therefore, the first chips in the adjacent positions are marked as third chips, and these first chips with potential risks are removed.

[0063] In one implementation, reference Figure 3 , which shows a flow chart of a method for marking a first chip as a third chip according to a positional relationship between a second chip and a first chip in the present application, and also includes:

[0064] S310, taking the second chip as a punctuation point, setting a first preset number of chips around the second chip as a first area;

[0065] S320: In the first area, mark the first chips that are greater than or equal to the second preset number as third chips.

[0066] Specifically, in the first test result diagram, the first chip and the second chip are cross-existing, and the first chip close to the second chip often has potential risks. Therefore, the second chip is anchored first, and the first chip and the second chip around the second chip are taken into consideration. For example, with the anchored second chip as the center, there may be first chips or second chips around and in the four corners, that is, the area with 8 chips around the nine-square grid area centered on the second chip and the anchored second chip as the first preset number of chips is 9, which are collectively set as the first area. In this first area, the second preset number of first chips contained in the first area is marked as the third chip. For example, there are 2 first chips in this first area, and when the second preset number is 2 or 1, then the two first chips are marked as the third chip. If the second preset number is 3, then the two first chips are not marked, and so on. Alternatively, with the anchored second chip as the upper right vertex, the chips of the 2*2 first preset number areas contained on the left are collectively set as the first area. In this first area, the first chip contained in the first area is marked as the third chip. Alternatively, the anchored second chip is used as the upper left vertex, and the chips in the 4*4 first preset number areas on the right are collectively set as the first area, and in this first area, the first chips in the first area are marked as the third chip. Therefore, in this application, the second chip is used as a punctuation point, and the first preset number of chips around the second chip are collectively set as the first area, and in the first area, the number of first chips greater than or equal to the second preset number is marked as the third chip.

[0067] In one implementation, marking the first chip as the third chip according to the positional relationship between the third chip and the first chip specifically includes:

[0068] Setting a closed area formed by connecting a plurality of third chips as a second area;

[0069] In the second area, the first chip is marked as the third chip.

[0070] After the first chip is marked as the third chip through the above step S120 and / or step S230 and / or step S320, there are usually some first chips with potential risks that are not marked. The reason for this may be due to the poor settings of the first area, the first preset number or the second preset number, or there may be a situation where the first chip is difficult to cover. The unmarked first chips with potential risks generated by this situation are often surrounded by third chips, so these third chips are searched, and the closed area formed by multiple adjacent third chips is set as the second area. In this second area, all or part of the first chips contained are set as third chips, completing the process of eliminating the omitted first chips with potential risks.

[0071] In one implementation, a closed area formed by connecting a plurality of third chips is set as the second area, and further includes:

[0072] Setting a closed area formed by connecting a plurality of third chips that meet the first ratio threshold as a second area;

[0073] In the second region, a plurality of first chips satisfying a second ratio threshold are marked as third chips.

[0074] Specifically, in the first test result diagram, the second area is set from the perspective of the percentage of the third chip in the whole wafer. The first chip to be marked in the second area is considered again from the perspective of percentage, and is marked after the conditions are met. In the second area formed by the continuous third chips that account for 2%-15% of the whole wafer, the first chips that account for less than 0.01%-1% of the whole wafer are marked as third chips. For example, the whole wafer has 20,000 pcs, and in the second area formed by 1,000 consecutive third chips (5%), 10 first chips are marked as third chips, that is, less than 0.05% of the first chips that account for the whole wafer.

[0075] Based on the same technical concept, the present application also provides a computer device / equipment / system, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the wafer test result processing method in any of the above implementations.

[0076] Based on the same technical concept, the present application also provides a computer-readable storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the wafer test result processing method in any of the above implementations are implemented.

[0077] Based on the same technical concept, the present application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the wafer test result processing method in any of the above implementations.

[0078] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims

1. A wafer test result processing method, characterized in that: Includes steps: Generate a first test result graph according to the wafer test result, wherein the first test result graph includes: a plurality of first chips and a plurality of second chips; The first chip is a chip that has passed the wafer test, and the second chip is a chip that has not passed the wafer test; According to the positional relationship between the second chip and the first chip, marking the first chip as a third chip; Wherein, the third chip is a failed chip; According to the positional relationship between the third chip and the first chip, marking the first chip as the third chip; A second test result graph is generated according to the marking result.

2. The wafer test result processing method according to claim 1, characterized in that: The step of marking the first chip as the third chip according to the positional relationship between the second chip and the first chip specifically includes: Setting a region where a plurality of the first chips are connected as a first continuous region; Setting a region where a plurality of the second chips are connected as a second continuous region; The first chip adjacent to the first continuous region and the second continuous region is marked as the third chip.

3. The wafer test result processing method according to claim 1, characterized in that: The method of marking the first chip as a third chip according to the positional relationship between the second chip and the first chip further includes: Taking the second chip as a punctuation point, setting a first preset number of chips around the second chip as a first area; In the first area, the first chips having a number greater than or equal to a second preset number of marks are the third chips.

4. The wafer test result processing method according to any one of claims 1 to 3, characterized in that: The step of marking the first chip as the third chip according to the positional relationship between the third chip and the first chip specifically includes: Setting a closed area formed by connecting a plurality of the third chips as a second area; In the second area, the first chip is marked as the third chip.

5. The wafer test result processing method according to claim 4, characterized in that: The enclosed area formed by connecting a plurality of the third chips is the second area, and further includes: Setting a closed area formed by connecting a plurality of the third chips that meet the first ratio threshold as the second area; In the second region, a plurality of the first chips satisfying a second ratio threshold are marked as the third chips.

6. A computer device / equipment / system comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the wafer test result processing method according to any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instruction is executed by a processor, the steps of the wafer test result processing method described in any one of claims 1 to 5 are implemented.

8. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the wafer test result processing method described in any one of claims 1 to 5 are implemented.

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