Copper metal layer forming method, semiconductor structure, chip and circuit
By aminating and hydroxylation of the silica layer, a barrier layer with good coverage is formed, which solves the problem of poor coverage of the barrier layer between copper and silicon and silicon dioxide in the prior art, and improves the compactness of the copper metal layer The performance and conductivity reduce the barrier layer thickness and enhance the integration of the integrated circuit.
Patent Information
- Application Number
- CN202411316440.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2024-12-20
AI Technical Summary
In the prior art, the barrier layer between copper, silicon and silicon dioxide has poor coverage, and the barrier effect is limited, resulting in uneven distribution of the copper film and there is a cavity, the device failure risk is high, and the barrier layer is thick, affecting the conductive performance.
The silica layer is aminated by organic solution to form an amino acid silica layer as the basis for the copper seed layer, reducing the thickness of the barrier layer and improving coverage, ensuring the density and uniformity of the copper metal layer, and through concentrated sulfuric acid The hydroxylation treatment with hydrogen peroxide increases the number of hydroxyl groups in the silica layer, forming a barrier layer with good coverage.
The uniformity of copper seed distribution is achieved, the resistance of the barrier layer is reduced, the conductive performance of the device is improved, the signal transmission delay is reduced, the size of the interconnection line is reduced, and the integration of the integrated circuit is improved.
Smart Images
Figure CN119170565A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a copper metal layer, a semiconductor structure, a chip and a circuit. Background Art
[0002] Copper has good electrical and mechanical properties and low cost, and is currently the best performing metal interconnect material for semiconductor device manufacturing. However, its high diffusion in silicon and silicon dioxide often leads to serious consequences of device failure. This problem can be effectively solved by adding a diffusion barrier layer between copper and silicon and silicon dioxide.
[0003] In the prior art, the barrier layer is a refractory metal and its nitride, such as the Ta / TaN system. In actual production, such barrier layers have insufficient coverage, which will lead to uneven distribution of the copper film and the appearance of voids, and the risk of device failure; in addition, the barrier layer has limited blocking effect. To ensure the blocking effect, such barrier layers often have a minimum thickness requirement, resulting in a thicker final barrier layer. Summary of the invention
[0004] In view of the technical problems of poor coverage, poor barrier effect and thickness of the barrier layer in the prior art, the present invention provides a copper metal layer forming method, a semiconductor structure, a chip and a circuit. The copper metal layer forming method can form a barrier layer with good coverage, and the copper seeds are more evenly distributed, which is beneficial to improving the density and uniformity of the subsequently deposited copper metal layer. While ensuring the barrier effect, the thickness of the barrier layer is reduced, the resistance of the barrier layer is reduced, the conductivity of the device is improved, the current transmission efficiency is improved, the delay of the signal during the transmission process is reduced, and the size of the interconnection line is reduced, thereby improving the integration of the integrated circuit.
[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a method for forming a copper metal layer, which comprises: providing a substrate having a metal wiring groove; forming a silicon dioxide layer on the surface of the substrate; performing an amination treatment on the silicon dioxide layer using an organic solution to obtain an amination silicon dioxide layer; wherein the organic solution comprises an organic functional group and a silaneoxy group; forming a copper seed layer on the surface of the amination silicon dioxide layer; and forming a copper metal layer on the surface of the copper seed layer.
[0006] Furthermore, after forming the silicon dioxide layer on the surface of the substrate, the method further comprises: performing a hydroxylation treatment on the silicon dioxide layer to increase the number of hydroxyl groups in the silicon dioxide layer.
[0007] Furthermore, the hydroxylation treatment of the silicon dioxide layer includes: immersing the silicon dioxide layer in a mixed solution of concentrated sulfuric acid and hydrogen peroxide to perform hydroxylation treatment on the silicon dioxide layer.
[0008] Furthermore, the volume ratio of concentrated sulfuric acid to hydrogen peroxide is between 4:1 and 6:1.
[0009] Furthermore, the amination treatment of the silicon dioxide layer with an organic solution includes: performing multiple amination treatments on the silicon dioxide layer with an organic solution, wherein each amination treatment includes: immersing the silicon dioxide layer in the organic solution; and washing the silicon dioxide layer after immersion in the organic solution with an ethanol solution.
[0010] Furthermore, the organic solution is a 3-aminopropyltrimethoxysilane solution.
[0011] Furthermore, the concentration of the 3-aminopropyltrimethoxysilane solution is between 20-50 mmol / L.
[0012] Furthermore, the substrate with metal wiring grooves is obtained by the following method: providing an initial substrate and forming an etch stop layer on the upper surface of the initial substrate; forming a metal oxide isolation layer on the upper surface of the etch stop layer; and etching the metal oxide isolation layer and the etch stop layer in sequence using a mask to form a substrate with metal wiring grooves.
[0013] Furthermore, the thickness of the silicon dioxide layer is between 40-60 nm.
[0014] A second aspect of the present invention provides a semiconductor structure, comprising a copper metal layer formed by the copper metal layer forming method described above.
[0015] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.
[0016] A fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.
[0017] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:
[0018] The copper metal layer forming method of the present invention first provides a substrate with a metal wiring groove, then forms a silicon dioxide layer on the surface of the substrate, uses an organic solution including an organic functional group and a silaneoxy group to perform an amination treatment on the silicon dioxide layer, forms an amination silicon dioxide layer on the surface of the silicon dioxide layer as a copper barrier layer, then forms a copper seed layer on the surface of the amination silicon dioxide layer, and forms a copper metal layer on the surface of the copper seed layer. Through the present invention, a barrier layer with good coverage can be formed, and the copper seeds are more evenly distributed, which is conducive to improving the compactness and uniformity of the copper metal layer deposited subsequently, and while ensuring the barrier effect, the thickness of the barrier layer is reduced, the resistance of the barrier layer is reduced, the conductivity of the device is improved, the transmission efficiency of the current is improved, the delay of the signal during the transmission process is reduced, and the size of the interconnection line is reduced, thereby improving the integration of the integrated circuit.
[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:
[0021] Figure 1 A flow chart of a method for forming a copper metal layer provided by an embodiment of the present invention;
[0022] Figure 2 A schematic structural diagram of a substrate, a metal oxide isolation layer and an etch stop layer formed in an embodiment of a method for forming a copper metal layer provided in an embodiment of the present invention;
[0023] Figure 3 A schematic diagram of the structure of a silicon dioxide layer formed in an embodiment of a method for forming a copper metal layer provided in an embodiment of the present invention;
[0024] Figure 4 A schematic diagram of immersing in an organic solution in an embodiment of a method for forming a copper metal layer provided by an embodiment of the present invention;
[0025] Figure 5 A schematic diagram of the structure of an amino silicon dioxide layer formed in an embodiment of the method for forming a copper metal layer provided in an embodiment of the present invention;
[0026] Figure 6 A schematic structural diagram of a copper seed layer formed in an embodiment of a method for forming a copper metal layer provided in an embodiment of the present invention;
[0027] Figure 7 A schematic structural diagram of a copper metal layer formed in an embodiment of a method for forming a copper metal layer provided in an embodiment of the present invention;
[0028] Figure 8 A schematic diagram of the formation principle of an amino silicon dioxide layer in one embodiment of the method for forming a copper metal layer provided in an embodiment of the present invention.
[0029] Description of Reference Numerals
[0030] 1-initial substrate; 2-etching stop layer; 3-metal oxide isolation layer; 4-silicon dioxide layer; 5-amino silicon dioxide layer; 6-copper seed layer; 7-copper metal layer. DETAILED DESCRIPTION
[0031] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.
[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0033] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.
[0034] As the background technology, the performance of the existing semiconductor structure is poor.
[0035] Please refer to Figure 1 A first aspect of an embodiment of the present invention provides a method for forming a copper metal layer, the method comprising: S101: providing a substrate having a metal wiring groove; S102: forming a silicon dioxide layer 4 on the surface of the substrate; S103: performing an amination treatment on the silicon dioxide layer 4 using an organic solution to obtain an amination silicon dioxide layer 5; wherein the organic solution comprises an organic functional group and a siloxy group; S104: forming a copper seed layer 6 on the surface of the amination silicon dioxide layer 5; S105: forming a copper metal layer 7 on the surface of the copper seed layer 6.
[0036] Specifically, step S101 is first performed: providing a substrate having a metal wiring trench.
[0037] Furthermore, the substrate with metal wiring grooves is obtained by the following method: providing an initial substrate 1, and forming an etch stop layer 2 on the upper surface of the initial substrate 1; forming a metal oxide isolation layer 3 on the upper surface of the etch stop layer 2; and etching the metal oxide isolation layer 3 and the etch stop layer 2 in sequence using a mask to form a substrate with metal wiring grooves.
[0038] Specifically, in the embodiment of the present invention, an initial substrate 1 is first provided, and the initial substrate is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. Those skilled in the art can select the type of the initial substrate according to the performance of the semiconductor device to be formed, so the type of the initial substrate should not excessively limit the protection scope of the present invention.
[0039] Then, a plasma chemical vapor deposition process is used to form an etch stop layer 2 on the upper surface of the initial substrate 1. In this embodiment, the etch stop layer 2 is SiCN with a thickness of 30-60nm. Then, a plasma chemical vapor deposition process is used to form a metal oxide isolation layer 3 on the upper surface of the etch stop layer 2 to reduce the parasitic capacitance between the metal layers. In this embodiment, the metal oxide isolation layer 3 is SiCOH with a thickness of 1750-3000nm. Next, a photoresist is formed on the upper surface of the metal oxide isolation layer 3, and the pattern on the metal mask is transferred to the photoresist by lithography technology, and a photoresist is formed on the photoresist. Figure 2 The etching window shown in FIG. 1 is formed by removing the metal oxide isolation layer 3 and the etching stop layer 2 not covered by the photoresist by dry etching. Figure 3 A substrate with metal wiring trenches is shown.
[0040] Then, step S102 is performed: forming a silicon dioxide layer 4 on the surface of the substrate.
[0041] Furthermore, the thickness of the silicon dioxide layer 4 is between 40-60 nm.
[0042] Furthermore, after the silicon dioxide layer 4 is formed on the surface of the substrate, the method further comprises: performing a hydroxylation treatment on the silicon dioxide layer 4 to increase the number of hydroxyl groups in the silicon dioxide layer 4 .
[0043] Furthermore, the hydroxylation treatment of the silicon dioxide layer 4 includes: immersing the silicon dioxide layer 4 in a mixed solution of concentrated sulfuric acid and hydrogen peroxide to perform hydroxylation treatment on the silicon dioxide layer 4 .
[0044] Furthermore, the volume ratio of concentrated sulfuric acid to hydrogen peroxide is between 4:1 and 6:1.
[0045] Specifically, in the embodiment of the present invention, a plasma chemical vapor deposition process is used to form a substrate surface as follows: Figure 3 The silicon dioxide layer 4 shown has a thickness of 40-60 nm. If the silicon dioxide layer 4 is too thin, it cannot protect the low dielectric film inside the silicon dioxide. If the silicon dioxide layer 4 is too thick, it will cause excessive stress, resulting in bending of the film layer or even the wafer.
[0046] Next, the silicon dioxide layer 4 is subjected to a hydroxylation treatment, the substrate is transferred to a mixed solution of concentrated sulfuric acid and hydrogen peroxide, the silicon dioxide layer 4 is immersed in the mixed solution for 0.5h-1h, and then rinsed with deionized water. The hydroxylation treatment can ensure the activity of the hydroxyl groups on the surface of the silicon dioxide layer 4, increase the number of hydroxyl groups on the silicon dioxide layer 4, and avoid affecting the distribution uniformity of the surface monolayer due to insufficient density of hydroxyl active sites on the surface of the silicon dioxide layer 4. The volume ratio of concentrated sulfuric acid to hydrogen peroxide is between 4:1-6:1, and this concentration can ensure that the silicon dioxide is fully hydroxylated.
[0047] Then, step S103 is performed: the silicon dioxide layer 4 is subjected to an amination treatment using an organic solution to obtain an amination silicon dioxide layer 5; wherein the organic solution includes an organic functional group and a silaneoxy group.
[0048] Furthermore, the amination treatment of the silicon dioxide layer 4 with an organic solution includes: performing multiple amination treatments on the silicon dioxide layer 4 with an organic solution, wherein each amination treatment includes: immersing the silicon dioxide layer 4 in the organic solution; and washing the silicon dioxide layer 4 after immersion in the organic solution with an ethanol solution.
[0049] Furthermore, the organic solution is a 3-aminopropyltrimethoxysilane solution.
[0050] Furthermore, the concentration of the 3-aminopropyltrimethoxysilane solution is between 20-50 mmol / L.
[0051] Specifically, in the embodiment of the present invention, Figure 4 and Figure 5 As shown, the substrate is transferred to an organic solution, and the silicon dioxide layer 4 is immersed in the organic solution for 0.5h-1h. The organic solution includes organic functional groups and silane oxy groups. After immersion, an amino silicon dioxide layer 5 is obtained, and then ethanol is used for cleaning. In this embodiment, the organic solution is a 3-aminopropyltrimethoxysilane solution (i.e., an APTMS solution). Figure 8 As shown, the methoxy group in the 3-aminopropyltrimethoxysilane solution reacts with the SiO2-OH on the surface of the silicon dioxide to form a Si-O-Si bond, thereby achieving the connection between the silicon dioxide and the 3-aminopropyltrimethoxysilane, and obtaining Figure 5The amino silicon dioxide layer 5 shown. The other end of the 3-aminopropyltrimethoxysilane molecule carries -NH2, which is a highly reactive group and will form a stable Cu-N chemical bond with the subsequently formed nano-copper seeds, thereby achieving the fixation of copper atoms. Therefore, the amino silicon dioxide layer 5 can be used as a copper barrier layer to tightly grasp copper atoms and prevent them from diffusing into the silicon substrate or other semiconductor materials, thereby affecting the performance of the device, preventing copper atoms from diffusing into the interior of the semiconductor, maintaining the predetermined circuit conductivity, ensuring the normal operation of the circuit, and preventing chemical reactions between copper and semiconductor materials, thereby improving the long-term reliability of the entire device.
[0052] In this embodiment, the solvent of the 3-aminopropyltrimethoxysilane solution is cyclohexane, and the concentration is between 20-50mmol / L. When the amination silicon dioxide layer 5 is formed, the concentration of the 3-aminopropyltrimethoxysilane solution has a great influence on the quality of the molecular film. If the concentration of the 3-aminopropyltrimethoxysilane solution is low, it cannot be fully connected with the hydroxyl groups on the surface of silicon dioxide, and the molecular film is not tight enough, which seriously affects the subsequent blocking effect on copper; if the concentration of the 3-aminopropyltrimethoxysilane solution is too high, intermolecular self-polymerization will occur, and an island structure generated by self-polymerization will appear on the molecular film, and the surface will be ups and downs, and the flatness is not good. In this embodiment, a concentration of 20-50mmol / L can be selected to perform 2-3 amination treatments on silicon dioxide to ensure the coverage and uniformity of the amination silicon dioxide layer 5.
[0053] Then, step S104 is performed: forming a copper seed layer 6 on the surface of the amino silicon dioxide layer 5 .
[0054] Finally, step S105 is performed: forming a copper metal layer 7 on the surface of the copper seed layer 6 .
[0055] Specifically, in the embodiment of the present invention, after the amino silicon dioxide layer 5 is formed, a physical vapor deposition process is used to form a surface of the amino silicon dioxide layer 5 as follows: Figure 6 The copper seed layer 6 shown in the figure has the copper seed tightly connected to SiO2 through -NH2-. Then, a layer of copper is deposited on the surface of the copper seed layer 6 by chemical electroplating process to obtain Figure 7 The copper metal layer is shown.
[0056] A second aspect of the present invention provides a semiconductor structure, comprising a copper metal layer formed by the copper metal layer forming method described above.
[0057] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.
[0058] A fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.
[0059] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
[0060] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.
[0061] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.
Claims
1. A method for forming a copper metal layer, characterized in that: The copper metal layer forming method comprises: Providing a substrate having a metal wiring trench; forming a silicon dioxide layer on the surface of the substrate; The silicon dioxide layer is subjected to an amination treatment using an organic solution to obtain an amination silicon dioxide layer; wherein the organic solution comprises an organic functional group and a silaneoxy group; forming a copper seed layer on the surface of the amino silicon dioxide layer; A copper metal layer is formed on the surface of the copper seed layer.
2. The method for forming a copper metal layer according to claim 1, characterized in that: After forming a silicon dioxide layer on the surface of the substrate, the method further comprises: The silicon dioxide layer is subjected to a hydroxylation treatment to increase the amount of hydroxyl groups in the silicon dioxide layer.
3. The method for forming a copper metal layer according to claim 2, characterized in that: The step of performing hydroxylation on the silicon dioxide layer comprises: The silicon dioxide layer is immersed in a mixed solution of concentrated sulfuric acid and hydrogen peroxide to perform a hydroxylation treatment on the silicon dioxide layer.
4. The method for forming a copper metal layer according to claim 3, characterized in that: The volume ratio of concentrated sulfuric acid to hydrogen peroxide is between 4:1 and 6:
1.
5. The method for forming a copper metal layer according to claim 1, characterized in that: The step of performing amination treatment on the silicon dioxide layer by using an organic solution comprises: The silicon dioxide layer is subjected to multiple amination treatments using an organic solution, wherein each amination treatment comprises: immersing the silicon dioxide layer in the organic solution; The silicon dioxide layer after being immersed in the organic solution is cleaned with an ethanol solution.
6. The method for forming a copper metal layer according to claim 1, characterized in that: The organic solution is 3-aminopropyltrimethoxysilane solution.
7. The method for forming a copper metal layer according to claim 6, characterized in that: The concentration of the 3-aminopropyltrimethoxysilane solution is between 20-50 mmol / L.
8. The method for forming a copper metal layer according to claim 1, characterized in that: The substrate having the metal wiring groove is obtained by the following method: Providing an initial substrate, and forming an etch stop layer on the upper surface of the initial substrate; forming a metal oxide isolation layer on the upper surface of the etch stop layer; The metal oxide isolation layer and the etching stop layer are etched in sequence using a mask to form a substrate with a metal wiring trench.
9. The method for forming a copper metal layer according to claim 1, characterized in that: The thickness of the silicon dioxide layer is between 40-60 nm.
10. A semiconductor structure, characterized in that: The semiconductor structure includes a copper metal layer formed by the method for forming a copper metal layer according to any one of claims 1 to 9.
11. A chip, characterized in that: The chip comprises the semiconductor structure according to claim 10.
12. A circuit, characterized in that: The circuit comprises the semiconductor structure of claim 10.