Manufacturing method of semiconductor structure, semiconductor structure and semiconductor packaging structure

Abstract

The invention provides a manufacturing method of a semiconductor structure, the semiconductor structure and a semiconductor packaging structure, and the manufacturing method comprises the steps: providing a wafer which comprises a plurality of crystal grains, and there is a cutting channel between the adjacent crystal grains; forming a control circuit in a part of the cutting channel between the adjacent crystal grains along the first direction and extending along the second direction; and cutting the wafer through the cutting channels extending in the first direction and the cutting channels extending in the second direction and not provided with the control circuits to form a plurality of semiconductor structures. The control circuit is arranged in the cutting channel between the adjacent crystal grains, the space of the cutting channel between the crystal grains is fully utilized, and the overall size of the semiconductor structure is reduced; the plurality of crystal grains are electrically connected with the same control circuit, the plurality of crystal grains are managed through one control circuit, and the number of the control circuits is reduced; and packaging can be carried out without cutting into single crystal grains, so that packaging is facilitated, and the product yield is not influenced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor packaging structure. Background Art

[0002] The semiconductor structure (e.g., semiconductor chip) includes multiple dies stacked together, and the dies need to be filled to enhance the reliability of the semiconductor structure. In the related art, when multiple dies are stacked side by side, it is necessary to ensure that the horizontal spacing of the dies is greater than 200 μm, which results in a larger overall size of the stacked semiconductor structure and is not conducive to the packaging of the semiconductor structure. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] According to some embodiments of the present disclosure, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] Providing a wafer, the wafer comprising a plurality of crystal grains, the plurality of crystal grains being arranged along a first direction and a second direction, the first direction and the second direction having a preset angle, and having a cutting path between adjacent crystal grains;

[0006] A control circuit is formed in a portion of the dicing path extending along the second direction and between the adjacent dies along the first direction, wherein the control circuit is electrically connected to the adjacent dies located on both sides of the control circuit in the first direction;

[0007] The wafer is cut along the dicing lanes extending along the first direction and the dicing lanes extending along the second direction and not formed with the control circuit to form a plurality of the semiconductor structures.

[0008] In some embodiments, the method for manufacturing the semiconductor structure further includes:

[0009] The plurality of dies are tested to determine whether each of the dies in each of the semiconductor structures is a good die or a bad die.

[0010] In some embodiments, the method for manufacturing the semiconductor structure further includes:

[0011] An interconnection through hole is formed on the cutting path. The interconnection through hole penetrates the cutting path along the thickness direction of the cutting path and is electrically connected to the control circuit.

[0012] In some embodiments, each of the semiconductor structures includes two dies, and the control circuit is disposed between the two dies in the same semiconductor structure;

[0013] If the two crystal grains in the same semiconductor structure are respectively a good crystal grain and a bad crystal grain, the method for manufacturing the semiconductor structure includes:

[0014] The semiconductor structure is cut along the cutting path where the control circuit is located, and the good grains are retained.

[0015] In some embodiments, a control circuit is formed in a portion of the scribe line extending along the second direction and between the dies adjacent to each other along the first direction, including:

[0016] Among all the scribe lines extending along the second direction, the scribe lines on which the control circuit is formed and the scribe lines on which the control circuit is not formed are alternately arranged along the first direction.

[0017] According to a second aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0018] A plurality of crystal grains, wherein the plurality of crystal grains are arranged along a first direction and a second direction, the first direction and the second direction have a preset angle, and a cutting path is provided between two adjacent crystal grains;

[0019] The control circuit is arranged on the cutting path, and the control circuit is electrically connected to each of the crystal grains.

[0020] In some embodiments, a redistribution layer and / or a top metal layer is disposed on the die;

[0021] The control circuit includes a power management circuit, which is electrically connected to the redistribution layer and / or the top metal layer and is used to drive each of the crystal grains.

[0022] In some embodiments, the die is provided with a self-refresh circuit, and the power management circuit is electrically connected to the self-refresh circuit.

[0023] In some embodiments, the semiconductor structure further includes an interconnection through hole, wherein the interconnection through hole is disposed in the cutting path, and the interconnection through hole passes through the cutting path and is electrically connected to the control circuit.

[0024] In some embodiments, a distance between two adjacent grains is less than 60 μm.

[0025] According to a third aspect of the present disclosure, there is provided a semiconductor structure, comprising a substrate, wherein the substrate is provided with a plurality of chip regions and a cutting region;

[0026] The cutting area is arranged between adjacent chip areas, and a control circuit is arranged in the cutting area, and the control circuit controls the chip area;

[0027] Any of the chip areas has an independent chip function.

[0028] In some embodiments, the cutting area is provided with interconnected through holes, and the interconnected through holes penetrate the cutting area along the thickness direction of the cutting area.

[0029] In some embodiments, two chip areas are provided, and the cutting area is provided between the two chip areas.

[0030] In some embodiments, the width of the cutting region is less than 60 μm.

[0031] According to a fourth aspect of the present disclosure, a semiconductor package structure is provided, comprising the semiconductor structure as described in the second aspect or the third aspect.

[0032] In some embodiments, the semiconductor package structure includes a package substrate, and a plurality of the semiconductor structures, wherein the plurality of the semiconductor structures are stacked on the package substrate along a thickness direction of the package substrate.

[0033] In some embodiments, projections of two adjacent semiconductor structures on the packaging substrate at least partially overlap, and projections of two spaced-apart semiconductor structures on the packaging substrate completely overlap.

[0034] In some embodiments, in the stacking direction of the semiconductor structures, a plurality of interconnection through holes of a plurality of the semiconductor structures are facing each other, and the control circuits of the plurality of the semiconductor structures are electrically connected through the interconnection through holes.

[0035] The embodiments of the present disclosure have at least the following advantages:

[0036] The control circuit is set in the cutting path between adjacent grains, which makes full use of the space of the cutting path between the grains. It does not need to be set separately in other positions of the semiconductor structure, which reduces the overall size of the semiconductor structure. At the same time, compared with the related art in which the control circuit is set in the filling space between adjacent grains, the size requirement of the filling space between adjacent grains is reduced. In addition, multiple grains are electrically connected to the same control circuit, and multiple grains can be managed by one control circuit. Compared with the related art in which each grain is managed by one control circuit, the number of control circuits is reduced, thereby reducing the overall size of the semiconductor structure. Moreover, it can be directly packaged without cutting into individual grains, which is beneficial to the packaging of semiconductor structures and will not affect the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a schematic diagram of a semiconductor packaging structure in the related art.

[0039] Figure 2 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0040] Figure 3 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0041] Figure 4 is a schematic diagram of a wafer according to an exemplary embodiment of the present disclosure.

[0042] Figure 5 An exemplary embodiment of the present disclosure is shown Figure 4 Schematic diagram of area A in center.

[0043] Figure 6 Another exemplary embodiment of the present disclosure is shown Figure 4 Schematic diagram of area A in center.

[0044] Figure 7 FIG. 4 is a schematic diagram showing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0045] Figure 8 is a schematic diagram of a semiconductor package structure according to an exemplary embodiment of the present disclosure.

[0046] Fig. 9 FIG. 4 is a schematic diagram of a semiconductor package structure according to another exemplary embodiment of the present disclosure.

[0047] Fig.10 is a schematic diagram of a semiconductor structure according to yet another exemplary embodiment of the present disclosure.

[0048] Reference numerals :

[0049] 200', semiconductor package structure; 30', package substrate; 11', die; 41', first die group; 42', second die group;

[0050] 100. Wafer;

[0051] 10. semiconductor structure; 11. grain; 11a. good grain; 11b. bad grain; 12. control circuit; 13. interconnection via;

[0052] 20. Cutting road;

[0053] 200. Semiconductor packaging structure;

[0054] 30. Packaging substrate;

[0055] 40. Stacked structure;

[0056] 50. Bonding wires;

[0057] 60. Substrate; 61. Chip area; 62. Cutting area; 63. Control circuit. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0059] A semiconductor structure (e.g., a semiconductor chip) has multiple dies stacked in a stacked arrangement, and the dies need to be filled to enhance the reliability of the semiconductor structure. In the related art, for example, when multiple dies are stacked side by side, it is necessary to ensure that the horizontal spacing between the dies is greater than 200 μm, resulting in a larger overall size of the stacked semiconductor structure and not conducive to the packaging of the semiconductor structure.

[0060] refer to Figure 1 , shows a semiconductor package structure 200' (e.g., semiconductor chip) in the related art, the semiconductor package structure 200' comprises a package substrate 30', and a plurality of dies 11' (also called bare die) stacked on the package substrate 30', wherein four dies 11' are stacked together to form a first die group 41', and another four dies 11' are stacked together to form a second die group 42', and the first die group 41' and the second die group 42' need to be filled to ensure the stability and reliability of the semiconductor package structure 200'. If the spacing between the first die group 41' and the second die group 42' ( Figure 1The y direction shown in FIG. 1 is small, which will result in incomplete filling between the first die group 41' and the second die group 42'. In order to ensure that the first die group 41' and the second die group 42' are fully filled, the spacing between the first die group 41' and the second die group 42' needs to be greater than 200 μm, which will result in a large overall size of the semiconductor structure and is not conducive to packaging.

[0061] In order to solve the above problems, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, in which a control circuit is arranged on the cutting path between adjacent grains, thereby fully utilizing the space of the cutting path between the grains. There is no need to arrange it separately at other positions of the semiconductor structure, thereby reducing the overall size of the semiconductor structure and facilitating the packaging of the semiconductor structure without affecting the yield of the product.

[0062] In the exemplary embodiments of the present disclosure, Figure 2 As shown, the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure 10, and the method for manufacturing the semiconductor structure 10 can form the semiconductor structure 10 by processing a wafer 100, and the semiconductor structure 10 is used to manufacture a semiconductor chip. Semiconductor chips such as dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM), static random access memory (Static Random-Access Memory, SRAM), etc.

[0063] refer to Figure 2 In an exemplary embodiment of the present disclosure, a method for manufacturing the semiconductor structure 10 includes:

[0064] Step S110 , providing a wafer, wherein the wafer includes a plurality of crystal grains, wherein the plurality of crystal grains are arranged along a first direction and a second direction, wherein the first direction and the second direction have a preset angle, and there are cutting paths between adjacent crystal grains.

[0065] refer to Figure 4 The wafer 100 may be a silicon wafer used to manufacture semiconductor circuits. After the semiconductor circuits are manufactured on the wafer 100, a plurality of die arranged in an array are formed on the wafer 100. Figure 4 As an example, the projection of each crystal grain 11 on the surface of the wafer 100 is generally rectangular, and the plurality of crystal grains 11 are arranged along a first direction ( Figure 4 y direction shown in ) and the second direction ( Figure 4 The first direction and the second direction have a preset angle (for example, 90°).

[0066] It should be noted that the first direction and the second direction are only used to facilitate the explanation of the technical solution of the embodiment of the present disclosure. In the actual production process, the directions of the first direction and the second direction in the space coordinate system can be set arbitrarily.

[0067] Continue to refer Figure 4 There is a scribe line 20 between adjacent dies 11. The scribe line 20 may be a marking line or marking area that separates adjacent dies 11, such as a line groove formed on the surface of the wafer 100. When the wafer 100 is cut along the scribe line 20, multiple dies 11 may be separated to form multiple independent dies, which may be packaged to form a semiconductor chip.

[0068] In one example, reference Figures 4 to 6 , a test pad may be provided in the cutting path 20, for example, the wafer 100 may be subjected to a wafer acceptance test (WAT) and a chip probing test (CP Test) through the test pad. Among them, the wafer acceptance test can test parameters that can reflect whether the process is normal, such as the resistance value of a resistor, the gate oxide capacitance value of a MOS tube, etc., to find out whether there is a production problem with the wafer 100. If there is a production problem with the wafer 100, it may be scrapped. The wafer-level test can test each grain 11 on the entire wafer 100, for example, it can select out bad grains 11, thereby reducing the subsequent packaging cost.

[0069] In some embodiments, the test pad can be set on the die 11 and electrically connected to the internal circuit of the die 11 through the redistribution layer (RDL) or the top metal line of the die 11, thereby avoiding the space of the cutting path 20, and then the size of the cutting path 20 can be reduced, or other devices can be set in the cutting path 20.

[0070] In step S120 , a control circuit is formed in a portion of the scribe line extending along the second direction and between the adjacent dies along the first direction, wherein the control circuit is electrically connected to the adjacent dies on both sides of the control circuit in the first direction.

[0071] In this step, a control circuit 12 may be formed in the cutting path 20 by using deposition, masking, etching and other processes, and the control circuit 12 is electrically connected to the plurality of adjacent grains 11. The control circuit includes a power management circuit

[0072] refer to Figures 4 to 6 , and Figure 4 As an example, the orientation shown in FIG. 1 can be between adjacent grains 11 and along the second direction ( Figure 4 The control circuit 12 is formed in the cutting lane 20 extending in the first direction (x direction shown in FIG. 1 ). The control circuit 12 is connected to the control circuit 12 in the first direction (x direction shown in FIG. 1 ). Figure 4The adjacent grains 11 on both sides (y direction as shown in FIG. 1 ) are electrically connected.

[0073] In one example, reference Figure 4 and Figure 5 , in the first direction ( Figure 5 In the y direction shown in the figure, each control circuit 12 has two grains 11 electrically connected to the control circuit 12 on both sides of the first direction, that is, a control circuit 12 is formed between two adjacent grains 11 along the first direction, and the two grains 11 are electrically connected to the control circuit 12 respectively, and the two grains 11 are controlled or driven at the same time by the control circuit 12.

[0074] In another example, refer to Figure 4 and Figure 6 , in the first direction ( Figure 6 In the y direction as shown in the figure, each control circuit 12 has four grains 11 electrically connected to the control circuit 12 on both sides of the first direction. The four grains 11 are arranged in two columns along the first direction and in two rows along the second direction. The four grains 11 are controlled simultaneously by the control circuit 12.

[0075] It is understandable that each control circuit 12 can also be electrically connected to a greater number of dies 11 , such as six dies, eight dies, etc., which will not be described in detail here.

[0076] In step S130 , the wafer is cut along the scribe lines extending in the first direction and along the scribe lines extending in the second direction and not forming the control circuit, to form a plurality of semiconductor structures.

[0077] In this step, refer to Figure 4 , a laser may be used to cut the wafer 100 along a predetermined cutting path 20 to separate the wafer 100 into a plurality of semiconductor structures 10. The predetermined cutting path 20 includes a first direction ( Figure 4 The scribe line 20 extends in the y direction as shown in FIG. 1 , and in the second direction ( Figure 4 The scribe line 20 extends in the x direction (as shown in FIG. 1 ) but does not have the control circuit 12 thereon.

[0078] refer to Figure 5 As an example, each semiconductor structure 10 includes a control circuit 12 and two crystal grains 11 located on both sides of the control circuit 12 in the first direction. Figure 6 Each semiconductor structure 10 may also include a control circuit 12 and four crystal grains 11. That is, each semiconductor structure 10 may include a control circuit 12 and an even number of crystal grains 11 located on both sides of the control circuit 12.

[0079] In the disclosed embodiment, the control circuit 12 is arranged in the cutting path 20 between adjacent crystal grains 11, which fully utilizes the space of the cutting path 20 between the crystal grains 11, and does not need to be arranged separately in other positions of the semiconductor structure 10, thereby reducing the overall size of the semiconductor structure 10. At the same time, compared with the related art in which the control circuit is arranged in the filling space between adjacent crystal grains, the size requirement of the filling space between adjacent crystal grains 11 is reduced. In addition, multiple crystal grains 11 are electrically connected to the same control circuit 12, and multiple crystal grains 11 can be managed by one control circuit 12. Compared with the related art in which each crystal grain is managed by one control circuit, the number of control circuits 12 is reduced, thereby reducing the overall size of the semiconductor structure 10. Moreover, it can be directly packaged without cutting into individual crystal grains, which is beneficial to the packaging of the semiconductor structure and will not affect the yield of the product.

[0080] In the above embodiment, when the multiple dies 11 in the semiconductor structure 10 are all good dies 11 a , the multiple dies 11 in the semiconductor structure 10 can be packaged as a whole, and the multiple dies 11 can be managed simultaneously by the control circuit 12 in the semiconductor structure 10 .

[0081] When some of the multiple crystal grains 11 in the semiconductor structure 10 are good crystal grains 11a and some are bad crystal grains 11b, after the wafer 100 is cut as described above, the formed semiconductor structure 10 can be further cut to screen out the good crystal grains 11a and the bad crystal grains 11b. Figure 3 As shown, the method for manufacturing a semiconductor structure provided in this embodiment includes the following steps:

[0082] Step S210 , providing a wafer, wherein the wafer includes a plurality of crystal grains, wherein the plurality of crystal grains are arranged along a first direction and a second direction, wherein the first direction and the second direction have a preset angle, and there are cutting paths between adjacent crystal grains.

[0083] The implementation method and principle of this step are the same as those of the above step S110, and will not be repeated here.

[0084] In step S220 , a control circuit is formed in a scribe line extending along a second direction and between adjacent dies along a first direction, wherein the control circuit is electrically connected to adjacent dies located on both sides of the control circuit in the first direction.

[0085] In this step, refer to Figure 5 , along the second direction ( Figure 5 Among all the cutting lanes 20 extending in the first direction (the x direction shown in FIG), the cutting lanes 20 formed with the control circuit 12 and the cutting lanes 20 not formed with the control circuit 12 are arranged along the first direction ( Figure 5 The y direction as shown in FIG. 2 is alternately arranged.

[0086] Step S230 , testing the plurality of crystal grains to determine whether each crystal grain in each semiconductor structure to be formed is a good crystal grain or a bad crystal grain.

[0087] In this step, a wafer-level test (CP Test) can be used to test each grain 11 on the wafer 100 to determine the quality of each grain 11 in each semiconductor structure 10 to be formed, and then different semiconductor structures 10 to be formed can be processed accordingly according to the quality of multiple grains 11 in each semiconductor structure 10 to be formed.

[0088] Here, it should be noted that step S230 can be performed after forming the control circuit 12, or can be performed before forming the control circuit 12.

[0089] In step S240 , the wafer is cut along the scribe lines extending in the first direction and along the scribe lines extending in the second direction and not having the control circuit formed thereon, to form a plurality of semiconductor structures.

[0090] The implementation method and principle of this step are the same as those of step S130 in the above embodiment, and will not be repeated here.

[0091] In some optional embodiments, after the wafer 100 is cut into a plurality of semiconductor structures 10 along the cutting streets 20, if it is tested that all the crystal grains 11 in the same semiconductor structure 10 are good crystal grains 11a, refer to Figure 3 The method for manufacturing the semiconductor structure 10 further includes the following steps:

[0092] In some other embodiments, after the wafer 100 is cut into a plurality of semiconductor structures 10 along the dicing streets 20, if good quality crystal grains 11a and bad quality crystal grains 11b exist in the same semiconductor structure 10, the method for manufacturing the semiconductor structure 10 further includes the following steps:

[0093] Step S260 , cutting the semiconductor structure along the cutting path where the control circuit is located, and retaining good quality crystals.

[0094] In this step, refer to Figure Figure 5 , the defective crystal grain 11b is the crystal grain 11 that cannot be put into use. If the semiconductor structure 10 containing the defective crystal grain 11b is packaged in the manner described in step S250, the packaged semiconductor structure 10 may not be used normally, which wastes costs. In the embodiment of the present disclosure, the defective crystal grain 11a in the semiconductor structure 10 can be removed, and only the single good crystal grain 11a is packaged.

[0095] refer to Figure 4 and Figure 5, the semiconductor structure 10 includes two crystal grains 11. The semiconductor structure 10 can be cut along the cutting path 20 where the control circuit 12 is located, so that the good crystal grain 11a is separated from the bad crystal grain 11b, and the good crystal grain 11a is retained; then, the good crystal grain 11a can be functionally supplemented according to actual needs, such as adding the function of the control circuit 12 to the good crystal grain 11a.

[0096] In some embodiments, the retained single good die 11 a may be packaged together with other single good die 11 a , and the packaging spacing between two good die 11 a is generally required to be greater than or equal to 200 μm.

[0097] In some embodiments, the method for manufacturing a semiconductor structure further includes:

[0098] Step S270: forming interconnection through holes on the cutting paths. The interconnection through holes penetrate the cutting paths along the thickness direction of the cutting paths and are electrically connected to the control circuit.

[0099] In this step, refer to Figure 7 , a mask, etching or other process may be used to remove part of the structure of the cutting path 20, and then a deposition or other process may be used to deposit a conductive material in the removed area to form an interconnecting through hole 13 capable of conducting electricity. In the disclosed embodiment, the conductive material is doped polysilicon, and the interconnecting through hole 13 is also called a through silicon via (TSV for short). In some optional implementations, the conductive material may also be a material with good conductive properties such as metal.

[0100] refer to Figure 4 and Figure 7 , the interconnection through hole 13 can be made before cutting the wafer 100. For example, after the control circuit 12 is formed in the cutting street 20, the interconnection through hole 13 is formed in the cutting street 20 where the control circuit 12 is formed. In this embodiment, the interconnection through hole 13 is formed before the semiconductor structure 100 is stacked. When making the interconnection through hole 13, it is necessary to adaptively set the position of the interconnection through hole 13 according to the different stacking modes of the semiconductor structure 10, so as to ensure that when multiple semiconductor structures 10 are stacked to form a stacked structure 40, the interconnection through holes 13 of the multiple semiconductor structures 10 are in the stacking direction ( Figure 8 Directly facing in the z direction (as shown in ).

[0101] In some optional embodiments, multiple semiconductor structures can be stacked together along the thickness direction of the semiconductor structure to form a stacked structure, and then interconnected through holes are formed in the multiple semiconductor structures of the stacked structure. The interconnected through holes penetrate each semiconductor structure along the stacking direction of the multiple semiconductor structures and electrically connect the multiple semiconductor structures together.

[0102] like Figures 4 to 7 As shown, the embodiment of the present disclosure provides a semiconductor structure 10, which can be formed by using the method for manufacturing the semiconductor structure 10 provided in the above embodiment. The semiconductor structure 10 includes a plurality of crystal grains 11 and a control circuit 12.

[0103] The die 11 is also called a die. Each die 11 includes an integrated circuit to achieve a specific function. The plurality of die 11 are arranged along a first direction ( Figure 4 y direction shown in ) and the second direction ( Figure 4 The first direction and the second direction are parallel to the surface of the wafer 100, and the angle between the first direction and the second direction may be 90°.

[0104] refer to Figures 4 to 6 A dicing street 20 is provided between two adjacent crystal grains 11. The dicing street 20 includes a dicing street extending along a first direction and a dicing street extending along a second direction. The dicing street extending along the first direction and the dicing street extending along the second direction separate the adjacent crystal grains 11 so as to subsequently divide the wafer 100 into a plurality of semiconductor structures 10. Each semiconductor structure 10 includes a plurality of crystal grains 11.

[0105] In one example, the width of the scribe line 20 ( Figure 7 The distance between adjacent grains 11 is equal to the width of the cutting road 20, and the spacing between two adjacent grains 11 is less than 60 μm. The size of the semiconductor structure 10 is small, which is conducive to packaging.

[0106] Continue to refer Figures 4 to 6 A control circuit 12 is provided in the dicing road 20, and the control circuit 12 can be electrically connected to a plurality of crystal grains 11, and a plurality of crystal grains 11 electrically connected to the same control circuit 12 form a semiconductor structure 10. The structure of the control circuit 12 can be flexibly set according to actual needs, for example, the number of crystal grains 11 that can be simultaneously connected to each control circuit 12 can be adjusted, thereby adjusting the number of crystal grains in the semiconductor structure 10.

[0107] In the disclosed embodiment, the control circuit 12 is arranged in the cutting path 20 between adjacent crystal grains 11, which fully utilizes the space of the cutting path 20 between the crystal grains 11, and does not need to be arranged separately in other positions of the semiconductor structure 10, thereby reducing the overall size of the semiconductor structure 10. At the same time, compared with the related art in which the control circuit is arranged in the filling space between adjacent crystal grains, the size requirement of the filling space between adjacent crystal grains 11 is reduced. In addition, multiple crystal grains 11 are electrically connected to the same control circuit 12, and multiple crystal grains 11 can be managed by one control circuit 12. Compared with the related art in which each crystal grain is managed by one control circuit, the number of control circuits 12 is reduced, thereby reducing the overall size of the semiconductor structure 10. Moreover, it can be directly packaged without cutting into individual crystal grains, which is beneficial to the packaging of the semiconductor structure.

[0108] In an exemplary embodiment, as shown in FIG. 1 , a semiconductor structure 10 includes a plurality of dies 11 and a control circuit 12 .

[0109] In this embodiment, Figures 5 to 7 As shown, the semiconductor structure 10 includes a control circuit 12 and a plurality of crystal grains 11, wherein the plurality of crystal grains 11 are arranged along a first direction and a second direction, wherein the first direction and the second direction have a preset angle, and a cutting path 20 is arranged between two adjacent crystal grains 11, wherein the control circuit 12 is arranged in the cutting path 20 extending along the second direction, and the control circuit 12 is electrically connected to each crystal grain 11.

[0110] In one example, if Figure 7 As shown, the control circuit 12 includes a power management circuit, which can supply power and drive the die 11, and adjust the current and voltage of the die 11, so that the die 11 can operate normally.

[0111] In some embodiments, Figure 7 As shown, a redistribution layer (RDL) is disposed on the top surface of the die 11. The redistribution layer or metal wire layer can connect the internal circuit of the die 11 with external devices. In some embodiments, Figure 7 As shown, a self-refresh circuit is provided in the die 11, and the power management circuit can be electrically connected to the self-refresh circuit inside the die 11. The power management circuit is connected to the self-refresh circuit in the semiconductor structure 10, and is used to group the word lines, and determine the self-refresh timing according to the grouping result, thereby reducing the number of switching word lines during each refresh, thereby reducing the power consumption of the semiconductor package structure 200.

[0112] In some embodiments, Figure 7As shown, the semiconductor structure 10 further includes an interconnection through hole 13, which is disposed in the cutting path 20, and penetrates the cutting path 20 along the thickness direction of the cutting path 20, and the interconnection through hole 13 is electrically connected to the control circuit 12. It can be understood that when multiple semiconductor structures 10 are stacked to form a stacked structure 40, the interconnection through holes 13 of the multiple semiconductor structures 10 are electrically connected, so that the control circuits 12 of the multiple semiconductor structures 10 are electrically connected.

[0113] like Fig.10 As shown, the embodiment of the present disclosure also provides a semiconductor structure, which includes a substrate 60, wherein the substrate 60 includes a plurality of chip areas 61 and a cutting area 62, wherein the cutting area 62 is arranged between adjacent chip areas 61, and the cutting area 62 is provided with a control circuit 63, and the control circuit 63 controls the chip area 61; any chip area 61 has an independent chip function.

[0114] As an example, the substrate 60 may be a wafer, and the substrate 60 is provided with a plurality of chip regions 61. In some embodiments, the plurality of chip regions 61 are arranged in an array. The chip regions 61 have independent chip functions. For example, each chip region 61 includes a crystal grain, and each crystal grain may have an independent chip function.

[0115] The cutting area 62 separates the chip areas 61. As an example, the cutting area 62 may be a cutting path formed on the substrate 60. The control circuit 63 is disposed in the cutting area 62 and is used to control the chip area 61. As an example, the control circuit 63 includes a power management circuit, which can be used to power and drive the chip area 61, and adjust the current and voltage of the chip area 61 so that the chip area 61 can operate normally.

[0116] In the disclosed embodiment, the cutting area 62 is arranged between adjacent chip areas 61, and a control circuit 63 is arranged in the cutting area 62. The control circuit 63 is electrically connected to the adjacent chip area 61, and the chip area 61 can be controlled by the control circuit 63. It can be determined that one control circuit 63 can be electrically connected to at least two chip areas 61, that is, multiple chip areas 61 can be controlled by one control circuit 63, which is conducive to simplifying the circuit and reducing the difficulty of packaging. In addition, the control circuit 63 is arranged in the cutting area 62, which makes full use of the space of the cutting area 62, improves the integration of the semiconductor structure, reduces the size of the semiconductor structure, and is conducive to packaging.

[0117] refer to Fig.10In the semiconductor structure provided by the embodiment of the present disclosure, any chip area 61 on the substrate 60 has an independent chip function, and the control circuit 63 can independently control the adjacent chip areas 61 so that each chip area 61 can complete the corresponding function. In some optional implementations, if there is a chip area 61 that cannot work normally in the substrate 60, the substrate 60 can be cut along the cutting area 62 to retain the chip area 61 that can work normally in the substrate 60. Since any chip area 61 has an independent chip function, the retained chip area 61 can continue to be used, thereby improving the utilization rate of the chip area 61.

[0118] In some embodiments, reference Fig.10 The cutting area 62 of the semiconductor structure is provided with interconnection through holes 13, and the interconnection through holes 13 are arranged along the thickness direction of the cutting area 62 (reference Fig. 9 The z direction shown in FIG. 1 ) penetrates the cutting area 62. When multiple substrates 60 are stacked to form a semiconductor package structure, the interconnection through holes of the substrates 60 at different layers can be arranged opposite to each other, so that the substrates 60 at the upper and lower layers can be electrically connected. In one example, the interconnection through hole 13 can be a through silicon via.

[0119] In some embodiments, reference Fig.10 The semiconductor structure includes two chip regions 61, and the two chip regions 61 are provided with a cutting region 62, that is, the cutting region 62 is located between the two chip regions 61, and the extension direction of the cutting region 62 ( Fig. 9 The x direction shown in FIG) and the arrangement direction of the two chip regions 61 ( Fig.10 The y direction shown in ) is vertical.

[0120] In some implementations, reference Fig.10 The width of the cutting area is less than 60μm, that is, the distance between the two chip areas is less than 60μm, which is much smaller than the 200μm in the related technology, so that the semiconductor structure can be smaller in size, which is conducive to packaging and reducing the overall volume.

[0121] The semiconductor structure may be a first to fifth generation low power double data rate synchronous dynamic random access memory (LowPower Double Data Rate 1-5, LPDDR1-5 for short).

[0122] Based on the semiconductor structure provided in the above embodiment, Figure 8 and Fig. 9 As shown, the embodiment of the present disclosure further provides a semiconductor package structure 200 , which includes a package substrate 30 (Package Substrate) and a plurality of semiconductor structures 10 provided by the above embodiments.

[0123] The packaging substrate 30 serves as a carrier of the semiconductor structure 10. On the one hand, it can protect, fix, and support the semiconductor structure 10, enhance the thermal conductivity and heat dissipation performance of the semiconductor structure 10, and prevent physical damage to the semiconductor structure 10. On the other hand, one side of the packaging substrate 30 is electrically connected to the semiconductor structure 10, and the other side of the packaging substrate 30 can be electrically connected to an external circuit to realize signal transmission between the external circuit and the semiconductor structure 10.

[0124] refer to Figure 8 and Fig. 9 , the plurality of semiconductor structures 10 are arranged along the third direction ( Figure 8 The third direction is stacked on the packaging substrate 30, and the third direction is parallel to the first direction ( Figure 8 y direction shown in ) and the second direction ( Figure 8 The x direction shown in ) is vertical.

[0125] In one example, reference Figure 8 , the semiconductor package structure 200 may be an LPDDR5 chip, the LPDDR5 chip includes a first die group and a second die group arranged side by side, the first die group includes a plurality of stacked die 11. The semiconductor package structure 200 provided with the semiconductor structure 10 provided in the embodiment of the present disclosure, the spacing between the first die group and the second die group ( Figure 7 The width of the cutting path 20 (in the y direction shown in FIG. 1 ), that is, the width of the cutting path 20 , can be less than 60 μm, and the semiconductor packaging structure 200 is smaller in size and easier to package.

[0126] The plurality of semiconductor structures 10 are arranged along the third direction ( Figure 8 In some embodiments, each semiconductor structure 10 may be electrically connected to the package substrate 30 through a bonding wire 50. In other embodiments, multiple semiconductor structures 10 are electrically connected through silicon via technology, and the semiconductor structure at the top layer is electrically connected to the package substrate 30 through a bonding wire 50.

[0127] In one example, if Figure 8 As shown, multiple semiconductor structures 10 are stacked along the third direction, and the projections of any two adjacent semiconductor structures 10 along the third direction on the package substrate 30 completely overlap, and the projections of two semiconductor structures 10 arranged at intervals on the package substrate 30 completely overlap. In other words, the circumferential side surfaces of each semiconductor structure 10 are aligned.

[0128] In another example, refer to Fig. 9, multiple semiconductor structures 10 are stacked along the third direction, and the projections of any two adjacent semiconductor structures 10 along the third direction on the package substrate 30 partially overlap, and the projections of the two semiconductor structures 10 arranged at intervals on the package substrate 30 completely overlap. In other words, among any three semiconductor structures 10 stacked in sequence, the circumferential side surfaces of the two adjacent semiconductor structures 10 are staggered and misaligned, and the circumferential side surfaces of the two semiconductor structures 10 arranged at intervals are aligned.

[0129] The method for forming a semiconductor package structure may include the following steps:

[0130] Step S250 , stacking a plurality of semiconductor structures to form a stacked structure.

[0131] In this step, refer to Figure 4 and Figure 5 , taking the semiconductor structure 10 including two crystal grains 11 as an example, the semiconductor structure 10 including two crystal grains 11 can meet the packaging requirements of the fifth generation low power double data rate memory (Low Power Double Data Rate SDRAM, LPDDR) chip. In the LPDDR5 chip, reference Figure 1 and Figure 7 A portion of the die 11 is stacked together to form a first die group, and another portion of the die is stacked together to form a second die group. The first die group and the second die group are arranged side by side. This packaging method is called a side by side stacking packaging method.

[0132] As an example, see Figure 1 and Figure 7 , four semiconductor structures 10 are stacked in sequence to form a stacked structure 40, that is, when eight grains 11 form the stacked structure 40, four grains 11 are stacked together to form a first grain group, and the other four grains 11 are stacked together to form a second grain group, thereby meeting the packaging requirements of LPDDR5.

[0133] Continue to refer Figure 5 , the spacing between the first die group and the second die group is the sawing street 20 ( Figure 5 The width of the scribe line 20 is small, so that the size of the stacked structure 40 is small and it is convenient for packaging. In one example, the size of the scribe line 20 may be less than 60 μm.

[0134] After stacking a plurality of semiconductor structures to form a stacked structure 40, the method for manufacturing the semiconductor packaging structure further includes:

[0135] A packaging layer covering the stacked structure is formed.

[0136] The packaging layer may be formed of, for example, a material having electromagnetic wave shielding properties. The packaging layer is used to reduce signal interference between adjacent grains 11 and reduce signal interference generated by an external circuit on the semiconductor structure 10 .

[0137] In some embodiments, Figure 7 As shown, an interconnection through hole 13 is provided in the cutting street 20 of each semiconductor structure 10, and the interconnection through hole 13 penetrates the cutting street 20 in the thickness direction of the semiconductor structure 10 and is electrically connected to the control circuit 12. The interconnection through hole 13 is used to electrically connect the control circuits 12 in each stacked semiconductor structure 10 to realize the interconnection between the control circuits 12 of these semiconductor structures 10.

[0138] Continue to refer Figures 7 to 9 When multiple semiconductor structures are stacked, in the stacking direction of the semiconductor structure 10, the interconnection through holes 13 of the multiple semiconductor structures 10 are directly opposite in the stacking direction of the semiconductor structure 10 and are electrically connected to each other so that the multiple semiconductor structures 10 can be managed by the control circuit 12.

[0139] In one example, reference Figures 7 to 9 The control circuit 12 may be, for example, a power management circuit, which can manage and drive the power supply of multiple semiconductor structures 10, thereby reducing the power consumption of the semiconductor packaging structure 200.

[0140] In the semiconductor packaging structure 200 using the semiconductor structure 10 provided by the embodiment of the present disclosure, the control circuit 12 is arranged in the cutting path 20 between adjacent crystal grains 11, which fully utilizes the space of the cutting path 20 between the crystal grains 11, and does not need to be arranged separately in other positions of the semiconductor structure 10, thereby reducing the overall size of the semiconductor structure 10. At the same time, compared with the related art in which the control circuit is arranged in the filling space between adjacent crystal grains, the size requirement of the filling space between adjacent crystal grains 11 is reduced. In addition, multiple crystal grains 11 are electrically connected to the same control circuit 12, and multiple crystal grains 11 can be managed by one control circuit 12. Compared with the related art in which each crystal grain is managed by one control circuit, the number of control circuits 12 is reduced, thereby reducing the overall size of the semiconductor structure 10. Moreover, it can be directly packaged without cutting into individual crystal grains 11, which is beneficial to the packaging of the semiconductor structure 10.

[0141] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0142] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0143] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0144] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0145] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0146] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a wafer, the wafer comprising a plurality of crystal grains, the plurality of crystal grains being arranged along a first direction and a second direction, the first direction and the second direction having a preset angle, and having a cutting path between adjacent crystal grains; A control circuit is formed in a portion of the dicing path extending along the second direction and between the adjacent dies along the first direction, wherein the control circuit is electrically connected to the adjacent dies located on both sides of the control circuit in the first direction; The wafer is cut along the dicing lanes extending along the first direction and the dicing lanes extending along the second direction and not formed with the control circuit to form a plurality of the semiconductor structures.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method for manufacturing the semiconductor structure further includes: The plurality of dies are tested to determine whether each of the dies in each of the semiconductor structures is a good die or a bad die.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method for manufacturing the semiconductor structure further includes: An interconnection through hole is formed on the cutting path. The interconnection through hole penetrates the cutting path along the thickness direction of the cutting path and is electrically connected to the control circuit.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Each of the semiconductor structures comprises two crystal grains, and the control circuit is arranged between the two crystal grains in the same semiconductor structure; If the two crystal grains in the same semiconductor structure are respectively a good crystal grain and a bad crystal grain, the method for manufacturing the semiconductor structure includes: The semiconductor structure is cut along the cutting path where the control circuit is located, and the good grains are retained.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: A control circuit is formed in a portion of the dicing road extending along the second direction and between the dies adjacent to each other along the first direction, comprising: Among all the scribe lines extending along the second direction, the scribe lines on which the control circuit is formed and the scribe lines on which the control circuit is not formed are alternately arranged along the first direction.

6. A semiconductor structure, characterized in that: include: A plurality of crystal grains, wherein the plurality of crystal grains are arranged along a first direction and a second direction, the first direction and the second direction have a preset angle, and a cutting path is provided between two adjacent crystal grains; The control circuit is arranged on the cutting path, and the control circuit is electrically connected to each of the crystal grains.

7. The semiconductor structure according to claim 6, characterized in that: A redistribution layer and / or a top metal layer is arranged on the crystal grain; The control circuit includes a power management circuit, which is electrically connected to the redistribution layer and / or the top metal layer and is used to drive each of the crystal grains.

8. The semiconductor structure according to claim 7, characterized in that: The die is provided with a self-refresh circuit, and the power management circuit is electrically connected to the self-refresh circuit.

9. The semiconductor structure according to any one of claims 6 to 8, characterized in that: The semiconductor structure further includes an interconnection through hole, which is disposed in the cutting path, passes through the cutting path and is electrically connected to the control circuit.

10. The semiconductor structure according to claim 8, characterized in that The distance between two adjacent grains is less than 60 μm.

11. A semiconductor structure, characterized in that: A substrate is provided with a plurality of chip areas and a cutting area; The cutting area is arranged between adjacent chip areas, and a control circuit is arranged in the cutting area, and the control circuit controls the chip area; Any of the chip areas has an independent chip function.

12. The semiconductor structure according to claim 11, characterized in that: The cutting area is provided with interconnected through holes, and the interconnected through holes penetrate the cutting area along the thickness direction of the cutting area.

13. The semiconductor structure according to claim 11, characterized in that: There are two chip areas, and the cutting area is arranged between the two chip areas.

14. The semiconductor structure according to any one of claims 11 to 13, characterized in that: The width of the cutting area is less than 60 μm.

15. A semiconductor packaging structure, characterized in that: Comprising the semiconductor structure according to any one of claims 6 to 14.

16. The semiconductor package structure according to claim 15, characterized in that: The semiconductor package structure includes a package substrate and a plurality of semiconductor structures, wherein the plurality of semiconductor structures are stacked and arranged on the package substrate along a thickness direction of the package substrate.

17. The semiconductor package structure according to claim 16, wherein: The projections of two adjacent semiconductor structures on the packaging substrate at least partially overlap, and the projections of two semiconductor structures spaced apart on the packaging substrate completely overlap.

18. The semiconductor package structure according to claim 16 or 17, characterized in that: In the stacking direction of the semiconductor structures, the plurality of interconnection through holes of the plurality of semiconductor structures are directly opposite to each other, and the control circuits of the plurality of semiconductor structures are electrically connected through the interconnection through holes.

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