Semiconductor structure and forming method

Abstract

The invention provides a method for forming a semiconductor structure. The method comprises the following steps: providing a substrate; forming a first gate structure and a second gate structure on the surface of the substrate, wherein the width of the first gate structure in the channel direction is greater than that of the second gate structure in the channel direction; forming a first offset side wall layer on the side wall of the first gate structure, wherein the first offset side wall layer comprises a first oxide layer; a second offset side wall layer is formed on the side wall of the second gate structure, the second offset side wall layer comprises a second oxide layer, and the thickness of the first oxide layer is different from that of the second oxide layer; since the segregation effect in the oxide layers mainly affects the surface of the channel below the offset side wall layer, the diffusion degree is enhanced by differentially adjusting the oxidation of the bottoms of the first gate structure and the second gate structure through different thicknesses of the first oxide layer and the second oxide layer, so that the threshold voltage of the corresponding channel is improved, and the device has a wide application range.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] The pocket process in the lightly doped drain structure improves source-drain punchthrough and drain-induced barrier lowering (DIBL) effects. The pocket process uses ion implantation, and its implantation type is the same as the substrate type. It can suppress the lateral widening of the source-drain depletion region, prevent source-drain punchthrough, suppress the short channel effect, and increase the threshold voltage of the MOS tube. The pocket process is very effective for short-channel devices, while the impact on long-channel devices is almost negligible.

[0003] However, in the current IO process, NIO devices only have a lightly doped drain structure and no halo ion implantation process. When the threshold voltage of the long channel device is adjusted by changing the well (Well) implantation, there is no method similar to the halo ion implantation process that can effectively adjust the threshold voltage of the short channel, so the performance of the current NIO device still needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a forming method thereof, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first gate structure and a second gate structure on the surface of the substrate, wherein the width of the first gate structure in a channel direction is greater than the width of the second gate structure in the channel direction; forming a first offset spacer layer on the sidewall of the first gate structure, wherein the first offset spacer layer includes a first oxide layer; forming a second offset spacer layer on the sidewall of the second gate structure, wherein the second offset spacer layer includes a second oxide layer, and the thickness of the first oxide layer is different from the thickness of the second oxide layer.

[0006] Optionally, the thickness of the first oxide layer is smaller than the thickness of the second oxide layer.

[0007] Optionally, a ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in a range of 0.1:1-1:1.

[0008] Optionally, the first offset spacer layer further includes a first dielectric layer formed on a surface of the first oxide layer; and the second offset spacer layer further includes a second dielectric layer formed on a surface of the second oxide layer.

[0009] Optionally, the method for forming the first offset spacer layer and the second offset spacer layer includes: forming an initial first oxide layer covering the first gate structure and the second gate structure on the substrate; forming an initial intermediate dielectric layer on the surface of the initial first oxide layer; etching and removing the initial first oxide layer and the initial intermediate dielectric layer on the surface of the second gate structure, and forming the first oxide layer and the intermediate dielectric layer on the sidewalls of the first gate structure; forming an initial second oxide layer on the sidewalls and top surface of the second gate structure; forming an initial second dielectric layer on the surface of the initial second oxide layer and the surface of the intermediate dielectric layer; etching and removing part of the initial second dielectric layer, the initial second oxide layer, the intermediate dielectric layer and the first oxide layer, forming the second oxide layer and the second dielectric layer on the sidewalls of the second gate structure, forming the first oxide layer and the first dielectric layer on the sidewalls of the first gate structure, and the intermediate dielectric layer and the second dielectric layer constitute the first dielectric layer.

[0010] Optionally, the material of the first dielectric layer includes silicon nitride, and the material of the second dielectric layer includes silicon nitride.

[0011] Optionally, a ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer is in a range of 1.25:1-2:1.

[0012] Optionally, the thickness of the first offset spacer layer is the same as the thickness of the second offset spacer layer.

[0013] Optionally, before forming the first gate structure and the second gate structure, the method further includes forming a well region in the substrate, and the first gate structure and the second gate structure are formed on a surface of the substrate in the well region.

[0014] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate; a first gate structure located on the substrate; a second gate structure located on the substrate, the width of the first gate structure in the channel direction being greater than the width of the second gate structure in the channel direction; a first offset spacer layer located on the sidewall and top surface of the first gate structure, the first offset spacer layer comprising a first oxide layer; a second offset spacer layer located on the sidewall and top surface of the second gate structure, the second offset spacer layer comprising a second oxide layer, and the thickness of the first oxide layer is different from the thickness of the second oxide layer.

[0015] Optionally, the thickness of the first oxide layer is smaller than the thickness of the second oxide layer.

[0016] Optionally, a ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in a range of 0.1:1-1:1.

[0017] Optionally, the first offset spacer layer further includes: a first dielectric layer located on the side wall surface of the first oxide layer; the second offset spacer layer further includes: a second dielectric layer located on the side wall surface of the second oxide layer, and the thickness of the first offset spacer layer is the same as the thickness of the second offset spacer layer.

[0018] Optionally, it further includes a well region located in the substrate, and the first gate structure and the second gate structure are formed on a surface of the substrate in the well region.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] In the method for forming a semiconductor structure of the present invention, a first gate structure and a second gate structure are formed on the surface of a substrate, the width of the first gate structure in the channel direction is greater than the width of the second gate structure on the channel, a first offset sidewall layer is formed on the sidewall and top surface of the first gate structure, wherein the first offset sidewall layer includes a first oxide layer, and a second offset sidewall layer is formed on the sidewall and top surface of the second gate structure, wherein the second offset sidewall layer includes a second oxide layer, wherein the thickness of the first oxide layer and the second oxide layer are different; since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, the degree of bottom oxidation enhancement diffusion of the first gate structure and the second gate structure is differentially adjusted through the different thicknesses of the first oxide layer and the second oxide layer, and there is no need to perform lightly doped drain injection (LDD), thereby improving the threshold voltage of the corresponding channel, and the method has a wider range of applications.

[0021] Furthermore, the thickness of the first oxide layer is smaller than the thickness of the second oxide layer, and subsequently source-drain doping layers are formed on the substrate on both sides of the gate structure. The solid solubility of the doped ions in the source-drain doping layers in the oxide layer is greater than the solid solubility in the silicon substrate, and therefore they gather and diffuse toward one side of the oxide layer. By taking advantage of the fact that the thickness of the first oxide layer is smaller than that of the second oxide layer, the doping concentration on the surface of the channel at the bottom of the second gate structure is greater than the doping concentration on the surface of the channel at the bottom of the first gate structure, and the threshold voltage corresponding to the channel at the bottom of the second gate structure is greater than the threshold voltage corresponding to the channel at the bottom of the first gate structure, thereby effectively adjusting the threshold voltage of the short channel (the channel at the bottom of the second gate structure between the source-drain doping regions). BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 6 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] As mentioned in the background art, in the current IO process, the NIO device only has a lightly doped drain structure and no halo ion implantation process, so it is difficult to adjust the threshold voltage of the NIO device under the short channel only.

[0024] After research, the inventors found that a first gate structure and a second gate structure are formed on the surface of a substrate, the width of the first gate structure in the channel direction is greater than the width of the second gate structure on the channel, a first offset sidewall layer is formed on the sidewall and top surface of the first gate structure, wherein the first offset sidewall layer includes a first oxide layer, and a second offset sidewall layer is formed on the sidewall and top surface of the second gate structure, wherein the second offset sidewall layer includes a second oxide layer, wherein the thickness of the first oxide layer and the second oxide layer are different; since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, the different thicknesses of the first oxide layer and the second oxide layer can be used to differentially adjust the degree of bottom oxidation enhancement diffusion of the first gate structure and the second gate structure, thereby improving the threshold voltage of the corresponding channel, and the invention has a wider range of applications.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figures 1 to 6 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0027] Please refer to Figure 1 , providing a substrate 100.

[0028] In this embodiment, the substrate 100 is made of silicon.

[0029] In other embodiments, the material of the substrate 100 also includes semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, and gallium arsenide.

[0030] Please continue to refer to Figure 1 , ion implantation is performed on the substrate 100 to form a well region 100 ′.

[0031] In this embodiment, the ions doped in the well region 100 ′ include B ions.

[0032] Please refer to Figure 2 The first gate structure 101 and the second gate structure 102 are formed on the surface of the substrate 100 , and the width of the first gate structure 101 in the channel direction is greater than the width of the second gate structure 102 in the channel direction.

[0033] In this embodiment, the direction of the channel refers to a thin semiconductor layer between source and drain doping regions, wherein the source and drain doping regions are formed in the substrate on both sides of the gate structure, so the channel is a thin substrate layer at the bottom of the gate structure between the source and drain doping regions.

[0034] In this embodiment, the width of the first gate structure 101 in the channel direction is greater than the width of the second gate structure 102 in the channel direction. After the source and drain doping regions are subsequently formed in the substrate 100 on both sides of the gate structure, a thin substrate 100 at the bottom of the first gate structure 101 is defined as a long channel, and a thin substrate 100 at the bottom of the second gate structure 102 is defined as a short channel.

[0035] In this embodiment, the first gate structure 101 includes a first gate dielectric layer 101b formed on the surface of the substrate 100 and a first gate layer 101a formed on the surface of the first gate dielectric layer 101b. The material of the first gate dielectric layer 101b is silicon oxide, and the material of the first gate layer 101a is polysilicon.

[0036] In this embodiment, the second gate structure 102 includes a second gate dielectric layer 102b formed on the surface of the substrate 100 and a second gate layer 102a formed on the surface of the second gate dielectric layer 102b. The material of the second gate dielectric layer 102b is silicon oxide, and the material of the second gate layer 102a is polysilicon.

[0037] For the process of forming the first offset spacer layer on the sidewall of the first gate structure 101 and the second offset spacer layer on the sidewall of the second gate structure 102, please refer to Figures 3 to 6 .

[0038] Please refer to Figure 3 , forming an initial first oxide layer 103 covering the first gate structure 101 and the second gate structure 102 on the substrate 100 ; and forming an initial intermediate dielectric layer 104 on the surface of the initial first oxide layer 103 .

[0039] In this embodiment, the material of the initial first oxide layer 103 is silicon oxide.

[0040] In this embodiment, the material of the initial intermediate dielectric layer 104 is silicon nitride.

[0041] Please refer to Figure 4 , the initial first oxide layer 103 and the initial intermediate dielectric layer 104 are etched to form the first oxide layer 105 and the intermediate dielectric layer 106 on the sidewalls of the first gate structure 101 .

[0042] In this embodiment, the first oxide layer 105 and the intermediate dielectric layer 106 are also formed on the top surface of the first gate structure 101 .

[0043] In this embodiment, after the intermediate dielectric layer 106 is formed on the side wall of the first oxide layer 105, in the subsequent process of forming the second oxide layer on the side wall of the second gate structure 102, the second oxide layer will not be formed on the surface of the intermediate dielectric layer 106, thereby reducing the process steps and reducing the damage to the first gate structure 101.

[0044] Please refer to Figure 5 , an initial second oxide layer 107 is formed on the sidewalls and top surface of the second gate structure 102 ; and an initial second dielectric layer 108 is formed on the surface of the initial second oxide layer 107 and the surface of the intermediate dielectric layer 106 .

[0045] In this embodiment, the material of the initial second oxide layer 107 is silicon oxide.

[0046] In this embodiment, the material of the initial second dielectric layer 108 is silicon nitride.

[0047] Please refer to Figure 6 , partially etching and removing the initial second dielectric layer 108, the initial second oxide layer 107, the intermediate dielectric layer 106 and the first oxide layer 105, forming the second oxide layer 109 and the second dielectric layer 110 on the sidewalls of the second gate structure 102, forming the first oxide layer 105 and the first dielectric layer 111 on the sidewalls of the first gate structure 101, and the intermediate dielectric layer 106 and the second dielectric layer 109 constitute the first dielectric layer 111.

[0048] In this embodiment, the second oxide layer 109 and the second dielectric layer 110 constitute the second offset spacer 113 , and the first oxide layer 105 and the first dielectric layer 111 constitute the first offset spacer 112 .

[0049] In the present embodiment, the thickness of the first oxide layer 105 is different from that of the second oxide layer 109, and the doped ions in the well region 100' will experience a segregation effect in the high-temperature oxidation environment in which the oxide layer is generated. Since the solid solubility of the doped ions in the well region 100' in the oxide layer is greater than that in the substrate, the doped ions in the well region 100' will gather and diffuse toward one side of the oxide layer, thereby increasing the doping concentration on the channel surface and thus increasing the threshold voltage. Since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, the different thicknesses of the first oxide layer 105 and the second oxide layer 109 can be used to differentially adjust the degree of bottom oxidation enhancement diffusion of the first gate structure 101 and the second gate structure 102, thereby increasing the threshold voltage of the corresponding channel, and the invention has a wider range of applications.

[0050] In this embodiment, the thickness of the first oxide layer 105 is less than the thickness of the second oxide layer 109. The thicker second oxide layer 109 is used to increase the threshold voltage of the short channel and reduce the difference between the short channel threshold voltage and the long channel threshold voltage, so that the increased short channel threshold voltage is close to the long channel threshold voltage, thereby effectively adjusting the threshold voltage of the short channel.

[0051] In this embodiment, the ratio of the thickness of the first oxide layer 105 to the thickness of the second oxide layer 109 is in the range of 0.1:1-1:1. Due to the short channel effect, the threshold voltage of the short channel device will decrease, resulting in an increase in leakage current. By adjusting the thickness of the first oxide layer, the diffusion of the B element can be adjusted, so that the surface B element content increases, the threshold voltage of the device is increased, and the leakage current of the short channel device is reduced.

[0052] In this embodiment, the thickness of the first offset spacer 112 is the same as the thickness of the second offset spacer 113 .

[0053] In other embodiments, the thickness of the first offset spacer layer 112 and the thickness of the second offset spacer layer 113 may be different.

[0054] In this embodiment, the ratio of the thickness of the first dielectric layer 111 to the thickness of the second dielectric layer 110 is in the range of 1.25:1-1:1. Since the back-end of the long-short channel device is consistent, by changing the thickness of the second dielectric layer 110 so that the thickness of the second dielectric layer 110 plus the second oxide layer 109 is equal to the thickness of the first dielectric layer 111 plus the first oxide layer 105, it is beneficial to maintain the consistency of the back-end design of the device and maintain the breakdown voltage of the device.

[0055] Correspondingly, the present invention also provides a semiconductor structure, including a substrate 100; a first gate structure 101 located on the substrate 100; a second gate structure located on the substrate 100, the width of the first gate structure 101 in the channel direction being greater than the width of the second gate structure 102 in the channel direction; a first offset spacer layer 112 located on the sidewall and top surface of the first gate structure 101, the first offset spacer layer 112 including a first oxide layer; a second offset spacer layer 113 located on the sidewall and top surface of the second gate structure 102, the second offset spacer layer 113 including a second oxide layer 109, and the thickness of the first oxide layer 105 is different from the thickness of the second oxide layer 109.

[0056] In this embodiment, ion implantation is further performed on the substrate 100 to form a well region 100 ′.

[0057] In this embodiment, the ions doped in the well region 100 ′ include B ions.

[0058] In this embodiment, the doped ions in the well region 100' will undergo a segregation effect in the high-temperature oxidation environment in which the oxide layer is generated. Since the solid solubility of the doped ions in the well region 100' in the oxide layer is greater than that in the substrate, the doped ions in the well region 100' will gather and diffuse toward one side of the oxide layer, thereby increasing the doping concentration on the channel surface and thus increasing the threshold voltage. Since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, the thickness of the first oxide layer 105 and the second oxide layer 109 are different, and the degree of oxidation enhancement diffusion at the bottom of the first gate structure 101 and the second gate structure 102 is differentially adjusted, thereby increasing the threshold voltage of the corresponding channel, and has a wider range of applications.

[0059] In this embodiment, the thickness of the first oxide layer 105 is smaller than that of the second oxide layer 109, and the threshold voltage corresponding to the short channel at the bottom of the second gate structure 102 is greater than the threshold voltage corresponding to the long channel at the bottom of the first gate structure 101, thereby effectively adjusting the threshold voltage of the short channel.

[0060] In this embodiment, the ratio of the thickness of the first oxide layer 105 to the thickness of the second oxide layer 109 is in the range of 0.1:1-1:1.

[0061] In this embodiment, the first offset spacer layer 112 further includes: a first dielectric layer located on the side wall surface of the first oxide layer 105; the second offset spacer layer 113 further includes: a second dielectric layer located on the side wall surface of the second oxide layer 109, and the thickness of the first offset spacer layer 112 is the same as the thickness of the second offset spacer layer 113.

[0062] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first gate structure and a second gate structure on the surface of the substrate, wherein a width of the first gate structure in a channel direction is greater than a width of the second gate structure in the channel direction; Forming a first offset spacer layer on the sidewall of the first gate structure, wherein the first offset spacer layer includes a first oxide layer; A second offset spacer is formed on the sidewall of the second gate structure, wherein the second offset spacer includes a second oxide layer, and the thickness of the first oxide layer is different from the thickness of the second oxide layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first oxide layer is smaller than the thickness of the second oxide layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in the range of 0.1:1-1:

1.

4. The method for forming a semiconductor structure according to claim 1, wherein: The first offset spacer layer further includes a first dielectric layer formed on the surface of the first oxide layer; the second offset spacer layer further includes a second dielectric layer formed on the surface of the second oxide layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the first offset spacer layer and the second offset spacer layer includes: forming an initial first oxide layer covering the first gate structure and the second gate structure on the substrate; forming an initial intermediate dielectric layer on the surface of the initial first oxide layer; etching and removing the initial first oxide layer and the initial intermediate dielectric layer on the surface of the second gate structure, forming the first oxide layer and the intermediate dielectric layer on the sidewall of the first gate structure; forming an initial second oxide layer on the sidewall and top surface of the second gate structure; forming an initial second dielectric layer on the surface of the initial second oxide layer and the surface of the intermediate dielectric layer; etching and removing part of the initial second dielectric layer, the initial second oxide layer, the intermediate dielectric layer and the first oxide layer, forming the second oxide layer and the second dielectric layer on the sidewall of the second gate structure, forming the first oxide layer and the first dielectric layer on the sidewall of the first gate structure, and the intermediate dielectric layer and the second dielectric layer constitute the first dielectric layer.

6. The method for forming a semiconductor structure according to claim 4, wherein: The ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer is in the range of 1.25:1-2:

1.

7. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first gate structure and the second gate structure, the method further includes forming a well region in the substrate, wherein the first gate structure and the second gate structure are formed on a surface of the substrate in the well region.

8. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first offset spacer layer is the same as the thickness of the second offset spacer layer.

9. A semiconductor structure, characterized in that: include: substrate; a first gate structure located on the substrate; a second gate structure located on the substrate, wherein a width of the first gate structure in a channel direction is greater than a width of the second gate structure in the channel direction; A first offset spacer layer located on the sidewall and top surface of the first gate structure, wherein the first offset spacer layer comprises a first oxide layer; A second offset spacer layer is located on the sidewall and top surface of the second gate structure, the second offset spacer layer includes a second oxide layer, and the thickness of the first oxide layer is different from the thickness of the second oxide layer.

10. The semiconductor structure according to claim 9, wherein: The thickness of the first oxide layer is smaller than the thickness of the second oxide layer.

11. The semiconductor structure according to claim 9, wherein: The ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in the range of 0.1:1-1:

1.

12. The semiconductor structure according to claim 9, wherein: The first offset spacer layer further includes: a first dielectric layer located on the side wall surface of the first oxide layer; the second offset spacer layer further includes: a second dielectric layer located on the side wall surface of the second oxide layer, and the thickness of the first offset spacer layer is the same as that of the second offset spacer layer.

13. The semiconductor structure according to claim 9, wherein: The method further includes a well region located in the substrate, wherein the first gate structure and the second gate structure are formed on a surface of the substrate in the well region.

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