Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the following steps: providing a substrate, and forming a buried layer in the substrate; forming a first epitaxial layer on the top surface of the substrate, wherein the first epitaxial layer covers the top surface of the substrate; forming a first groove in the first epitaxial layer, wherein the first groove corresponds to the buried layer in position; forming a first injection well in the first epitaxial layer on the bottom surface of the first groove through an ion injection process, wherein the buried layer and the first injection well have the same conduction type; and executing a heat treatment process, diffusing the first injection well in the first epitaxial layer and the substrate, and enabling the bottom surface of the first injection well to be in contact with the buried layer so as to lead out the buried layer. Therefore, the connection reliability of the injection well in the epitaxial layer and the buried layer in the substrate can be improved, the electric leakage of the semiconductor device is reduced, and the electrical performance of the semiconductor device is improved. The invention also provides the semiconductor device manufactured by using the manufacturing method of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The BCD process is a technology that can integrate bipolar transistors, CMOS (complementary metal oxide semiconductor) and DMOS (double diffused metal oxide semiconductor) on a single chip. It has the characteristics of low cost, easy packaging, easy design and simpler peripheral chips, and has rapidly developed into the mainstream technology in the field of power ICs. The bipolar transistors in the BCD technology have high analog accuracy and are mainly used in analog circuits, CMOS has high integration and is mainly used in logic circuits, and DMOS has high power (high voltage) characteristics and is often used as a switch.

[0003] Figures 1 to 5 FIG. 1 is a schematic diagram of a process of manufacturing a conventional BCD device. The manufacturing method of the BCD device comprises the following steps: Figure 1 As shown, a first hard mask layer 21 is formed on the substrate 10, and a patterned first photoresist layer 22 is formed on the first hard mask layer 21. Ions are implanted into the substrate 10 using the patterned first photoresist layer 22 as a mask to form an N-type buried layer 11 in the substrate 10. Then, the first hard mask layer 21 and the patterned first photoresist layer 22 are removed. Figure 2 As shown, a first epitaxial layer 12 is formed on a substrate 10; Figure 3 As shown, a second hard mask layer 23 and a patterned second photoresist layer 24 are formed on the first epitaxial layer 12, and a first N well 13 is formed in the first epitaxial layer 12 by an ion implantation process using the patterned second photoresist layer 24 as a mask, and then the second hard mask layer 23 and the patterned second photoresist layer 24 are removed; Figure 4 As shown, a second epitaxial layer 14 is formed on the first epitaxial layer 12; Figure 5 As shown, a third hard mask layer 25 and a patterned third photoresist layer 26 are formed on the second epitaxial layer 14, and a second N well 15 located above the first N well 13 is formed in the second epitaxial layer 14 by an ion implantation process using the patterned third photoresist layer 26 as a mask.

[0004] However, as the thickness of the epitaxial layer increases, and due to the limitation of the injection energy of the ion implantation machine, the N-type well is not implanted deep enough when the N-type well is implanted in the thick epitaxial layer, which leads to insufficient contact area between the N-type well and the N-type buried layer, or even no contact. Figure 6As shown, the first N-well 13 is not in contact with the N-type buried layer 11, which causes leakage problems in the device and affects the electrical performance of the device. In addition, in the prior art, in order to enhance the connection between the N-well and the N-type buried layer, a larger injection energy and a longer heat treatment are usually required, but this greatly increases the manufacturing cost and time cost, and limits the application of the epitaxial layer. Therefore, the manufacturing process of the existing BCD device needs to be optimized. Summary of the invention

[0005] One of the purposes of the present invention is to improve the connection reliability between the implantation well and the buried layer, reduce the leakage of the semiconductor device, and improve the electrical performance of the semiconductor device.

[0006] In order to achieve the above-mentioned purpose, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device comprises: providing a substrate, forming a buried layer in the substrate; forming a first epitaxial layer on the top surface of the substrate, the first epitaxial layer covering the top surface of the substrate; forming a first trench in the first epitaxial layer, the first trench and the buried layer corresponding to each other; forming a first injection well in the first epitaxial layer at the bottom surface of the first trench by an ion implantation process, the buried layer and the first injection well have the same conductivity type; and performing a heat treatment process, the first injection well diffuses in the first epitaxial layer and the substrate, the bottom surface of the first injection well contacts the buried layer to lead out the buried layer.

[0007] Optionally, the method for forming a buried layer in the substrate includes: forming a first hard mask layer on the substrate, the first hard mask layer covering the substrate; forming a patterned first photoresist layer on the first hard mask layer; and performing an ion implantation process using the patterned first photoresist layer as a mask to form the buried layer in the substrate.

[0008] Optionally, the method for forming a first groove in the first epitaxial layer includes: forming a second hard mask layer on the top surface of the first epitaxial layer; forming a patterned second photoresist layer on the second hard mask layer; etching the second hard mask layer and the first epitaxial layer using the patterned second photoresist layer as an etching mask to form a first groove in the first epitaxial layer.

[0009] Optionally, after forming the first trench and before forming the first injection well, a protective layer is formed in the first trench, the protective layer covering the side walls and bottom surface of the first trench; in the step of forming the first injection well in the first epitaxial layer at the bottom surface of the first trench through an ion implantation process, the protective layer protects the first epitaxial layer.

[0010] Optionally, in the step of forming a first injection well in the first epitaxial layer at the bottom of the first trench through an ion implantation process, the first injection well contacts the top surface of the buried layer toward the bottom surface of the buried layer, or, there is a distance greater than zero between the bottom surface of the first injection well and the top surface of the buried layer.

[0011] Optionally, the method for manufacturing the semiconductor device also includes: after forming a first injection well in the first epitaxial layer at the bottom of the first trench through an ion implantation process and before performing a heat treatment process, forming a second epitaxial layer on the top surface of the first epitaxial layer, the second epitaxial layer covering the first epitaxial layer and filling the first trench; after performing the heat treatment process, forming a second injection well in the second epitaxial layer through an ion implantation process, the second injection well corresponding to the position of the first trench and in contact with the first injection well, and the second injection well and the first injection well have the same conductivity type.

[0012] Optionally, in the step of performing the heat treatment process, the top surface of the first injection well diffuses into the second epitaxial layer in the first trench, and the bottom surface of the first injection well diffuses at least to the top surface of the buried layer.

[0013] Optionally, after performing the heat treatment process, before forming a second injection well in the second epitaxial layer through an ion implantation process, a second trench is formed in the second epitaxial layer, and the second trench is located directly above the first trench; in the step of forming a second injection well in the second epitaxial layer through an ion implantation process, a second injection well is formed in the second epitaxial layer at the bottom of the second trench.

[0014] Optionally, after forming a second injection well in the second epitaxial layer by an ion implantation process, a top surface of the second epitaxial layer is planarized so that a top surface of the second injection well is flush with a top surface of the second epitaxial layer on a side of the second injection well.

[0015] The present invention also provides a semiconductor device. The semiconductor device comprises: a substrate; a buried layer located in the substrate; a first epitaxial layer located on the top surface of the substrate, the first epitaxial layer having a first groove, the first groove and the buried layer corresponding in position; and a first injection well, at least partially located in the first epitaxial layer at the bottom surface of the first groove, the first injection well and the buried layer have the same conductivity type, and the bottom surface of the first injection well contacts the buried layer to lead out the buried layer.

[0016] In the semiconductor device and its manufacturing method provided by the present invention, a first groove is formed in the first epitaxial layer, and then a first injection well is formed in the first epitaxial layer at the bottom of the first groove through an ion implantation process, so that the thickness of the first epitaxial layer in the first injection well formation area is reduced, so that the bottom surface of the first injection well is more easily in contact with the buried layer, which is beneficial to improving the connection reliability between the first injection well and the buried layer, reducing the leakage of the semiconductor device, and improving the electrical performance of the semiconductor device. In this way, there is no need to increase the ion implantation energy and increase the heat treatment time, which can reduce the manufacturing cost and time cost, and also reduce the restriction on the thickness of the epitaxial layer, that is, expand the application range of the epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1 to 5 The present invention is a schematic diagram of a process of manufacturing a conventional BCD device.

[0018] Figure 6 The figure is a schematic diagram showing the disadvantage that the N-well and the buried layer are not in contact when the BCD device is manufactured by the existing method for manufacturing the BCD device.

[0019] Figure 7 The present invention is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0020] Figures 8 to 16 A schematic diagram of a process of manufacturing a semiconductor device provided by an embodiment of the present invention.

[0021] Description of reference numerals: 10-substrate; 11-N-type buried layer; 12-first epitaxial layer; 13-first N-well; 14-second epitaxial layer; 15-second N-well; 21-first hard mask layer; 22-patterned first photoresist layer; 23-second hard mask layer; 24-patterned second photoresist layer; 25-third hard mask layer; 26-patterned third photoresist layer; 100-substrate; 101-buried layer; 102-first epitaxial layer; 103-first trench; 104-first injection well; 105-second epitaxial layer; 106-second trench; 107-second injection well; 201-first hard mask layer; 202-patterned first photoresist layer; 203-second hard mask layer; 204-patterned second photoresist layer; 205-first protective layer; 206-third hard mask layer; 207-patterned third photoresist layer; 208-second protective layer. DETAILED DESCRIPTION

[0022] In order to improve the connection reliability between the injection well and the buried layer, reduce the leakage of the semiconductor device, and improve the electrical performance of the semiconductor device, the present invention provides a semiconductor device and a manufacturing method thereof.

[0023] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] Figure 7 Flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 7 As shown, the method for manufacturing the semiconductor device includes: Step S1, providing a substrate, and forming a buried layer in the substrate; Step S2, forming a first epitaxial layer on the top surface of the substrate, wherein the first epitaxial layer covers the top surface of the substrate; Step S3, forming a first trench in the first epitaxial layer, wherein the first trench corresponds to the buried layer; Step S4, forming a first implantation well in the first epitaxial layer at the bottom surface of the first trench by an ion implantation process, wherein the buried layer and the first implantation well have the same conductivity type; and Step S5, performing a heat treatment process, the first injection well diffuses in the first epitaxial layer and the substrate, and the bottom surface of the first injection well contacts the buried layer to lead out the buried layer.

[0025] It should be understood that although Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0026] Figures 8 to 16 The following is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 7 , Figures 8 to 16 The method for manufacturing the semiconductor device provided by the present invention is described.

[0027] like Figure 8As shown, step S1 is performed to provide a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc. Certain doping particles may be implanted into the substrate 100 according to design requirements to change electrical parameters.

[0028] refer to Figure 8 As shown, a buried layer 101 is formed in a substrate 100. Exemplarily, the method for forming the buried layer 101 in the substrate 100 includes: forming a first hard mask layer 201 on the substrate 100, the first hard mask layer 201 covering the substrate 100; forming a patterned first photoresist layer 202 on the first hard mask layer 201, the patterned first photoresist layer 202 being formed by an exposure and development process; performing an ion implantation process using the patterned first photoresist layer 202 as a mask to form the buried layer 101 in the substrate 100; and removing the first hard mask layer 201 and the patterned first photoresist layer 202.

[0029] In this embodiment, the top surface of the buried layer 101 is flush with the top surface of the substrate 100. In other embodiments, as required, the top surface of the buried layer 101 may be located below the top surface of the substrate 100, that is, the top surface of the buried layer 101 may be located inside the substrate 100. It should be noted that the buried layer 101 provided in the substrate 100 can block most of the carriers from flowing from the surface to the body, thereby achieving efficient isolation of the semiconductor device.

[0030] In this embodiment, after performing the ion implantation process to form the buried layer 101 in the substrate 100, a heat treatment (Anneal) process may be performed to diffuse the buried layer 101 in the substrate 100, for example, to expand the bottom surface of the buried layer 101 toward the bottom surface of the substrate. The substrate 100 may be heat treated after removing the patterned first photoresist layer 202, so that the difficulty of removing the patterned first photoresist layer 202 can be reduced.

[0031] like Fig. 9 As shown, step S2 is performed to form a first epitaxial layer 102 on the top surface of the substrate 100 , and the first epitaxial layer 102 covers the top surface of the substrate 100 .

[0032] In this embodiment, the first epitaxial layer 102 may be formed on the substrate 100 by a selective epitaxial growth process, but the invention is not limited thereto. The material of the first epitaxial layer 102 may be the same as that of the substrate 100, but the invention is not limited thereto.

[0033] In this embodiment, the thickness of the first epitaxial layer 102 may be greater than or equal to 6 μm and less than or equal to 7 μm.

[0034] like Fig.10As shown, step S3 is performed to form a first trench 103 in the first epitaxial layer 102 , and the first trench 103 and the buried layer 101 are located correspondingly.

[0035] Specifically, the method for forming the first groove 103 in the first epitaxial layer 102 may include: forming a second hard mask layer 203 on the top surface of the first epitaxial layer 102; forming a patterned second photoresist layer 204 on the second hard mask layer 203; etching the second hard mask layer 203 and the first epitaxial layer 102 using the patterned second photoresist layer 204 as an etching mask to form the first groove 103 in the first epitaxial layer 102.

[0036] In this embodiment, the second hard mask layer 203 and the first epitaxial layer 102 may be etched by dry etching to form the first trench 103 , but the present invention is not limited thereto.

[0037] In this embodiment, the depth of the first trench 103 can be selected according to the thickness of the first epitaxial layer 102 .

[0038] like Fig.11 As shown, step S4 is performed to form a first implantation well 104 in the first epitaxial layer 102 at the bottom of the first trench 103 by an ion implantation process, and the buried layer 101 and the first implantation well 104 have the same conductivity type. Exemplarily, the buried layer 101 and the first implantation well 104 are both N-type, but not limited thereto.

[0039] In this embodiment, the first epitaxial layer 102 at the bottom of the first trench 103 is a first injection well formation region. Due to the existence of the first trench 103, the thickness of the first epitaxial layer in the first injection well formation region is reduced, thereby reducing the difficulty of the first injection well 104 contacting the buried layer 101.

[0040] refer to Fig.11 As shown, after forming the first trench 103 and before forming the first injection well 104, a first protection layer 205 may be formed in the first trench 103, and the first protection layer 205 covers the sidewalls and the bottom surface of the first trench 103; in the step of forming the first injection well 104 in the first epitaxial layer at the bottom surface of the first trench 103 by an ion implantation process, the first protection layer 205 may protect the first epitaxial layer 102, specifically, the inner surface of the first trench 103. The material of the first protection layer 205 may be the same as that of the second hard mask layer 203, but is not limited thereto. Fig.11 2. The boundary line between the first protection layer 205 and the second hard mask layer 203 is not shown in FIG. The first protection layer 205 may be formed by a thermal oxidation process, but is not limited thereto.

[0041] In some embodiments, in step S4, reference is made to Fig.11As shown, the bottom surface of the first injection well 104 facing the buried layer 101 may contact the top surface of the buried layer 101. In some embodiments, in step S4, the bottom surface of the first injection well 104 and the top surface of the buried layer 101 may have a spacing greater than zero, and after performing step S5, the bottom surface of the first injection well 104 may contact the buried layer 101.

[0042] Step S5 is executed to perform a heat treatment process, and the first implantation well 104 is diffused in the first epitaxial layer 102 and the substrate 100 . The bottom surface of the first implantation well 104 contacts the buried layer 101 to lead out the buried layer 101 .

[0043] In this embodiment, reference Fig.12 As shown, after forming a first injection well 104 in the first epitaxial layer 102 at the bottom of the first trench 103 by an ion implantation process and before performing a heat treatment process, a second epitaxial layer 105 can be formed on the top surface of the first epitaxial layer 102, and the second epitaxial layer 105 covers the first epitaxial layer 102 and fills the first trench 103.

[0044] Among them, since the second epitaxial layer 105 fills the first trench 103, as shown in FIG. Fig.12 As shown, there is a pit on the top surface of the second epitaxial layer 105 corresponding to the position of the first trench 103. After the second epitaxial layer 105 is formed, when step S5 is performed, compared with the reference Fig.12 and Fig.13 The top surface of the first injection well 104 diffuses into the second epitaxial layer 105 in the first groove 103, and the bottom surface of the first injection well 104 diffuses at least to the top surface of the buried layer. For example, the bottom surface of the first injection well 104 diffuses into the interior of the buried layer 101. In this way, the first injection well 104 spans into the second epitaxial layer 105, which facilitates the connection between the second injection well subsequently formed in the second epitaxial layer 105 and the first injection well 104, and helps to improve the reliability of the buried layer lead-out.

[0045] After performing the heat treatment process, such as Fig.15 As shown, a second injection well 107 can be formed in the second epitaxial layer 105 by an ion implantation process, the second injection well 107 corresponds to the position of the first trench 103 and contacts the first injection well 104, and the second injection well 107 and the first injection well 104 have the same conductivity type. It should be noted that in the step of forming the second injection well 107 by an ion implantation process, the second injection well 107 can be directly in contact with the first injection well 104, or the second injection well 107 can be thermally pushed after a heat treatment is performed on the second injection well 107 after the ion implantation process, so that the second injection well 107 contacts the first injection well 104. Specifically, the bottom surface of the second injection well 107 can extend into the first injection well 104.

[0046] In the present application, it can be selected whether to form a second trench corresponding to the position of the first trench in the second epitaxial layer 105 and then form the second injection well 107 according to the thickness of the second epitaxial layer 105. That is, when the second epitaxial layer 105 is thin, the second injection well 107 can be directly formed in the second epitaxial layer 105 after the second epitaxial layer 105 is formed; when the second epitaxial layer 105 is thick, the second injection well 107 can be directly formed in the second epitaxial layer 105 after the second epitaxial layer 105 is formed. Fig.15 As shown, a second trench 106 is formed in the second epitaxial layer 105, and the second trench 106 is located directly above the first trench 103, and then a second injection well 107 is formed in the second epitaxial layer 105 at the bottom of the second trench 106. This can reduce the difficulty of the second injection well 107 contacting the first injection well 104, which helps to improve the connection reliability between the second injection well 107 and the first injection well 104.

[0047] Taking the formation of the second trench 106 in the second epitaxial layer 105 as an example, specifically, Fig.14 As shown, a third hard mask layer 206 is formed on the top surface of the second epitaxial layer 105, and a patterned third photoresist layer 207 is formed on the third hard mask layer 206; the third hard mask layer 206 and the second epitaxial layer 105 are etched using the patterned third photoresist layer 207 as a mask to form a second trench 106 in the second epitaxial layer 105; Fig.15 As shown, a second protective layer 208 is formed in the second trench 106 , and the second protective layer 208 covers the sidewalls and the bottom surface of the second trench 106 ; a second implantation well 107 is formed in the second epitaxial layer 105 at the bottom surface of the second trench 106 by an ion implantation process.

[0048] In the step of forming the second implantation well 107 in the second epitaxial layer at the bottom of the second trench 106 by ion implantation, the second protective layer 208 can protect the surface of the second epitaxial layer 105. The material of the second protective layer 208 can be the same as that of the third hard mask layer 206, but is not limited thereto. Fig.15 2. The boundary line between the second protection layer 208 and the third hard mask layer 206 is not shown in FIG. The second protection layer 208 may be formed by a thermal oxidation process, but is not limited thereto.

[0049] In this embodiment, the patterned third photoresist layer 207 and the patterned second photoresist layer 204 can be formed by exposure using the same mask, that is, the width and position of the first groove 103 and the second groove 106 can be defined by the same mask, which helps save masks and helps save costs.

[0050] In this embodiment, the hard mask layer includes a first hard mask layer 201, a second hard mask layer 203 and a third hard mask layer 206. The material of the hard mask layer includes one or more combinations of oxide, nitride or oxynitride, but is not limited thereto. Taking the hard mask layer as a silicon oxide layer as an example, the silicon oxide layer can be formed by a process known to those skilled in the art, such as a dry oxygen process or a chemical vapor deposition process.

[0051] After forming the second implantation well 107 in the second epitaxial layer 105 by an ion implantation process, as shown in FIG. Fig.16 As shown, the top surface of the second epitaxial layer 105 may be planarized so that the top surface of the second injection well 107 is flush with the top surface of the second epitaxial layer at the side of the second injection well 107. The planarization process may be implemented by a chemical mechanical polishing (CMP) process.

[0052] The method for manufacturing the semiconductor device of this embodiment can be used to manufacture a BCD device.

[0053] This embodiment further provides a semiconductor device, which can be manufactured using the above-mentioned method for manufacturing a semiconductor device. The semiconductor device can be a BCD device, but is not limited thereto.

[0054] like Fig.16 As shown, the semiconductor device includes a substrate 100, a buried layer 101, a first epitaxial layer 102 and a first injection well 104. The buried layer 101 is located in the substrate 100; the first epitaxial layer 102 is located on the top surface of the substrate 100, and the first epitaxial layer 102 has a first trench 103, and the first trench 103 and the buried layer 101 are located at corresponding positions; the first injection well 104 is at least partially located in the first epitaxial layer 102 at the bottom of the first trench 103, the first injection well 104 and the buried layer 101 have the same conductivity type, and the bottom surface of the first injection well 104 contacts the buried layer 101 to lead out the buried layer 101.

[0055] Illustratively, a bottom surface of the first implantation well 104 may extend into the buried layer 101 .

[0056] The semiconductor device may further include a second epitaxial layer 105, which is located on the top surface of the first epitaxial layer 102 and fills the first trench 103. A second injection well 107 is formed in the second epitaxial layer 105, and the second injection well 107 corresponds to the position of the first trench 103 and is in contact with the first injection well 104. The second injection well 107 and the first injection well 104 have the same conductivity type, and the second injection well 107 and the first injection well 104 jointly lead out the buried layer 101.

[0057] In this embodiment, the top of the first implantation well 104 may diffuse and extend into the second epitaxial layer 105 in the first trench 103 .

[0058] In the semiconductor device and the manufacturing method thereof provided by the present invention, a first groove 103 is formed in the first epitaxial layer 102, and then a first injection well 104 is formed in the first epitaxial layer at the bottom of the first groove 103 by an ion implantation process, so that the thickness of the first epitaxial layer in the first injection well formation area is reduced, so that the bottom surface of the first injection well 104 is more easily in contact with the buried layer 101, which is beneficial to improving the connection reliability between the first injection well 104 and the buried layer 101, reducing the leakage of the semiconductor device, and improving the electrical performance of the semiconductor device. In this way, there is no need to increase the ion implantation energy and increase the heat treatment time, which can reduce the manufacturing cost and time cost, and also reduce the restriction on the thickness of the epitaxial layer, that is, expand the application range of the epitaxial layer.

[0059] It should be noted that this specification adopts a progressive description method, and the semiconductor device described later focuses on the differences from the manufacturing method of the semiconductor device described earlier, and the same and similar parts between the various parts can be referred to each other.

[0060] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate in which a buried layer is formed; forming a first epitaxial layer on the top surface of the substrate, wherein the first epitaxial layer covers the top surface of the substrate; forming a first trench in the first epitaxial layer, wherein the first trench corresponds to the buried layer; Forming a first implantation well in the first epitaxial layer at the bottom surface of the first trench by an ion implantation process, wherein the buried layer and the first implantation well have the same conductivity type; as well as A thermal treatment process is performed, the first implantation well is diffused in the first epitaxial layer and the substrate, and a bottom surface of the first implantation well contacts the buried layer to lead out the buried layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming a buried layer in the substrate comprises: forming a first hard mask layer on the substrate, the first hard mask layer covering the substrate; forming a patterned first photoresist layer on the first hard mask layer; performing an ion implantation process using the patterned first photoresist layer as a mask to form the buried layer in the substrate.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming a first groove in the first epitaxial layer includes: forming a second hard mask layer on the top surface of the first epitaxial layer; forming a patterned second photoresist layer on the second hard mask layer; etching the second hard mask layer and the first epitaxial layer using the patterned second photoresist layer as an etching mask to form a first groove in the first epitaxial layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the first trench and before forming the first injection well, forming a protection layer in the first trench, wherein the protection layer covers the sidewall and bottom surface of the first trench; In the step of forming a first implantation well in the first epitaxial layer at the bottom surface of the first trench by an ion implantation process, the protection layer protects the first epitaxial layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: In the step of forming a first injection well in the first epitaxial layer at the bottom of the first trench by an ion implantation process, the first injection well contacts the top surface of the buried layer toward the bottom surface of the buried layer, or a distance greater than zero is provided between the bottom surface of the first injection well and the top surface of the buried layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for manufacturing the semiconductor device further includes: After forming a first implantation well in the first epitaxial layer at the bottom surface of the first trench by an ion implantation process and before performing a heat treatment process, forming a second epitaxial layer on the top surface of the first epitaxial layer, wherein the second epitaxial layer covers the first epitaxial layer and fills the first trench; After performing the heat treatment process, a second injection well is formed in the second epitaxial layer through an ion implantation process, the second injection well corresponds to the position of the first trench and contacts the first injection well, and the second injection well and the first injection well have the same conductivity type.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: In the step of performing the heat treatment process, the top surface of the first implantation well diffuses into the second epitaxial layer in the first trench, and the bottom surface of the first implantation well diffuses at least to the top surface of the buried layer.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: After performing a heat treatment process, before forming a second implantation well in the second epitaxial layer by an ion implantation process, forming a second trench in the second epitaxial layer, wherein the second trench is located directly above the first trench; In the step of forming a second implantation well in the second epitaxial layer by an ion implantation process, the second implantation well is formed in the second epitaxial layer at the bottom surface of the second trench.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: After forming a second injection well in the second epitaxial layer by an ion implantation process, a top surface of the second epitaxial layer is planarized so that the top surface of the second injection well is flush with the top surface of the second epitaxial layer at the side of the second injection well.

10. A semiconductor device, characterized in that: include: substrate; a buried layer located in the substrate; A first epitaxial layer, located on the top surface of the substrate, wherein the first epitaxial layer has a first trench, and the first trench corresponds to the buried layer; as well as The first injection well is at least partially located in the first epitaxial layer at the bottom of the first trench. The first injection well and the buried layer have the same conductivity type. The bottom surface of the first injection well contacts the buried layer to lead out the buried layer.

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