Efficient heat dissipation chip packaging structure and chip with same
The dual-sided heat dissipation channels in the chip packaging structure address the inefficiencies of single-sided heat dissipation, improving efficiency and stability by over 30% and stabilizing chip performance through temperature equalization.
Patent Information
- Application Number
- CN202411487258.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-19
- Publication Date
- 2024-12-20
Smart Images
Figure CN119170584A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip heat dissipation, and in particular relates to a chip packaging structure with high-efficiency heat dissipation and a chip with the structure. Background Art
[0002] Against the backdrop of increasing demand for supercomputing services, the use of Ai chips and supercomputing chips has begun to increase. These chips have more advanced manufacturing processes, high power consumption, and high heat generation, and the heat dissipation solution is still at the system level. Although these chips use the Open Moding process during packaging and use the back of the die as the exposed heat dissipation surface, this single heat dissipation surface can no longer meet the heat dissipation needs of higher-manufactured chips. The front of the die and the welding surface of the substrate are separated by an insulating layer, and the existing process does not perform special heat dissipation treatment in a targeted manner. This will accumulate a lot of heat on the front side of the chip, resulting in a temperature difference between the two sides of the chip. This temperature difference will further affect the performance of the chip and the system. Summary of the invention
[0003] The object of the present invention is to provide a chip packaging structure with high efficiency in heat dissipation and a chip with the structure, so as to solve the above-mentioned problems existing in the prior art.
[0004] In order to achieve the above object, the present invention adopts the following technical solutions:
[0005] In a first aspect, the present invention provides a chip packaging structure with high efficiency in heat dissipation, comprising a chip housing, a chip die and a PCB substrate, wherein the chip housing is arranged on the PCB substrate, a first heat sink is arranged on the top of the chip die, the first heat sink is connected to the chip housing, and the chip die is packaged in the chip housing, a heat dissipation conductive member is arranged on the bottom of the chip die, the heat dissipation conductive member is connected to the PCB substrate, the PCB substrate comprises a connected substrate heat dissipation layer, a contact surface between the PCB substrate and the heat dissipation conductive member exposes the substrate heat dissipation layer, the substrate heat dissipation layer is connected to the heat dissipation conductive member, and a second heat sink is connected to a side of the substrate heat dissipation layer facing away from the heat dissipation conductive member.
[0006] When it is used, the chip die is exposed through the process, so that the first heat sink on the top of the chip die can effectively dissipate the heat of the top surface of the chip die, and the heat of the top surface of the chip die can be dissipated to the external environment. The heat dissipation conductive member at the bottom of the chip die can effectively dissipate the heat of the bottom surface of the chip die, and the heat of the bottom surface of the chip die can be conducted to the substrate heat dissipation layer of the PCB substrate, and then conducted to the second heat sink through the substrate heat dissipation layer, and finally the heat can be dissipated to the external environment through the second heat sink. Through the design of heat dissipation at both ends, an efficient heat conduction path from the inside to the outside of the chip can be formed, greatly increasing the heat dissipation efficiency of the chip after packaging. In addition, by dissipating the heat on the two end surfaces of the chip die, the temperature difference between the two sides of the chip die can be effectively leveled, greatly improving the instability problem of the chip caused by the temperature difference during high-speed operation or calculation.
[0007] In a possible design, the PCB substrate further includes a connected electrical connection layer, the electrical connection layer is conductive, the bottom surface of the chip die is provided with a conductive pad, the conductive pad is connected to the PCB substrate, and the contact surface between the PCB substrate and the conductive pad exposes the electrical connection layer, so that the electrical connection layer and the conductive pad are electrically connected. When it is used, the conductive pad of the chip die is connected through the electrical connection layer of the PCB substrate, which can provide the chip die with electrical paths for various signals and power supply, thereby ensuring the normal operation of the chip.
[0008] In a possible design, the PCB substrate further includes a connected insulating adhesive layer, which is provided between the substrate heat dissipation layer and the electrical connection layer, and is used to bond the substrate heat dissipation layer and the electrical connection layer, and to thermally and electrically separate the substrate heat dissipation layer and the electrical connection layer. When used, through the design of the thermal and electrical separation process, the insulating adhesive layer can be made to bond the substrate heat dissipation layer and the electrical connection layer respectively, and at the same time, the substrate heat dissipation layer and the electrical connection layer can be thermally and electrically separated, thereby ensuring that the thermal conduction path of the substrate heat dissipation layer and the conductive path of the electrical connection layer are independent of each other and do not affect each other.
[0009] In a possible design, the PCB substrate is also provided with functional electronic components, the conductive ends of the functional electronic components are electrically connected to the electrical connection layer, and the heat dissipation surface of the functional electronic components is connected to the substrate heat dissipation layer. When it is used, by integrating other functional electronic components on the PCB substrate, it can be matched with the chip bare die of the main body to play a corresponding auxiliary role in the operation function. The PCB substrate connects the conductive ends of the functional electronic components through the electrical connection layer, so that the functional electronic components are effectively connected to the conductive path, and the PCB substrate connects the heat dissipation surface of the functional electronic components through the substrate heat dissipation layer, so that the functional electronic components are effectively connected to the heat conduction path, and the stable operation of the functional electronic components is simultaneously guaranteed.
[0010] In a possible design, the PCB substrate is a copper substrate. When used, the copper substrate has excellent thermal conductivity, which is beneficial to the operation and heat dissipation of the chip, and the copper substrate has good processing performance and stability.
[0011] In a possible design, the heat dissipation conductive member is made of copper-based material, aluminum-based material or ceramic material. When used, the heat dissipation conductive member made of copper-based material, aluminum-based material or ceramic material has good heat dissipation performance and can effectively absorb and dissipate heat from the bottom surface of the chip bare die.
[0012] In a possible design, the chip housing is a plastic housing, a ceramic housing or a metal housing. When used, the plastic housing is lighter and cheaper, while the ceramic housing and the metal housing have good thermal conductivity, and the selection can be made according to actual conditions.
[0013] In a possible design, the first heat sink and the second heat sink are both made of aluminum alloy material. When used, the first heat sink and the second heat sink made of aluminum alloy material have good heat dissipation performance, are light in weight, and have low cost.
[0014] In a possible design, the first heat sink and the second heat sink are both provided with integrally formed heat sink fins. When used, by designing heat sink fins on the first heat sink and the second heat sink, the contact area between the heat sink and the external medium can be increased, which is conducive to the rapid dissipation of heat and improves the heat dissipation efficiency of the heat sink.
[0015] In a second aspect, the present invention provides a chip with high heat dissipation efficiency, wherein the chip comprises any one of the packaging structures in the first aspect.
[0016] Beneficial effects: The present invention opens a heat dissipation channel on one side and separately adds a heat conduction channel on the other side under the premise of complex signal transmission and large power supply plane of the existing packaging process, thereby realizing double-sided heat dissipation of the chip and effectively improving the heat dissipation effect of the chip; and can level the temperature difference between the two sides of the chip, greatly improving the instability problem of the chip caused by the temperature difference during high-speed operation or calculation; at the same time, in conjunction with the corresponding layered PCB board design, it can achieve a thermoelectric separation effect to ensure the stable operation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1It is a schematic diagram of the packaging structure of the present invention from a first viewing angle;
[0019] Figure 2 It is a schematic diagram of the packaging structure of the present invention from a second viewing angle.
[0020] In the figure: 1. chip housing; 2. chip bare die; 3. PCB substrate; 31. substrate heat dissipation layer; 32. electrical connection layer; 33. insulating adhesive layer; 4. first heat sink; 5. heat dissipation conductive member; 6. second heat sink; 7. conductive pad; 8. functional electronic components. DETAILED DESCRIPTION
[0021] It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. The specific structures and functional details disclosed herein are only used to describe the exemplary embodiments of the present invention. However, the present invention can be embodied in many alternative forms, and it should not be understood that the present invention is limited to the embodiments set forth herein.
[0022] It should be understood that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments can be understood according to specific circumstances.
[0023] In the following description, certain details are provided to facilitate a complete understanding of the example embodiments. However, it will be appreciated by those of ordinary skill in the art that the example embodiments may be implemented without these certain details. For example, the system may be shown in a block diagram to avoid obscuring the example with unnecessary details. In other embodiments, well-known processes, structures, and techniques may not be shown in unnecessary detail to avoid obscuring the embodiments.
[0024] Embodiment 1:
[0025] This embodiment provides a chip packaging structure with high efficiency in heat dissipation, such as Figure 1 and Figure 2As shown, it includes a chip housing 1, a chip bare die 2 and a PCB substrate 3, the chip housing 1 is arranged on the PCB substrate 3, a first heat sink 4 is arranged on the top of the chip bare die 2, the first heat sink 4 is connected to the chip housing 1, and the chip bare die 2 is encapsulated in the chip housing 1, a heat dissipation conductive member 5 is arranged on the bottom of the chip bare die 2, the heat dissipation conductive member 5 is connected to the PCB substrate 3, the PCB substrate 3 includes a connected substrate heat dissipation layer 31, the contact surface between the PCB substrate 3 and the heat dissipation conductive member 5 exposes the substrate heat dissipation layer 31, so that the substrate heat dissipation layer 31 is connected to the heat dissipation conductive member 5, and the substrate heat dissipation layer 31 is connected to the heat dissipation conductive member 5, and the second heat dissipation member 6 is connected to the side of the substrate heat dissipation layer 31 away from the heat dissipation conductive member 5.
[0026] In specific implementation, by exposing the chip die 2 through the process, the first heat sink 4 on the top of the chip die 2 can effectively dissipate the heat on the top surface of the chip die 2, and dissipate the heat on the top surface of the chip die 2 to the external environment. The heat dissipation conductive member 5 at the bottom of the chip die 2 can effectively dissipate the heat on the bottom surface of the chip die 2, and conduct the heat on the bottom surface of the chip die 2 to the substrate heat dissipation layer 31 of the PCB substrate 3, and then conduct it to the second heat sink 6 through the substrate heat dissipation layer 31, and finally dissipate the heat to the external environment through the second heat sink 6. Through the design of heat dissipation at both ends, an efficient heat conduction path from the inside to the outside of the chip can be formed, which greatly increases the heat dissipation efficiency of the chip after packaging (the heat dissipation efficiency can be increased by more than 30%). In addition, by dissipating the heat on the two end surfaces of the chip die 2, the temperature difference between the two sides of the chip die 2 can be effectively leveled, which greatly improves the instability problem of the chip caused by the temperature difference during high-speed operation or calculation.
[0027] Furthermore, the PCB substrate 3 further includes a connected electrical connection layer 32, the electrical connection layer 32 is conductive, the bottom surface of the chip die 2 is provided with a conductive pad 7, the conductive pad 7 is connected to the PCB substrate 3, and the contact surface between the PCB substrate 3 and the conductive pad 7 exposes the electrical connection layer 32, so that the electrical connection layer 32 is electrically connected to the conductive pad 7. In specific implementation, the conductive pad 7 of the chip die 2 is connected through the electrical connection layer 32 of the PCB substrate 3, which can provide the chip die 2 with electrical pathways for various signals and power supply, thereby ensuring the normal operation of the chip.
[0028] Furthermore, the PCB substrate 3 further includes a connected insulating adhesive layer 33, which is provided between the substrate heat dissipation layer 31 and the electrical connection layer 32, and is used to bond the substrate heat dissipation layer 31 and the electrical connection layer 32, and to thermally and electrically separate the substrate heat dissipation layer 31 from the electrical connection layer 32. In specific implementation, through the design of the thermal and electrical separation process, the insulating adhesive layer 33 can be made to bond the substrate heat dissipation layer 31 and the electrical connection layer 32 respectively, and at the same time, the substrate heat dissipation layer 31 and the electrical connection layer 32 are thermally and electrically separated, so as to ensure that the thermal conduction path of the substrate heat dissipation layer 31 and the conductive path of the electrical connection layer 32 are independent of each other and do not affect each other.
[0029] Furthermore, the PCB substrate 3 is also provided with a functional electronic component 8, the conductive end of the functional electronic component 8 is electrically connected to the electrical connection layer 32, and the heat dissipation surface of the functional electronic component 8 is connected to the substrate heat dissipation layer 31. In specific implementation, by integrating other functional electronic components 8 on the PCB substrate 3, it can be matched with the chip bare die 2 of the main body to play a corresponding auxiliary role in the operation function. The PCB substrate 3 is connected to the conductive end of the functional electronic component 8 through the electrical connection layer 32, so that the functional electronic component 8 is effectively connected to the conductive path, and the PCB substrate 3 is connected to the heat dissipation surface of the functional electronic component 8 through the substrate heat dissipation layer 31, so that the functional electronic component 8 is effectively connected to the heat conduction path, and the stable operation of the functional electronic component 8 is simultaneously guaranteed.
[0030] Furthermore, the PCB substrate 3 is made of a copper substrate. In a specific implementation, the copper substrate has excellent thermal conductivity, which is beneficial to the heat dissipation of the chip, and the copper substrate has good processing performance and stability. The heat dissipation conductive member 5 is made of a copper-based material, an aluminum-based material or a ceramic material. In a specific implementation, the heat dissipation conductive member 5 made of a copper-based material, an aluminum-based material or a ceramic material has good heat dissipation performance, and can effectively absorb heat and dissipate heat from the bottom surface of the chip die 2. The selection of copper-based material, aluminum-based material or ceramic material can be determined according to actual conditions. The chip housing 1 is made of a plastic housing, a ceramic housing or a metal housing. The plastic housing is lighter and cheaper, and the ceramic housing and the metal housing have good thermal conductivity, which can be selected according to actual conditions.
[0031] Furthermore, the first heat sink 4 and the second heat sink 6 are both made of aluminum alloy. In a specific implementation, the first heat sink 4 and the second heat sink 6 made of aluminum alloy have good heat dissipation performance, and the material is light and the cost is low. The first heat sink 4 and the second heat sink 6 are both provided with integrally formed heat sink fins. In a specific implementation, by designing heat sink fins on the first heat sink 4 and the second heat sink 6, the contact area between the heat sink and the external medium can be increased, which is conducive to the rapid dissipation of heat and improves the heat dissipation efficiency of the heat sink.
[0032] Embodiment 2:
[0033] This embodiment provides a chip with high efficiency in heat dissipation, wherein the chip includes a packaging structure and corresponding external electrical components and electrical connectors matched with the packaging structure, such as Figure 1 and Figure 2 As shown, the packaging structure includes a chip housing 1, a chip die 2 and a PCB substrate 3, the chip housing 1 is arranged on the PCB substrate 3, a first heat sink 4 is arranged on the top of the chip die 2, the first heat sink 4 is connected to the chip housing 1, and the chip die 2 is packaged in the chip housing 1, a heat dissipation conductive member 5 is arranged on the bottom of the chip die 2, the heat dissipation conductive member 5 is connected to the PCB substrate 3, the PCB substrate 3 includes a connected substrate heat dissipation layer 31, the contact surface between the PCB substrate 3 and the heat dissipation conductive member 5 exposes the substrate heat dissipation layer 31, so that the substrate heat dissipation layer 31 is connected to the heat dissipation conductive member 5, and a second heat dissipation member 6 is connected to the side of the substrate heat dissipation layer 31 away from the heat dissipation conductive member 5.
[0034] In specific implementation, by exposing the substrate of the chip die 2 through the process, the first heat sink 4 on the top of the chip die 2 can effectively dissipate the heat on the top surface of the chip die 2, and dissipate the heat on the top surface of the chip die 2 to the external environment. The heat dissipation conductive member 5 at the bottom of the chip die 2 can effectively dissipate the heat on the bottom surface of the chip die 2, and conduct the heat on the bottom surface of the chip die 2 to the substrate heat dissipation layer 31 of the PCB substrate 3, and then conduct it to the second heat sink 6 through the substrate heat dissipation layer 31, and finally dissipate the heat to the external environment through the second heat sink 6. Through the design of heat dissipation at both ends, an efficient heat conduction path from the inside to the outside of the chip can be formed, which greatly increases the heat dissipation efficiency of the chip after packaging (the heat dissipation efficiency can be increased by more than 30%). In addition, by dissipating the heat on the two end surfaces of the chip die 2, the temperature difference between the two sides of the chip die 2 can be effectively leveled, which greatly improves the instability problem of the chip caused by the temperature difference during high-speed operation or calculation.
[0035] Furthermore, the PCB substrate 3 further includes a connected electrical connection layer 32, the electrical connection layer 32 is conductive, the bottom surface of the chip die 2 is provided with a conductive pad 7, the conductive pad 7 is connected to the PCB substrate 3, and the contact surface between the PCB substrate 3 and the conductive pad 7 exposes the electrical connection layer 32, so that the electrical connection layer 32 is electrically connected to the conductive pad 7. In specific implementation, the conductive pad 7 of the chip die 2 is connected through the electrical connection layer 32 of the PCB substrate 3, which can provide the chip die 2 with electrical pathways for various signals and power supply, thereby ensuring the normal operation of the chip.
[0036] Furthermore, the PCB substrate 3 further includes a connected insulating adhesive layer 33, which is provided between the substrate heat dissipation layer 31 and the electrical connection layer 32, and is used to bond the substrate heat dissipation layer 31 and the electrical connection layer 32, and to thermally and electrically separate the substrate heat dissipation layer 31 from the electrical connection layer 32. In specific implementation, through the design of the thermal and electrical separation process, the insulating adhesive layer 33 can be made to bond the substrate heat dissipation layer 31 and the electrical connection layer 32 respectively, and at the same time, the substrate heat dissipation layer 31 and the electrical connection layer 32 are thermally and electrically separated, so as to ensure that the thermal conduction path of the substrate heat dissipation layer 31 and the conductive path of the electrical connection layer 32 are independent of each other and do not affect each other.
[0037] Furthermore, the PCB substrate 3 is also provided with a functional electronic component 8, the conductive end of the functional electronic component 8 is electrically connected to the electrical connection layer 32, and the heat dissipation surface of the functional electronic component 8 is connected to the substrate heat dissipation layer 31. In specific implementation, by integrating other functional electronic components 8 on the PCB substrate 3, it can be matched with the chip bare die 2 of the main body to play a corresponding auxiliary role in the operation function. The PCB substrate 3 is connected to the conductive end of the functional electronic component 8 through the electrical connection layer 32, so that the functional electronic component 8 is effectively connected to the conductive path, and the PCB substrate 3 is connected to the heat dissipation surface of the functional electronic component 8 through the substrate heat dissipation layer 31, so that the functional electronic component 8 is effectively connected to the heat conduction path, and the stable operation of the functional electronic component 8 is simultaneously guaranteed.
[0038] Furthermore, the PCB substrate 3 is made of a copper substrate. In a specific implementation, the copper substrate has excellent thermal conductivity, which is beneficial to the heat dissipation of the chip, and the copper substrate has good processing performance and stability. The heat dissipation conductive member 5 is made of a copper-based material, an aluminum-based material or a ceramic material. In a specific implementation, the heat dissipation conductive member 5 made of a copper-based material, an aluminum-based material or a ceramic material has good heat dissipation performance, and can effectively absorb heat and dissipate heat from the bottom surface of the chip die 2. The selection of copper-based material, aluminum-based material or ceramic material can be determined according to actual conditions. The chip housing 1 is made of a plastic housing, a ceramic housing or a metal housing. The plastic housing is lighter and cheaper, and the ceramic housing and the metal housing have good thermal conductivity, which can be selected according to actual conditions.
[0039] Furthermore, the first heat sink 4 and the second heat sink 6 are both made of aluminum alloy. In a specific implementation, the first heat sink 4 and the second heat sink 6 made of aluminum alloy have good heat dissipation performance, and the material is light and the cost is low. The first heat sink 4 and the second heat sink 6 are both provided with integrally formed heat sink fins. In a specific implementation, by designing heat sink fins on the first heat sink 4 and the second heat sink 6, the contact area between the heat sink and the external medium can be increased, which is conducive to the rapid dissipation of heat and improves the heat dissipation efficiency of the heat sink.
[0040] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A chip packaging structure with high heat dissipation efficiency, characterized in that: The invention comprises a chip housing (1), a chip bare die (2) and a PCB substrate (3), wherein the chip housing (1) is arranged on the PCB substrate (3), a first heat sink (4) is arranged on the top of the chip bare die (2), the first heat sink (4) is connected to the chip housing (1), and the chip bare die (2) is encapsulated in the chip housing (1), a heat dissipation conductive member (5) is arranged on the bottom of the chip bare die (2), the heat dissipation conductive member (5) is connected to the PCB substrate (3), the PCB substrate (3) comprises a connected substrate heat dissipation layer (31), the contact surface between the PCB substrate (3) and the heat dissipation conductive member (5) exposes the substrate heat dissipation layer (31), so that the substrate heat dissipation layer (31) is connected to the heat dissipation conductive member (5), and a second heat sink (6) is connected to the side of the substrate heat dissipation layer (31) facing away from the heat dissipation conductive member (5).
2. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The PCB substrate (3) further comprises a connected electrical connection layer (32), the electrical connection layer (32) is electrically conductive, a conductive pad (7) is provided on the bottom surface of the chip die (2), the conductive pad (7) is connected to the PCB substrate (3), and the contact surface between the PCB substrate (3) and the conductive pad (7) exposes the electrical connection layer (32), so that the electrical connection layer (32) and the conductive pad (7) are electrically connected.
3. The chip packaging structure with high heat dissipation efficiency according to claim 2, characterized in that: The PCB substrate (3) further comprises a connected insulating adhesive layer (33), wherein the insulating adhesive layer (33) is provided between the substrate heat dissipation layer (31) and the electrical connection layer (32), and is used to adhere the substrate heat dissipation layer (31) and the electrical connection layer (32), and to thermally and electrically separate the substrate heat dissipation layer (31) and the electrical connection layer (32).
4. The chip packaging structure with high heat dissipation efficiency according to claim 2, characterized in that: The PCB substrate (3) is also provided with a functional electronic component (8), the conductive end of the functional electronic component (8) is electrically connected to the electrical connection layer (32), and the heat dissipation surface of the functional electronic component (8) is connected to the substrate heat dissipation layer (31).
5. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The PCB substrate (3) is a copper substrate.
6. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The heat dissipation conductive element (5) is made of copper-based material, aluminum-based material or ceramic material.
7. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The chip housing (1) is a plastic housing, a ceramic housing or a metal housing.
8. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The first heat sink (4) and the second heat sink (6) are both made of aluminum alloy material.
9. The chip packaging structure with high heat dissipation efficiency according to claim 8, characterized in that: The first heat sink (4) and the second heat sink (6) are both provided with integrally formed heat sink fins.
10. A chip with high efficiency heat dissipation, characterized in that: The chip comprises the packaging structure described in any one of claims 1-9.