Image sensor

Abstract

The invention relates to an image sensor. A semiconductor device according to the present disclosure includes: a semiconductor layer; and a plurality of metal isolation features disposed in the semiconductor layer, where some of the metal isolation features extend through the substrate to provide complete isolation between adjacent photodetectors, and some of the metal isolation features extend partially through the semiconductor layer to provide partial isolation between adjacent photodetectors.

Description

Technical Field

[0001] The present disclosure relates to image sensors. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down also increases the complexity of processing and manufacturing ICs.

[0003] Image sensors, such as complementary metal oxide semiconductor (CMOS) image sensors (CIS), are common in modern consumer electronics. As image sensors continue to shrink in size to meet ever-increasing pixel resolution requirements, some existing image sensor structures may not provide adequate performance when receiving unbalanced light going to pixels. Thus, while existing CIS are generally adequate for their intended purpose, they are not satisfactory in all respects. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor layer; a plurality of isolation trench features arranged in the semiconductor layer, wherein the plurality of isolation trench features include a first trench extending through the entire semiconductor layer, a second trench extending through a portion of the semiconductor layer and having an end within the semiconductor layer, and a third trench extending through the entire semiconductor layer, wherein a cross-sectional view is that the second trench is inserted between the first trench and the third trench; a color filter, above the semiconductor layer; and a microlens, arranged above the color filter.

[0005] According to an embodiment of the present disclosure, an image sensor is provided, comprising: a lens array, comprising a first lens and a second lens, each of which is arranged on a semiconductor substrate; a first color filter and a second color filter, the first color filter is vertically below the first lens and the second color filter is vertically below the second lens; a first deep trench isolation (DTI) feature, a second DTI feature, and a third DTI feature, wherein each of the first DTI feature, the second DTI feature, and the third DTI feature extends from a first surface of the semiconductor substrate to an isolation region on a second surface of the semiconductor substrate; a first dual photodetector (DPD) and a second DPD, the first DPD is vertically below the first lens and the first color filter, and the second DPD is vertically below the second lens and the second color filter, wherein the first DPD is arranged between the first DTI feature and the second DTI feature, and wherein the second DPD is arranged between the second DTI feature and the third DTI feature; wherein the first DPD is configured to allow photocurrent to flow from a first photodetector of the first DPD to a second photodetector of the first DPD.

[0006] According to one embodiment of the present disclosure, a method for operating an image sensor is provided, comprising: providing the image sensor having a color filter array, wherein a plurality of photodetector channels are associated with each filter in the color filter array; providing incident light to the color filter array, including a first filter incident on the color filter array; passing the incident light to a first photodetector channel and a second photodetector channel through the first filter; and providing a photocurrent from the first photodetector channel to the second photodetector channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. It is also emphasized that the drawings illustrate only typical embodiments of the present invention and are not to be considered limiting in scope as the present invention may be equally applicable to other embodiments.

[0008] Figure 1A is a top view of an embodiment of a layout of a CIS device having multiple color filter pixels according to various aspects of the present disclosure.

[0009] Figure 1B is a perspective view of an embodiment of a layout of a CIS device having a plurality of pixels according to various aspects of the present disclosure.

[0010] Figure 2is a top view of an embodiment of another layout of a CIS device having a plurality of color filter pixels according to various aspects of the present disclosure.

[0011] Figure 3 is a top view of an embodiment of another layout of a CIS device having a plurality of color filter pixels according to various aspects of the present disclosure.

[0012] Figure 4 is a cross-sectional view of an embodiment of an image sensor having multiple dual photodetectors (DPDs) according to various aspects of the present disclosure.

[0013] Figure 5A and Figure 5B A top view and a cross-sectional view, respectively, of an embodiment of an image sensor having multiple dual photodetectors (DPDs) and showing current flow according to various aspects of the present disclosure are shown.

[0014] Figure 5C A cross-sectional view of an embodiment of an image sensor having multiple dual photodetectors (DPDs) including an offset component and showing current flow is shown in accordance with various aspects of the present disclosure.

[0015] Fig. 6A and Figure 6B A top view and a cross-sectional view, respectively, of an embodiment of an image sensor having a plurality of quad photodetectors (QPDs) and showing current flow, according to various aspects of the present disclosure.

[0016] Figure 7 A block diagram of an embodiment of a CIS device with a lateral field charge modulator according to various aspects of the present disclosure is shown.

[0017] Figure 8 The present disclosure shows various aspects of the Figure 7 An embodiment of a waveform diagram corresponding to a device.

[0018] Fig.9A is a top view of another layout of an embodiment of a CIS device having multiple color filter pixels according to various aspects of the present disclosure.

[0019] Fig. 9B A method of manufacturing a lateral field charge modulator according to various aspects of the present disclosure is shown. Fig.9A A block diagram of the corresponding array of CIS devices.

[0020] Fig. 9C and Fig.9D A cross-sectional view of an embodiment of a CIS device having a lateral field charge modulator according to various aspects of the present disclosure is shown.

[0021] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D Diagrams showing example implementations of gates according to various aspects of the present disclosure are shown.

[0022] Fig.11 is a flow chart of an embodiment of a method of forming a CIS device according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0024] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0025] In addition, when a number or a range of numbers is described using "about," "approximately," or the like, the term is intended to include numbers that fall within a reasonable range that takes into account the inherent variations during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances (which are associated with manufacturing features having characteristics associated with the numbers), the number or range of numbers includes a reasonable range with the described number, for example, within + / -10% of the described number. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / -15%. In addition, the present disclosure may also repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0026] The CIS device can be implemented by a substrate or stacked substrate (e.g., a semiconductor wafer) with a backside illumination (BSI) configuration process. In some implementations, the CIS is a color sensor and uses a color filter with 1 color (1C), 4 colors (4C), and 4C quad photodetector (QPD) configuration. The present disclosure provides an image sensor including a photodetector (or photodiode), which is also called a channel, the photodetector is disposed in a semiconductor layer, and a microlens is arranged above the photodetector so that light passes through the microlens and is guided to the photodetector. The photodetectors are separated from each other by a plurality of isolation features, and in some implementations, the plurality of isolation features include a grid composite having a deep trench isolation feature (e.g., backside deep trench isolation) that partially or completely extends through the semiconductor layer. In an embodiment, the isolation feature may include a metal layer and a dielectric liner layer.

[0027] Due to the imbalance from one photodetector to another, CIS may face challenges in capturing light / radiation and processing the reception of the light. Specifically, due to manufacturing coverage constraints and / or the main ray angle of the incident light, each photodetector may receive unbalanced light (e.g., different intensities or quantities) compared to its neighboring photodetectors. Coverage constraints lead to alignment challenges between microlenses, composite metal grids, and backside deep trench isolations of metal isolation features. In an embodiment, at the edge of the array, different channels may have different adjacent pixel color filters (CF) n values, which causes differences in the incident light and the final quantum efficiency (QE) in the same CF pixel. In an embodiment, at the center and / or edge of the array, the microlens is offset from the backside deep trench isolation coverage so that the incident light is not in the center of the backside deep trench isolation, which may cause scattered light and final QE differences even within the same color filter pixel (e.g., within a four-photodetector pixel). In some instances of the embodiments discussed above, receiving unbalanced light may cause the photodetector to fail to reach full well capacity (full well capacity, FWC) in sufficient time. Therefore, it is desirable to increase the response time of the sensor while compensating for these challenges.

[0028] Various aspects of the present disclosure are described in more detail with reference to the accompanying drawings. Figure 1A , Figure 2 and Figure 3 , three different local refinement strategies based on population diversity are shown, realizing the layout of the dual photodetector array, which are shown as CIS100, CIS200 and CIS 300 respectively. Specifically, Figure 1A , Figure 2 and Figure 3 Each shows a top view of a pixel array.

[0029] exist Figure 1A In the figure, CIS100 is an illustration of a first pixel structure. CIS100 has a color filter array covered with a microlens (also in the array). Below the color filter is an array of photodetectors. In CIS100, the photodetectors are configured as dual photodetectors (DPDs). Each DPD includes two photodetectors of the same size. Both photodetectors of the DPD are associated with a given color filter. That is, between the first DPD (associated with the first color filter) and the adjacent DPD (associated with the second color filter), a metal isolation feature including a metal grid and deep trench isolation is provided to provide complete isolation. Within the DPD, the two photodetectors or channels are not completely isolated from each other. Alternatively, between the two photodetectors, the trench of the deep trench isolation only partially extends between the channels, as described below. Each of the two photodetectors of the DPD is associated with the same color filter. In other words, complete isolation is provided between the DPD arrays (e.g., between the DPD of the first color and the DPD of the second color), while partial isolation is provided within the DPD. Further discussion of partial isolation is described below, including references Figure 4 and Figure 5.

[0030] CIS100 includes pixels of a first color (e.g., green), a second color (e.g., red), and a third color (e.g., blue). The DPD of the CIS on the left side of the array is oriented at a 90 degree angle in comparison of the DPDs at the top and bottom of the array portion. The DPD of the CIS on the right side of the array is oriented at a 90 degree angle in comparison from top to bottom. In an embodiment, the top is horizontally oriented (e.g., a groove providing partial isolation between the first channel and the second channel extends horizontally on the page), and the bottom is vertically oriented (e.g., a groove providing partial isolation between the first channel and the second channel extends vertically on the page). That is, one microlens is placed above two photodiodes (e.g., two and only two photodiodes). And in some implementations, the two photodiodes can share Figure 4 , Figure 5A and Figure 5B The charge discussed in .

[0031] In many implementations of CIS 100, radiation or light sources can come from all directions (e.g., three-dimensional (3D) and light with an incident angle of 0 to 180 degrees), and the DPD is configured to capture the incident light. Specifically, in some implementations, there may be an offset or shift between the microlens (represented by a circle) and the underlying photodiode during manufacturing. This is shown in FIG. Figure 1B In some implementations, it is also possible to isolate (see, for example, Figure 4 , Figure 5A , Figure 5BThe manufacturing tolerance of the offset or shift between the lens and the photodiode / isolation can be Figure 1A Specifically, the offset between the microlens and the photodiode / isolation can occur in the x-direction (in Figure 1A From left to right, and vice versa, you can also participate Figure 1B ), and can also occur in the y direction (in Figure 1A From top to bottom, and vice versa, you can also participate Figure 1B ). This offset can be addressed by CIS100 because CIS100 provides a combination of vertically and horizontally oriented DPDs. In other words, some DPDs are oriented so that the photodetectors share an interface oriented along the x-direction, such as the first two rows of CIS100, and some DPDs are oriented so that the photodetectors share an interface oriented along the y-direction, such as the third and fourth rows of CIS100. The orientation combination allows CIS100 to better compensate for the offset between the microlenses and the photodiodes / isolation in both the x-direction and the y-direction. In some implementations, the configuration of CIS 100 (from the angle of the x-direction and y-direction interface between the photodiodes and the microlenses) (i.e., the orientation of the DPD configuration) is determined for the array based on computer simulations using input factors of the incident light angle. It should be noted that the interface is provided by a trench isolation structure that allows the photoelectric charge to be transferred from one side to the other (e.g., the isolation trench 408' discussed below).

[0032] Figure 1B The perspective view in Figure 1 shows the offset direction. Figure 1B The lens 102 is shown above the DPD 104 and the DPD 106. The DPD 104 has two photodetectors or channels, where the interface extends along the x-direction; and the DPD 106 has two photodetectors or channels, where the interface extends along the y-direction. Therefore, because the lens is offset in the x-direction and / or the y-direction (or both directions), the DPD can compensate for the offset by sharing the photocharge over the interface from one photodetector to the other.

[0033] Figure 2 and Figure 1A The CIS100 share several common features and offer different array configurations for DPD. Figure 2, CIS200 is an illustration of a second pixel structure. CIS200 has a color filter and a lens array. And, CIS200 includes a dual photodetector (DPD) under the color filter. Each DPD includes two photodetectors of the same size, as described above. Similarly, the two photodetectors or channels of the DPD are associated with the same color filter pixel. CIS200 includes color filters of a first color (e.g., green), a second color (e.g., red), and a third color (e.g., blue). The DPD of the CIS on the left side of the array is oriented at a 90-degree angle in a comparison from top to bottom. The DPD of the CIS on the right side of the array is oriented at a 90-degree angle in a comparison from top to bottom (e.g., the interface between the photodetectors is oriented in a vertical direction). Here, the top is vertically oriented and the bottom is.

[0034] Similar to that discussed for CIS 100, CIS 200 may provide advantages in handling the offset between the photodiodes (and the isolation surrounding the photodiodes) and the lenses by implementing the following DPDs in CIS 200, some of which are oriented so that the interface between the photodiodes (under a given lens) is oriented in the y-direction and some of which are oriented so that the interface between the photodiodes (under a given lens) is oriented in the x-direction, so that each direction is compensated.

[0035] Figure 3 and Figure 1A The CIS100 share several common features and offer different array configurations for DPD. Figure 3, CIS300 is a diagram of the third pixel structure. CIS 300 has a color filter and a lens array. And, CIS 300 has a dual photodetector (DPD) array below the color filter. Each DPD includes two photodetectors of the same size, and each of the two photodetectors is used for the same color filter pixel. CIS 300 includes pixels of a first color (e.g., green), a second color (e.g., red), and a third color (e.g., blue). The DPD of CIS 300 includes two vertically oriented top rows of pixels; and the next two rows (below the top two rows) oriented horizontally; and the next two rows (below the middle two rows) oriented vertically again. In some implementations, where the incident light comes from all directions (e.g., 360 degrees of surround light), CIS 300 can have advantages in sensing efficiency. Similarly, similar to what is discussed for CIS 100, CIS 300 can provide advantages in processing the offset between the photodiode (and the isolation around the photodiode) and the lens. By implementing the following DPDs in CIS300, some DPDs are oriented so that the interface between photodiodes (under a given lens) is oriented along the y direction, and some DPDs are oriented so that the interface between photodiodes (under a given lens) is oriented along the x direction, so that each direction is compensated.

[0036] The array of CIS100, CIS200, and CIS300 can be repeated any number of times across the respective device. In some implementations, CIS100, CIS200, and CIS300 are well suited for machine vision applications. A disadvantage of one or more of the layouts may be the resolution in a selected direction. For example, the vertical resolution may be only half the horizontal resolution, or vice versa, depending on the orientation of the DPD. Compare the upper left quadrant of the portion shown in Figure A, which has greater resolution in the horizontal direction than in the vertical direction, and compare Figure 1A The lower left quadrant of the portion shown has greater resolution in the vertical direction than in the horizontal direction.

[0037] The array of CIS100, CIS200 and CIS 300 provides filters of three different colors. In some implementations, these colors are blue, green and red. However, for these and all color filters of the present disclosure, other implementations are also possible. In some implementations, the color filter may include a color filter of red, blue, green, yellow, cyan, white, and / or other suitable colors. The array of CIS100, CIS200 and CIS 300 may be 1 color (C), 4C, 9C, 16C, 32C, 36C, etc. In some cases, one or more layouts of CIS100, CIS200 and CIS 300 provide improved local refinement (PDLR) based on population diversity to enhance the high dynamic range (HDR) of the sensor.

[0038] In each configuration layout of the DPD, the orientation of the interface between the photodetectors of each DPD (e.g., two photodiodes under a lens) is chosen to extend in a given direction, such as the x-direction or the y-direction. Figure 4 As discussed, the x-directed interface allows for charge sharing through interfaces oriented in the x-direction. Therefore, if the lens is offset from the photodetector, the DPD is able to better capture light by, for example, sharing the charge generated in the top diode to the bottom diode through the x-oriented interface. Figure 4 As discussed, the y-directed interface allows for charge sharing through interfaces oriented in the y-direction. Therefore, if the lens and photodiode are offset, the DPD is able to better capture light by, for example, sharing the charge generated in the right diode to the left diode through the y-directed interface.

[0039] Reference now Figure 4 , shows a cross-sectional view of an image sensor 400 including two DPDs 402 for a given color filter of a pixel array, for example, as implemented in CIS100, CIS200, and / or CIS300 discussed above. Specifically, Figure 3 The cross section AA' of CIS 300 corresponds to Figure 4 Cross-sectional view of the CIS 400.

[0040] CIS 400 includes a substrate 401. Substrate 401 is a semiconductor substrate. Substrate 401 may be a bulk silicon (Si) substrate. Alternatively, substrate 401 may include a single element semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenic phosphide (GaInAsP); or a combination thereof. In some implementations, substrate 401 includes one or more III-V materials, one or more II-VI materials, or a combination thereof. In some other cases, substrate 401 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. In some other embodiments, substrate 401 may be a diamond substrate or a sapphire substrate.

[0041] To form CIS 400, a photosensitive region is formed in substrate 401 to form a photodetector. Thus, substrate 401 may include various doped regions (not shown), such as p-type doped regions, n-type doped regions, or combinations thereof. In one embodiment, substrate 401 may include p-type dopants, such as boron (B), boron difluoride (BF2), or other p-type dopants; and n-type dopants, such as phosphorus (P), arsenic (As), or other n-type dopants. The implants may form channels (e.g., 404A / 404B, 414A / 414B), which may also be referred to as photodetectors or photodiodes when defined by metal isolation features (e.g., 406, 408, 408') discussed below.

[0042] The substrate 401 has been processed to form features on a first side (referred to as the front side). In some implementations, the features formed on the substrate 401 include a plurality of transistors 424 configured to process signals for the CIS 400. Each transistor 424 includes a source, a drain, a channel region disposed between the source and the drain, and a gate structure over the channel region. It should be noted that Figure 4The transistor 424 shown in can represent transistors of different configurations. For example, transistor 424 can be a planar transistor, a fin field effect transistor (FINFET), a multi-bridge channel (MBC) transistor, a gate all around (GAA) transistor, a nanowire transistor, a nanosheet transistor, a transistor with a nanostructure, or other multi-gate transistors (wherein the gate structure is bonded to more than one surface of the channel region). Transistor 424 can be a high-k metal gate device, for example, providing a high-k dielectric as a gate dielectric and a metal gate electrode. Transistor 424 can also be a transistor with a polysilicon gate. In an embodiment, transistor 242 includes a source / drain region formed by an epitaxial growth material on a recess in substrate 401 (or on the surface of substrate 401). In some implementations, the epitaxial growth material includes silicon germanium (SiGe). In an embodiment, transistor 424 can be a silicon on insulator (SOI) device.

[0043] On the first side of substrate 401, isolation features 426 are also formed. Isolation features 426 may also be referred to as shallow trench isolation (STI) features, and may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. CIS 400 may also include additional layers, such as an interlayer dielectric (ILD) disposed above the surface and transistor 424. The ILD may include materials such as tetraethylorthosilicate (TEOS) oxide; undoped silicate glass; or doped silicon oxides such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. One or more multi-layer conductive interconnect features (not shown) may be formed above and connected to transistor 424, and extend through the ILD to form a multi-layer interconnect (MLI), as discussed in further detail below.

[0044] In some implementations, CIS 400 is a backside illuminated sensor (BIS). In another embodiment, substrate 401 is flipped, and the image sensor features discussed below are then formed on the back side of substrate 401, thereby forming a BIS. CIS 400 includes a first DPD 402 associated with a first color filter 416 (left). DPD 402 includes a first photodetector or channel 404A and a second photodetector or channel 404B. CIS 400 also includes a second DPD 412 associated with a second color filter (right). DPD 412 includes a first channel 414A and a second channel 414B.

[0045] The isolation structure defines a photodetector region for forming a pixel. The isolation structure includes a metal grid 406 and a backside deep trench isolation (BDTI) 408 to form a composite isolation grid between channels. Each of the adjacent metal grids 406 and BDTI 408 includes a liner layer, shown as a liner 410 (e.g., a dielectric liner). And, a metal layer on the liner 410 may be included. The BDTI 408 extends between the first DPD 402 and the second DPD 412, providing complete isolation. The BDTI 408 extends through the substrate 401 to the isolation 426, so that the BDTI 408 interface is connected to the isolation region 426. The BDTI 408 also provides complete isolation of the DPD 402 and the adjacent channel (not shown), as well as complete isolation of the DPD 412 and the adjacent channel (not shown). The isolation structure also shows a trench isolation 408 ', which extends between the first channel 404A and the second channel 404B of the DPD 402. Trench isolation 408' does not provide complete isolation between channels 404A and 404B, instead trench isolation 408' terminates at a depth within the channel region.

[0046] A first color filter 416A is formed on the DPD 402, and a second color filter 416B is formed on the DPD 412. The first color filter 416A has a different color from the second color filter 416B. For example, in an embodiment, the first color filter 416A is green, and the second color filter 416B is red. The lower layer 418 is disposed on the filter 416A / 416B. The lower layer 418 can be a dielectric film, and in some implementations, can be formed by chemical vapor deposition (CVD). The first microlens 420 is formed on the first color filter 416A, and the second microlens 420 is formed on the second color filter 416B. As described above, the directions (e.g., above and below) are only for illustrating the relative positions of the components, and can be reversed in orientation.

[0047] These features of CIS 400 introduced above will now be discussed in further detail. In some implementations, after forming a front device (e.g., transistor 424 and isolation region 426), the back side of substrate 401 is patterned to form an opening for deep trench isolation feature 408 / 408'. In some implementations, photolithography and etching processes are performed to pattern a hard mask on the back side of substrate 401. For example, a photoresist layer (not shown) is formed on the hard mask, is exposed to a suitable photolithography radiation source, and is developed to form a patterned photoresist layer. Then, a patterned hard mask and / or resist are used as an etching mask to anisotropically etch substrate 401, thereby forming a plurality of grooves. In an embodiment, the groove is formed by anisotropic etching, which can be a dry etching process utilizing sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), other fluorine-containing gases, oxygen (O2), or a combination thereof. like Figure 4 As shown, more than one deep trench may be formed, some extending to isolation features 426 formed on the front side of substrate 401, as shown by BDTI 408, and some terminating within substrate 401, as shown by trench 408'. These trenches may be formed in the same or different patterning and etching processes.

[0048] In an embodiment, dielectric liner layer 410 is formed as part of a metal isolation feature included on the back side of substrate 401 and BDTI 408 / 408'. Dielectric liner layer 410 can be a multilayer structure. Example compositions include high-k dielectric materials, such as aluminum oxide, hafnium oxide, tantalum oxide, and the like. Dielectric liner layer 410 can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable processes. In an implementation, dielectric liner layer 410 also includes a silicon oxide layer. For example, in some embodiments, dielectric liner layer 410 includes a high-k dielectric layer and a silicon oxide layer.

[0049] To form the isolation structure including the BDTI 408 / 408' and the metal grid 406, metal may be deposited on the back side of the substrate 401 and along the etched trenches. The deposition may be performed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable deposition processes. After the metal is deposited, a chemical mechanical polishing (CMP) process may be performed. The BDTI 408 and 408' may be formed of aluminum (Al), tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), or other suitable materials. In one embodiment, the BDTI 408 and 408' are formed of tungsten (W).

[0050] BDTI 408 extends through substrate 401 to isolation region 426 on the front side of substrate 401, providing complete isolation between regions (e.g., between pixels). Metal isolation features (metal grid 406, BDTI 408) are formed in a grid shape at the edge of each pixel (e.g., FIG. 1, Figure 2 and Figure 3 The trench isolation feature 408' of the isolation structure does not provide complete isolation, but instead allows flow between adjacent channels. The trench isolation feature 408' provides a barrier between portions of two channels of a single pixel (e.g., between two photodetectors associated with a single color filter). For example, the trench isolation feature 408' defines a separation of portions of the two channels of DPD402, and a separation of portions of the two channels of DPD 412. The trench isolation feature 408' defines FIG. 1, Figure 2 and Figure 3 4. The vertical / horizontal lines within the DPD in the corresponding CIS100, CIS200 and CIS300 in FIG. That is, the trench isolation features 408 and 408' (completely or partially) define and isolate the photodetector to provide a channel (e.g., 404, 414). The isolation feature 408' extends from the surface of the substrate but terminates so that the isolation feature 408' has an end within the substrate. Therefore, the distance of the substrate that can transfer charge is provided below.

[0051] The isolation features including the grid 406 with trench isolation 408 / 408' may include a metal portion and a dielectric portion. In some implementations, the dielectric portion is provided by a liner layer 410. Similar to the grid 406 area, the DTI features 408 / 408' may be configured in a grid (e.g., a grid defining a photodetector). In an embodiment, the grid 406 and / or the DTI features 408 / 408' include tungsten and titanium nitride (TiN). Other materials include tungsten, pure metals, compound alloys, TiN, ceramic materials, and / or other suitable compositions. In an embodiment, in addition to or in place of the liner layer, the grid 406 and / or the DTI features 408 / 408' may include a dielectric portion including Al2O3, SiO2, or other suitable dielectric materials.

[0052] In some implementations, the grid 406 and / or DTI features 408 / 408' include a first dielectric portion including SiO2, other suitable dielectric materials, or ceramic materials, wherein the refractive index n of the material is between about 1 and about 1.48. In some implementations, the grid 406 and / or DTI features 408 / 408' include a second dielectric portion (in addition to the first dielectric portion) including SiO2, other suitable dielectric materials, or ceramic materials, wherein the refractive index n of the material is between about 1 and about 1.48. In another embodiment, the second portion of the grid 406 and / or DTI features 408 / 408' includes a dielectric material that includes a filler that provides a refractive index n, without limitation. In some implementations, the grid 406 and / or DTI features 408 / 408' include a first dielectric portion and a second dielectric portion, wherein the refractive index of the first dielectric portion is equal to or less than the refractive index of the second dielectric portion.

[0053] Color filters 416A, 416B are formed on the back side of substrate 401. Color filters 416A, 416B can be formed by polymer materials, or resins containing color pigments. The color filter layer is formed by the following material, which allows the transmission of radiation (e.g., light) with a specific wavelength range while blocking the light with wavelengths exceeding the specified range. The following layer 418 is formed on color filters 416A, 416B. Example compositions include organic or polymer materials with high transmittance to visible light. This allows light to pass through the following layer 418 with very little distortion, so that the light can be detected by the photodetector or column 404 / 414. The following layer 418 can be formed by a spin coating method that provides a consistent and uniform layer.

[0054] Microlens (or simple lens) features 420 are formed on the underlying layer 418 and filters 416A, 416B, respectively. Microlenses 420 can be formed of any material that can be patterned and formed into a lens, for example, a high-transmittance acrylic polymer. In an embodiment, a liquid material and spin coating technology can be used to form the microlens layer. Other methods, such as CVD, PVD, etc. can also be used. The planar material of the microlens layer can be patterned using photolithography and etching techniques to pattern the planar material in an array corresponding to the photodetector array. The deposited material can then be reflowed to form an appropriate curved surface for the microlens 420. The microlens 420 can be cured using ultraviolet (UV) treatment. For DPD configurations, such as DPD 402 and DPD 412, a single lens extends over each channel or photodetector 404A and 404B of DPD 402; a single lens extends over each channel or photodetector 414A and 414B of DPD 412.

[0055] It should be noted that although Figure 4 A backside illuminated sensor (BSI) is shown, but in other embodiments, the present disclosure is also applicable to frontside illuminated sensors. In embodiments, various combinations of SOC and ASIC substrates (eg, wafers) may be used to manufacture Figure 4 and image sensors of other embodiments of the present disclosure. In another embodiment, the CIS is a FSI device and includes a single wafer image sensor. In an embodiment, the CIS is a BSI device and is based on multiple combinations of SOC and ASIC wafers.

[0056] Reference now Figure 5A and Figure 5B , shows the same as above reference Figure 4 The CIS 400 discussed is substantially similar to CIS 400'. CIS 400' includes a plurality of dual photodetector (DPD) devices, shown as 402 and 412, which form part of an array of CIS 400'. BDTI 408 extends through substrate 401 between pixels, as described above. Also, back trench isolation 408' provides partial isolation by extending partially through substrate 401 between photodetectors within a given pixel (e.g., between adjacent channels of a single DPD associated with a color filter). Figure 5B , incident light 504 is shown. Incident light 504 passes through lens 420 and color filters 416A / 416B to the photodetector.

[0057] Figure 5B The resulting current flow 502 (eg, photocurrent) is shown extending from the first photodetector or channel 402B of the DPD 402 to the second photodetector or channel 402A of the DPD 402. And, Figure 5B Also shown is a separate current flow 502 extending from a first photodetector or channel 414A of the DPD 412 to a second photodetector or channel 414B of the DPD 412. In some implementations, the current flow 502 of the DPD 402 is used to balance the charge between the channel 402A and the channel 402B. In the DPD 412, the current flow 502 is used to balance the charge of its channels 414A and 414B, respectively. The charge generated in each channel or photodetector 402A, 402B, 402C, 402D is determined by Figure 5B The dashed outline is shown.

[0058] In an embodiment, current flow 502 from channel 402B to channel 402A alleviates the problem of unbalanced reception of light within DPD 402. For example, in an embodiment of DPD 402 that may include color filter 416 of a first color (e.g., green), channel or photodetector 402B may have a larger photocurrent than channel or photodetector 402A due to the imbalance in received light, for example. See Figure 5C When the stored charge level exceeds the trench isolation 408' (which only provides partial isolation), a spillover current 502 will occur from channel 402B to channel 402A. Therefore, in some implementations, the charge storage of channel 402A to channel 402B can be balanced to more efficiently reach full well capacity (FWC).

[0059] Similarly, in an embodiment, the photoelectric current flow 502 from channel 414A to channel 414B alleviates the problem of unbalanced reception of light within DPD 412. In some implementations, the unbalanced reception of light within DPD 412 is due to overlay errors, or received light as described above. For example, in some implementations, grid 406, BDTI 408 / 408', and channels 414A / 414B are offset from a desired alignment, in other words, there is an alignment offset in a given direction. Figure 5C An offset in the x-direction is shown. In some implementations, the unbalanced reception of light within the DPD 412 is due to a variation in the incident light reaching the DPD 412. For example, in an embodiment of the DPD 412, which may include a color filter 416 of a second color (e.g., red), for example, due to the imbalance in the received light, the channel or photodetector 414A has a larger photocurrent than the channel or photodetector 414B. Similarly, when the stored charge level exceeds the back trench isolation 408', which provides partial isolation, an overflow current 502 from the channel 414A to the channel 414B will be generated. Therefore, in some implementations, the charge storage of the channel 414A to the channel 414B can be balanced, thereby more efficiently reaching the full well capacity (FWC).

[0060] Thus, in operation, in some implementations, current flow 502 can cause photocurrent to flow to neighboring PDs of its DPD to balance the FWC before pixel binning. Binning refers to the process of summing or averaging the values ​​of neighboring pixels during or after readout to combine neighboring pixels in the overall image. As the FWC is reached more efficiently, the response time of the sensor is improved.

[0061] Figure 5CThe CIS device shown is referred to as CIS 400, which is substantially similar to the CIS device described above. Figure 5A and Figure 5B CIS 400 as discussed. Figure 5C 4 is a diagram of the offset of lens 420 (and color filter 416) relative to photodetector 414 (shown here in the x-direction). Due to the merging process described above, the offset can be tolerated and the performance impact minimized because the photocurrent can be transferred from photodetector or channel 414B to channel or photodetector 414A (which receives less light due to the offset in the x-direction). In other examples, the offset may alternatively or additionally exist in a vertical direction (e.g., into Figure 5C direction of the page).

[0062] Reference now Fig. 6A and Figure 6B , shows a CIS 600. The CIS 600 includes a plurality of quad photodetectors (QPDs) in an array. Fig. 6A In the top view of CIS 600 in FIG. 1 , QPDs 602A, 602B, 602C, and 602D are shown. QPD 602A is associated with a first color filter (e.g., green), QPD 602B is associated with a second color filter (e.g., red), QPD 602C is associated with a third color filter (e.g., blue), and QPD 602D is associated with the first color filter. However, other arrangements of the array are possible. Fig. 6A The portion shown in represents a small portion of the QPD array that forms CIS 600. Each QPD includes four photodetectors (or channels or cells) of equal quadrant size. Each of the four quadrants is associated with a single color filter.

[0063] Some features of the CIS 600 implementing QPD are basically similar to those of the above reference Figure 4 The associated features for implementing DPD are discussed with respect to CIS 400, and like reference numerals refer to like features. Figure 6B A cross-sectional view of QPD 602A and QPD 602B along BB' is shown. BDTI 408 extends through substrate 401 between QPD 602A and QPD 602B. BDTI 408 can completely isolate QPD 602A from QPD 602B. Trench isolation 408' provides partial isolation between channels within QPD 602A (and within QPD 602B) by partially passing through substrate 401; trench isolation 408' extends between each of the four quadrants of the photodetector within a given QPD. Note that a given QPD (e.g., QPD 602A) is not isolated from the photodetector along a cut plane perpendicular to the BB' cut plane (e.g., Fig. 6A The cross-sectional view along the vertical section in FIG. 602A is substantially similar to the cross-sectional view shown along section BB′ because QPD 602A includes four equal quadrants.

[0064] Figure 6B Also shown is a first current flow 608A extending from a first photodetector or channel 604A of QPD 602A to a second photodetector or channel 604B of QPD 602A. In other words, the first current flow 608A extends along Fig. 6A , or along the cross-sectional plane BB'. Similarly, current flow 608A extends from a first photodetector or channel 606A of QPD 602B to a second photodetector or channel 606B of QPD 602B. In some implementations, current flow 608A is used to balance the charge of channels 604A and 604B, similar to that discussed above with reference to FIG5. And, in some implementations, a separate current flow 608A is used to similarly balance the charge of channels 606A and 606B.

[0065] Figure 6B Also shown is a second current flow 608B extending from the first photodetector or channel 604A and / or the second photodetector or channel 604B of the QPD 602A to other quadrants (other channels, specifically the other two channels) of the QPD 602A. Specifically, the current flow 608B is a current extending perpendicular to the cross-sectional plane BB' (e.g., entering or leaving the page of the drawing) such that charge is distributed to and / or leaving the other two channels (not shown in FIG. 1 ) of the QPD 602A. Figure 6B 604A). Similarly, current flow 608B extends from the first photodetector or channel 606A and / or the second photodetector or channel 606B of QPD 602B to other quadrants (other channels) of QPD 602B. In some implementations, current flows 608A and 608B in QPD 602A are used to balance the charge of each of the four photodetectors or channels of QPD 602A. In some implementations, separate current flows 608A and 608B in QPD 602B are used to balance the charge of each of the four photodetectors or channels of QPD 602B. In other words, for a given channel (e.g., 604A), the other three channels of the QPD can provide charge to / from the given channel. Likewise, in an implementation, there is complete isolation between the photodetectors or channels of QPD 602A and QPD 602B, resulting in no current flow between the two QPDs.

[0066] In an embodiment, the current flow 608A / 608B between the four (4) channels or photodetectors of the QPD 602A mitigates the problem of unbalanced reception of light within the QPD 602A. In some implementations, the unbalanced reception of light within the QPD 602A is due to overlay errors as described above. And, in some implementations, the unbalanced reception of light within the QPD 602A is due to variations in incident light. In an exemplary operation of the CIS 600, in an embodiment of the QPD 602A (which may include a color filter 416 of a first color (e.g., green)), for example, due to the imbalance of received light, the channel or photodetector 604A has a larger photocurrent than the channel or photodetector 604B (and / or one or more other channels or photodetectors of the QPD 602A). When the stored charge level exceeds the trench isolation 408' (which provides partial isolation), an overflow current 608A will be generated from channel 604A to channel 604B, and an overflow current 608B will be generated from channel 604A and / or channel 604B to one or both of the other two channels of QPD 602A. Thus, in some implementations, the charge storage of the channels or photodetectors of a QPD can be balanced to more efficiently reach full well capacity (FWC).

[0067] Reference now Figure 7-Figure 8 , the present disclosure discusses the use of (one or more) lateral electric field charge modulators (LEFM) to CIS. In some implementations, providing LEFM enhances the high dynamic range (HDR) of the CIS. LEFM has no transfer gate in the signal path for output from the pixel, allowing high speed charge modulation, and / or lossless charge modulation.

[0068] Figure 7 A top view of a device 700 including a LEFM with a drain is shown, wherein two sets of gates (G1 and G2) generate a lateral electric field. FD1 and FD2 provide floating diffusions. FD1 and / or FD2 can be N-type implants, P-type implants (e.g., B), PN junction floating capacitors, or metal insulator metal (MIM) capacitors.

[0069] In an embodiment, the gate cannot be used to transfer charge through the gate, but rather to control the photodiode by changing the hole concentration at the surface of the pinned photodiode of the photodetector (aperture). Figure 7 In an embodiment, when G1 is high and G2 is low, photoelectrons generated in the aperture region are transferred to FD1. That is, the direction of electron flow in the pinned photodiode is controlled by the gate. Figure 8An exemplary operation of the device 700 is shown in the waveform diagram 800. At time t1, gate G1 is turned on, and a lateral electric field is generated between the two gates G1. And, charge is stored at FD1. At time t2, gate G1 is turned off, and gate G2 is turned on, and then the charge at FD1 will flow to FD2. At time t3, both gate G1 and gate G2 are turned off, and gate GD is turned on, and charge will flow to gate GD. Therefore, in some embodiments, each channel (photodetector) in the same color filter pixel (e.g., red, blue, green) can reach full well capacity (FWC) more efficiently. And, in some implementations, the output pixel value can reach a higher level, thereby improving HDR.

[0070] In some implementations, when the sensor experiences significant light exposure (e.g., >1,000,000 lux), the order of G1, G2, and GD turning on and off is G1, then G2, then GD. In such an implementation, gates G1 and G2 act as receivers of signals (e.g., as primary signal receivers). Also, gate GD in such an implementation can be a background noise receiver. In an embodiment, gate GD is a dual control gate and performs the role of a drain gate (e.g., drains sunlight noise).

[0071] When the sensor experiences relatively low light exposure (e.g., dimmed light, almost dark, e.g., <100 lux), the order of gates G1, G2, and GD turning on and off is GD, then G1, then G2. In such an implementation, gate GD performs the role of the main signal receiver. And, gates G1 and G2 are background noise receivers for weak light. Gate GD may be very sensitive to weak light because of its dual control gates (more current signal), and G1 and G2 change their role from control gate to drain gate (drain noise current).

[0072] Therefore, it can be considered an advantage of the present disclosure that gate GD is a dual gate, while gates G1 and G2 are separate single gates. This is because at higher illumination, gate GD collects more background sunlight noise that needs to be discharged. And, at low light illumination, gate GD (and its dual gate configuration) acts as a primary signal collector with higher sensitivity. Therefore, at Figure 7 In some implementations of the device, the layout includes: gate GD has a dual control gate, and each of gates G1 and G2 is a single control gate.

[0073] In some implementations, the device can be implemented with a bipolar gate. Figure 7In the illustrated embodiment, a p-type gate and an n-type gate are formed for each of G1 , G2 , and GD.

[0074] Additional details of the device 700 are provided, and the additional details apply not only to the device 700, but also to the CIS 900 discussed below. In some implementations, LEFM is applied to the photodetector layer (including as described above) to move the charge of the photodetector layer. As described above, in an embodiment, G1, G2, and GD are control gates as described above. In some implementations, under very strong illumination (e.g., >1,000,000 lux), G1 and G2 provide the primary signal detection, and GD collects surrounding noise, such as ambient sunlight. Under very weak illumination (e.g., <100 lux), G1 and G2 can change function with GD; and GD can provide the primary signal detection, and G1 and G2 can provide background noise reference detection.

[0075] The gate structures G1, G2 and GD can be NMOS or CMOS devices, and in an embodiment, each G1, G2 and GD is disposed on an NMOS region of a substrate. In an embodiment, the width ratio of the p-type gate to the n-type gate ranges from 1:1 to 1000:1, G1 and G2 are substantially the same, and / or GD is omitted. In an embodiment, the length ratio of the p-type gate to the n-type gate ranges from 1:1 to 1000:1, G1 and G2 are substantially the same, and / or GD is omitted. In an embodiment, because the ambient direct sunlight collected by GD is a very strong signal, it requires a larger p-type gate area to enable GD to be turned off in a controlled manner. In an embodiment, the width and length of the gate GD can be equal to or greater than the width and length of G1 and G2. This arrangement can be made because, in some implementations, the device can easily control the steep slope of the charge signal channel during operation, thereby providing it to the floating diffusion regions FD1 and FD2 more quickly. In some implementations, Figure 7 The P-type gate and the n-type gate shown in FIG. 4 form a PN junction to generate an electric field to control the slope of the channel (eg, to provide a steep slope).

[0076] In an embodiment, gates G1, G2, GD are each connected to the same drain. In other embodiments, one or more of gates G1, G2, and GD may be connected to different drain regions. In an embodiment, the width and length ratio of the GD p-type gate and n-type gate to the G1 and G2 p-type gate and n-type gate ranges from 1:1 to 1000:1. In an embodiment, gates G1 and G2 are substantially the same size and shape, but may be mirror images of each other (or in other implementations, may not be mirror images of each other). That is, G1 and G2 may be opposite to each other without any horizontal shift. Alternatively, G1 and G2 may also be opposite to each other with a horizontal shift.

[0077] Notice, Figure 7 The gates G1, G2, and / or GD shown in the figure may represent transistors of different configurations. For example, the gates G1, G2, and / or GD may be planar transistors, fin field effect transistors (FINFETs), multi-bridge channel (MBC) transistors, gate all-around (GAA) transistors, nanowire transistors, nanosheet transistors, nanostructure transistors, or other multi-gate transistors (wherein the gate structure is bonded to more than one surface of the channel region). The gates G1, G2, and / or GD may be high-k metal gate devices, such as providing a high-k dielectric as a gate dielectric and a metal gate electrode. In an embodiment, the gates G1, G2, and / or GD include source / drain regions formed by epitaxially grown materials on a recess or surface of the substrate 401. In some implementations, the epitaxially grown material includes silicon germanium (SiGe).

[0078] Fig.9A and Fig. 9B A top view of a CIS 900 having a LEFM configuration is shown. Fig.9A With the above Figure 3 is substantially similar, and includes a plurality of pixels in an array, wherein each pixel includes a color filter and a DPD photodetector configuration. As described above, each DPD includes two photodetectors of equal size. And, each of the two photodetectors is associated with the same color filter. CIS 900 includes pixels of a first color (e.g., green), a second color (e.g., red), and a third color (e.g., blue). However, the arrangement is not limited. The array of CIS 900 includes the first two rows of pixels having a vertically oriented DPD; and the next two rows (below the top two rows) having a horizontally oriented DPD; and the next two rows (below the middle two rows) having a vertically oriented DPD again. That is, the first two rows of the DPD array provide overflow current flow from left to right or right to left (i.e., in the x-direction) to balance the charge of each photodetector or channel of a given DPD, as discussed above with reference to FIG. 5. Similarly, the third and fourth rows (from Fig.9A ) provides overflow current flow in the y-direction to balance the charge of each photodetector or channel of a given DPD, as discussed above with reference to FIG5 .

[0079] Fig. 9B A top view of a block diagram of a CIS 900 with a LEFM configuration is shown. Note that each aperture corresponds to a photodetector or channel of a DPD (or QPD). The gates G1, G2 and / or GD may include n-type and / or p-type gates as described above. Fig. 9Bis a diagram of a portion of a pixel array and may be repeated any number of times on the CIS 900 .

[0080] Fig. 9C Shown along Fig. 9B A cross-sectional view of a portion of CIS 900 in the C-C' direction. Specifically, Fig. 9C A portion of a CIS 900 is shown, including two DPDs 902A and 902B. In an embodiment, DPDs 902A and 902B are alternative QPDs, substantially similar to those discussed above.

[0081] CIS 900 shares many common features with CIS 400 discussed above, and similar features use similar reference numbers. CIS 900 includes substrate 401, which can be substantially similar to that discussed above. A first DPD 902A includes a first channel or photodetector 904A and a second channel or photodetector 904B. A second DPD 902B includes a first channel or photodetector 906A and a second channel or photodetector 906B. Metal isolation features including a composite metal grid 406 and BDTI408 / grooves 408' are formed between the channels. BDTI 408 extends between the first DPD 902A and the second DPD 902B, providing complete isolation. (and between adjacent pixels of different colors). The trench isolation 408' extending between the first channel 904A and the second channel 904B of the DPD 902A does not provide complete isolation, but terminates in the channel region of the substrate 401. Similarly, the trench isolation 408' extending between the first channel 906A and the second channel 906B of the DPD 902B does not provide complete isolation, but terminates within the channel region. Thus, in both cases, the trench isolation 408' allows charge to flow from one channel to an adjacent channel, including the above referenced Figure 5A-Figure 5C discussed.

[0082] A first color filter 416A is formed on the DPD 902A, and a second color filter 416B is formed on the DPD 902B. The first color filter 416A has a different color from the second color filter 416B. For example, in an embodiment, the first color filter 416A is green, and the second color filter 416B is red. The following layer 418 is arranged on the filter 416A / 416B. A first micro lens 420 is formed on the first color filter 416A, and a second micro lens 420 is formed on the second color filter 416B. Each of these features has been discussed in detail above, and it is also applicable to the embodiment of the CIS 900.

[0083] As described above, the front side devices (eg, transistor 424 and isolation regions) are formed on the first side of substrate 401. Furthermore, in an embodiment of CIS 900, the LEFM configuration provides the above-described gates G1, G2, and GD formed on the first side of substrate 401. Fig. 9C In an example, a plurality of gates G1 and G2 are formed. In an embodiment, for DPD 902A, two gates G1 and two gates G2 are formed. In an embodiment, for DPD 902A, two gates G1 and two gates G2 are formed. In an embodiment, for DPD 902A, two gates G1 and two gates G2 are formed. In an embodiment, a first gate G1 is adjacent to gate G2 and is spaced a distance apart, and a trench isolation 408' providing incomplete isolation is directly vertically disposed above a distance between G1 and G2. In other words, one G1 and one G2 are associated with each channel (e.g., 906A) of the DPD. In an embodiment, for DPD 902A, two gates G1 and two gates G2 are formed. In an embodiment, for DPD 902A, two gates G1 and two gates G2 are formed. In an embodiment, one first gate G1 and one second gate G2 are adjacent to BDTI 408, which provides isolation between DPD 902A and adjacent pixels. On the first side of the substrate 401, the devices 424, G1, G2, etc. can be multi-layer interconnects (MLI) 908, which provide multiple conductive metal lines, vias, contacts, and input / output terminals. The MLI 908 electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate electrodes and / or epitaxial source / drain features of p-type transistors and / or n-type transistors) so that the various devices and / or components can be operated as specified by the design requirements of the CIS 900. The MLI features typically include a combination of dielectric layers and conductive layers (e.g., metal layers) that are configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features (e.g., device horizontal contacts and / or vias), and / or horizontal interconnect features (e.g., conductive lines). The vertical interconnect features typically connect horizontal interconnect features in different layers (or different planes) of the MLI. The contact features extend to each G1, G2, and / or device 424. In some implementations, the contact features can include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low-resistivity metal compositions, alloys thereof, or combinations thereof.

[0084] Fig.9D Shown along Fig. 9B A cross-sectional view of a portion of CIS 900 in the D-D' direction. Specifically, Fig.9D A portion of a CIS 900 is shown, including two DPDs (or QPDs) 902A and 902B.

[0085] It should be noted that Fig.9D The cross-sectional view includes Fig. 9C Many features are the same as in the cross-sectional view of FIG. 1 , and similar features are numbered similarly. In some implementations, Fig. 9C The DPD provided in the Fig.9D The cross-sectional views provided in FIG. 1 are different array regions (e.g., different DPDs). Specifically, Fig.9D A cross-sectional view through the gate GD of a LEFM configuration device is shown. Also as described above, the front-side devices (e.g., transistor 424 and isolation regions) are formed on the first side of the substrate 401. Furthermore, in an embodiment of the CIS 900, the LEFM configuration provides a gate GD formed on the first side of the substrate 401. Fig.9D In an example, a plurality of gates GD are formed. In an embodiment, for DPD 902A, two gates GD are formed for the first channel 904A, and two gates GD are formed for the second channel 904B. In an embodiment, the gate GD of channel 904A is adjacent to the gate GD of channel 904B and is spaced a distance apart, and the trench isolation 408' providing incomplete isolation is directly and vertically disposed above a distance between these GDs. On the device 424, GD, etc. on the first side of the substrate 401 may be MLI 908, which provides a plurality of conductive metal lines, vias, contacts, and input / output terminals. The contact features extend to each GD and / or device 424. In some implementations, the contact features may include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low resistivity metal components, alloys thereof, or combinations thereof.

[0086] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a diagram of an example implementation of gates G1 , G2 , and / or GD. Fig. 10A and Fig. 10B Exemplary gate(s) formed on a region of a P-doped substrate 1002 are shown. Fig. 10C and Fig. 10D Exemplary gate(s) formed on an n-well region 1004 of a substrate 1002 are shown. Fig. 10A and Fig. 10B N of GD, G1 and / or G2 is shown + P configuration. Fig. 10C and Fig. 10D PN of GD, G1 and / or G2 is shown + Configuration.

[0087] In some implementations, such as Fig. 10A and Fig. 10BAs shown, the device includes a deep p-well 1006 that forms a guard ring. A P+ region 1008 is formed with a contact to region 1008. P+ region 1008 has a doping profile where the P+ doping is greater than substrate 1002 and P- region 1010. In an embodiment, as shown in FIG. Fig. 10B As shown, region 1010 is formed on substrate 1002. In an embodiment, region 1010 includes p-type dopants. The concentration of p-type dopants may be greater than substrate 1002. N-well 1012 is formed near region 1010. The n-well region may include N-type dopants at a concentration less than that of N+ region 1014.

[0088] In an embodiment, Fig. 10C and Fig. 10D As shown, n-well 1004 is formed on substrate 1002. Substrate 1002 may be a p-type substrate. In some implementations, such as Fig. 10C and Fig. 10D As shown, the device includes a deep p-well 1016, which forms a guard ring. An N+ region 1018 is formed with a contact to region 1018. N+ region 1018 has a doping profile in which the N+ doping is greater than that of n-well 1004. Region 1020 is formed in n-well 1004. Region 1020 may include an n-type dopant having a concentration (e.g., N-) less than the concentration of the n-type dopant of n-well 1004 in which region 1020 is located. P-well 1022 is formed in n-well 1004. P+ region 1024 is formed on p-well 1022. Notably, the concentration of the p-type dopant in P+ region 1024 is greater than the concentration of the p-type dopant in p-well 1022.

[0089] therefore, Figures 10A-10D For example, in the above Figure 7 , Figure 8 , Figure 9A-9D An exemplary structure in which one or more of G1, G2 and / or GD can be implemented in the embodiments discussed in .

[0090] refer to Fig.11 , a flow chart of a method 1100 for forming a CIS according to one or more aspects of the present disclosure is shown. Method 1100 can be implemented to form any device discussed above, alone or in combination. Method 1100 is merely an example, and it is not intended to limit the present disclosure to what is explicitly shown in method 1100. Other steps may be provided before, during, and after method 1100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein.

[0091] At block 1102, a substrate is provided on which a plurality of devices are formed. In some implementations, the substrate is substantially similar to substrate 401 discussed above. In an embodiment, the plurality of devices formed thereon may include transistor devices and surrounding dielectric features formed on a first surface of the substrate. For example, the transistor device may be substantially similar to device 424, as described above with reference to FIG. Figure 4 In an embodiment, the surrounding dielectric features may include isolation features, such as those described above with reference to Figure 4 Isolation features 426 discussed. In an embodiment, the MLI is formed over and connected to devices disposed on the first surface of the substrate. In other embodiments, gates such as G1, G2, and GD may also be fabricated on the first surface.

[0092] At block 1104 of method 1100 (which is optional), the substrate may be flipped over so that further processing is performed on the second surface of the substrate. Block 1104 may be implemented when forming a BSI device. In other embodiments including forming a FSI device, block 1104 may be omitted.

[0093] At block 1106 of method 1100, metal isolation features including a metal grid and a BDTI feature are formed on a surface (e.g., a second surface) of the substrate. The BDTI may include features that provide complete isolation between the photodetectors of the first color filter and the photodetectors of the second color filter. The complete isolation BDTI feature may be substantially similar to the one described above with reference to Figure 4 The BDTI 408 discussed above. The BDTI may also include features that provide partial isolation between photodetectors below the color filter. For example, between photodetectors or channels of a DPD or QPD device. The partial isolation BDTI features may be substantially similar to those described above with reference to Figure 4 The trench isolation 408' is discussed.

[0094] At block 1108 of method 1100, a color filter may then be disposed over the substrate. In some implementations, the color filter is disposed over the second surface of the substrate. For example, when forming a BSI device, the color filter is disposed over the second surface of the substrate, which is opposite to the first surface of the substrate including the plurality of devices of block 1102. The color filter may be substantially similar to the above referenced Figure 4 The color filters 416A, 416B discussed. The color filters can be placed at the openings of the grid of metal isolation features of block 1106. At block 1110 of method 1100, microlenses are formed over the color filter layer. The microlenses can be substantially similar to those described above with reference to Figure 4 The microlens 420 in question.

[0095] Embodiments of the present disclosure provide benefits. For example, the present disclosure provides an image sensor including a photodiode in a sensor substrate. The photodiode is separated by a metal deep trench isolation feature that can extend completely through the thickness of the sensor substrate to isolate adjacent pixels. The metal deep trench isolation feature can also include a trench that extends partially through the thickness of the substrate to provide partial isolation between adjacent channels / photodetectors within a pixel, such as between the dual photodetectors of a single color filter pixel in a DPD, or between adjacent channels / photodetectors within a QPD. The path for current to flow between partially isolated channels allows the device to reach the FWC in a faster time because the charge overflowing from one channel is provided to the adjacent channel. This will produce a faster response time of the device. Embodiments are also provided that provide the advantage of using a lateral field charge modulator to enhance high dynamic range (HDR) performance. Advantages of using various layouts of DPD for a given color pixel are also provided, which can also provide faster response times. These features can be used together or separately.

[0096] Therefore, in some embodiments, the present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor device, the semiconductor device includes a semiconductor layer and a plurality of isolation trench features disposed in the semiconductor layer. The plurality of isolation trench features include a first trench extending through the entire semiconductor layer, a second trench extending through a portion of the semiconductor layer and having an end in the semiconductor layer, and a third trench extending through the entire semiconductor layer, wherein the cross-sectional view is that the second trench is inserted between the first trench and the third trench. A color filter is above the semiconductor layer, and a microlens is disposed on the color filter.

[0097] In an embodiment, the color filter is a monochrome color filter and is vertically located above the first trench, the second trench, and the third trench. In an embodiment, the second trench extends in a first direction in a top view. In a further implementation, the first photodetector extends between the first trench and the second trench, and the second photodetector extends between the second trench and the third trench. The photocurrent from the first photodetector can be used to transmit to the second photodetector. In some implementations, a third photodetector and a fourth photodetector are also included, wherein a fourth trench extending through a portion of the semiconductor layer and having an end in the semiconductor layer is inserted between the third photodetector and the fourth photodetector, and the fourth trench extends in a second direction in a top view. In an embodiment, a plurality of isolation trench features are adjacent to a metal grid disposed above the semiconductor layer and below the microlens. A control gate is formed on a surface of the semiconductor layer, the surface being opposite to the color filter. And, in some implementations, the control gate includes a double gate. In another embodiment, a second control gate and a third control gate on the surface of the semiconductor layer are also included, and the second control gate and the third control gate are single gates. In an embodiment of the structure, the isolation trench feature includes a dielectric liner layer and a metal layer.

[0098] In a broader form of an embodiment of the present disclosure, an image sensor includes a lens array, including a first lens and a second lens, each of which is disposed on a semiconductor substrate. A first color filter is disposed vertically below the first lens, and a second color filter is disposed vertically below the second lens. It also includes a first deep trench isolation (DTI) feature, a second DTI feature, and a third DTI feature, wherein each of the first DTI feature, the second DTI feature, and the third DTI feature extends from a first surface of the semiconductor substrate to an isolation region on a second surface of the semiconductor substrate. A first dual photodetector (DPD) is vertically below the first lens and the first color filter, and a second DPD is vertically below the second lens and the second color filter. The first DPD is disposed between the first DTI feature and the second DTI feature, and the second DPD is disposed between the second DTI feature and the third DTI feature. The first DPD is configured to allow a photocurrent to flow from a first photodetector of the first DPD to a second photodetector of the first DPD.

[0099] In a further embodiment, the first DPD includes a first trench isolation structure extending from a first surface of the semiconductor substrate to an end within the semiconductor substrate and spaced a certain distance from a second surface of the semiconductor substrate. The first trench isolation structure is disposed between the first photodetector and the second photodetector. In an embodiment, the second DPD is configured to allow a photocurrent to flow from a third photodetector of the second DPD to a fourth photodetector of the second DPD. And, in a further implementation, the second DPD includes a second trench isolation structure extending from a first surface of the semiconductor substrate to an end within the semiconductor substrate and spaced a certain distance from the second surface of the semiconductor substrate. The second trench isolation structure is disposed between the third photodetector and the fourth photodetector. In an embodiment, the first trench isolation structure provides an interface between the first photodetector and the second photodetector of the first DPD extending in the x-direction, and the second trench isolation structure provides an interface between the third photodetector and the fourth photodetector of the second DPD extending in the y-direction. In an embodiment, the first DPD is located in a first row of the DPD array, and the second DPD is located in a second row of the DPD array. Furthermore, the first lens and the second lens may provide an aperture, and in a top view, the first control gate (G1) and the second control gate (G2) are disposed on a first side and an opposite second side of the aperture. In an embodiment, in a top view, the third control gate is disposed on a third side of the aperture, and the fourth control gate is disposed on a fourth side of the aperture, the third control gate and the fourth control gate are dual-gate structures, and G1 and G2 are each single-gate structures.

[0100] In another broader embodiment discussed herein, a method of operating an image sensor is discussed. The method includes providing an image sensor having a color filter array, and a plurality of photodetector channels are associated with each filter in the color filter array. Incident light is provided to the color filter array, including a first color filter incident on the color filter array. The incident light is passed through the first color filter to a first photodetector channel and a second photodetector channel. A photocurrent is provided from the first photodetector channel to the second photodetector channel.

[0101] In another embodiment, providing an image sensor includes providing a lens array over a color filter array, and the lens array is offset in an x-direction and a y-direction. In an embodiment, providing a photoelectric current includes implementing a transverse electric field charge modulator.

[0102] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure. For example, by achieving different thicknesses for bit line conductors and word line conductors, different resistances can be achieved for the conductors. However, other techniques for changing the resistance of metal conductors can also be used.

[0103] Example 1 is a semiconductor device comprising: a semiconductor layer; a plurality of isolation trench features disposed in the semiconductor layer, wherein the plurality of isolation trench features include a first trench extending through the entire semiconductor layer, a second trench extending through a portion of the semiconductor layer and having an end within the semiconductor layer, and a third trench extending through the entire semiconductor layer, wherein a cross-sectional view is that the second trench is inserted between the first trench and the third trench; a color filter above the semiconductor layer; and a microlens disposed above the color filter.

[0104] Example 2 is the semiconductor device of Example 1, wherein the color filter is a monochrome color filter and is vertically located above the first trench, the second trench, and the third trench.

[0105] Example 3 is the semiconductor device of Example 1, wherein the second trench extends along a first direction in a top view.

[0106] Example 4 is a semiconductor device described in Example 3, further including: a first photodetector and a second photodetector, wherein the first photodetector extends between the first trench and the second trench and the second photodetector extends between the second trench and the third trench, wherein a photocurrent from the first photodetector can be used to be transmitted to the second photodetector.

[0107] Example 5 is the semiconductor device described in Example 4, further including: a third photodetector and a fourth photodetector, wherein a fourth trench extending through a portion of the semiconductor layer and having an end within the semiconductor layer is inserted between the third photodetector and the fourth photodetector, wherein the fourth trench extends along the second direction in a top view.

[0108] Example 6 is the semiconductor device of Example 1, wherein the plurality of isolation trench features are adjacent to a metal grid disposed above the semiconductor layer and below the microlens.

[0109] Example 7 is the semiconductor device described in Example 1, wherein the control gate is on a surface of the semiconductor layer, the surface being opposite to the color filter.

[0110] Example 8 is the semiconductor device of Example 7, wherein the control gate comprises a double gate.

[0111] Example 9 is the semiconductor device described in Example 8, further comprising: a second control gate and a third control gate on the surface of the semiconductor layer, wherein the second control gate and the third control gate are single gates.

[0112] Example 10 is the semiconductor device of Example 1, wherein the isolation trench feature comprises a dielectric liner layer and a metal layer.

[0113] Example 11 is an image sensor, comprising: a lens array, including a first lens and a second lens, each of which is arranged on a semiconductor substrate; a first color filter and a second color filter, the first color filter is vertically below the first lens and the second color filter is vertically below the second lens; a first deep trench isolation (DTI) feature, a second DTI feature, and a third DTI feature, wherein each of the first DTI feature, the second DTI feature, and the third DTI feature extends from a first surface of the semiconductor substrate to an isolation region on a second surface of the semiconductor substrate; a first dual photodetector (DPD) and a second DPD, the first DPD is vertically below the first lens and the first color filter, and the second DPD is vertically below the second lens and the second color filter, wherein the first DPD is arranged between the first DTI feature and the second DTI feature, and wherein the second DPD is arranged between the second DTI feature and the third DTI feature; wherein the first DPD is configured to allow photocurrent to flow from a first photodetector of the first DPD to a second photodetector of the first DPD.

[0114] Example 12 is the image sensor described in Example 11, wherein the first DPD includes a first trench isolation structure extending from a first surface of the semiconductor substrate to an end within the semiconductor substrate and spaced a certain distance from a second surface of the semiconductor substrate, wherein the first trench isolation structure is arranged between the first photodetector and the second photodetector.

[0115] Example 13 is the image sensor of Example 12, wherein the second DPD is configured to allow photocurrent to flow from a third photodetector of the second DPD to a fourth photodetector of the second DPD.

[0116] Example 14 is the image sensor described in Example 13, wherein the second DPD includes a second trench isolation structure extending from the first surface of the semiconductor substrate to an end within the semiconductor substrate and spaced a certain distance from the second surface of the semiconductor substrate, wherein the second trench isolation structure is arranged between the third photodetector and the fourth photodetector.

[0117] Example 15 is the image sensor of Example 14, wherein the first trench isolation structure provides an interface extending in the x-direction between the first photodetector and the second photodetector of the first DPD, and wherein the second trench isolation structure provides an interface extending in the y-direction between the third photodetector and the fourth photodetector of the second DPD.

[0118] Example 16 is the image sensor of Example 11, wherein the first lens and the second lens provide an aperture, and wherein, in a top view, a first control gate (G1) and a second control gate (G2) are disposed on a first side and an opposite second side of the aperture.

[0119] Example 17 is the image sensor described in Example 16, wherein, in a top view, a third control gate is disposed on a third side of the aperture, and a fourth control gate is disposed on a fourth side of the aperture, wherein the third control gate and the fourth control gate are a dual gate structure, and wherein G1 and G2 are each a single gate structure.

[0120] Example 18 is a method of operating an image sensor, comprising: providing the image sensor having a color filter array, wherein a plurality of photodetector channels are associated with each filter in the color filter array; providing incident light to the color filter array, including a first filter incident on the color filter array; passing the incident light through the first filter to a first photodetector channel and a second photodetector channel; and providing a photocurrent from the first photodetector channel to the second photodetector channel.

[0121] Example 19 is the method of Example 18, wherein providing the image sensor includes: providing a lens array above the color filter array, wherein the lens array is offset in the x-direction and the y-direction.

[0122] Example 20 is the method of Example 18, wherein providing the photoelectric current includes: implementing a lateral electric field charge modulator.

Claims

1. A semiconductor device, include: Semiconductor layer; a plurality of isolation trench features disposed in the semiconductor layer, wherein the plurality of isolation trench features include a first trench extending through the entire semiconductor layer, a second trench extending through a portion of the semiconductor layer and having a terminal end within the semiconductor layer, and a third trench extending through the entire semiconductor layer, wherein a cross-sectional view is such that the second trench is interposed between the first trench and the third trench; a color filter on the semiconductor layer; and The microlens is arranged on the color filter.

2. The semiconductor device according to claim 1, in, The color filter is a monochrome color filter and is vertically located above the first trench, the second trench, and the third trench.

3. The semiconductor device according to claim 1, in, The second trench extends along a first direction in a top view.

4. The semiconductor device according to claim 3, further comprising: include: and a first photodetector and a second photodetector, the first photodetector extending between the first trench and the second trench and the second photodetector extending between the second trench and the third trench, wherein a photocurrent from the first photodetector is available for transfer to the second photodetector.

5. The semiconductor device according to claim 4, further comprising: include: A third photodetector and a fourth photodetector, wherein a fourth trench extending through a portion of the semiconductor layer and having an end in the semiconductor layer is interposed between the third photodetector and the fourth photodetector, wherein the fourth trench extends along the second direction in a top view.

6. The semiconductor device according to claim 1, in, The plurality of isolation trench features are adjacent to a metal grid disposed above the semiconductor layer and below the microlenses. 7 . The semiconductor device according to claim 1 , wherein a control gate is on a surface of the semiconductor layer, the surface being opposite to the color filter.

8. The semiconductor device according to claim 7, in, The control gate includes a double gate.

9. An image sensor, include: A lens array includes a first lens and a second lens, each of which is disposed on a semiconductor substrate; a first color filter and a second color filter, the first color filter being vertically below the first lens and the second color filter being vertically below the second lens; a first deep trench isolation (DTI) feature, a second DTI feature, and a third DTI feature, wherein each of the first DTI feature, the second DTI feature, and the third DTI feature extends from a first surface of the semiconductor substrate to an isolation region on a second surface of the semiconductor substrate; a first dual photodetector DPD and a second DPD, the first DPD being vertically below the first lens and the first color filter, and the second DPD being vertically below the second lens and the second color filter, wherein the first DPD is disposed between the first DTI feature and the second DTI feature, and wherein the second DPD is disposed between the second DTI feature and the third DTI feature; The first DPD is configured to allow photocurrent to flow from a first photodetector of the first DPD to a second photodetector of the first DPD.

10. A method of operating an image sensor, include: providing said image sensor with a color filter array, wherein a plurality of photodetector channels are associated with each color filter in said color filter array; providing incident light to the color filter array, including incident light to a first color filter of the color filter array; passing the incident light through the first color filter to a first photodetector channel and a second photodetector channel; and A photocurrent is provided from the first photodetector channel to the second photodetector channel.

Images