Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming the same are provided. The method includes forming a plurality of structures on a substrate; forming a layer between the structures; performing a first etching process to recess the layer to a surface having a serrated profile; optionally forming one or more films on the surface, wherein the one or more films retain a serrated profile; depositing a material on the substrate; selectively masking the material to define a masked portion of the material and an unmasked portion of the material; and performing a second etching process to etch a portion of the material and form a material having sidewalls, where the second etching process exposes the serrated profile, and where ions are reflected by the serrated profile in the second etching process.

Description

Technical Field

[0001] The present disclosure provides a semiconductor device and a method for forming the same. Background Art

[0002] The electronics industry continues to demand smaller and faster electronic devices that can support increasingly complex and sophisticated functions. As a result, the semiconductor industry continues to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by reducing the size (e.g., minimum feature size) of semiconductor integrated circuits, thereby increasing production efficiency and reducing associated costs. However, this development has also increased the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor integrated circuits and devices require similar advances in semiconductor manufacturing processes and technologies. Summary of the invention

[0003] The present disclosure provides a method for forming a semiconductor device. The method includes the following operations. A plurality of structures are formed on a substrate. A layer is formed between the structures. A first etching process is performed to recess the layer to a surface having a sawtooth profile. One or more thin films are optionally formed on the surface, wherein the thin films retain the sawtooth profile. A material is deposited on the substrate. A second etching process is performed to etch a portion of the material and form the material having a sidewall, wherein the second etching process exposes the sawtooth profile, and wherein a plurality of ions are reflected by the sawtooth profile during the second etching process.

[0004] The present disclosure also provides a method for forming a semiconductor device. The method includes the following operations. Forming a first fin structure and a second fin structure. Forming an isolation region between the first fin structure and the second fin structure. Recessing the isolation region to provide an isolation region having a corrugated recessed surface. Depositing a sacrificial gate material on the isolation region. Etching a portion of the sacrificial gate material to form a sacrificial gate.

[0005] The present disclosure further provides a semiconductor device. The semiconductor device includes: a first dielectric region spaced apart from a second dielectric region in a longitudinal direction Y; a first source / drain region spaced apart from a second source / drain region in a lateral direction X, wherein the first source / drain region is located between the first dielectric region and the second dielectric region; a fin structure including a semiconductor nanosheet spaced apart from a mesa portion in a vertical direction Z, wherein the semiconductor nanosheet extends from the first source / drain region to the second source / drain region in the lateral direction X; a gate structure overlying the fin structure, wherein the gate structure includes a metal gate and a high-k gate dielectric, wherein the gate structure extends along the longitudinal direction Y, and wherein the bottommost portion of the gate structure is located between the mesa portion and the semiconductor nanosheet; a first inner spacer separating the first source / drain region from the bottommost portion of the gate structure in the lateral direction X; a first spacer structure separating the first dielectric region from the gate structure in the lateral direction X; and a second spacer structure separating the second dielectric region from the gate structure in the lateral direction X. A minimum first distance between the first spacer structure and the first inner spacer in the longitudinal direction Y is 0 nm to 2 nm, and a minimum second distance between the second spacer structure and the first inner spacer in the longitudinal direction Y is 0 nm to 2 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 The various aspects of the present disclosure are best understood from the following detailed description when read together. It should be noted that, in accordance with standard practice in the industry, various features may not be drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced to make the discussion clear.

[0007] Figure 1 is a perspective view of a semiconductor device according to some embodiments;

[0008] Figure 2 yes Figure 1 Along Figure 1 A vertical cross-sectional view of the semiconductor device in the direction X and the direction Z;

[0009] Figure 3 yes Figure 1 Along Figure 1 A horizontal cross-sectional view of the semiconductor device in the direction X and the direction Y;

[0010] Figure 4 is a flowchart of a method according to some embodiments;

[0011] Figures 5 to 25 is a diagram of a structure of a semiconductor device in successive manufacturing stages according to some embodiments, wherein Figure 5 It is a perspective view. Figure 6 is a perspective view in successive stages, Figure 7 is the cross-sectional view along direction X in the continuous stage, Figure 8 is the cross-sectional view along direction X in the continuous stage, Fig. 9 yes Figure 8 And with Figure 8 Cross-section of the focused part at the same stage, Fig.10 is the cross-sectional view along direction X in the continuous stage, Figures 11 to 13 Shown with Fig.11 Perspective drawings of the installation at the same successive stages, Fig.12 yes Fig.11 Cross-section along direction X, Fig.13 yes Fig.11 Cross-section along direction X, Figures 14 to 17 Shown with Fig.14 perspective view of the device at the same successive stages, Fig.15 yes Fig.14 A cross-sectional view along the direction Y through the fin, Fig.16 yes Fig.14 A cross-sectional view along a direction X adjacent to the sacrificial gate structure and through the gate residue, Fig.17 yes Fig.14 A cross-sectional view along direction Y adjacent to the fin and through the gate residue, Fig.18 is a perspective view in successive stages, Fig.19 is a perspective view in successive stages, Fig. 20 yes Fig.19 A cross-sectional view of the device along line 6-6 of the stage, Fig.21 is a perspective view in successive stages, Fig. 22 yes Fig.21 A cross-sectional view of the device along line 7-7 of the stage, Fig.23 is the cross-sectional view along direction Y in the continuous stage, Fig.24 is the cross-section along direction Y in the successive stages, and Fig.25 It is a cross-sectional view along direction Y in the continuous stages.

[0012]

Explanation of symbols

[0013] 6-6: Line

[0014] 7-7: Line

[0015] 100:Substrate

[0016] 200: Fin

[0017] 200a: Part

[0018] 210: Countertop

[0019] 211: Surface

[0020] 212: Epitaxial stacking

[0021] 214: Epitaxial layer

[0022] 217: Mask layer

[0023] 218: First mask layer

[0024] 219: Second mask layer

[0025] 220:Nanosheet

[0026] 221:Nanosheet

[0027] 222:Nanosheet

[0028] 223:Nanosheet

[0029] 225: Mask layer

[0030] 226: Mask layer

[0031] 227: Mask layer

[0032] 229: Side wall

[0033] 233: Bottom clearance surface

[0034] 234: Gap

[0035] 235: Fin segment

[0036] 236: Cavity

[0037] 299: Oxide layer

[0038] 300: Isolation Features

[0039] 310: Surface

[0040] 311: Middle trough

[0041] 312: Terminal trough

[0042] 313: Terminal trough

[0043] 314: Middle peak

[0044] 315: Middle peak

[0045] 316: terminal peak

[0046] 317: terminal peak

[0047] 336: Concave surface

[0048] 350: Layer

[0049] 390: Isolation material

[0050] 391: Flattening the surface

[0051] 400: Gate structure

[0052] 400': Sacrificial gate structure

[0053] 410: Gate dielectric

[0054] 410': Sacrificial gate dielectric layer

[0055] 420:Metal Electrode

[0056] 420': Sacrificial gate electrode layer

[0057] 421: Part

[0058] 422: Part

[0059] 423: Part

[0060] 424: Part

[0061] 430': Sidewall

[0062] 499: Residue

[0063] 500: Source / drain region

[0064] 501: first source / drain region

[0065] 502: Second source / drain region

[0066] 503: third source / drain region

[0067] 550: epitaxial region

[0068] 560: Dielectric layer

[0069] 600: Dielectric structure

[0070] 601: Area

[0071] 602: Area

[0072] 610: Layer

[0073] 620: Layer

[0074] 631: Edge

[0075] 700: Interstitial

[0076] 701: First spacer structure

[0077] 702: Second spacer structure

[0078] 710: Lining material layer

[0079] 720: Dielectric material layer

[0080] 800:Internal gap

[0081] 801: First End

[0082] 802: Second end

[0083] 805: Interface

[0084] 900: Method

[0085] 1000: Installation

[0086] A1:Inner corner

[0087] A2: Angle

[0088] d1: minimum distance

[0089] d2: minimum distance

[0090] D1: vertical distance

[0091] D2: vertical distance

[0092] D3: Vertical distance

[0093] D4: Vertical distance

[0094] D5: Vertical distance

[0095] D6: Vertical distance

[0096] D7: Vertical distance

[0097] H1: Vertical height

[0098] H2: Height

[0099] P1: Plane

[0100] P2: Plane

[0101] S902: Operation

[0102] S904: Operation

[0103] S906: Operation

[0104] S908: Operation

[0105] S910: Operation

[0106] S912: Operation

[0107] S914: Operation

[0108] S916: Operation

[0109] S918: Operation

[0110] S920: Operation

[0111] S922: Operation

[0112] S924: Operation

[0113] S926: Operation

[0114] S928: Operation

[0115] S930: Operation

[0116] S932: Operation

[0117] S934: Operation

[0118] W1: Maximum horizontal width

[0119] W2: Maximum vertical width

[0120] X: Direction

[0121] Y: direction

[0122] Z: Direction DETAILED DESCRIPTION

[0123] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter. Specific examples of components and compositions are described below to simplify the disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the subsequent description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. As used herein, "directly covering" refers to the vertical alignment between features, so that when the upper feature is directly located on the lower feature, the vertical axis passes through the two features. In addition, the disclosure may repeat figure numerals and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0124] As used herein, "positive slope" and "negative slope" refer to a typical reference system where a positive slope is defined as an increase in the vertical or z-axis as the lateral or x-axis increases, and a negative slope is defined as a decrease in the vertical or z-axis as the lateral or x-axis increases.

[0125] In addition, spatially relative terms, such as "directly above," "above," "overlying," "on," "above," "below," "underlying," "lower," "below," "bottom," "side," "positively sloped," and "negatively sloped," etc., may be used herein to facilitate description to describe the relationship of one element or feature to another element or feature in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

[0126] In some embodiments herein, a "material layer" is a layer comprising at least 50% by weight of a discernible material, such as at least 60% by weight of a discernible material, or at least 75% by weight of a discernible material, or at least 90% by weight of a discernible material; and a layer as a "material" comprises at least 50% by weight of a discernible material, such as at least 60% by weight of a discernible material, at least 75% by weight, at least 90% by weight, at least 99% by weight, or at least 99.9% by weight of a discernible material. For example, in some embodiments, a titanium nitride layer and a layer having titanium nitride are a layer of at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 99% by weight, or at least 99.9% by weight of titanium nitride.

[0127] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices may not be described in detail herein. In addition, the various operations and processes described herein may be incorporated into a more comprehensive process or process having additional functions not described in detail herein. In particular, the various processes in the manufacture of semiconductor devices are well known, and therefore, for the sake of brevity, many processes are only briefly mentioned herein, or are completely omitted without providing well-known process details. As is readily recognized by those of ordinary skill in the art upon a complete reading of the disclosure, the structure of the disclosure herein may employ a variety of techniques and may be incorporated into a variety of semiconductor devices and products. In addition, it should be noted that the semiconductor device structure includes different numbers of elements, and a single element shown in the figure may represent multiple elements.

[0128] As described herein, a method is performed to reduce residue on the sidewalls of a structure after an etching process. Specifically, the method reduces residue at the intersection or junction of two sidewalls, i.e., at an inner corner, such as a 90 degree inner corner. For example, during the formation of a sacrificial structure (e.g., a sacrificial gate), a sacrificial material is deposited on a fin structure and on an isolation material located between the fin structures. The sacrificial material is then patterned to form a sacrificial gate. During this process, unintended residues of the sacrificial material may remain at the junction of the sidewalls of the fin structure and the sidewalls of the sacrificial gate. In addition, such residues may cause improper formation of later formed structures, resulting in electrical shorts or other problems.

[0129] In this embodiment, before the sacrificial material is deposited, the isolation material is recessed into a jagged surface. For example, the recessed surface of the isolation material has a waveform shape or pattern and includes alternating peaks and valleys. Then, the sacrificial material is deposited on the fin structure and the recessed isolation material. In the etching process for patterning the sacrificial material, after removing the selected portion of the sacrificial material, the plasma ions are reflected from the waveform to the sidewalls of the sacrificial gate and / or the sidewalls of the fin structure. Therefore, the amount of unwanted residue is reduced or eliminated.

[0130] Implementations of the present disclosure provide advantages over the prior art, although it is understood that other implementations may provide different advantages and that not all advantages are necessarily discussed herein, and not all implementations require a particular advantage.

[0131] To facilitate the following discussion, Figures 1 to 3 A portion of a semiconductor device 1000 fabricated according to the methods described herein is shown. Figure 1 It is a perspective view. Figure 2 It is along Figure 1 The cross-sectional views in the X and Z directions, and Figure 3 It is along Figure 1 Cross-sectional views in the X and Y directions.

[0132] Although Figures 1 to 3 The semiconductor device 1000 is shown as a gate-all-around (GAA) device, but the device 1000 may form another type of semiconductor device. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA device, where the GAA device has gate material disposed on four sides of at least one channel element of the device. The channel element may be referred to as a "nanosheet."

[0133] like Figures 1 to 3As shown, the device 1000 includes a substrate 100, such as a semiconductor substrate. In some embodiments, the substrate 100 may be formed of silicon and include silicon. Alternatively or additionally, the substrate 100 includes another element semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP. In another alternative, the substrate 100 is a semiconductor on insulator (SOI). A plurality of conductive and non-conductive films may include insulators or conductive materials. For example, conductive materials include metals such as aluminum (Al), copper (Cu), tungsten (W), nickel (Ni), titanium (Ti) and platinum (Pt) and alloys of such metals and other conductive substances, such as nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN)) and carbides (e.g., titanium carbide (TiC), tantalum carbide (TaC)). Insulator materials may include silicon oxide and silicon nitride.

[0134] like Figures 1 to 3 As shown, the device 1000 further includes a fin 200. The fin 200 may be formed by the substrate 100. For example, the fin 200 may include a mesa portion 210 formed by the substrate 100. In addition, the fin 200 may include a semiconductor nanosheet 220, and the nanosheet 220 may include a nanosheet 221, a nanosheet 222, and a nanosheet 223. Figures 1 to 3 Three nanosheets 220 are shown, but the fins 200 of the device 1000 may include any suitable number of nanosheets 220. Each fin 200 may include a bottom-most semiconductor nanosheet 221 spaced apart from the mesa portion 210 in the vertical direction Z, and nanosheets 222 and 223 spaced apart from the bottom-most semiconductor nanosheet 221 in the vertical direction Z.

[0135] The fins 200 extend in the X direction and are spaced apart from each other in the Y direction.

[0136] Likewise, the device 1000 may include an isolation feature 300, such as a shallow trench isolation (STI) region, adjacent to each fin 200. The isolation features 300 extend in a direction X and are spaced apart from each other in a direction Y. In some embodiments, the isolation features 300 include silicon oxide. The isolation features 300 may include other suitable materials.

[0137] like Figures 1 to 3As shown, the device 1000 further includes a gate structure 400. The gate structures extend in a direction Y and are spaced apart from each other in a direction X. In some embodiments, the gate structure 400 is a high-K metal gate structure and includes a high-K gate dielectric 410 and a metal electrode 420. As shown, the high-K gate dielectric 410 can be formed on the isolation feature 300, on and around the semiconductor nanosheet 220, and on the mesa portion 210 of the fin 200.

[0138] Therefore, the gate structure 400 may include a portion 421 located between the bottommost nanosheet 221 and the mesa portion 210 , a portion 422 between the middle nanosheet 222 and the bottommost nanosheet 221 , a portion 423 between the topmost nanosheet 223 and the middle nanosheet 222 , and an upper portion 424 located on the topmost nanosheet 223 .

[0139] like Figures 1 to 3 As shown, the device 1000 also includes a source / drain region 500. As used herein, "source / drain region" may refer to a source region or a drain region individually or collectively, depending on the context. The source / drain region 500 includes a first source / drain region 501 spaced apart from a second source / drain region 502 and a third source / drain region 503 in a lateral direction X, such as Figure 2 shown.

[0140] like Figure 2 As further shown in FIG. 5 , the nanosheets 220 extend along a lateral direction X between adjacent source / drain regions 500 .

[0141] like Figure 2 As further shown in FIG. 5 , the bottom epitaxial region 550 may be located below the source / drain region 500 .

[0142] Likewise, inner spacers 800 are laterally located between portions 421 , 422 , and 423 of the gate and source / drain regions 500 .

[0143] like Figures 1 to 3 As further shown in FIG. 6 , a dielectric structure 600 is vertically disposed on each source / drain region 500. The dielectric structure 600 may include a layer 610 and a layer 620. For example, the layer 610 may be an etch stop layer, and the layer 620 may be an interlayer dielectric material.

[0144] exist Figures 1 to 3, a spacer 700 is located between each dielectric structure 600 and the gate structure 400. The spacer 700 may include a first liner material layer 710 and a second dielectric material layer 720. For example, the first liner material layer 710 may be a first spacer layer, and the second dielectric material layer 720 may be a second spacer layer.

[0145] refer to Figure 3 , the dielectric structure 600 includes a first dielectric structure or region 601 spaced apart from a second dielectric structure or region 602 in a longitudinal direction Y. As shown, the first source / drain region 501 is located between the first dielectric region 601 and the second dielectric region 602 in the longitudinal direction Y.

[0146] Figure 3 It is shown that the inner spacer 800 separates the first source / drain region 501 from the bottommost portion 421 of the gate structure 400 in the lateral direction X, the first spacer structure 701 separates the first dielectric region 601 from the gate structure 400 in the lateral direction X, and the second spacer structure 702 separates the second dielectric region 602 from the gate structure 400 in the lateral direction X.

[0147] As a result of the fabrication methods described herein, the device 1000 is formed to reduce susceptibility to shorting between the source / drain regions 500 and the gate structure 400. Specifically, the distance between the inner spacer 800 and the adjacent spacer 700 in the longitudinal direction Y is reduced. Figure 3 In the embodiment, the inner spacer 800 extends along the longitudinal direction Y to a first end 801 , and extends along the longitudinal direction Y to a second end 802 .

[0148] The first end 801 is spaced a minimum distance d1 from the first spacer structure 701. In some embodiments, the minimum distance d1 is from zero (i.e., the inner spacer 800 is in contact with the first spacer structure 701) to 2 nanometers (nm). The second end 802 is spaced a minimum distance d2 from the second spacer structure 702. In some embodiments, the minimum distance d2 is from zero (i.e., the inner spacer 800 is in contact with the second spacer structure 702) to 2 nanometers (nm).

[0149] In some embodiments, the minimum distance d1 between the first spacer structure 701 and the inner spacer 800 is located at the interface 805 between the inner spacer 800 and the spacer 700 in the longitudinal direction Y, and the metal gate structure 400 extends toward the interface 805 to the vertical edge 631. As shown, the lateral profile of the edge 631 of the metal electrode 420 has an internal angle A1 greater than 100 degrees. For example, the internal angle A1 can be 100 degrees to 120 degrees. In some embodiments, the internal angle A1 can be at least 100 degrees, at least 105 degrees, at least 110 degrees, or at least 115 degrees, and can also be at most 120 degrees, at most 115 degrees, at most 110 degrees, or at most 105 degrees.

[0150] Now refer to Figure 4 , according to various aspects of the present disclosure, for forming, for example, Figures 1 to 3 A method 900 of structuring a multi-gate device 1000 of an embodiment is shown in a flow chart.

[0151] Figure 4 Combination Figures 5 to 25 1 and 10. The present invention is described and shows a semiconductor device 1000 at various stages of manufacture according to some embodiments of the method 900 of the present disclosure. The method 900 is only an example and is not intended to limit the present disclosure beyond the contents explicitly listed in the scope of the patent application. Additional steps may be provided before, between, and after the method 900, and some of the steps described may also be moved, replaced, or eliminated as other embodiments of the method 900. Additional features may be added to the semiconductor device described in the figure, and some of the features described below may be replaced, modified, or removed in other embodiments of the semiconductor device.

[0152] As with other embodiments and devices discussed herein, it is understood that the elements in the semiconductor device 1000 can be manufactured by typical semiconductor technology process flows, so only some processes are briefly described herein. In addition, the semiconductor device can include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses and / or other logic devices, etc., but are simplified for a better understanding of the concepts of the present disclosure. In some embodiments, these devices include multiple semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., and they can be connected to each other.

[0153] In operation S902, method 900 ( Figure 4 ) provides a substrate 100, such as Figure 5As shown. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 100 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. The substrate 100 may include various doping configurations, depending on design requirements known in the art. For example, different doping profiles (e.g., p-well, n-well) may be formed on the substrate 100 for regions of different device types (e.g., n-type field effect transistor (NFET), p-type field effect transistor (PFET)). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for p-well and phosphorus (P) for n-well. In some embodiments, the substrate 100 includes a single crystalline semiconductor layer at least on a surface portion thereof. The substrate 100 may include a single crystalline semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, the substrate 100 may include a compound semiconductor and / or an alloy semiconductor. In the illustrated embodiment, the substrate 100 is formed of crystalline Si.

[0154] like Figure 5 As shown, in operation S904, method 900 ( Figure 4 ) One or more epitaxial layers are formed on the substrate 100. In some embodiments, an epitaxial stack 212 is formed on the substrate 100. The epitaxial stack 212 includes an epitaxial layer 214 of a first component and an epitaxial layer or nanosheet 220 of a second component interposed between the epitaxial layers 214. The first component and the second component may be different. Embodiments may include providing a first component and a second component with different oxidation rates and / or etching selectivities. In one embodiment, the epitaxial layer 214 is SiGe, and the epitaxial layer or nanosheet 220 is silicon. In embodiments where the epitaxial layer 214 includes SiGe and the epitaxial layer or nanosheet 220 includes silicon, the oxidation rate of silicon is less than the oxidation rate of SiGe. It should be noted that the oxidation rate shown in Figure 5 The three layers of epitaxial layers 214 and the three layers of epitaxial layers or nanosheets 220 are for illustrative purposes only and are not intended to be limiting beyond the specific contents listed in the scope of the patent application. It is understood that any number of epitaxial layers can be formed in the epitaxial stack 212, and the number of layers depends on the number of channel regions required in the GAA device 1000. In some embodiments, the number of epitaxial layers or nanosheets 220 is between 2 and 10, such as 6 or 7.

[0155] In some embodiments, the epitaxial layer 214 has a thickness range of 5 nanometers to 15 nanometers. The thickness of the epitaxial layer 214 can be substantially uniform. In some embodiments, the epitaxial layer or nanosheet 220 has a thickness range of 5 nanometers to 15 nanometers. In some embodiments, the thickness of the epitaxial layer or nanosheet 220 in the stack is substantially uniform. As described in more detail below, the epitaxial layer or nanosheet 220 can be used as a channel region of a subsequently formed multi-gate device 1000 and has a thickness selected based on device performance considerations. The epitaxial layer 214 is used to define the gap between adjacent channel regions for the subsequently formed multi-gate device 1000 and has a thickness selected based on device performance considerations.

[0156] As an example, the epitaxial growth of the epitaxial stack 212 can be achieved by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer, such as the epitaxial layer or the nanosheet 220, includes the same material as the substrate 100. In some embodiments, the epitaxially grown epitaxial layer 214 and / or the nanosheet 220 includes a different material from the substrate 100. As described above, in at least some examples, the epitaxial layer 214 includes an epitaxially grown Si 1-x Ge x layer (where x is 0.10 to 0.55), and the epitaxial layer or nanosheet 220 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, any one of the epitaxial layer 214 and the nanosheet 220 may include other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP; or combinations thereof. As described above, the materials of the epitaxial layer 214 and the nanosheet 220 can be selected based on properties that provide different oxidation and etching selectivities. In different embodiments, the epitaxial layer 214 and the nanosheet 220 are substantially free of dopants (i.e., have 0 cm -3 Up to 1×10 17 cm -3 In some embodiments, the bottom and top layers of the epitaxial stack 212 are SiGe layers (not shown). In an alternative embodiment, the bottom layer of the epitaxial stack 212 is a Si layer, and the top layer of the epitaxial stack 212 is a SiGe layer (not shown).

[0157] like Figure 6 As shown, in operation S906, method 900 ( Figure 4 ) patterning the epitaxial stack 212 to form the semiconductor fin 200. In some embodiments, operation S906 includes forming a mask layer 217 on the epitaxial stack 212, such as Figure 5 As shown. The mask layer 217 includes a first mask layer 218 and a second mask layer 219. The first mask layer 218 may be a pad oxide layer formed of silicon oxide and may be formed by thermal oxidation. The second mask layer 219 may be formed of silicon nitride (SiN) and may be formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD); physical vapor deposition (PVD); atomic layer deposition (ALD); or other suitable processes. The mask layer 217 is patterned into a mask pattern using patterning operations including lithography and etching.

[0158] like Figure 6 As shown, operation S906 then patterns the epitaxial stack 212 through the defined openings in the patterned mask layer 217 in a process such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The stacked epitaxial layer 214 and nanosheets 220 are thereby patterned into the fin 200. Figure 6 The formation of one fin 200 is shown, but any suitable number of fins may be formed. Trenches are etched between adjacent fins 200 .

[0159] In various embodiments, each fin 200 includes an upper portion having staggered epitaxial layers 214 and nanosheets 220, and a lower portion of a mesa portion 210 formed by the substrate 100 subjected to etching. Each fin 200 protrudes upward from the substrate 100 along the direction Z and extends longitudinally in the direction Y. The sidewalls of each fin 200 can be straight or inclined (not shown). Other fins are spaced apart along the direction X. The fins 200 can have the same width or different widths.

[0160] like Figure 7 As shown, in operation S908, method 900 ( Figure 4)Isolation material 390 is deposited above and around the fins 200 of the semiconductor. Specifically, the deposition process fills the trenches between adjacent fins 200, covers the sidewalls of the fins 200 and the mask layer 217. Isolation material 390 may include one or more dielectric materials. Dielectric materials suitable for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-K dielectric materials and / or other suitable dielectric materials. Isolation material 390 may be deposited by any suitable technique, including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD and / or spin coating techniques.

[0161] like Figure 7 As shown, method 900 includes planarizing isolation material 390 to have a planarized surface 391 by using, for example, chemical mechanical planarization (CMP), and a top surface of mask layer 217 is exposed.

[0162] like Figure 8 As shown, in operation S910, method 900 ( Figure 4 ) recesses the isolation material 390 to form a shallow trench isolation (STI) feature 300. In the illustrated embodiment, the shallow trench isolation feature 300 is formed on the substrate 100. As shown, the shallow trench isolation feature 300 has an uppermost surface 310. In some embodiments, the uppermost surface 310 has a sawtooth profile, as shown. In some embodiments, the uppermost surface 310 has a wave shape, as shown. The recessed surface 310 extends between and contacts the sidewalls 229 of adjacent fins 200. In some embodiments, the recessed surface 310 contacts the mesa portion 210 of each fin 200 at a position below the uppermost surface 211 of the mesa portion 210.

[0163] like Figure 8 As shown, the recessed surface 310 contacts the sidewall 229 of each fin 200 at an angle A2. In some embodiments, the angle A2 is 120 to 160 degrees. For example, the angle A2 can be at least 120 degrees, at least 125 degrees, at least 130 degrees, at least 135 degrees, at least 140 degrees, at least 145 degrees, at least 150 degrees, or at least 155 degrees. In addition, the angle A2 can be at most 125 degrees, at most 130 degrees, at most 135 degrees, at most 140 degrees, at most 145 degrees, at most 150 degrees, at most 155 degrees, or at most 160 degrees.

[0164] In some embodiments, the etching technique used to recess the isolation material to form the isolation feature 300 includes chemical etching and plasma etching. In some embodiments, the etching technique used to recess the isolation feature 300 includes one or more cycles of chemical etching and plasma etching. For example, the etching technique may include one to five cycles of chemical etching and plasma etching. In one embodiment, the etching technique includes three cycles of chemical etching and plasma etching.

[0165] In some embodiments, the etching technique for recessing the isolation feature 300 uses an etching gas selected from the group consisting of NH 3 , NF 3 , HBr, and H 2 .

[0166] In some embodiments, the etching technique for recessed isolation feature 300 uses a passivating gas selected from N 2 and O 2 to achieve selectivity.

[0167] In some embodiments, the etching technique for recessing the isolation feature 300 uses a diluent gas selected from He, Ar, and N 2 .

[0168] In some embodiments, the etching technique for recessing the isolation feature 300 is performed at a power of 10 watts to 4000 watts.

[0169] In some embodiments, the etching technique for recessing the isolation feature 300 is performed at a pressure of 10 mTorr to 3 Torr.

[0170] In some embodiments, the etching technique for recessing the isolation feature 300 is performed with a gas flow rate of 20 standard cubic centimeters per minute (sccm) to 3000 sccm.

[0171] In one embodiment, the etching technique used to recess the isolation material to form the isolation feature 300 selectively removes the isolation material 390 without etching the fin 200. Figure 7 300) can be removed before, during, and / or after recessing the isolation feature 300. In some embodiments, the mask layer 217 is removed by performing a CMP process before the isolation feature 300 is recessed. In some embodiments, the mask layer 217 is removed by an etchant used to recess the isolation feature 300.

[0172] Fig. 9 A focused view of an isolation feature 300 located between adjacent fins 200 is provided. Specifically, Fig. 9 The jagged profile or wave shape of the surface 310 of the isolated feature 300 is shown.

[0173] As shown, the surface 310 includes an end crest 316 or peak adjacent to the sidewall 229 of the fin 200, and an end crest 317 or peak adjacent to the sidewall 229 of the fin 200. In addition, the surface 310 includes an intermediate crest 314 or peak located between the end crest 316 and the end crest 317; and includes an intermediate crest 315 or peak located between the intermediate crest 314 and the end crest 317. The distance between the end crest 316 and the intermediate crest 314 may be equal to the distance between the end crest 317 and the intermediate crest 315.

[0174] As shown, surface 310 includes a terminal trough 312 or lowest point located between terminal peak 316 and intermediate peak 314. In addition, surface 310 includes a terminal trough 313 located between terminal peak 317 and intermediate peak 315. Likewise, surface 310 includes an intermediate trough 311 located between intermediate peak 314 and intermediate peak 315. The distance between intermediate trough 311 and terminal trough 312 may be equal to the distance between intermediate trough 311 and terminal trough 313.

[0175] As shown, each trough and peak is a vertical distance (in direction Z) from a horizontal plane P1 defined by an uppermost surface 211 of a mesa portion 210 of a fin 200 or an adjacent fin 200 .

[0176] The intermediate valley 311 is located at a vertical distance D1 from the plane P1. In some embodiments, the vertical distance D1 is 15 nanometers to 35 nanometers. For example, the vertical distance D1 can be at least 15 nanometers, at least 20 nanometers, at least 25 nanometers, or at least 30 nanometers. In addition, the vertical distance D1 can be at most 20 nanometers, at most 25 nanometers, at most 30 nanometers, or at most 35 nanometers.

[0177] In embodiments where the fins 200 are formed with a larger pitch, the vertical distance D1 is 25 nanometers to 45 nanometers. For example, the vertical distance D1 may be at least 25 nanometers, at least 30 nanometers, at least 35 nanometers, or at least 40 nanometers. In addition, the vertical distance D1 may be at most 30 nanometers, at most 35 nanometers, at most 40 nanometers, or at most 45 nanometers.

[0178] The end valley 312 is located at a vertical distance D2 from the plane P1. The end valley 313 is located at a vertical distance D3 from the plane P1. The vertical distance D2 and the vertical distance D3 may be the same or different. In some embodiments, the vertical distance D2 or the vertical distance D3 is 10 nanometers to 20 nanometers. For example, the vertical distance D2 or the vertical distance D3 may be at least 10 nanometers, at least 12.5 nanometers, at least 15 nanometers, or at least 17.5 nanometers. In addition, the vertical distance D2 or the vertical distance D3 may be at most 20 nanometers, at most 17.5 nanometers, at most 15 nanometers, or at most 12.5 nanometers.

[0179] In an embodiment where the fin 200 is formed with a larger pitch, the vertical distance D2 or the vertical distance D3 is 20 nanometers to 30 nanometers. For example, the vertical distance D2 or the vertical distance D3 can be at least 20 nanometers, at least 22.5 nanometers, at least 25 nanometers, or at least 27.5 nanometers. In addition, the vertical distance D2 or the vertical distance D3 can be at most 30 nanometers, at most 27.5 nanometers, at most 25 nanometers, or at most 22.5 nanometers.

[0180] Intermediate peak 314 is located at a vertical distance D4 from plane P1. Intermediate peak 315 is located at a vertical distance D5 from plane P1. Vertical distance D4 and vertical distance D5 may be the same or different. In some embodiments, vertical distance D4 or vertical distance D5 is 5 nanometers to 15 nanometers. For example, vertical distance D4 or vertical distance D5 may be at least 5 nanometers, at least 7.5 nanometers, at least 10 nanometers, or at least 12.5 nanometers. In addition, vertical distance D4 or vertical distance D5 may be at most 15 nanometers, at most 12.5 nanometers, at most 10 nanometers, or at most 7.5 nanometers.

[0181] In an embodiment where the fin 200 is formed with a larger pitch, the vertical distance D4 or the vertical distance D5 is 15 nanometers to 25 nanometers. For example, the vertical distance D4 or the vertical distance D5 can be at least 15 nanometers, at least 17.5 nanometers, at least 20 nanometers, or at least 22.5 nanometers. In addition, the vertical distance D4 or the vertical distance D5 can be at most 25 nanometers, at most 22.5 nanometers, at most 20 nanometers, or at most 17.5 nanometers.

[0182] The end peak 316 is located at a vertical distance D6 from the plane P1. The end peak 317 is located at a vertical distance D7 from the plane P1. The vertical distance D6 and the vertical distance D7 may be the same or different. In some embodiments, the vertical distance D6 or the vertical distance D7 is 2 nanometers to 12 nanometers. For example, the vertical distance D6 or the vertical distance D7 can be at least 2 nanometers, at least 5 nanometers, at least 7.5 nanometers, or at least 10 nanometers. In addition, the vertical distance D6 or the vertical distance D7 can be at most 12 nanometers, at most 10 nanometers, at most 7.5 nanometers, or at most 5 nanometers.

[0183] In an embodiment where the fins 200 are formed with a larger pitch, the vertical distance D6 or the vertical distance D7 is 5 nanometers to 20 nanometers. For example, the vertical distance D6 or the vertical distance D7 can be at least 5 nanometers, at least 7.5 nanometers, at least 10 nanometers, at least 12.5 nanometers, at least 15 nanometers, or at least 17.5 nanometers. In addition, the vertical distance D6 or the vertical distance D7 can be at most 20 nanometers, at most 17.5 nanometers, at most 15 nanometers, at most 12.5 nanometers, at most 10 nanometers, or at most 7.5 nanometers.

[0184] exist Fig. 9 314, a positive slope from the terminal trough 312 to the intermediate peak 314, a negative slope from the intermediate peak 314 to the intermediate trough 311, a positive slope from the intermediate trough 311 to the intermediate peak 315, a negative slope from the intermediate peak 315 to the terminal trough 313, and a positive slope from the terminal trough 313 to the terminal peak 317.

[0185] like Fig.10 As shown, in operation S912, method 900 ( Figure 4 ) optionally includes forming a layer 350 on the isolation feature 300. In some embodiments, the layer 350 is an etch stop layer. For example, the layer 350 can be a dielectric material, such as silicon oxide. In some embodiments, the layer 350 is formed by conformal deposition to a thickness of 2 nanometers to 3 nanometers. The layer 350 is conformal and thin, and retains the jagged profile or waveform of the underlying isolation feature 300, such as Fig.10 shown.

[0186] like Figures 11 to 13 As shown, in operation S914, method 900 ( Figure 4 ) A sacrificial (dummy) gate material is deposited on the fin 200 and the isolation feature 300.

[0187] The deposition of the sacrificial gate material may include first conformally depositing a sacrificial gate dielectric layer 410' over the fin 200 and the isolation feature 300. Then, a sacrificial gate electrode layer 420' is blanket deposited over the sacrificial gate dielectric layer 410'. It is noted that the sacrificial gate dielectric layer 410' may be deposited without depositing layer 350. Thus, in embodiments using a sacrificial gate dielectric layer 410', layer 350 need not be deposited. The sacrificial gate dielectric layer 410' is conformal and thin, and preserves the jagged profile or waveform of the underlying isolation feature 300.

[0188] The sacrificial gate dielectric layer 410' may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer 420' may be 100 nanometers to 200 nanometers. The sacrificial gate electrode layer 420' includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer 410' may be 1 nanometer to 5 nanometers, such as 2 nanometers to 3 nanometers. In some embodiments, the sacrificial gate electrode layer 420' may be subjected to a planarization operation. The sacrificial gate dielectric layer 410' and the sacrificial gate electrode layer 420' are deposited using CVD, including LPCVD and PECVD, PVD, ALD or other suitable processes.

[0189] like Figure 14 to Figure 15As shown, in operation S916, method 900 ( Figure 4 ) to form a sacrificial (dummy) gate structure 400'. Specifically, operation S916 includes etching a portion of the sacrificial gate electrode layer 420' and the sacrificial gate dielectric layer 410' to form a sacrificial gate structure 400'.

[0190] The sacrificial gate structure 400' is formed on a portion of the fin 200 where a channel region is to be formed. The sacrificial gate structure 400' may extend onto many adjacent fins (not shown). The sacrificial gate structure 400' is directly located on the channel region of the GAA device to be formed and defines the channel region. Each sacrificial gate structure 400' includes a sacrificial gate dielectric layer 410' and a sacrificial gate electrode layer 420' on the sacrificial gate dielectric layer 410'. As shown, the sacrificial gate structures 400' extend longitudinally in direction X and are spaced apart in direction Y.

[0191] In order to form the (virtual) sacrificial gate structure 400', a mask layer (not shown) may be formed on the sacrificial gate electrode layer 420'. The mask layer may include multiple layers, including a silicon oxide layer and a silicon nitride layer. Subsequently, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer 420' and the sacrificial gate dielectric layer 410' are patterned into a sacrificial gate structure 400' including the sacrificial gate dielectric layer 410' and the sacrificial gate electrode layer 420'.

[0192] Etching the sacrificial gate layer to form the (dummy) sacrificial gate structure 400' may include a plasma etching process, wherein the sacrificial gate dielectric layer 410' acts as an etch stop layer to etch the sacrificial gate electrode layer 420', and then etching the sacrificial gate dielectric layer 410' using a wet cleaning process. After the wet cleaning process, a native oxide layer 299 may be formed on the fin 200.

[0193] like Fig.14 As shown, the etching process used to form the sacrificial gate structure 400' forms a sacrificial gate structure 400' having substantially flat sidewalls 430', and the sidewalls 430' define a plane P2. In some embodiments, plane P2 is a vertical plane. As shown, residues 499 of the sacrificial gate dielectric layer 410' and the sacrificial gate electrode layer 420' may remain at the intersection of the sidewalls 229 of the fin and the sidewalls 430' of the sacrificial gate structure 400'. Embodiments herein provide for reducing or eliminating the residues 499. It should be noted that Fig.14 The size of the residue 499 may be exaggerated to make the illustration clearer.

[0194] For example, in a plasma etching process, plasma ions are directed to the sacrificial gate electrode layer 420' and toward the isolation feature 300. When the portion of the sacrificial gate electrode layer 420' covering the area of ​​the isolation feature 300 is removed, the plasma ions strike the optional layer 350 or the sacrificial gate dielectric layer 410' and are reflected. Due to the jagged profile or waveform of the layer 350 or the sacrificial gate dielectric layer 410', the plasma ions are reflected laterally and / or longitudinally in the direction X and / or direction Y. Specifically, the plasma ions may be reflected to the sidewalls 229 of the fin 200 and / or the sidewalls 430' of the sacrificial gate structure 400' being formed. Therefore, the ion bombardment at the junction of the sidewalls 229 of the fin and the sidewalls 430' of the sacrificial gate structure 400' is increased. The plasma bombardment increases the physical etching of the material.

[0195] Fig.16 Sacrificial gate residues 499 are shown adjacent to the fin 200 in the direction X. As shown, the sacrificial gate residues 499 extend from the sidewall 229 of the fin 200 along the direction X. Each sacrificial gate residue 499 has a maximum lateral width W1 in the direction X.

[0196] In some embodiments, the maximum lateral width W1 is 4 nanometers. For example, the maximum lateral width W1 can be 1 nanometer to 4 nanometers. In some embodiments, the maximum lateral width W1 is at least 1 nanometer, at least 1.5 nanometers, at least 2 nanometers, or at least 2.5 nanometers. In some embodiments, the maximum lateral width W1 is at most 1.5 nanometers, at most 2 nanometers, at most 2.5 nanometers, at most 3 nanometers, at most 3.5 nanometers, or at most 4 nanometers.

[0197] like Fig.16 As further shown in FIG. 1 , the sacrificial gate residue 499 extends from the isolation feature 300 along the sidewall 229 of the fin 200 to a vertical height H1 above the topmost surface 211 of the mesa portion 210 in the direction Z. The maximum vertical height H1 of each sacrificial gate residue 499 is 0 nanometers to 4 nanometers. For example, the maximum vertical height H1 is at least 0 nanometers, at least 0.5 nanometers, at least 1 nanometer, at least 1.5 nanometers, at least 2 nanometers, at least 2.5 nanometers, at least 3 nanometers, or at least 3.5 nanometers. In some embodiments, the maximum vertical height H1 is at most 0 nanometers, at most 0.5 nanometers, at most 1 nanometer, at most 1.5 nanometers, at most 2 nanometers, at most 2.5 nanometers, at most 3 nanometers, at most 3.5 nanometers, or at most 4 nanometers.

[0198] Fig.17Sacrificial gate residues 499 are shown adjacent to sacrificial gate structure 400' in direction Y. As shown, sacrificial gate residues 499 extend from sidewalls 430' of sacrificial gate structure 400' along direction Y. Each sacrificial gate residue 499 has a maximum longitudinal width W2 in direction Y.

[0199] In some embodiments, the maximum longitudinal width W2 is 4 nanometers. For example, the maximum longitudinal width W2 can be 1 nanometer to 4 nanometers. In some embodiments, the maximum longitudinal width W2 is at least 1 nanometer, at least 1.5 nanometers, at least 2 nanometers, or at least 2.5 nanometers. In some embodiments, the maximum longitudinal width W2 is at most 1.5 nanometers, at most 2 nanometers, at most 2.5 nanometers, at most 3 nanometers, at most 3.5 nanometers, or at most 4 nanometers.

[0200] like Fig.17 As further shown in FIG. 1 , the sacrificial gate residue 499 extends from the isolation feature 300 along the sidewall 229 of the fin 200 to a height H2 above the isolation feature 300 in the direction Z. The maximum vertical height H2 of each sacrificial gate residue 499 is 1 nanometer to 20 nanometers. For example, the maximum vertical height H2 is at least 1 nanometer, at least 2 nanometers, at least 3 nanometers, at least 4 nanometers, at least 5 nanometers, at least 6 nanometers, at least 7 nanometers, at least 8 nanometers, at least 9 nanometers, at least 10 nanometers, at least 12.5 nanometers, at least 15 nanometers, or at least 17.5 nanometers. For example, the maximum vertical height H2 is at most 5 nanometers, at most 6 nanometers, at most 7 nanometers, at most 8 nanometers, at most 9 nanometers, at most 10 nanometers, at most 12.5 nanometers, at most 15 nanometers, at most 17.5 nanometers, or at most 20 nanometers.

[0201] like Fig.15 As clearly shown in FIG. 4 , after the sacrificial gate structure 400' is formed, each fin 200 is partially exposed on and between opposite sides of the sacrificial gate structure 400', thereby defining a source / drain (S / D) region. As used herein, "source / drain region" may refer individually or collectively to a source region or a drain region, depending on the context.

[0202] like Fig.18 As shown, in operation S918, method 900 ( Figure 4 ) Spacers 700 are formed on the sidewalls of the sacrificial gate structure 400 ′ and the sidewalls of the fin 200 by depositing a spacer material and then etching.

[0203] Although not in Figures 14 to 17As shown in FIG. 1 , a mask layer 225 may be formed on a sacrificial gate electrode layer 420' before patterning to form a sacrificial gate structure 400'. The mask layer 225 may include a mask layer 226 (e.g., silicon oxide) and a mask layer 227 (e.g., silicon nitride). Subsequently, a patterning operation is performed on the mask layer 225 to pattern the sacrificial gate electrode layer and the sacrificial gate dielectric layer into a sacrificial gate structure 400' including a sacrificial gate dielectric layer 410' and a sacrificial gate electrode layer 420'. Fig.18 As shown, spacers 700 may be formed on the mask layer 225 .

[0204] The spacers 700 may include spacer materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each spacer 700 includes multiple layers, such as a liner material layer 710 and a dielectric material layer 720 as a main spacer on the sidewalls of the liner material layer 710.

[0205] As an example, the spacer 700 may be formed by depositing a spacer material including a liner material layer 710 and a dielectric material layer 720 on the sacrificial gate structure 400 ′ using a subatmospheric CVD (SACVD) process, a flow CVD process, an ALD process, a PVD process or other suitable processes.

[0206] like Fig.19 and Fig. 20 As shown, the deposition operation of the liner material layer 710 and the dielectric material layer 720 is then followed by an etch-back (e.g., anisotropic) process in operation S920 to expose and remove the portion 200a (e.g., source / drain region) of the fin 200 adjacent to the sacrificial gate structure 400' and not covered by the sacrificial gate structure 400'. Specifically, the method 900 ( Figure 4 ) The portion of the fin 200 not covered by the sacrificial gate structure 400' is recessed to form a cavity, groove or gap 234 in the source / drain region. It should be noted that Fig.19 Only the sacrificial gate structure 400' and the adjacent portion of the fin 200 are shown, so that Fig.18 The etching of the source / drain regions between the sacrificial gate structures 400 ′ can be more clearly shown. Fig. 20 yes Fig.19 The cross section along line 6-6 is shown in Figure 1, but it is different from Fig.18 Same, Fig. 20 Two sacrificial gate structures 400 ′ are shown adjacent to the fin 200 .

[0207] The liner material layer 710 and the dielectric material layer 720 may be retained on the sidewalls of the sacrificial gate structure 400' and serve as the spacer 700 of the sidewalls of the gate, and retained on the sidewalls of the fin 200 and serve as the spacer 700 of the sidewalls of the fin. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The thickness of the spacer 700 may range from 5 nanometers to 20 nanometers.

[0208] like Fig. 20 As clearly shown in FIG. 1 , the stacked epitaxial layer 214 and the nanosheet 220 and the upper portion of the substrate 100 forming the fin 200 are etched down in the source / drain region. As a result, a bottom gap surface 233 is formed in the fin 200. In some embodiments, operation S920 forms the gap 234 by a suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. As a result of the etching process, the fin segments 235 at the upper portion of the fin 200 are defined and separated from each other by the gap 234.

[0209] like Fig.21 and Fig. 22 As shown, in operation S922, method 900 ( Figure 4 ) etches the lateral end of the epitaxial layer 214 along direction Y to have a recessed surface 336, thereby forming a cavity 236.

[0210] It should be noted that Fig.21 and Fig.19 Similarly, only one sacrificial gate structure 400 ′ and the adjacent portion of the fin 200 are shown, thus illustrating the etching of the source / drain regions between the sacrificial gate structures 400 ′.

[0211] Fig. 22 yes Fig.21 Sectional view of the structure along line 7-7, but with Fig.18 and Fig. 20 Likewise, a sacrificial gate structure 400 ′ and an adjacent fin 200 are shown.

[0212] The epitaxial layer 214 may be selectively etched by using a wet etchant, such as, but not limited to, ammonia (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), potassium hydroxide (KOH), HF, O3, H2O2, or HCl solution. Alternatively, operation S922 may first selectively oxidize the lateral ends of the epitaxial layer 214 exposed in the gap 234 to increase the etching selectivity between the epitaxial layer 214 and the nanosheet 220. In some examples, the oxidation process may be performed by exposing the GAA device 1000 to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0213] like Fig.23 As shown, method 900 can continue to operation S924 to form an inner spacer 800 laterally adjacent to epitaxial layer 214. For example, one or more inner spacer material layers can be deposited on the gap sidewalls in the gap, including the lateral ends of epitaxial layer 214. The inner spacer material can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or other suitable dielectric materials. In some embodiments, the inner spacer material layer is deposited as a conformal layer. The inner spacer material layer can be formed by ALD or any other suitable method. In addition, operation S924 can include trimming the inner spacer material to form the inner spacer 800. Removing a portion of the inner spacer can be performed by an etching process, such as an anisotropic etching process, such as a dry etching process.

[0214] like Fig.24 As shown, method 900 can continue to operation S926, forming the epitaxial region 550 at the bottom in the gap 234. For example, semiconductor material can grow on the bottom surface of the gap. For example, undoped silicon can be grown on the bottom surface of the gap as an epitaxial semiconductor material. In addition, operation S926 can include a part of etching semiconductor material. Similarly, a dielectric layer 560 at the bottom can be formed on the epitaxial region 550 at the bottom, as shown in the figure. For example, dielectric material can be deposited and trimmed to form the dielectric layer 560 at the bottom. As shown, the dielectric layer 560 at the bottom can contact and extend between the bottommost relative inner spacers 800.

[0215] In addition, if Fig.24 As shown, method 900( Figure 4) can continue to operation S928, growing epitaxial material in the groove to form the source / drain region 500. It should be noted that the source / drain region 500 can be formed by continuously forming layers. Similarly, the layer forming the source / drain region 500 can be selected for use in NFET or PFET. The epitaxial source / drain region 500 can be formed by epitaxial growth using CVD, ALD or molecular beam epitaxy (MBE). The epitaxial source / drain region 500 can include SiGe for PFET and silicon for NFET.

[0216] like Fig.24 As further shown in the method 900 ( Figure 4 ) may continue to operation S930 to form an interlayer dielectric structure 600 on the source / drain regions 500 and between the spacers 700. In some embodiments, the interlayer dielectric structure 600 includes a layer 610 and a layer 620.

[0217] like Fig.25 As shown, method 900( Figure 4 ) can continue to operation S932, including performing a replacement metal gate process. Specifically, a sacrificial gate structure 400' including a sacrificial gate electrode layer 420' and a sacrificial gate dielectric layer 410' and a sacrificial epitaxial layer 214 are removed. In addition, a metal gate structure 400 is formed in a replacement metal gate process. The metal gate structure 400 includes a gate dielectric 410 (e.g., a gate dielectric with a high K value) and a metal electrode 420. After removing the sacrificial epitaxial layer 214 and forming the metal gate structure 400, the remaining epitaxial layer or nanosheet 220 may be referred to as a semiconductor nanosheet 220. As shown in the figure, the gate dielectric 410 may be formed around the nanosheet 220, and the metal electrode 420 may be deposited on the gate dielectric 410 to form a metal gate structure 400. As shown in the figure, the metal gate structure 400 is adjacent to the inner spacer 800.

[0218] In some embodiments, the replacement metal gate process may include a wire-release process to form vertically spaced nanosheets. The steps of the wire-release process may also be referred to as steps of a sheet release process, steps of a sheet formation process, steps of a nanosheet formation process, or steps of a wire formation process. In one embodiment, the epitaxial layer 214 of the first layer may be removed using a wet etching process to selectively remove the material of the first layer (e.g., silicon germanium (SiGe)) without significantly removing the material of the nanosheet 220 of the second layer (e.g., silicon (Si)). However, any suitable removal process may also be used.

[0219] For example, in one embodiment, an etchant such as high temperature HCl may be used to selectively remove the material of the first epitaxial layer 214 (e.g., SiGe) without substantially removing the material of the second nanosheet 220 (e.g., Si). In addition, the wet etching process may be performed at a temperature of 400° C. to 600° C., such as about 560° C., and may be performed for a time of 100 seconds to 600 seconds, such as about 300 seconds. However, any suitable etchant, process parameters, and time may be used.

[0220] According to some embodiments, the gate dielectric 410 includes a high-K material (e.g., a material with a K value greater than or equal to 9), such as Ta2O5, Al2O3, Hf oxide, Ta oxide, Ti oxide, Zr oxide, Al oxide, La oxide (e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO), combinations thereof, or the like, and is deposited by atomic layer deposition, chemical vapor deposition, or the like. In some embodiments, the gate dielectric 410 includes a nitrogen-doped oxide dielectric and is formed prior to forming a high-K (e.g., K value>13) dielectric material. The gate dielectric 410 can be deposited to a thickness of 1 nm to 3 nm, although any suitable material and thickness can be used.

[0221] According to some embodiments, metal electrode 420 is formed using multiple layers, each layer being sequentially deposited adjacent to each other using a highly conformal deposition process such as atomic layer deposition, although any suitable deposition process may be used. According to some embodiments, a capping layer, a barrier layer, an n-type metal work function layer, a p-type metal work function layer, and a fill material may be provided.

[0222] The capping layer may be formed adjacent to the gate dielectric 410 and may be formed of a metallic material such as TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations thereof, or the like. The metallic material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.

[0223] The barrier layer may be formed adjacent to the capping layer and may be formed of a different material than the capping layer. For example, the barrier layer may be formed of a metallic material such as one or more layers of TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations thereof, or the like. The barrier layer may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.

[0224] The n-type metal work function layer may be formed near the barrier layer. In one embodiment, the n-type metal work function layer is a suitable n-type work function material such as W, Cu, AlCu, TiAlC, TiAlN, TiAl, Pt, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaC, TaCN, TaSiN, Mn, Zr, or a combination thereof. For example, the n-type metal work function layer may be deposited using an atomic layer deposition (ALD) process, a CVD process, or the like. However, any suitable material and process may be used to form the n-type metal work function layer.

[0225] The p-type metal work function layer may be formed adjacent to the n-type metal work function layer. In one embodiment, the p-type metal work function layer may be formed of a metal material, such as W, Al, Cu, TiN, Ti, TiAlN, TiAl, Pt, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, AlCu, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. In addition, the p-type metal work function layer may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, etc., although any suitable deposition process may be used.

[0226] After forming the p-type metal work function layer, a filling material is deposited to fill the rest of the opening. In an embodiment, the filling material may be a material such as Al, Cu, AlCu, W, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or the like, or a combination thereof, and may be formed using a deposition process such as electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination thereof, or the like. However, any suitable material may be used.

[0227] After the opening created by removing the virtual sacrificial gate structure 400' is filled, the material of the metal electrode 420 and the gate dielectric 410 can be planarized to remove any material outside the opening created by removing the virtual sacrificial gate structure 400'. In a particular embodiment, the removal can be performed using a planarization process such as chemical mechanical polishing, although any suitable planarization and removal process can be used. According to some embodiments, the metal gate structure 400 can be formed in the direction Z and have a vertical height, and the height is from 70 nanometers to 85 nanometers. However, it can have any suitable height.

[0228] Method 900( Figure 4 ) may continue to operation S934, including performing further processes to complete the semiconductor device, its interconnect structure, and other types of back-end-of-line (BEOL) processes.

[0229] In one embodiment, a method for forming a semiconductor device is provided. The method includes the following operations. A plurality of structures are formed on a substrate. A layer is formed between the structures. A first etching process is performed to recess the layer to a surface having a sawtooth profile. One or more thin films are optionally formed on the surface, wherein the thin films retain the sawtooth profile. A material is deposited on the substrate. A second etching process is performed to etch a portion of the material and form the material having a sidewall, wherein the second etching process exposes the sawtooth profile, and wherein a plurality of ions are reflected by the sawtooth profile in the second etching process.

[0230] In some embodiments of the method, the structures include a first structure having a first sidewall and a second structure having a second sidewall. The portion of the material removed by the second etching process extends from the first sidewall to the second sidewall. In the second etching process, ions are reflected by the sawtooth profile to remove material on the first sidewall and the second sidewall.

[0231] In some embodiments of the method, the structures include a first structure having a first sidewall. After the second etching process, a residue of material remains on the first sidewall above the sawtooth profile. The residue has a thickness in a lateral direction perpendicular to the first sidewall. The thickness is less than 4 nanometers.

[0232] In some embodiments of the method, the structures include a first structure having a first sidewall. The first structure includes a mesa portion composed of a first semiconductor material, a second semiconductor layer on the mesa portion, and a first semiconductor layer on the second semiconductor layer. After the second etching process, residues of the material remain on the first sidewall. The residues do not contact the first semiconductor layer.

[0233] In some embodiments of the method, the second etching process includes selectively masking the material to define masked portions of the material and unmasked portions of the material, wherein the second etching process removes the unmasked portions of the material.

[0234] In some embodiments of the method, the first etching process includes multiple cycles of chemical etching and plasma etching.

[0235] In some embodiments of the method, the first etching process uses an etching gas selected from NH3, NF3, HBr and H2; a passivation gas selected from N2 and O2; and a dilution gas selected from He, Ar and N2.

[0236] In some embodiments of the method, the first etching process is performed with a power of 10 watts to 4000 watts, a pressure of 10 mTorr to 3 Torr, and a gas flow rate of 20 sccm to 3000 sccm.

[0237] In another embodiment, a method of forming a semiconductor device includes the following operations: forming a first fin structure and a second fin structure; forming an isolation region between the first fin structure and the second fin structure; recessing the isolation region to provide the isolation region with a corrugated recessed surface; depositing a sacrificial gate material on the isolation region; and etching a portion of the sacrificial gate material to form a sacrificial gate.

[0238] In some embodiments of the method, the waveform includes a first end peak adjacent to the first fin structure, a second end peak adjacent to the second fin structure, a first intermediate peak between the first end peak and the second end peak, and a second intermediate peak between the first intermediate peak and the second end peak.

[0239] In some embodiments of the method, the waveform further includes a first terminal trough between the first terminal peak and the first intermediate peak, a second terminal trough between the second terminal peak and the second intermediate peak, and an intermediate trough between the first intermediate peak and the second intermediate peak.

[0240] In some embodiments of the method, each of the first fin structure and the second fin structure includes a mesa portion of a first semiconductor material and a second layer of a second semiconductor material, wherein the mesa portion has an uppermost surface, and a first end valley is located at a first vertical depth from the uppermost surface, a second end valley is located at a second vertical depth from the uppermost surface, an intermediate valley is located at an intermediate vertical depth from the uppermost surface, and a center vertical depth is greater than the first vertical depth and the second vertical depth.

[0241] In some embodiments of this method, the first terminal valley is between 10 nm and 20 nm, the second terminal valley is between 10 nm and 20 nm, and the intermediate valley is between 15 nm and 35 nm.

[0242] In some embodiments of this method, the first terminal valley is 20 nm to 30 nm, the second terminal valley is 20 nm to 30 nm, and the intermediate valley is 25 nm to 45 nm.

[0243] In some embodiments of the method, the first fin structure has a sidewall, an angle is defined between the sidewall and the recessed surface, and the angle is 120 degrees to 160 degrees.

[0244] In some embodiments of this method, recessing the isolation region to provide an isolation region having a corrugated recessed surface includes performing an etching process, the etching process using an etching gas selected from NH3, NF3, HBr and H2; using a passivation gas selected from N2 and O2; and using a dilution gas selected from He, Ar and N2, and the etching process is performed with a power of 10 watts to 4000 watts, a pressure of 10mTorr to 3Torr, and a gas flow rate of 20sccm to 3000sccm.

[0245] In another embodiment, a semiconductor device is provided. The semiconductor device includes: a first dielectric region spaced from a second dielectric region in a longitudinal direction Y; a first source / drain region spaced from a second source / drain region in a lateral direction X, wherein the first source / drain region is located between the first dielectric region and the second dielectric region; a fin structure including a semiconductor nanosheet spaced from a mesa portion in a vertical direction Z, wherein the semiconductor nanosheet extends from the first source / drain region to the second source / drain region in the lateral direction X; a gate structure overlying the fin structure, wherein the gate structure includes a metal gate and a high-k gate dielectric, wherein the gate structure extends along the longitudinal direction Y, and wherein a bottommost portion of the gate structure is located between the mesa portion and the semiconductor nanosheet; a first inner spacer separating the first source / drain region from a bottommost portion of the gate structure in the lateral direction X; a first spacer structure separating the first dielectric region from the gate structure in the lateral direction X; and a second spacer structure separating the second dielectric region from the gate structure in the lateral direction X. A minimum first distance between the first spacer structure and the first inner spacer in the longitudinal direction Y is 0 nm to 2 nm, and a minimum second distance between the second spacer structure and the first inner spacer in the longitudinal direction Y is 0 nm to 2 nm.

[0246] In some embodiments of the semiconductor device, the minimum first distance is located at an interface, wherein the metal gate extends to an edge toward the interface, and wherein a lateral profile of the edge of the metal gate has an internal angle greater than 100 degrees.

[0247] In some embodiments of the semiconductor device, the minimum first distance is located at an interface, wherein the metal gate extends to an edge toward the interface, and wherein a lateral profile of the edge of the metal gate has an internal angle of 100 degrees to 120 degrees.

[0248] In some embodiments, the semiconductor device further includes a first shallow isolation region spaced apart from the second shallow isolation region in a longitudinal direction Y. The mesa portion of the fin structure is located between the first shallow isolation region and the second shallow isolation region. The mesa portion of the fin structure has a sidewall adjacent to the first shallow isolation region. The first shallow isolation region has an uppermost surface. An angle is defined between the sidewall and the uppermost surface. The angle is 120 degrees to 160 degrees.

[0249] The foregoing summarizes the features of some embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that: include: forming a plurality of structures on a substrate; forming a layer between the plurality of structures; performing a first etching process to recess the layer to a surface having a sawtooth profile; optionally forming one or more thin films on the surface, wherein the film or films retain the sawtooth profile; depositing a material on the substrate; as well as A second etching process is performed to etch a portion of the material and form the material having a sidewall, wherein the second etching process exposes the sawtooth profile, and wherein a plurality of ions are reflected by the sawtooth profile during the second etching process.

2. The method according to claim 1, characterized in that in: The plurality of structures include a first structure having a first sidewall and a second structure having a second sidewall; the portion of the material removed by the second etching process extends from the first sidewall to the second sidewall; as well as In the second etching process, the ions are reflected by the sawtooth profile to remove the material on the first sidewall and the second sidewall.

3. A method for forming a semiconductor device, characterized in that: include: forming a first fin structure and a second fin structure; forming an isolation region between the first fin structure and the second fin structure; Recessing the isolation region to provide the isolation region with a recessed surface having a waveform; depositing a sacrificial gate material on the isolation region; as well as A portion of the sacrificial gate material is etched to form a sacrificial gate.

4. The method according to claim 3, characterized in that The waveform includes: a first terminal crest adjacent to the first fin structure; a second terminal crest adjacent to the second fin structure; a first intermediate peak located between the first terminal peak and the second terminal peak; and A second intermediate peak is located between the first intermediate peak and the second terminal peak.

5. The method according to claim 4, characterized in that The waveform also includes: a first terminal trough located between the first terminal crest and the first intermediate crest; a second terminal trough located between the second terminal peak and the second intermediate peak; and An intermediate trough is located between the first intermediate peak and the second intermediate peak.

6. The method according to claim 5, characterized in that wherein each of the first fin structure and the second fin structure comprises a mesa portion of a first semiconductor material and a second layer of a second semiconductor material, wherein the mesa portion has an uppermost surface, and wherein: The first terminal trough is located at a first vertical depth from the uppermost surface; The second terminal trough is located at a second vertical depth from the uppermost surface; The intermediate valley is located at an intermediate vertical depth from the uppermost surface; and The central vertical depth is greater than the first vertical depth and the second vertical depth.

7. The method according to claim 3, characterized in that The step of recessing the isolation region to provide the recessed surface with the waveform includes performing an etching process, the etching process using an etching gas selected from NH3, NF3, HBr and H2; using a passivation gas selected from N2 and O2; and using a dilution gas selected from He, Ar and N2, and the etching process is performed with a power of 10 watts to 4000 watts; a pressure of 10mTorr to 3Torr; and a gas flow rate of 20sccm to 3000sccm.

8. A semiconductor device, characterized in that: include: a first dielectric region spaced apart from a second dielectric region in a longitudinal direction Y; a first source / drain region spaced apart from a second source / drain region in a lateral direction X, wherein the first source / drain region is located between the first dielectric region and the second dielectric region; a fin structure comprising a semiconductor nanosheet partially spaced from a mesa in a vertical direction Z, wherein the semiconductor nanosheet extends from the first source / drain region to the second source / drain region in the lateral direction X; a gate structure overlying the fin structure, wherein the gate structure comprises a metal gate and a high-k gate dielectric, wherein the gate structure extends along the longitudinal direction Y, and wherein a bottommost portion of the gate structure is located between the mesa portion and the semiconductor nanosheet; A first inner spacer separates the first source / drain region from the bottommost portion of the gate structure in the lateral direction X; A first spacer structure separates the first dielectric region from the gate structure in the lateral direction X; as well as A second spacer structure separates the second dielectric region from the gate structure in the lateral direction X; wherein a minimum first distance between the first spacer structure and the first inner spacer in the longitudinal direction Y is 0 nm to 2 nm; as well as A minimum second distance between the second spacer structure and the first inner spacer in the longitudinal direction Y is 0 nanometers to 2 nanometers.

9. The semiconductor device according to claim 8, wherein: The minimum first distance is located at an interface, the metal gate extends to an edge toward the interface, and a lateral profile of the edge of the metal gate has an internal angle of 100 degrees to 120 degrees.

10. The semiconductor device according to claim 8, wherein Also included is a first shallow isolation region spaced apart from a second shallow isolation region in the longitudinal direction Y; wherein: The mesa portion of the fin structure is located between the first shallow isolation region and the second shallow isolation region; The mesa portion of the fin structure has a sidewall adjacent to the first shallow isolation region; The first shallow isolation region has an uppermost surface; An angle is defined between the side wall and the uppermost surface; and The angle is 120 to 160 degrees.

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