Transistor and memory array

Abstract

The invention discloses a transistor and a memory array, the transistor comprises a source electrode, a drain electrode and at least one channel group, the at least one channel group is located between the source electrode and the drain electrode along the horizontal direction, the channel group comprises an inner core and a channel layer surrounding the inner core, the channel layer is in contact with the source electrode and the drain electrode, the inner core comprises a first insulating layer, and the first insulating layer is located between the source electrode and the drain electrode. The channel group further comprises a first dielectric layer surrounding the channel layer and a grid electrode, and the source electrode, the drain electrode and the grid electrode are isolated from one another; or the inner core comprises a grid electrode and a first dielectric layer surrounding the grid electrode, and the source electrode, the drain electrode and the grid electrode are mutually isolated. According to the scheme, the performance of the transistor can be guaranteed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a transistor and a storage array. Background Art

[0002] With the continuous development of chip technology, the difficulty of process miniaturization after FinFET is increasing, while the percentage of power-performance-area (PPA) improvement is gradually decreasing. The gate all around (GAA) structure has stronger gate control capability. Semiconductor devices based on the GAA structure can effectively reduce leakage current and increase saturation current, so the GAA structure has received widespread attention.

[0003] However, the design flexibility of current GAA devices is poor. In the current design of GAA devices, devices with different currents can usually be designed by adjusting the size of the channel, thereby optimizing the performance and power consumption of the device. In actual applications, the larger channel size may seriously affect the gate control capability of the GAA device.

[0004] Therefore, how to ensure the performance of semiconductor devices becomes an urgent problem to be solved. Summary of the invention

[0005] The present application provides a transistor and a memory array, which are helpful to ensure the performance of the transistor and the memory array.

[0006] In a first aspect, a transistor is provided, comprising: a source, a drain and at least one channel group, wherein at least one channel group is located between the source and the drain in a horizontal direction, the channel group comprises a core and a channel layer surrounding the core, and the channel layer is in contact with the source and the drain, wherein the core comprises a first insulating layer, and the channel group further comprises a first dielectric layer surrounding the channel layer and a gate, and the source, the drain and the gate are isolated from each other; or, the core comprises a gate and a first dielectric layer surrounding the gate, and the source, the drain and the gate are isolated from each other.

[0007] In an embodiment of the present application, the channel layer surrounds the core, and the channel layer has a surrounding gate structure, for example, the gate surrounds the channel layer, or the channel layer surrounds the gate, which is conducive to improving the flexibility of design while ensuring the gate control performance. Specifically, in the scheme of the embodiment of the present application, the channel layer surrounds the core, and the equivalent width of the channel layer can be adjusted by adjusting the size of the core, and devices with different currents can be designed, thereby optimizing the performance and power consumption of the device. At the same time, the thickness of the channel layer is not limited by the size of the core. For example, the channel layer can be set as a thin film, which is conducive to ensuring the control ability of the gate over the channel layer, that is, ensuring the gate control ability of the device.

[0008] Exemplarily, in a channel group, the structures from inside to outside are a first insulating layer, a channel layer, a first dielectric layer and a gate.

[0009] Exemplarily, in a channel group, the structures from inside to outside are a gate, a first dielectric layer and a channel layer.

[0010] In combination with the first aspect, in some implementations of the first aspect, the material of the channel layer is an oxide semiconductor material.

[0011] OS materials have a low thermal budget, and the use of OS channel materials is conducive to reducing the process difficulty of manufacturing transistors and reducing the manufacturing cost. At the same time, compared with the planar OS FET, in the solution of the embodiment of the present application, the use of a surrounding gate structure is conducive to improving the gate control capability, increasing the effective value of the current Ieff, and reducing the parasitic capacitance, thereby helping to improve the performance of the transistor.

[0012] In combination with the first aspect, in some implementations of the first aspect, when the core includes a first insulating layer, at least one channel group includes a plurality of channel groups distributed along a vertical direction.

[0013] This helps to increase the equivalent width of the channel, thereby increasing the device current and improving the performance of the device.

[0014] In combination with the first aspect, in some implementations of the first aspect, a second insulating layer is included between every two channel groups in the plurality of channel groups.

[0015] In combination with the first aspect, in certain implementations of the first aspect, a portion of the source electrode near the first insulating layer invades the first insulating layer, and a portion of the source electrode that invades the first insulating layer contacts the channel layer, or a portion of the drain electrode near the first insulating layer invades the first insulating layer, and a portion of the drain electrode that invades the first insulating layer contacts the channel layer.

[0016] In this way, the contact area between the channel layer and the source electrode can be increased, or the contact area between the channel layer and the drain electrode can be increased.

[0017] In combination with the first aspect, in certain implementations of the first aspect, when the core includes a gate and a first dielectric layer surrounding the gate, at least one channel group includes multiple channel groups distributed in a vertical direction, and a third insulating layer is included between every two channel groups in the multiple channel groups.

[0018] In combination with the first aspect, in some implementations of the first aspect, the channel layer is in direct contact with the source, or the channel layer is in direct contact with the drain.

[0019] In combination with the first aspect, in some implementations of the first aspect, the transistor further includes a filling layer, the channel layer is in contact with the source through the filling layer, or the channel layer is in contact with the drain through the filling layer, and the material of the filling layer is an oxide semiconductor material.

[0020] In the solution of the embodiment of the present application, the channel layer contacts the source and / or drain through the filling layer, which is equivalent to increasing the contact area between the channel layer and the source and / or drain, which is conducive to reducing the contact resistance. At the same time, this structure is conducive to preventing impurities in the source and / or drain from diffusing into the channel, thereby helping to improve the stability of the device.

[0021] In a second aspect, a memory array is provided, comprising: a substrate and one or more layers of memory cells arranged on the substrate, the multi-layer memory cells are stacked in a direction perpendicular to the surface of the substrate, each memory cell in the one or more layers of memory cells comprises a transistor, the transistor comprises: a source, a drain and at least one channel group, at least one channel group is located between the source and the drain in a direction parallel to the surface of the substrate, the channel group comprises a core and a channel layer surrounding the core, the channel layer is in contact with the source and the drain, wherein the core comprises a first insulating layer, and the channel group further comprises a first dielectric layer surrounding the channel layer and a gate, and the source, the drain and the gate are isolated from each other; or, the core comprises a gate and a first dielectric layer surrounding the gate, and the source, the drain and the gate are isolated from each other.

[0022] In the solution of the embodiment of the present application, the transistor is a gate transistor of the storage array, and the channel layer has a surrounding gate structure, for example, the gate surrounds the channel layer, or the channel layer surrounds the gate. This structure enables the transistor to have a higher read and write current, which is beneficial to optimizing the read and write speed and power consumption performance of the storage array. At the same time, the channel layer surrounds the core, and the channel layer has a surrounding gate structure, which is beneficial to improve the flexibility of the design while ensuring the gate control performance.

[0023] In combination with the second aspect, in some implementations of the second aspect, the material of the channel layer is an oxide semiconductor material.

[0024] OS materials have a low thermal budget, and using OS channel materials is conducive to reducing the process difficulty of preparing multi-layer storage cells and reducing the preparation cost. At the same time, OS FETs have extremely low leakage current, which is conducive to ensuring the retention time of state information in the storage array.

[0025] In combination with the second aspect, in certain implementations of the second aspect, when the core includes a first insulating layer, the memory array further includes a plurality of word lines extending in a direction perpendicular to the substrate surface, and transistors in memory cells in the multi-layer memory cells that are on the same straight line in a direction perpendicular to the substrate surface are connected to the same word line among the plurality of word lines.

[0026] The use of vertical word lines matches the characteristic that the gates of transistors are connected in a vertical direction, which is conducive to achieving a reasonable layout of the storage array.

[0027] In combination with the second aspect, in certain implementations of the second aspect, each layer of memory cells of one or more layers of memory cells is arranged along a first direction and a second direction, the first direction is parallel to the surface of the substrate, the second direction is parallel to the surface of the substrate, and the first direction is perpendicular to the second direction. When the core includes a first insulating layer, the memory array also includes multiple word lines extending along the first direction, transistors in the memory cells that are on the same straight line in the first direction are connected to the same word line among the multiple word lines, and a second insulating layer is included between each two channel groups in the channel groups of the transistors of the memory cells that are on the same straight line in a direction perpendicular to the surface of the substrate.

[0028] In combination with the second aspect, in some implementations of the second aspect, each storage unit further includes a capacitor, the capacitor is connected to the first end of the transistor, the storage array further includes a plurality of first signal lines, the second end of the transistor in each storage unit is connected to one of the plurality of first signal lines, the first end is a source, the second end is a drain, or the first end is a drain, the second end is a source, a side portion of the second end of the transistor close to the second insulating layer intrudes into the second insulating layer, and a portion of the second end intruding into the second insulating layer contacts the channel layer, or

[0029] A portion of the second end of the transistor on a side close to the first insulating layer intrudes into the first insulating layer, and a portion of the second end intruding into the first insulating layer contacts the channel layer.

[0030] This is beneficial to increasing the contact area between the first signal layer and the channel layer.

[0031] In combination with the second aspect, in some implementations of the second aspect, the transistor further includes a filling layer, the channel layer is in contact with the source through the filling layer, or the channel layer is in contact with the drain through the filling layer, and the material of the filling layer is an oxide semiconductor material.

[0032] This helps reduce contact resistance and improve device stability.

[0033] In a third aspect, a complementary transistor is provided, comprising a first transistor and a second transistor stacked in a vertical direction, the first transistor being located above the second transistor, the channel layer of the first transistor being an electron type channel, the channel layer of the second transistor being a hole type channel, the first transistor comprising a source, a drain and at least one channel group, at least one channel group being located between the source and the drain in a horizontal direction, the channel group comprising an inner core and a channel layer surrounding the inner core, the channel layer being in contact with the source and the drain, the material of the channel layer being an oxide semiconductor material, wherein the inner core comprises a first insulating layer, and the channel group further comprises a first dielectric layer surrounding the channel layer and a gate, and the source, the drain and the gate are isolated from each other; or, the inner core comprises a gate and a first dielectric layer surrounding the gate, and the source, the drain and the gate are isolated from each other.

[0034] Since OS materials have a low thermal budget, this helps avoid degrading the performance of lower-layer transistors when fabricating top-layer transistors.

[0035] In addition, in the solution of the embodiment of the present application, the surround gate structure of the first transistor can effectively compensate for the problem that the OS channel mobility is lower than the Si channel mobility. If the second transistor is a Si transistor, that is, when it forms a complementary transistor together with the Si transistor, it is beneficial to achieve performance balance between the two transistors, thereby helping to ensure the overall power consumption and processing speed of the complementary transistor.

[0036] In a fourth aspect, a memory is provided, comprising a memory array and a memory controller according to the second aspect or any possible implementation of the second aspect, wherein the memory controller and the memory array are electrically connected.

[0037] According to a fifth aspect, an electronic device is provided, comprising the memory according to the fourth aspect and a circuit board, wherein the memory is disposed on the circuit board and is electrically connected to the circuit board.

[0038] The technical effects that can be achieved by any possible implementation method in any of the second to fifth aspects mentioned above can be correspondingly referred to the description of the technical effects that can be achieved by the first aspect mentioned above or any possible implementation method in the first aspect, and the repetitions will not be discussed here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the circuit structure of the memory cell.

[0040] Figure 2 A schematic diagram of a GAA FET.

[0041] Figure 3 It is a schematic structural diagram of a transistor according to an embodiment of the present application.

[0042] Figure 4 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0043] Figure 5 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0044] Figure 6 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0045] Figure 7 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0046] Figure 8 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0047] Fig. 9 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0048] Fig.10 It is a schematic diagram of a method for preparing a transistor according to an embodiment of the present application.

[0049] Fig.11 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0050] Fig.12 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0051] Fig.13 It is a schematic diagram of another method for preparing a transistor according to an embodiment of the present application.

[0052] Fig.14 It is a schematic diagram of the structure of a transistor during the preparation process in an embodiment of the present application.

[0053] Fig.15 It is a schematic structural diagram of another transistor according to an embodiment of the present application.

[0054] Fig.16 It is a schematic diagram of another method for preparing a transistor according to an embodiment of the present application.

[0055] Fig.17 It is a schematic diagram of a gate lead-out method of an embodiment of the present application.

[0056] Fig.18 It is a schematic diagram of a circuit structure of a storage array according to an embodiment of the present application.

[0057] Fig.19 It is a schematic diagram of a sub-storage array in a storage array according to an embodiment of the present application.

[0058] Fig. 20 It is a schematic diagram of a sub-storage array in another storage array according to an embodiment of the present application.

[0059] Fig.21 It is a schematic diagram of the circuit structure of another storage array according to an embodiment of the present application.

[0060] Fig. 22 It is a schematic diagram of a sub-storage array in another storage array according to an embodiment of the present application.

[0061] Fig.23 It is a schematic diagram of a sub-storage array in another storage array according to an embodiment of the present application.

[0062] Fig.24 It is a schematic diagram of the comparison results of performance power consumption curves of different CFETs in the embodiments of the present application. DETAILED DESCRIPTION

[0063] The scheme in the embodiment of the present application will be described below in conjunction with the accompanying drawings.

[0064] In order to better illustrate the solutions of the embodiments of the present application, the concepts that may be involved in the embodiments of the present application are first described below.

[0065] (1) Dynamic random access memory (DRAM);

[0066] DRAM is a semiconductor memory whose main working principle is to use the amount of charge stored in a capacitor to represent one or more binary bits.

[0067] DRAM includes multiple memory cells, each of which can adopt multiple structures such as one transistor one capacitor (1T1C) structure, two transistor two capacitor (2T2C) structure or two transistor one capacitor (2T1C) structure.

[0068] The DRAM also includes a plurality of word lines, a plurality of bit lines, and a plurality of plate lines connected to the plurality of storage cells. The gate of the transistor in the storage cell is connected to the word line. One end of the capacitor in the storage cell is connected to the plate line. The other end of the capacitor is connected to the first end of the transistor, and the second end of the transistor is connected to the bit line. The first end of the transistor can be the drain of the transistor. Alternatively, the first end of the transistor can be the source of the transistor.

[0069] The following is an exemplary description using a storage unit having a 1T1C structure as an example.

[0070] Figure 1 Figure 1 is a schematic diagram of the 1T1C structure. Figure 1 As shown, the 1T1C structure includes a transistor and a capacitor. The gate (gate, G) of the transistor is connected to the word line (word line, WL). The drain (drain, D) of the transistor can be connected to the bit line (bitline, BL), one end of the capacitor can be connected to the source (source, S) of the transistor, and the other end of the capacitor is connected to the plate line (plateline, PL). Alternatively, the source of the transistor is connected to BL, one end of the capacitor is connected to the drain of the transistor, and the other end of the capacitor is connected to the plate line PL. WL is used to control the gating and shutting off of the transistor. By applying corresponding potentials to BL and WL, information can be written into the capacitor or read from the capacitor.

[0071] (2)GAA;

[0072] Figure 2 2 shows a schematic diagram of a GAA FET. The perspective of the schematic diagram is along the direction of the connection between the source and the drain. The source, gate and drain are arranged on the substrate 240 along the horizontal direction. Figure 2 As shown, the GAA structure realizes the wrapping of the outer contour of the channel 210 by the gate 230. A dielectric layer 220 is provided between the gate 230 and the channel 210. Compared with Fin FET, the gate control capability of GAA FET is stronger, and the GAA structure can reduce leakage current and increase saturation current. Figure 2 The material of the channel 210 in the embodiment is usually silicon (Si), and the field effect transistor (FET) prepared based on this can be called Si FET. In the embodiment of the present application, the field effect transistor can also be called field effect tube or transistor. For the convenience of description, the embodiment of the present application will be Figure 2 The channel shown is referred to as a channel made from bulk material.

[0073] (3) Oxide semiconductor transistors

[0074] Oxide semiconductor (OS) material is an electronic amorphous non-crystalline channel material with low thermal budget, high mobility and good uniformity. Oxide semiconductor field effect transistor (OS FET) can be prepared within 400°C. In the embodiments of the present application, oxide semiconductor field effect transistor can be referred to as oxide semiconductor transistor.

[0075] In many logic and storage applications, oxide semiconductor transistors can supplement or even replace Si transistors.

[0076] For example, in logic applications, the traditional Si complementary field effect transistor (CFET) is formed by stacking an N-type metal oxide semiconductor (NMOS) device and a P-type metal oxide semiconductor (PMOS) device. If OS FET is used to replace the upper NMOS in CFET, the structure and complex process of traditional Si CFET can be overturned, and a low thermal budget process can be used to prepare the top OS FET without degrading the performance of the lower Si transistor.

[0077] For example, in storage applications, especially in the field of DRAM, OS FET can replace Si transistors in DRAM. Since OS FET has extremely low leakage current Ioff, DRAM with a retention time several orders of magnitude longer can be prepared based on OS FET. At the same time, OS FET has a low thermal budget, which is conducive to reducing the preparation cost of 3D DRAM.

[0078] In a related scheme, OS FET can adopt a nanosheet structure, that is, Figure 2 The material of the channel in the FET shown is replaced by OS material instead of Si. The nanosheet structure based on the oxide semiconductor channel can be directly generated by alternating the growth of oxide semiconductor and sacrificial layer, and the rest of the process is consistent with the FET using the nanosheet structure based on Si channel.

[0079] The current GAA device has poor design flexibility. In the current GAA device design, the device with different currents can usually be designed by adjusting the channel size, thereby optimizing the device performance and power consumption. In actual applications, a larger channel size may seriously affect the gate control capability of the GAA device.

[0080] In view of this, an embodiment of the present application provides a transistor, which is helpful in ensuring the performance of the transistor.

[0081] The transistor provided in the embodiment of the present application may be a field effect transistor.

[0082] Figures 3 to 9 , Fig.11 , Fig.12 , Fig.15 Schematic diagrams showing structures of various transistors provided in embodiments of the present application are shown. Figures 3 to 7 It is a schematic diagram of the perspective along the connection direction of the source and the drain. Figure 8 , Fig. 9 , Fig.11 , Fig.12 , Fig.15 The transistor of the embodiment of the present application is described below with reference to the accompanying drawings.

[0083] The transistor includes a source 310, a drain 320 and at least one channel group 330. At least one channel group 330 is located between the source 310 and the drain 320 in the horizontal direction. Figure 8 , Fig. 9 , Fig.11 , Fig.12 or Fig.15 shown.

[0084] Each channel group 330 includes a core and a channel layer 331 surrounding the core. The channel layer 331 is in contact with the source 310 and the drain 320.

[0085] The channel layer 331 has a wraparound gate structure. If the transistor includes a plurality of channel groups 330, then correspondingly, each channel layer in the plurality of channel groups 330 has a wraparound gate structure. The wraparound gate structure may be implemented in any of the following ways.

[0086] In a possible implementation manner (method 1), the core includes a first insulating layer 332 , and the channel group 330 further includes a first dielectric layer 333 surrounding the channel layer 331 and a gate 334 , and the source 310 , the drain 320 and the gate 334 are isolated from each other.

[0087] In other words, in the first embodiment, the surrounding gate structure can be understood as a structure in which the gate 334 surrounds the channel layer 331 .

[0088] The transistor in the embodiment of the present application may also be referred to as a semiconductor on insulator (SOI) GAA device, or SOI GAA FET.

[0089] In another possible implementation manner (method 2), the core includes a gate 334 and a first dielectric layer 333 surrounding the gate 334 , and the source 310 , the drain 320 and the gate 334 are isolated from each other.

[0090] In other words, in Mode 2, the surrounding gate structure can be understood as a structure in which the channel layer 331 surrounds the gate 334 .

[0091] Exemplarily, the transistor may further include a substrate 340. The source 310, the drain 320 and at least one channel group 330 may be disposed on the substrate 340. In some implementations, the horizontal direction may also be understood as a direction parallel to the surface of the substrate 340. For ease of description, the embodiments of the present application are described based on this.

[0092] At least one channel group 330 is located between the source 310 and the drain 320 in the horizontal direction, that is, the source 310, at least one channel group 330 and the drain 320 are sequentially arranged in a direction parallel to the surface of the substrate 340. In other words, the source 310, at least one channel group 330 and the drain 320 are arranged horizontally on the substrate 340. Alternatively, it can also be understood that the projection of the at least one channel group 330 on the substrate surface is located between the projection of the source 310 on the substrate 340 surface and the projection of the drain 320 on the substrate 340 surface.

[0093] It should be noted that in the embodiment of the present application, A surrounds B can be understood as, with one axis of B as the center line, A is distributed outside B, that is, away from the center line. A surrounds B means that, in the vertical cross section, A is distributed at least above and below B.

[0094] A surrounding B does not limit the entire area of ​​the surface of B to be surrounded by A. Taking B as a cuboid or a cube as an example, for example, A surrounding B can be six surfaces of B surrounded by A, or four surfaces of B surrounded by A, or three surfaces of B surrounded by A, etc. For another example, A surrounding the four outer surfaces of B can be that A covers the entire area of ​​the four outer surfaces of B, or that A covers a partial area of ​​each of the four outer surfaces of B. Taking B as a cylinder as an example, for example, A surrounding B can be that A surrounds the side surface of B, or it can be that A surrounds the side surface and the upper and lower bottom surfaces of B, etc. For another example, A surrounding B can be that A surrounds the side surface of B, can be the entire area of ​​the side surface of B surrounded by A, or it can be a partial area of ​​the side surface of B surrounded by A.

[0095] In addition, A surrounding B does not limit A to being in direct contact with B, and other structures may be provided between A and B. Specific examples may be referred to later, and will not be described in detail here.

[0096] Exemplarily, an axis of the channel group 330 may be perpendicular to the side surface of the source 310 on the side close to the drain 320. In other words, an axis of the channel group 330 may be perpendicular to the side surface of the drain 320 on the side close to the source 310. In this case, the channel layer 331 surrounds the core, and the channel layer 331 surrounds the core with the axis as the center line. For example, if the core is a cuboid or a cube, the channel layer 331 surrounds the four outer surfaces of the core with the axis as the center line. For another example, if the core is a cylinder, the channel layer 331 surrounds the side surface of the cylinder.

[0097] Exemplarily, the channel layer 331 surrounds the core, and the material used for the channel layer 331 can also be called a thin film material. In this case, the transistor in the embodiment of the present application can also be called a GAA thin film transistor.

[0098] By way of example, the thickness of the channel layer 331 may be 0.1 nm to 20 nm.

[0099] Exemplarily, other structures may be included below the substrate 340, such as a front-end device structure, or the substrate 340 may be a structure obtained by depositing an insulating material after the front-end device is prepared. For example, the solution of the embodiment of the present application may be applied to a CFET, and the front-end device may be a front-end Si FET. The embodiment of the present application does not limit the structure and formation method of the substrate 340.

[0100] In the first embodiment, the core includes a first insulating layer 332 , a first dielectric layer 333 surrounds the channel layer 331 , and a gate 334 surrounds the first dielectric layer 333 .

[0101] In mode 1, the directions of the layers are the same. In other words, in a channel group 330, the structures from the inside to the outside are the first insulating layer 332, the channel layer 331, the first dielectric layer 333 and the gate 334. Figure 3 shown.

[0102] Alternatively, it can be understood as follows: in one channel group, in the vertical direction, with the first insulating layer 332 as the center, upward and downward there are the channel layer 331 , the first dielectric layer 333 and the gate 334 in sequence.

[0103] In approach 1, the channel layer 331 is wrapped around the insulating core (ie, the first insulating layer 332 ).

[0104] In the second embodiment, the core includes a gate 334 and a first dielectric layer 333 surrounding the gate 334 .

[0105] In mode 2, the directions of the layers are the same. In other words, in a channel group 330, the structures from the inside to the outside are the gate 334, the first dielectric layer 333 and the channel layer 331, as shown in FIG. Figure 4 shown.

[0106] Alternatively, it can be understood as follows: in one channel group, in the vertical direction, with the gate 334 as the center, the first dielectric layer 333 and the channel layer 331 are arranged upward and downward in sequence.

[0107] The detailed description of Method 1 and Method 2 can be found in the following text and will not be described in detail here.

[0108] By way of example, the material of the metal electrode of the source 310 may include metal and / or metal nitride, such as tungsten (W) and / or titanium nitride (TiN).

[0109] For example, the source electrode 310 may include two materials, such as Figure 8 , Fig. 9 , Fig.11 or Fig.12 As shown, the material close to the gate is TiN, and the material far from the gate is W.

[0110] For example, the source electrode 310 may include a material such as Fig.15 As shown, the material may be W.

[0111] By way of example, the material of the metal electrode of the drain 320 may include metal and / or metal nitride, such as W and / or TiN.

[0112] For example, the drain 320 may include two materials, such as Figure 8 , Fig. 9 , Fig.11 or Fig.12 As shown, the material close to the gate is TiN, and the material far from the gate is W.

[0113] For example, the drain 320 may include a material such as Fig.15 As shown, the material may be W.

[0114] For example, the gate 334 may be a metal gate, and the material of the gate 334 may include at least one of the following: TiN, titanium aluminide (TiAl), or W.

[0115] For example, the gate 334 may include a material such as Figure 8 or Fig. 9 As shown, the material may be W.

[0116] For another example, the gate 334 may include two materials, such as Fig.11 , Fig.12 or Fig.15 As shown, the outer material is TiN and the inner material is W.

[0117] The source and drain can also use tungsten silicide (WSi), InSnO, nickel (Ni), NiPt and other materials as contacts.

[0118] Exemplarily, the transistor may further include other structures, such as a liner metal layer or a work function adjustment layer, etc. This embodiment of the present application does not limit this.

[0119] Exemplarily, the material of the first insulating layer 332 may be an oxide or nitride material, such as silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon oxycarbide (SiOC), silicon carbonitride (SiNC), etc.

[0120] Exemplarily, the first insulating layer 332 may be formed by plasma enhanced chemical vapor deposition (PECVD).

[0121] Exemplarily, the material of the first dielectric layer 333 may be an oxide material, for example, a high dielectric constant (high-k) material.

[0122] For example, the material of the first dielectric layer 333 may be hafnium dioxide (HfO 2 ), hafnium aluminum oxide (HfAlO) or hafnium lanthanum oxide (HfLaO).

[0123] Exemplarily, the first dielectric layer 333 may be formed by atomic layer deposition (ALD).

[0124] Exemplarily, the thickness of the first dielectric layer 333 is 0.1 nm to 10 nm.

[0125] Exemplarily, the first dielectric layer 333 may include a dipole layer, for example, lanthanum oxide (LnO).

[0126] Exemplarily, the material of the second insulating layer 350 may be an insulating material having a selective etching ratio with the first insulating layer 332. For example, the material of the first insulating layer 332 may be SiO2, and the material of the second insulating layer 350 may be silicon oxycarbon (SiOC).

[0127] By way of example, the material of the third insulating layer 360 may be an oxide material, for example, silicon dioxide (SiO 2 ) or the like.

[0128] In the scheme of the embodiment of the present application, the channel layer surrounds the core, and the channel layer has a surrounding gate structure, for example, the gate surrounds the channel layer, or the channel layer surrounds the gate, which is conducive to improving the flexibility of the design while ensuring the gate control performance. Specifically, as mentioned above, the size of the channel of the GAA device using the bulk material as the channel is difficult to flexibly adjust, and the size of the larger channel may seriously affect the gate control capability of the GAA device. In the scheme of the embodiment of the present application, the channel layer surrounds the core, and the equivalent width of the channel layer can be adjusted by adjusting the size of the core, and devices with different currents can be designed, thereby optimizing the performance and power consumption of the device. At the same time, the thickness of the channel layer is not limited by the size of the core. For example, the channel layer can be set as a thin film, which is conducive to ensuring the control ability of the gate over the channel layer, that is, ensuring the gate control capability of the device.

[0129] Optionally, in Mode 1, the at least one channel group 330 may include a plurality of channel groups 330 distributed along the vertical direction.

[0130] Alternatively, it can also be understood that the at least one channel group 330 includes a plurality of channel groups stacked along a direction perpendicular to the substrate 340 .

[0131] This helps to increase the equivalent width of the channel, thereby increasing the device current and improving the performance of the device.

[0132] For example, Figure 5 As shown, the at least one channel group can be considered to include two channel groups. Alternatively, it can also be understood that the structure of the gate 334 and the first dielectric layer 333 and the structure of the channel layer 331 and the first insulating layer 332 appear alternately.

[0133] It should be understood that Figure 5 Only two channel groups are used as an example, and the transistor may also include other numbers of channel groups, which is not limited in the embodiments of the present application.

[0134] Optionally, in the first embodiment, a second insulating layer 350 is disposed between every two channel groups 330 in the plurality of channel groups 330 .

[0135] In other words, in a direction perpendicular to the substrate surface, the channel groups 330 and the second insulating layers 350 appear alternately.

[0136] For example, in the first embodiment, the second insulating layer 350 may surround the gate 334, such as Figure 6 shown.

[0137] In mode 1, the directions of the layers can be consistent. In other words, the structures from the inside to the outside are the first insulating layer 332, the channel layer 331, the first dielectric layer 333, the gate 334, and the second insulating layer 350. Alternatively, in the direction perpendicular to the substrate surface, with the first insulating layer 332 as the center, the channel layer 331, the first dielectric layer 333, the gate 334, and the second insulating layer 350 are arranged upward and downward.

[0138] Optionally, in Mode 2, the at least one channel group 330 may include a plurality of channel groups 330 distributed in the vertical direction. A third insulating layer 360 is disposed between every two channel groups 330 in the plurality of channel groups 330 .

[0139] For example, in the second embodiment, the third insulating layer 360 may surround the channel layer 331, such as Figure 7 or Figure 4 shown.

[0140] In mode 2, the directions of the layers can be consistent. In other words, the structure from the inside to the outside is the gate 334, the first dielectric layer 333, the channel layer 331 and the third insulating layer 360. Alternatively, in the direction perpendicular to the substrate surface, with the gate 334 as the center, the first dielectric layer 333, the channel layer 331 and the third insulating layer 360 are arranged upward or downward.

[0141] Next, the channel layer 331 will be described.

[0142] As described above, the channel layer 331 may be a thin film material. For example, the channel layer 331 may be formed by ALD or physical vapor deposition (PVD).

[0143] By way of example, the material of the channel layer 331 may be amorphous silicon, polycrystalline silicon, carbon nanotubes or two-dimensional materials.

[0144] Optionally, the material of the channel layer 331 may be an oxide semiconductor (OS) material.

[0145] By way of example, the material of the channel layer 331 may be an amorphous, polycrystalline, or other specific crystalline oxide semiconductor material.

[0146] For example, the material of the channel layer 331 may be any one of the following: indium gallium zinc oxide (IGZO / InGaZnO), indium tin oxide (InSnO), indium tungsten oxide (InWO), indium aluminum zinc oxide (InAlZnO), and the like.

[0147] When OS material is used as the channel material, the transistor in the embodiment of the present application may also be referred to as an OSGAA transistor or an OS GAA FET.

[0148] OS materials have a low thermal budget, and the use of OS channel materials is beneficial to reducing the process difficulty of manufacturing transistors and reducing manufacturing costs.

[0149] Compared with the planar OS FET, in the solution of the embodiment of the present application, the surrounding gate structure is adopted, which is beneficial to improving the gate control capability, increasing the effective value of the current Ieff, and reducing the parasitic capacitance, thereby helping to improve the performance of the transistor.

[0150] As mentioned above, in some related schemes, the nanosheet structure can be directly generated by alternating the growth of oxide semiconductor and sacrificial layer. However, OS is prone to over-etching during the etching of the sacrificial layer, especially in the case of short channels, the OS channel is etched or damaged. At the same time, when the OS and the sacrificial layer grow alternately to form the initial structure, the growth of the sacrificial layer will cause the OS to be severely degraded.

[0151] In the solution of the embodiment of the present application, a structure in which the channel layer surrounds the core is adopted, and the above-mentioned method can be avoided when preparing the transistor, thereby preventing the channel layer from being affected by degradation, which is beneficial to ensuring the performance of the transistor.

[0152] The OS GAA FET in the embodiment of the present application can be applied to CFET. For example, the OS GAA FET can be used to replace the upper Si transistor in the CFET. Since the thermal budget of the OS material is low, this helps to avoid degrading the performance of the lower Si transistor when preparing the top OS GAA FET.

[0153] CFET can be considered as consisting of two complementary transistors. If there is a difference in performance between the two, that is, the performance between the two is unbalanced, the overall power consumption and processing speed of CFET will be reduced. In the solution of the embodiment of the present application, the use of a surround gate structure can effectively compensate for the problem that the OS mobility is lower than the Si mobility. When applied to CFET, it is beneficial to achieve a performance balance between the two transistors, thereby facilitating the optimization of the overall power consumption and processing speed of CFET.

[0154] Fig.24 The performance-dynamic power curve of CFET formed by OS FET and Si PMOS based on different device structures is shown. The performance can be frequency. Fig.24 As shown in the simulation diagram, after replacing the OS FET from the planar OS FET with the OS GAA FET of the embodiment of the present application, the performance of the CFET formed based on the OS GAA FET and Si PMOS is improved by 10.2% and the power consumption is reduced by 19.8% under the 5nm process. The OS GAA FET is a GAA FET based on a sheet, that is, an OS GAA FET with one channel group.

[0155] The OS GAA FET of the embodiment of the present application can be applied to DRAM, which is conducive to realizing a large-capacity DRAM.

[0156] At the same time, OS materials have a low thermal budget, and the use of OS channel materials is conducive to reducing the process difficulty of preparing three-dimensional (3D) DRAM and reducing the preparation cost. In addition, the OS GAA FET of the embodiment of the present application adopts a surround gate structure, which can make the OS GAA FET have a higher read and write current and extremely low leakage current, which is conducive to optimizing the read and write speed and power consumption performance of DRAM.

[0157] In a possible implementation, the channel layer 331 contacts the source 310 , which may be direct contact with the source 310 . The channel layer 331 contacts the drain 320 , which may be direct contact with the drain 320 .

[0158] In another possible manner, the channel layer 331 contacts the source 310 through the filling layer 370. The channel layer 331 contacts the drain 320 through the filling layer 370. The filling layer 370 is made of an oxide semiconductor material. This structure may be referred to as a raised source or drain (raised S / D) structure.

[0159] In other words, an additional layer of oxide semiconductor material is deposited between the source electrode 310 and the channel layer 331. An additional layer of oxide semiconductor material is deposited between the drain electrode 320 and the channel layer 331.

[0160] The material of the filling layer 370 and the material of the channel layer 331 may be the same or different.

[0161] Exemplarily, the material of the filling layer 370 may be a crystallized oxide semiconductor, such as polycrystalline indium oxide (In2O3), or may be doped at a high concentration. The carrier concentration, i.e., the doping concentration, in the thin film material may be adjusted by process, element composition, or doping. For example, the doping concentration of the channel is 1e18cm-3, and the doping concentration of the filling layer is 1e20cm-3. For example, high concentration doping may be a doping concentration greater than or equal to 1e19cm-3.

[0162] By way of example, the filling layer 370 may be formed by ALD or the like.

[0163] In the solution of the embodiment of the present application, a raised S / D structure can be used, which is equivalent to increasing the contact area between the channel layer and the source and / or drain, which is conducive to reducing the contact resistance and also reduces the resistance of the channel between the gate region and the contact. At the same time, this structure is conducive to preventing hydrogen (H) impurities in the source and / or drain from diffusing into the channel, thereby helping to improve the stability of the device.

[0164] The detailed description of the raised S / D structure can be found later and will not be elaborated here.

[0165] The structure of the transistor in the embodiment of the present application is exemplarily described below in combination with three examples (Example 1, Example 2 and Example 3).

[0166] Example 1

[0167] In the solution of Example 1, the channel group 330 includes a first insulating layer 332, a channel layer 331, a first dielectric layer 333 and a gate 334 from the inside to the outside. In the case where the transistor includes a plurality of channel groups 330, the transistor does not include a second insulating layer 350, for example, Figure 5 Shown or Figure 8 Alternatively, it can also be understood that, in the solution of Example 1, multiple channel groups 330 share a gate. In a possible implementation, Figure 8 and Figure 5 A schematic that can be used as two views of the same transistor.

[0168] Exemplarily, on the side of the gate 334 close to the source 310, the first dielectric layer 333 and the channel layer 331 cover the side surface of the gate 334. Specifically, the first dielectric layer 333 covers the side surface of the gate, and the channel layer 331 covers the side surface of the first dielectric layer 333 away from the gate.

[0169] In this way, if the source electrode 310 is in direct contact with the region of the channel layer 331 covering the side surface of the gate electrode 334 , the contact area between the channel layer 331 and the source electrode 310 can be increased, thereby reducing the contact resistance.

[0170] Exemplarily, on the side of the gate 334 close to the drain 320, the first dielectric layer 333 and the channel layer 331 cover the side surface of the gate 334. Specifically, the first dielectric layer 333 covers the side surface of the gate, and the channel layer 331 covers the side surface of the first dielectric layer 333 away from the gate.

[0171] In this way, if the drain electrode 320 is in direct contact with the region of the channel layer 331 covering the side surface of the gate electrode 334 , it is beneficial to increase the contact area between the channel layer 331 and the drain electrode 320 , thereby reducing the contact resistance.

[0172] For example, Figure 8 As shown, the first dielectric layer 333 and the channel layer 331 cover the side surface of the gate 334 close to the drain 320 and the side surface of the gate 334 close to the source 310 .

[0173] Exemplarily, an isolation layer 381 is provided between the source 310 and the gate 334, for example, Figure 8 shown.

[0174] If the first dielectric layer 333 and the channel layer 331 cover the side surface of the gate 334 close to the source 310, the channel layer 331 is also in contact with the isolation layer 381, for example, Figure 8 shown.

[0175] Alternatively, when the first dielectric layer 333 and the channel layer 331 cover the side surface of the gate 334 close to the source 310 , the width of the isolation layer 381 between the source 310 and the gate 334 may also be 0, or in other words, no isolation layer is provided between the source 310 and the gate 334 .

[0176] In this case, the channel layer 331 may be in direct contact with the source electrode 310 at the side.

[0177] Exemplarily, an isolation layer 382 is provided between the drain 320 and the gate 334, for example, Figure 8 shown.

[0178] If the first dielectric layer 333 and the channel layer 331 cover the side surface of the gate 334 close to the drain 320, the channel layer 331 is also in contact with the isolation layer 382, ​​for example, Figure 8 shown.

[0179] Alternatively, when the first dielectric layer 333 and the channel layer 331 cover the side surface of the gate 334 close to the drain 320 , the width of the isolation layer 382 between the drain 320 and the gate 334 may be 0, or in other words, no isolation layer is provided between the drain 320 and the gate 334 .

[0180] In this case, the channel layer 331 may be in direct contact with the drain electrode 320 at a side.

[0181] For example, the material of the isolation layer may be a nitride material, for example, silicon nitride (SiN x ).

[0182] Exemplarily, the isolation layer may be formed by PECVD.

[0183] Exemplarily, a projection of the source electrode 310 in the horizontal direction is in contact with a projection of the channel layer 331 in the horizontal direction without overlapping.

[0184] Alternatively, a portion of the source electrode 310 near the first insulating layer 332 intrudes into the first insulating layer 332, and the intruded portion contacts the channel layer 331, for example, Figure 8 shown.

[0185] One side of the source electrode 310 close to the first insulating layer 332 partially intrudes into the first insulating layer 332 , which means that a projection of the source electrode 310 in the horizontal direction partially overlaps with a projection of the channel layer 331 in the horizontal direction.

[0186] The source electrode 310 partially intrudes into the first insulating layer 332 , which may also be referred to as the source electrode 310 partially intrudes into the channel region.

[0187] In this way, the contact area between the channel layer and the source electrode can be increased.

[0188] Exemplarily, a projection of the drain 320 in the horizontal direction and a projection of the channel layer 331 in the horizontal direction do not overlap.

[0189] Alternatively, a portion of the drain electrode 320 near the first insulating layer 332 intrudes into the first insulating layer 332, and the intruded portion contacts the channel layer 331, for example, Figure 8 shown.

[0190] One side of the drain electrode 320 close to the first insulating layer 332 partially intrudes into the first insulating layer 332 , which means that a projection of the drain electrode 320 in the horizontal direction partially overlaps with a projection of the channel layer 331 in the horizontal direction.

[0191] The drain 320 partially intrudes into the first insulating layer 332 , which may also be referred to as the drain 320 partially intruding into the channel region.

[0192] In this way, the contact area between the channel layer and the drain electrode can be increased.

[0193] Furthermore, a filling layer 370 (raised S / D structure) may be provided in the transistor, that is, a layer of oxide semiconductor material is deposited between the source 310 and the channel layer 331 . Alternatively, a layer of oxide semiconductor material is deposited between the drain 320 and the channel layer 331 .

[0194] For example, Fig. 9 As shown, a layer of oxide semiconductor material is deposited between the source 310 and the channel layer 331 , and a layer of oxide semiconductor material is deposited between the drain 320 and the channel layer 331 .

[0195] It should be understood that Fig. 9 The deposition method is only an example, and it can also be deposited in other forms, as long as an additional layer of oxide semiconductor material is deposited between the channel layer and the source or drain. The embodiments of the present application are not limited to this.

[0196] The raised S / D structure can reduce contact resistance and improve device stability. At the same time, the raised S / D structure can increase the distance between the channel layer and the source and drain, reducing the degradation of the channel layer by impurities in the source and drain.

[0197] Fig. 9 (a) and (b) show two different thicknesses of the filling layer. Fig. 9As shown, the thickness of the filling layer 370 affects the distance between the source, drain and gate. By adjusting the thickness of the filling layer, the distance between the source, drain and gate can be adjusted, thereby controlling the parasitic capacitance and current level.

[0198] Fig.10 A schematic diagram showing a process for preparing a semiconductor device according to an embodiment of the present application is shown.

[0199] Combine the following Fig.10 right Figure 8 The preparation process of the semiconductor device shown is exemplified.

[0200] The process of preparing a semiconductor device may include the following steps.

[0201] S11, two materials with a selective etching ratio are alternately deposited on the substrate, such as Fig.10 As shown in (a).

[0202] One material is the material of the first insulating layer, and the other material is the material of the sacrificial layer.

[0203] Exemplarily, the two materials may be oxide and nitride. For example, the two materials may be SiO2 and SiN x For example, nitride can be used as the material of the sacrificial layer, and oxide can be used as the material of the first insulating layer.

[0204] Illustratively, the oxide may be deposited by PECVD.

[0205] For example, the nitride may be deposited by PECVD.

[0206] S12, performing longitudinal etching in the lateral area of ​​the deposition area.

[0207] In the embodiments of the present application, "lateral", "side", and "side" are all based on the perspective perpendicular to the direction of the source and drain connection.

[0208] For example, Fig.10 As shown in (a), the lateral SiO2 and lateral SiN are etched x .

[0209] In addition, in this step, lateral device insulation can be achieved by longitudinal etching of the side surface. For example, if multiple transistors are prepared on a substrate, lateral insulation between the multiple transistors can be achieved by longitudinal etching of the side surface.

[0210] S13, filling the etched area with oxide.

[0211] like Fig.10As shown in (b), SiO2 can be filled in the etched area and polished by chemical-mechanical planarization (CMP).

[0212] S14, nitride is laterally etched.

[0213] like Fig.10 As shown in (c), SiN is laterally etched in the central area of ​​the device in the horizontal direction in the current view. x , and retain the part adjacent to SiO2 as an isolation layer. Alternatively, SiN x of the entire area, in which case the transistor may not include an isolation layer.

[0214] S15, depositing the material of the channel layer and the material of the first dielectric layer in sequence to form the channel layer and the first dielectric layer, such as Fig.10 as shown in (d).

[0215] Exemplarily, the channel layer can be deposited by ALD.

[0216] By way of example, the material of the channel layer may be IGZO.

[0217] Exemplarily, the first dielectric layer can be deposited by ALD.

[0218] By way of example, the material of the first dielectric layer may be a high-k material.

[0219] Through S15 , the channel layer can surround the insulating layer, and the first dielectric layer can surround the channel layer.

[0220] Furthermore, a dipole layer (not shown in the figure) may be formed by deposition.

[0221] S16, depositing a metal material of a gate to form a gate metal layer, such as Fig.10 As shown in (e).

[0222] Specifically, a metal material of the gate is deposited and then planarized by CMP.

[0223] Exemplarily, the gate metal layer can be deposited by ALD or CVD.

[0224] By way of example, the material of the gate metal layer may include W, ruthenium (Ru), TiN or TiAl.

[0225] Through S16, the gate metal layer can surround the first dielectric layer. At the same time, the side of the gate close to the isolation layer is covered with the first dielectric layer and the channel layer. In other words, the first dielectric layer and the channel layer are deposited between the gate and the isolation layer.

[0226] S17, etching the lateral regions of the oxide, e.g. Fig.10 As shown in (f).

[0227] If SiN is not retained in step S14 x After etching the lateral area of ​​the oxide, after depositing the source and drain metal electrodes in step S18, the source and drain metal electrodes are in contact with the channel layer at the side.

[0228] Furthermore, in step S17, part of the oxide may be etched laterally to retain the central region of the oxide. Fig.10 As shown in (f), the lateral SiO2 is etched. The lateral etching partially invades the SiO2 inside the channel region, or in other words, the end of the SiO2 region surrounded by the channel region is etched laterally, leaving the middle region.

[0229] If SiN is retained in step S14 x Etching only the lateral area of ​​the oxide may not allow the subsequently deposited source and drain metal electrodes to contact the channel layer. Lateral etching partially intrudes into the SiO2 inside the channel area, which can allow the subsequently deposited source and drain metal electrodes to contact the channel layer.

[0230] S18, depositing metal material in the etched area to form source and drain metal electrodes, such as Fig.10 As shown in (g).

[0231] Exemplarily, the materials of the source and drain metal electrodes include TiN and W. In step S18 , TiN and W may be deposited in sequence and polished by CMP.

[0232] It should be understood that Fig.10 The preparation process shown is only an example and does not constitute a limitation on the embodiments of the present application.

[0233] Example 2

[0234] In the solution of Example 2, the channel group 330 includes a first insulating layer 332, a channel layer 331, a first dielectric layer 333 and a gate 334 from the inside to the outside. In the case where the transistor includes a plurality of channel groups 330, a second insulating layer 350 is provided between two channel groups 330. Fig.11 As shown, the channel group 330 and the second insulating layer 350 appear in sequence. For example, the second insulating layer 350 may surround the gate 334, for example, Figure 6 In one possible implementation, Fig.11 and Figure 6 A schematic that can be used as two views of the same transistor.

[0235] In the solution of Example 2, the material of the second insulating layer 350 may be different from the material of the first insulating layer 332. The material of the first insulating layer 332 and the material of the second insulating layer 350 may be two materials having a selective etching ratio. For example, the material of the second insulating layer 350 may be SiO2, and the material of the first insulating layer may be SiOC.

[0236] Exemplarily, the gate 334 surrounds a portion of the channel layer 331, such as Fig.11 shown.

[0237] For example, Fig.11 As shown, the length of the projection of the gate 334 in the horizontal direction is less than the length of the projection of the channel layer 331 in the horizontal direction, and the width of the projection of the gate 334 in the horizontal direction is greater than the width of the projection of the channel layer 331 in the horizontal direction. Alternatively, the width of the projection of the gate 334 in the horizontal direction is less than the width of the projection of the channel layer 331 in the horizontal direction, and the length of the projection of the gate 334 in the horizontal direction is greater than the length of the projection of the channel layer 331 in the horizontal direction.

[0238] By way of example, the source 310 and the gate 334 may be separated by an isolation layer.

[0239] An isolation layer is provided between the source 310 and the gate 334. The channel layer 331 is in contact with the source 310 but not with the isolation layer. The isolation layer is the region between the gate 334 and the source 310. Fig.11 As shown in FIG. 3 , the isolation layer can be regarded as a part of the second insulating layer 350. Alternatively, as shown in FIG. Fig. 22 As shown, the isolation layer 380 can be obtained by etching a sacrificial layer.

[0240] By way of example, the drain 320 and the gate 334 may be separated by an isolation layer.

[0241] An isolation layer is provided between the drain 320 and the gate 334. The channel layer 331 is in contact with the drain 320 but not with the isolation layer. The isolation layer is the region between the gate 334 and the drain 320. Fig.11 As shown, the isolation layer can be regarded as a part of the second insulating layer 350. Alternatively, as Fig. 22 As shown, the isolation layer 380 can be obtained by etching a sacrificial layer.

[0242] exist Fig.11 In the transistor shown, the width of the isolation layer is not zero.

[0243] Exemplarily, the material of the isolation layer may be the material of the second insulating layer 350 , such as oxide.

[0244] It should be understood that this is only an example, and the material of the isolation layer may also be other insulating materials.

[0245] Exemplarily, the isolation layer may be formed by PECVD.

[0246] Furthermore, a raised S / D structure may be provided in the transistor, that is, a layer of oxide semiconductor material is deposited between the source 310 and the channel layer 331 . Alternatively, a layer of oxide semiconductor material is deposited between the drain 320 and the channel layer 331 .

[0247] Fig.12 A schematic diagram of another transistor structure is shown. The viewing angle of the schematic diagram is perpendicular to the connection direction of the source and the drain.

[0248] For example, Fig.12 As shown, a filling layer 370 is disposed between the source 310 and the channel layer 331, that is, a layer of oxide semiconductor material is deposited between the source 310 and the channel layer 331. A filling layer 370 is disposed between the drain 320 and the channel layer 331, that is, a layer of oxide semiconductor material is deposited between the drain 320 and the channel layer 331.

[0249] It should be understood that Fig.12 The deposition method is only an example, and it can also be deposited in other forms, as long as an additional layer of oxide semiconductor material is deposited between the channel layer and the source or drain. The embodiments of the present application are not limited to this.

[0250] like Fig.11 As shown, in this solution, the contact area between the channel layer 331 and the source 310 and the drain 320 depends on the thickness of the channel layer 331. The thickness of the channel layer 331 is usually small, which may be less than 10nm. Therefore, the contact area between the source 310 and the drain 320 and the channel layer 331 is also usually small. In this case, the raised S / D structure can greatly reduce the contact resistance of the source and drain. At the same time, the raised S / D structure can increase the distance between the channel layer and the source and drain, and reduce the degradation of the channel layer by impurities in the source and drain.

[0251] Fig.13 A schematic diagram showing a process for preparing a semiconductor device according to an embodiment of the present application is shown.

[0252] Combine the following Fig.13 right Fig.12 The preparation process of the semiconductor device shown is exemplified for illustration. The deposition method of each material can refer to the description in Example 1, and to avoid repetition, this part of the description is omitted here.

[0253] The process of preparing a semiconductor device may include the following steps.

[0254] S21, two materials with a selective etching ratio are alternately deposited on the substrate, and longitudinal etching is performed in the side regions to achieve lateral insulation of the device, such as Fig.13 As shown in (a).

[0255] One material is the material of the second insulating layer, and the other material is the material of the sacrificial layer.

[0256] Exemplarily, the two materials may be oxide and nitride. For example, the two materials may be SiO2 and SiN x For example, oxide can be used as the material of the second insulating layer, and nitride can be used as the material of the sacrificial layer. Below, nitride is taken as an example as the material of the sacrificial layer.

[0257] In the embodiments of the present application, "lateral", "side", and "side" are all based on the perspective perpendicular to the direction of the source and drain connection.

[0258] Exemplarily, the side region may be a region where a source electrode and a drain electrode are subsequently formed. In this case, step S21 may also be understood as performing longitudinal etching in the region where a source electrode and a drain electrode are subsequently formed.

[0259] For example, Fig.13 As shown in (a), the lateral SiO2 and lateral SiN are etched x , vertical etching is performed in the middle area, so that two transistors can be prepared simultaneously later. The middle area can be regarded as the side area of ​​the two transistors formed later.

[0260] It should be understood that Fig.13 (a) is only an example, and in other implementations, longitudinal etching may not be performed in the middle region. For example, if only one transistor is prepared, longitudinal etching may not be performed in the middle region.

[0261] Fig.14 (a) shows a schematic diagram of a region where a channel group is located after step S21, Fig.14 (b) shows a schematic diagram of a channel group area after step S23. Fig.14 As shown in (b), the virtual gate region is the region where the gate is subsequently deposited. Fig.14 This is the viewing angle along the line connecting the source and the drain.

[0262] S22, nitride is laterally etched.

[0263] like Fig.13 As shown in (b), SiN is laterally etched x .

[0264] S23, sequentially depositing in the following order: nitride, the material of the first dielectric layer, the material of the channel layer, and an insulating material having a selective etching ratio with both materials in step S21, such as Fig.13 (c) and Fig.14 as shown in (b).

[0265] Exemplarily, the nitride deposited in step S23 may also be replaced by other material #A having a selective etching ratio with the material of the second insulating layer. In this case, the insulating material deposited last in step S23 may be replaced by an insulating material having a selective etching ratio with both material #A and the material of the second insulating layer.

[0266] Exemplarily, the material of the channel layer may be an oxide semiconductor, such as IGZO.

[0267] By way of example, the material of the first dielectric layer may be a high-k material.

[0268] Exemplarily, the two materials in step S21 may be oxide and nitride, and the material having a selective etching ratio with oxide and nitride may be SiOC. SiOC may be used as the material of the first insulating layer.

[0269] For example, SiN x , high-k materials, oxide semiconductors and SiOC.

[0270] The structures obtained by depositing high-k materials may include Fig.12 The first dielectric layer and the dummy first dielectric layer in the embodiment. The dummy first dielectric layer will be etched in the subsequent steps. Fig.13 In (c), the dummy first dielectric layer is a vertically distributed high-k material. The structure obtained by depositing the oxide semiconductor may include Fig.12 The channel layer and dummy OS in the PCB. The dummy OS will be etched in the subsequent steps. Fig.13 In (c), the dummy OS is the vertically distributed OS.

[0271] S24, performing longitudinal etching in the side region.

[0272] For example, Fig.13 As shown in (d), etching is performed in the side region to cut part of the SiOC, part of the high-k material (ie, the dummy first dielectric layer) and part of the oxide semiconductor (ie, the dummy OS).

[0273] S25, etching nitride.

[0274] like Fig.13 As shown in (e), SiN is laterally etched x .

[0275] S26, depositing metal material and etching the side regions to form a gate metal layer, such as Fig.13 As shown in (f).

[0276] For example, Fig.13 As shown in (f), two materials are deposited sequentially, for example, TiN and W are deposited sequentially.

[0277] S27, depositing oxide and etching the side regions, such as Fig.13 As shown in (g).

[0278] S28, depositing a raised S / D structured oxide semiconductor, such as Fig.13 As shown in (h).

[0279] Exemplarily, the oxide semiconductor of the raised S / D structure may be In2O3.

[0280] Exemplarily, the oxide semiconductor may be deposited by ALD.

[0281] S29, depositing metal material to form source and drain metal electrodes, such as Fig.13 As shown in (i).

[0282] Exemplarily, the material of the source-drain metal electrodes may be W. In step S28, W may be deposited and then polished by CMP to form the source-drain metal electrodes.

[0283] It should be understood that Fig.13 For example only, Fig.13 In (i), the two transistors share a middle electrode. In other possible implementations, the two transistors may not share a middle electrode, that is, the electrode in the middle region may be two electrodes insulated from each other.

[0284] In addition, in the solution of Example 2, in the same transistor, each gate needs to be electrically connected ( Fig.13 and Figure 6 ), such as Figure 6 The gates in the two channel groups need to be electrically connected.

[0285] It should be understood that Fig.13 The preparation process shown is only an example and does not constitute a limitation on the embodiments of the present application.

[0286] Example 3

[0287] In the solution of Example 3, in the longitudinal direction, the channel group 330 extends to both sides with the gate 334 as the center. Specifically, with the gate 334 as the center, the gate 334, the first dielectric layer 333 and the channel layer 331 are arranged upward and downward in sequence.

[0288] In the solution of Example 3, the channel group 330 adopts a structure in which the gate 334 is inside and the channel layer 331 is outside. The channel group 330 includes the gate 334, the first dielectric layer 333 and the channel layer 331 from the inside to the outside. In the case where the transistor includes multiple channel groups 330, a third insulating layer 360 is provided between two channel groups 330. For example, Fig.15 As shown, the channel group 330 and the third insulating layer 360 appear in sequence. For example, the third insulating layer 360 may surround the gate 334, for example, Figure 7 In one possible implementation, Fig.15 and Figure 7 A schematic that can be used as two views of the same transistor.

[0289] The channel layer 331 contacts the source 310 and the drain 320 .

[0290] Exemplarily, the source 310 and the gate 334 may be separated by an isolation layer 381, for example, Fig.15 shown.

[0291] An isolation layer 381 is provided between the source 310 and the gate 334. Fig.15 As shown, the channel layer 331 is in contact with the source 310, but not in contact with the isolation layer 381. Fig.15 In the transistor shown, the width of the isolation layer 381 is not zero.

[0292] For example, the drain 320 and the gate 334 may be separated by an isolation layer 382, ​​for example, Fig.15 shown.

[0293] An isolation layer 382 is provided between the drain 320 and the gate 334. Fig.15 As shown, the channel layer 331 is in contact with the drain 320 but not in contact with the isolation layer 382. Fig.15 In the transistor shown, the width of the isolation layer 382 is not zero.

[0294] For example, the material of the isolation layer may be a nitride material, such as SiN x It should be understood that this is only an example, and the material of the isolation layer may also be other insulating materials.

[0295] Exemplarily, the isolation layer may be formed by PECVD.

[0296] For example, the isolation layer may be made of a material different from that of the third insulating layer 360, such as Fig.15 shown.

[0297] Alternatively, the isolation layer may be made of the same material as the third insulating layer 360. Fig.23 As shown, the isolation layer 380 is made of the same material as the third insulating layer 360 .

[0298] It should be understood that the above is only an example, and the source 310 and the gate 334 as well as the drain 320 and the gate 334 may be separated by other means, for example, Fig.23 As shown, they are separated by a first dielectric layer 333 , a channel layer 331 , and a filling layer 370 .

[0299] Optionally, a side of the source electrode 310 close to the third insulating layer 360 intrudes into the third insulating layer 360 , and a portion of the source electrode 310 intruding into the third insulating layer 360 contacts the channel layer 331 .

[0300] In this way, the contact area between the source electrode 310 and the channel layer 331 can be increased.

[0301] Optionally, a side of the drain electrode 320 close to the third insulating layer 360 intrudes into the third insulating layer 360 , and a portion of the drain electrode 320 intruding into the third insulating layer 360 contacts the channel layer 331 .

[0302] In this way, the contact area between the drain electrode 320 and the channel layer 331 can be increased.

[0303] Furthermore, a raised S / D structure may be provided in the transistor, that is, a layer of oxide semiconductor material is deposited between the source 310 and the channel layer 331 . Alternatively, a layer of oxide semiconductor material is deposited between the drain 320 and the channel layer 331 .

[0304] Fig.16 A schematic diagram showing a process for preparing a semiconductor device according to an embodiment of the present application is shown.

[0305] Combine the following Fig.16 right Fig.15 The preparation process of the semiconductor device shown is exemplified for illustration. The deposition method of each material can refer to the description in Example 1, and to avoid repetition, this part of the description is omitted here.

[0306] The process of preparing a semiconductor device may include the following steps.

[0307] S31, alternately depositing two materials with a selective etching ratio on the substrate, and performing longitudinal etching on the side regions to achieve lateral insulation of the device, such as Fig.16 As shown in (a).

[0308] One material is the material of the third insulating layer, and the other material is the material of the sacrificial layer.

[0309] Exemplarily, the two materials may be oxide and nitride. For example, the two materials may be SiO2 and SiN x For example, oxide may be used as the material of the third insulating layer, and nitride may be used as the material of the sacrificial layer.

[0310] In the embodiments of the present application, "lateral", "side", and "side" are all based on the perspective perpendicular to the direction of the source and drain connection.

[0311] For example, Fig.16 As shown in (a), the lateral SiO2 and lateral SiN are etched x , vertical etching is performed in the middle area, so that two transistors can be prepared simultaneously later. The middle area can be regarded as the side area of ​​the two transistors formed later.

[0312] It should be understood that Fig.16 (a) is only an example, and in other implementations, longitudinal etching may not be performed in the middle region. For example, if only one transistor is prepared, longitudinal etching may not be performed in the middle region.

[0313] S32, nitride is laterally etched.

[0314] like Fig.16 As shown in (b), SiN is laterally etched x .

[0315] S33, sequentially depositing materials for the channel layer and the first dielectric layer, such as Fig.16 as shown in (c).

[0316] Exemplarily, the material of the channel layer may be an oxide semiconductor, such as IGZO.

[0317] By way of example, the material of the first dielectric layer may be a high-k material.

[0318] For example, an oxide semiconductor and a high-k material are deposited in sequence.

[0319] S34, depositing metal materials, such as Fig.16 as shown in (d).

[0320] Exemplarily, the metal material may include TiN and W. For example, TiN and W are deposited sequentially.

[0321] S35, performing longitudinal etching on the side region.

[0322] like Fig.16As shown in (e), etching is performed in the side area to cut part of the metal material, part of the high-k material and part of the oxide semiconductor material.

[0323] S36, etching the lateral metal material.

[0324] like Fig.16 As shown in (f), the metal material is etched inwardly so as to retain the position of the isolation layer. In other words, the etched area can be used as the formation area of ​​the isolation layer.

[0325] S37, depositing nitride and etching the side regions.

[0326] like Fig.16 As shown in (g), SiN is deposited x , and etching the side regions to form an isolation layer.

[0327] S38, etch part of the oxide laterally.

[0328] like Fig.16 As shown in (h), part of SiO2 is laterally etched so that the subsequently formed source and drain electrodes can invade the insulating layer to increase the contact area between the source and drain electrodes and the channel layer.

[0329] S39, depositing metal material to form source and drain metal electrodes, such as Fig.16 As shown in (h).

[0330] It should be understood that Fig.16 (h) is only an example, for example Fig.16 In (h), the two transistors share a middle electrode. In other possible implementations, the two transistors may not share a middle electrode, that is, the electrodes in the middle region may be two electrodes insulated from each other.

[0331] It should be understood that Fig.16 The preparation process shown is only an example and does not constitute a limitation on the embodiments of the present application.

[0332] In the solution of Example 3, since the gate 334 is wrapped in the first dielectric layer 333 and the channel layer 331 , the gate 334 can be led out through the through-hole structure. Fig.17 FIG. 3 shows a schematic diagram of a channel group 330 and a third insulating layer 360. The schematic diagram is a perspective along the direction of the source and drain connection. Fig.17 As shown, through holes can be etched from top to bottom on the side, and the gates 334 of each layer can be connected, for example, the gates 334 of each channel group can be connected. It should be understood that Fig.17 The lead-out method of the gate 334 shown is only an example and does not constitute a limitation to the solution of the embodiment of the present application.

[0333] The present application also provides a memory array, in which the transistors can be the transistors described in the above embodiments of the present application, and the above description can be referred to. To avoid repetition, some descriptions are appropriately omitted when describing the memory array.

[0334] Fig.19 , Fig. 20 , Fig. 22 and Fig.23 A schematic diagram showing the structure of a subbank in various memory arrays provided in an embodiment of the present application is shown. Fig.19 , Fig. 20 , Fig. 22 and Fig.23 The memory array of the embodiment of the present application is described below with reference to the accompanying drawings.

[0335] The memory array includes a substrate 340 and one or more layers of memory cells disposed on the substrate 340. The multiple layers of memory cells are stacked in a direction perpendicular to a surface of the substrate 340.

[0336] Each memory cell in the one or more layers of memory cells includes a transistor. The transistor includes a source 310, a drain 320 and at least one channel group 330. The at least one channel group 330 is located between the source 310 and the drain 320 in a direction parallel to the surface of the substrate 340. The channel group 330 includes a core and a channel layer 331 surrounding the core. The channel layer 331 is in contact with the source 310 and the drain 320.

[0337] As described in the above method 1, the core includes a first insulating layer 332, and the channel group 330 further includes a first dielectric layer 333 surrounding the channel layer 331 and a gate 334, and the source 310, the drain 320 and the gate 334 are isolated from each other.

[0338] As described in the above-mentioned method 2, the core includes a gate 334 and a first dielectric layer 333 surrounding the gate 334, and the source 310, the drain 320 and the gate 334 are isolated from each other.

[0339] The memory array further includes a plurality of first signal lines, a plurality of second signal lines, and a plurality of word lines.

[0340] Exemplarily, the storage unit may adopt a 1T1C cell structure. For the convenience of description, the present application embodiment is described only by taking this as an example.

[0341] The transistor and the capacitor can be placed horizontally. Alternatively, it can be understood that a capacitor structure and a second signal line electrode are added to one side of the transistor of Example 1, Example 2 or Example 3. The first electrode 441 of the capacitor is connected to the first end of the transistor. The second end of the transistor is connected to the first signal line 420. The second electrode 443 of the capacitor is connected to the second signal line. The gate 334 of the transistor is connected to the word line 410. The first electrode 441 and the second electrode 443 of the capacitor are isolated by the second dielectric layer 442.

[0342] It should be noted that the “first electrode” and “second electrode” of the capacitor are only used to distinguish the two plates of the capacitor and have no other limiting function, that is, the two ends of the capacitor are connected to the transistor and the signal line respectively.

[0343] Exemplarily, the first end of the transistor is a source, and the second end of the transistor is a drain. Alternatively, the first end of the transistor is a drain, and the second end of the transistor is a source.

[0344] Exemplarily, the first signal line is a bit line, and the second signal line is a plate line. Alternatively, the first signal line is a plate line, and the second signal line is a bit line. For ease of description, the first signal line is a bit line, and the second signal line is a plate line.

[0345] In some implementations, the first electrode 441 of the capacitor is connected to the first end of the transistor, and the first electrode 441 of the capacitor and the first end of the transistor may share a metal layer. Fig.19 , Fig. 20 , Fig. 22 or Fig.23 As shown, the first electrode 441 of the capacitor can be regarded as the first terminal of the transistor.

[0346] In some implementations, the second end of the transistor is connected to the first signal line 420, which can be understood as the second end of the transistor and the first signal line 420 share a metal layer. Fig.19 , Fig. 20 , Fig. 22 or Fig.23 As shown, the first signal line 420 can serve as the second end of the transistor, or in other words, include the second end of the transistor.

[0347] In some implementations, the second electrode 443 of the capacitor is connected to the second signal line, which can be understood as the second electrode 443 of the capacitor and the second signal line sharing a metal layer. Fig.19 , Fig. 20 , Fig. 22 or Fig.23 As shown, the second signal line can serve as the second electrode 443 , or in other words, includes the second electrode 443 .

[0348] In some implementations, the gate 334 of the transistor is connected to the word line 410, which can be understood as the gate 334 of the transistor and the word line 410 share a metal layer. Fig.19 , Fig. 20 , Fig. 22 or Fig.23 As shown, the word line 410 may serve as the gate 334 , or include the gate 334 .

[0349] In the solution of the embodiment of the present application, the transistor is a gate transistor of the storage array, and the channel layer has a surrounding gate structure, for example, the gate surrounds the channel layer, or the channel layer surrounds the gate. This structure enables the transistor to have better gate control capability, so that the transistor has higher read and write current, lower leakage current and smaller parasitic capacitance, which is conducive to optimizing the read and write speed and power consumption performance of the storage array. At the same time, the channel layer surrounds the core, and the channel layer has a surrounding gate structure, which is conducive to improving the flexibility of the design while ensuring the gate control performance.

[0350] By way of example, the material of the channel layer 331 may be amorphous silicon, polycrystalline silicon, carbon nanotubes or two-dimensional materials.

[0351] Optionally, the material of the channel layer is an oxide semiconductor material.

[0352] OS materials have a low thermal budget, and using OS channel materials is conducive to reducing the process difficulty of preparing multi-layer storage cells and reducing the preparation cost. At the same time, OS FETs have extremely low leakage current, which is conducive to ensuring the retention time of state information in the storage array.

[0353] For example, the electrical connection parts of the transistor and the capacitor may be arranged in the following order: metal #1 - dielectric layer #1 - metal #2 - metal #3, such as Fig.19 , Fig. 20 , Fig. 22 or Fig.23 shown.

[0354] Among them, metal #2 and metal #3 can be used as the second electrode 443 of the capacitor. Metal #1 can be used as the first terminal of the transistor, or in other words, the first electrode 441 of the capacitor. Dielectric layer #1 can be used as the second dielectric layer 442 between the two electrodes of the capacitor.

[0355] Metal #2 and metal #3 are made of different metal materials. Metal #1 and metal #2 can be made of the same metal material or different metal materials. Metal #1 and metal #3 can be made of the same metal material or different metal materials.

[0356] For example, the metal material may be TiN, tantalum mononitride (TaN), TiAl, nickel platinum alloy (NiPt), W or indium tin oxide (ITO), etc.

[0357] For example, the metal material may be grown by ALD, chemical vapor deposition (CVD) or PVD.

[0358] It should be understood that the above is only an example, and the embodiments of the present application do not limit the specific type and formation method of the metal material.

[0359] The dielectric layer #1 may be made of a high-k material, that is, the dielectric layer #1 may be a high-k dielectric layer.

[0360] By way of example, dielectric layer #1 may be made of oxide materials such as HfO2, zirconium dioxide (ZrO2), Al2O3, hafnium zirconium oxide (HfZrO) or HfAlO.

[0361] Exemplarily, the dielectric layer #1 may adopt a stacked structure of different oxide materials. For example, the dielectric layer #1 may be an alternating stacked structure of zirconium oxide and aluminum oxide.

[0362] This is beneficial for making the dielectric layer #1 have a higher dielectric constant and a lower leakage current.

[0363] For example, dielectric layer #1 may be grown by ALD.

[0364] It should be understood that the above is only an example, and the embodiment of the present application does not limit the specific type and formation method of the dielectric layer #1.

[0365] For example, metal #1 may be TiN, dielectric layer #1 may be HfO2, metal #2 may be TiN, and metal #3 may be W. Then the electrical connection part of the transistor and the capacitor may adopt the following structure: TiN-HfO2-TiN-W.

[0366] Each layer of storage units is arranged along a first direction and a second direction, the first direction is parallel to the surface of the substrate, the second direction is parallel to the surface of the substrate, and the first direction is perpendicular to the second direction.

[0367] Alternatively, the above directions may also be described by xyz coordinate axes, for example, the first direction may be the y direction, the second direction may be the x direction, and the direction perpendicular to the substrate surface may be the z direction.

[0368] In a possible implementation, the channel layer contacts the source electrode, which may be that the channel layer directly contacts the source electrode. The channel layer contacts the drain electrode, which may be that the channel layer directly contacts the drain electrode.

[0369] In another possible manner, the channel layer is in contact with the source electrode through the filling layer, and the channel layer is in contact with the drain electrode through the filling layer.

[0370] Exemplarily, the filling layer is an oxide semiconductor material.

[0371] In the solution of the embodiment of the present application, a raised S / D structure can be used, which is conducive to reducing the contact resistance. At the same time, this structure is conducive to preventing H impurities in the source and / or drain from diffusing into the channel, thereby improving the stability of the device.

[0372] The structure of the memory array of the embodiment of the present application is exemplarily described below in combination with three examples (Example 4, Example 5 and Example 6). The transistors in Example 4, Example 5 and Example 6 correspond to the transistors in Example 1, Example 2 and Example 3, respectively. For specific descriptions, reference can be made to the foregoing text. To avoid repetition, some descriptions are appropriately omitted when describing Example 4, Example 5 and Example 6.

[0373] Example 4

[0374] In the solution of Example 4, the core includes a first insulating layer 332, and the channel group 330 further includes a first dielectric layer 333 surrounding the channel layer 331 and a gate 334. In other words, the channel group 330 includes the first insulating layer 332, the channel layer 331, the first dielectric layer 333 and the gate 334 in sequence from the inside to the outside.

[0375] Furthermore, if the at least one channel group 330 includes a plurality of channel groups 330 distributed in a direction perpendicular to the substrate surface, the second insulating layer 350 is not included between each two channel groups 330, for example, Figure 5 , Figure 8 or Fig.19 shown.

[0376] Optionally, the memory array includes a plurality of word lines extending in a direction perpendicular to the substrate surface, and transistors in memory cells that are on the same straight line in the direction perpendicular to the substrate surface are connected to the same word line among the plurality of word lines.

[0377] In other words, the memory array may use vertical word lines (VWL).

[0378] Gates of transistors in memory cells that are in different lines in the vertical direction may be connected to different word lines among the plurality of word lines.

[0379] The gates of the transistors in Example 1 or Example 4 may be connected in a vertical direction, for example, Figure 5 The VWL method matches the characteristic that the gates of transistors are connected in the vertical direction, which is conducive to realizing a reasonable layout of the storage array.

[0380] Fig.18 FIG. 1 is a schematic diagram showing a circuit structure of a storage array according to an embodiment of the present application. Fig.18 As shown, the word lines extend along the z direction and the bit lines extend along the y direction. The memory array may include a plurality of subbanks arranged along the x direction. In this case, each subbank is a row of memory cells perpendicular to the x direction. Fig.18 , i+1 subbanks are shown, namely, sub-storage array 1 to sub-storage array i+1. i is a positive integer. In this architecture, the word lines and bit lines BL in each subbank are arranged crosswise. As mentioned above, the word lines in this architecture are vertical word lines, and correspondingly, the bit lines can be horizontal bit lines. In a subbank, Fig.18 FIG. 4 shows m+1 word lines, namely WL0 to WLm, Fig.18 Also shown are n+1 bit lines, namely BL0 to BLn, where m is a positive integer and n is a positive integer. The WLs in different subbanks are independent of each other. The BLs in different subbanks are independent of each other. For example, the PL may extend along the z direction. Two adjacent subbanks may share the same PL, for example, Fig.18 Alternatively, two adjacent subbanks can also be connected to different board lines.

[0381] As mentioned above, the bit lines in each subbank are horizontal bit lines. Specifically, the transistors in the memory cells that are in the same straight line in the y direction are connected to the same bit line. The transistors in the memory cells that are in different straight lines in the y direction are connected to different bit lines. In this case, the word line electrodes need to be isolated between the memory cells in different layers. In other words, the second ends of the transistors in the memory cells in different layers need to be isolated.

[0382] As mentioned above, the word lines in each subbank are vertical word lines. Therefore, the WL electrodes need to be electrically connected between the memory cells at different layers. In other words, the gates of the transistors in the memory cells at different layers need to be electrically connected.

[0383] Fig.19 A schematic diagram of a subbank is shown. The schematic diagram is a view perpendicular to the direction of the connection between the source and the drain.

[0384] Fig.19The side structure of two 1T1C cells is shown in FIG. As mentioned above, cells in the same straight line in the z direction are connected to different bit lines. Fig.19 The two cells shown are connected to two bit lines respectively.

[0385] The word line 410 surrounds the channel layer 331, such as Fig.19 As mentioned above, cells in the same straight line in the z direction are connected to the same word line 410 . Fig.19 The two cells shown are connected to the same word line 410 .

[0386] like Fig.19 As shown, the projection of the capacitor structure on the yz plane and the projection of the word line on the yz plane may be alternately distributed.

[0387] like Fig.19 As shown, except for the topmost cell, the first dielectric layer 333 in the surrounding gate of other cells is in the xz cross section (i.e. Fig.19 The cross section shown in FIG. 4 is in contact with the word line on all four sides.

[0388] Optionally, the electrical connection portion between the transistor and the capacitor may adopt a raised S / D structure.

[0389] For example, an additional layer of oxide semiconductor material is deposited between the first electrode 441 of the capacitor and the channel layer 331 .

[0390] Optionally, the bit line 420 and the transistor electrical connection portion may adopt a raised S / D structure.

[0391] For example, a layer of oxide semiconductor material is additionally deposited between the bit line 420 and the channel layer 331 .

[0392] This helps reduce the contact resistance of the transistor and improve the stability of the device.

[0393] Example 5

[0394] In the solution of Example 5, the core includes a first insulating layer 332, and the channel group 330 further includes a first dielectric layer 333 surrounding the channel layer 331 and a gate 334. In other words, the channel group 330 includes the first insulating layer 332, the channel layer 331, the first dielectric layer 333 and the gate 334 in sequence from the inside to the outside.

[0395] If a transistor includes a plurality of channel groups 330 distributed in a direction perpendicular to the substrate surface, a second insulating layer 350 is disposed between every two channel groups, for example, Figure 6 , Fig.11 , Fig. 20 or Fig. 22 shown.

[0396] Optionally, the memory array includes a plurality of word lines 410 extending in a first direction. Transistors in memory cells that are in the same straight line in the first direction are connected to the same word line 410 among the plurality of word lines. A second insulating layer 350 is included between each two channel groups 330 of transistors of memory cells that are in the same straight line in a direction perpendicular to the surface of the substrate 340.

[0397] In other words, the memory array may employ horizontal word lines.

[0398] Transistors in memory cells that are in different straight lines in the first direction may be connected to different word lines among the plurality of word lines.

[0399] A second insulating layer is included between every two channel groups, which means that a second insulating layer is provided between two adjacent channel groups.

[0400] Among them, two adjacent channel groups may belong to the same transistor, for example, Figure 6 or Fig.11 shown.

[0401] Alternatively, two adjacent channel groups may also belong to different transistors, for example, Fig. 20 or Fig. 22 shown.

[0402] The gates of the transistors in Example 2 or Example 5 are isolated from each other in the vertical direction. Therefore, when a three-dimensional memory array is prepared based on the transistors, the gates of the transistors in each layer are isolated from each other. The use of horizontal word lines matches the characteristic that the gates of the transistors are isolated from each other in the vertical direction, which is conducive to realizing a reasonable layout of the memory array.

[0403] Optionally, the memory array includes a plurality of bit lines 420 extending in a direction perpendicular to the surface of the substrate 340 .

[0404] That is, the memory array may adopt a structure of horizontal word lines and vertical bit lines (VBL).

[0405] Fig.21 FIG. 2 is a schematic diagram showing a circuit structure of another storage array according to an embodiment of the present application. Fig.21 As shown, the word lines extend along the y direction and the bit lines extend along the z direction. The memory array may include a plurality of subbanks arranged along the x direction. Fig.21 , i+1 subbanks are shown, where i is a positive integer. In this architecture, the word lines and BLs in each subbank are arranged crosswise. As mentioned above, the word lines in this architecture are horizontal word lines, and correspondingly, the bit lines can be vertical bit lines. Fig.21, where m+1 word lines and n+1 bit lines are shown, m is a positive integer, and n is a positive integer. WLs in different subbanks are independent of each other. BLs in different subbanks are independent of each other. For example, PL can extend along the z direction. Two adjacent subbanks can share the same PL, for example, Fig.21 Alternatively, two adjacent subbanks can also be connected to different board lines.

[0406] As mentioned above, the bit lines in each subbank are vertical bit lines. Specifically, transistors in memory cells that are in the same straight line in the z direction are connected to the same bit line. Transistors in memory cells that are in different straight lines in the z direction are connected to different bit lines.

[0407] Fig. 20 FIG. 4 shows two subbanks sharing a BL, or it can also be understood as a subbank sharing a BL.

[0408] Cells in the same straight line in the z direction are connected to the same bit line. Fig. 20 The four cells shown are connected to the same bit line 420. That is, the transistors in the same straight line in the z direction are electrically connected through the BL.

[0409] The word line surrounds the channel layer, such as Fig. 20 As shown, transistors in the same straight line in the z direction are connected to different WLs respectively.

[0410] In Example 2, the gate 334 and the source 310 are isolated by an isolation layer, and the gate 334 and the drain 320 are isolated by an isolation layer. Fig. 20 In the illustrated solution, the word line 410 is isolated from the first electrode 441 of the capacitor by an isolation layer 380. The word line 410 is isolated from the bit line 420 by an isolation layer.

[0411] Exemplarily, the isolation layer may be made of the material of the sacrificial layer and / or the material of the second insulating layer.

[0412] like Fig. 20 As shown, in a cell, the projection of the word line 410 on the xy plane does not overlap with the projection of the capacitor on the xy plane. In a cell, the projection of the word line 410 on the yz plane overlaps with the projection of the capacitor on the yz plane.

[0413] The first dielectric layer 333 in the surround gate structure contacts the word line 410 at the side in the xz cross section, that is, the first dielectric layer 333 exists between the word line 410 and the isolation layer.

[0414] Optionally, the electrical connection portion between the transistor and the capacitor may adopt a raised S / D structure.

[0415] For example, an additional layer of oxide semiconductor material, namely, a filling layer 370, is deposited between the first electrode 441 of the capacitor and the channel layer 331. Fig. 20 shown.

[0416] Optionally, the bit line 420 and the transistor electrical connection portion may adopt a raised S / D structure.

[0417] For example, an additional layer of oxide semiconductor material, namely, a filling layer 370, is deposited between the bit line 420 and the channel layer 331. Fig. 20 shown.

[0418] This helps reduce the contact resistance of the transistor and improve the stability of the device.

[0419] like Fig. 22 As shown, a protection layer 390 is disposed between the channel layer 331 and the first insulating layer 332. This is beneficial for protecting the channel surface.

[0420] like Fig. 22 As shown, the side of the bit line 420 close to the second insulating layer 350 intrudes into the second insulating layer 350, and the portion of the bit line 420 intruding into the second insulating layer 350 contacts the channel layer 331. That is, the bit line metal line has an irregular shape.

[0421] This is beneficial to increasing the contact area between the bit line and the channel layer.

[0422] It should be understood that Fig. 22 This is merely an example. In other possible implementations, a side of the bit line 420 close to the first insulating layer 332 may invade the first insulating layer 332 , and a portion of the bit line 420 that invades the first insulating layer 332 contacts the channel layer 331 .

[0423] This is beneficial to increasing the contact area between the bit line and the channel layer.

[0424] Fig. 22 Other structures in Fig. 20 Similar, for detailed description, please refer to Fig. 20 To avoid repetition, it will not be described here.

[0425] Example 6

[0426] In the solution of Example 5, the core includes a gate 334 and a first dielectric layer 333 surrounding the gate 334. In other words, the channel group 330 includes the gate 334, the first dielectric layer 333, the channel layer 331 and the third insulating layer 360 in sequence from the inside to the outside.

[0427] If a transistor includes a plurality of channel groups 330 distributed in a direction perpendicular to the surface of the substrate 340, a third insulating layer 360 is disposed between every two channel groups 330, for example, Figure 7 , Fig.15 or Fig.23 shown.

[0428] A horizontal word line or a vertical word line structure may be used in the solution of Example 6. For ease of description, Example 6 is described by taking a horizontal word line as an example.

[0429] Optionally, the memory array includes a plurality of word lines extending along a first direction, and transistors in memory cells that are in a same straight line in the first direction are connected to a same word line among the plurality of word lines.

[0430] Gates of transistors in memory cells that are in different straight lines in the first direction may be connected to different word lines among the plurality of word lines.

[0431] The gate 334 is located inside the first dielectric layer 333 and can be led out through a through hole or the like.

[0432] Optionally, the memory array includes a plurality of bit lines extending in a direction perpendicular to a surface of the substrate.

[0433] That is, the memory array may adopt a structure of horizontal word lines and vertical bit lines, for example Fig.21 shown.

[0434] Fig.23 Two subbanks are shown in FIG.

[0435] In some implementations, the second terminal of the transistor is connected to a bit line, and the bit line is the second terminal of the transistor, for example Fig.23 As shown. The cells in the same straight line in the z direction are connected to the same bit line. Fig.23 The four cells shown are connected to the same bit line, that is, the transistors in the same straight line in the z direction are electrically connected through the BL.

[0436] It should be understood that Fig.23 The four cells sharing the bit line is only an example. In other possible implementations, the different subbanks may not share the bit line. That is, the four cells may also be connected to two bit lines respectively, the two cells on the left share one bit line, and the two cells on the right share another bit line. For example, Fig.23 The bit line 420 in the middle region of the transistor may be formed as two bit lines isolated from each other.

[0437] like Fig.23As shown, the channel layer 331 of the transistor surrounds the word line 410. Transistors in the same straight line in the z direction are connected to different WLs respectively.

[0438] In Example 3, the gate 334 and the source 310 are isolated from each other, and the gate 334 and the drain 320 are isolated from each other. Accordingly, in the solution of Example 6, the word line 410 and the first electrode 441 of the capacitor are isolated from each other. The word line 410 and the bit line 420 are isolated from each other. For example, Fig.23 As shown, the word line 410 is isolated from the first electrode 441 of the capacitor by the channel layer 331 and the first dielectric layer 333. Fig.23 As shown, the word line 410 and the bit line 420 are isolated from each other by an isolation layer 380 .

[0439] It should be understood that the above is only an example, and the embodiments of the present application do not limit the specific method of isolation.

[0440] Optionally, the electrical connection portion between the transistor and the capacitor may adopt a raised S / D structure.

[0441] For example, an additional layer of oxide semiconductor material, namely, a filling layer 370, is deposited between the first electrode 441 of the capacitor and the channel layer 331. Fig.23 shown.

[0442] Optionally, the bit line and the transistor electrical connection portion may adopt a raised S / D structure.

[0443] For example, an additional layer of oxide semiconductor material, namely, a filling layer 370, is deposited between the bit line 410 and the channel layer 331. Fig.23 shown.

[0444] This helps reduce the contact resistance of the transistor and improve the stability of the device.

[0445] The second conductive layer 220 can be used as a gate of the transistor to control the switching of the channel, or in other words, to control the on and off of the transistor.

[0446] It should be noted that the storage array in the embodiment of the present application is only an example. In the specific implementation process, those skilled in the art should understand that the storage array in the embodiment of the present application may also include other devices necessary for normal operation. At the same time, according to specific needs, those skilled in the art should understand that the storage array in the embodiment of the present application may also include hardware devices for realizing other additional functions.

[0447] The embodiment of the present application also provides a complementary transistor, which includes a first transistor and a second transistor stacked in a vertical direction. The first transistor is located above the second transistor, the channel layer of the first transistor is an electron-type channel, and the channel layer of the second transistor is a hole-type channel. The first transistor includes a source, a drain and at least one channel group. At least one channel group is located between the source and the drain in the horizontal direction. The channel group includes a core and a channel layer surrounding the core. The channel layer is in contact with the source and the drain. The material of the channel layer is an oxide semiconductor material.

[0448] Optionally, as described in the above method 1, the core includes a first insulating layer, and the channel group further includes a first dielectric layer surrounding the channel layer and a gate, and the source, drain and gate are isolated from each other.

[0449] Optionally, as described in the above method 2, the core includes a gate and a first dielectric layer surrounding the gate, and the source, drain and gate are isolated from each other.

[0450] The first transistor may be the transistor described above in the embodiment of the present application. For specific description, please refer to the above text and will not be repeated here.

[0451] The electron channel is also called an N channel, and the hole channel is also called a P channel.

[0452] Exemplarily, the material of the channel layer of the second transistor may be Si, that is, the second transistor may be SiPMOS.

[0453] Since the thermal budget of OS materials is low, this helps avoid deteriorating the performance of the lower transistor when preparing the top OS GAA FET. In addition, in the solution of the embodiment of the present application, the surrounding gate structure of the first transistor can effectively make up for the problem that the OS channel mobility is lower than the Si channel mobility. If the second transistor is a Si transistor, that is, when forming a complementary transistor together with the Si transistor, it is beneficial to achieve performance balance of the two transistors, thereby ensuring the overall power consumption and processing speed of the complementary transistor.

[0454] The embodiment of the present application also provides a memory, comprising the memory array and the memory controller as described above, wherein the memory controller and the memory array are electrically connected. For example, the memory array can be any memory array in the embodiment of the present application.

[0455] An embodiment of the present application also provides an electronic device, including the memory and circuit board mentioned above, wherein the memory is arranged on the circuit board and is electrically connected to the circuit board.

[0456] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0457] In this application, "at least one" means one or more, and "more" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0458] Prefixes such as "first" and "second" are used in the embodiments of the present application only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects.

[0459] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0460] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0461] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0462] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0463] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0464] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0465] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A transistor, characterized in that: include: A source, a drain and at least one channel group, wherein the at least one channel group is located between the source and the drain in the horizontal direction, the channel group includes a core and a channel layer surrounding the core, and the channel layer is in contact with the source and the drain, wherein: The core includes a first insulating layer, and the channel group further includes a first dielectric layer surrounding the channel layer and a gate, and the source, the drain and the gate are isolated from each other; or, The core includes a gate and a first dielectric layer surrounding the gate, and the source, the drain and the gate are isolated from each other.

2. The transistor according to claim 1, characterized in that The material of the channel layer is an oxide semiconductor material.

3. The transistor according to claim 1 or 2, characterized in that: In a case where the core includes a first insulating layer, the at least one channel group includes a plurality of channel groups distributed along a vertical direction.

4. The transistor according to claim 3, characterized in that A second insulating layer is included between every two channel groups in the plurality of channel groups.

5. The transistor according to any one of claims 1 to 3, characterized in that A portion of the source electrode near the first insulating layer intrudes into the first insulating layer, and a portion of the source electrode intruding into the first insulating layer contacts the channel layer, or, A portion of the drain electrode on one side close to the first insulating layer intrudes into the first insulating layer, and a portion of the drain electrode intruding into the first insulating layer contacts the channel layer.

6. The transistor according to claim 1 or 2, characterized in that: In the case where the core includes a gate and a first dielectric layer surrounding the gate, the at least one channel group includes a plurality of channel groups distributed along a vertical direction, and a third insulating layer is included between every two channel groups in the plurality of channel groups.

7. The transistor according to any one of claims 2 to 6, characterized in that The transistor further includes a filling layer, the channel layer is in contact with the source electrode through the filling layer, or the channel layer is in contact with the drain electrode through the filling layer, and the material of the filling layer is an oxide semiconductor material.

8. A storage array, characterized in that: include: A substrate and one or more layers of memory cells arranged on the substrate, the multi-layer memory cells are stacked in a direction perpendicular to the surface of the substrate, each memory cell in the one or more layers of memory cells comprises a transistor, the transistor comprises: a source, a drain and at least one channel group, the at least one channel group is located between the source and the drain in a direction parallel to the surface of the substrate, the channel group comprises a core and a channel layer surrounding the core, the channel layer is in contact with the source and the drain, wherein, The core includes a first insulating layer, and the channel group further includes a first dielectric layer surrounding the channel layer and a gate, and the source, the drain and the gate are isolated from each other; or, The core includes a gate and a first dielectric layer surrounding the gate, and the source, the drain and the gate are isolated from each other.

9. The storage array according to claim 8, characterized in that: The material of the channel layer is an oxide semiconductor material.

10. The storage array according to claim 8 or 9, characterized in that: In the case where the core includes a first insulating layer, the memory array further includes a plurality of word lines extending in a direction perpendicular to the surface of the substrate, and transistors in memory cells in the multi-layer memory cells that are on the same straight line in a direction perpendicular to the surface of the substrate are connected to the same word line among the plurality of word lines.

11. The storage array according to claim 8 or 9, characterized in that: Each layer of the one or more layers of memory cells is arranged along a first direction and a second direction, the first direction is parallel to the surface of the substrate, the second direction is parallel to the surface of the substrate, and the first direction is perpendicular to the second direction. When the core includes a first insulating layer, the memory array also includes a plurality of word lines extending along the first direction, transistors in the memory cells that are in the same straight line in the first direction are connected to the same word line among the plurality of word lines, and a second insulating layer is included between each two channel groups of the transistors of the memory cells that are in the same straight line in a direction perpendicular to the surface of the substrate.

12. The storage array according to claim 11, characterized in that: Each of the memory cells further includes a capacitor, and the capacitor is connected to a first end of the transistor. The memory array further includes a plurality of first signal lines. The second end of the transistor in each of the memory cells is connected to one of the plurality of first signal lines. The first end is the source, and the second end is the drain. Alternatively, the first end is the drain, and the second end is the source. A portion of the second end of the transistor on a side close to the second insulating layer intrudes into the second insulating layer, and a portion of the second end intruding into the second insulating layer contacts the channel layer. Alternatively, A portion of a second end of the transistor on a side close to the first insulating layer intrudes into the first insulating layer, and a portion of the second end intruding into the first insulating layer contacts the channel layer.

13. The storage array according to any one of claims 9 to 12, characterized in that: The transistor further includes a filling layer, the channel layer is in contact with the source electrode through the filling layer, or the channel layer is in contact with the drain electrode through the filling layer, and the material of the filling layer is an oxide semiconductor material.

14. A complementary transistor, characterized in that: The invention comprises a first transistor and a second transistor stacked in a vertical direction, wherein the first transistor is located above the second transistor, a channel layer of the first transistor is an electron channel, and a channel layer of the second transistor is a hole channel, the first transistor comprises a source, a drain and at least one channel group, wherein the at least one channel group is located between the source and the drain in a horizontal direction, the channel group comprises a core and a channel layer surrounding the core, the channel layer is in contact with the source and the drain, and a material of the channel layer is an oxide semiconductor material, wherein: The core includes a first insulating layer, and the channel group further includes a first dielectric layer surrounding the channel layer and a gate, and the source, the drain and the gate are isolated from each other; or, The core includes a gate and a first dielectric layer surrounding the gate, and the source, the drain and the gate are isolated from each other.

15. A memory, characterized in that: It comprises a storage array and a storage controller as described in any one of claims 8 to 13, wherein the storage controller and the storage array are electrically connected.

16. An electronic device, characterized in that: It comprises the memory and a circuit board as claimed in claim 15, wherein the memory is arranged on the circuit board and is electrically connected to the circuit board.

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