High voltage bidirectional switching device with improved electrical characteristics

Abstract

The invention relates to a high voltage bidirectional switching device with improved electrical characteristics. Described is a switching device formed of a first switching MOS transistor having a drain terminal connected to a first switching terminal, a source terminal connected to an internal source node, and a gate terminal connected to an internal gate node, a second switching MOS transistor, and a voltage limiting element; a second switching MOS transistor having a drain terminal connected to the second switching terminal, a source terminal connected to the internal source node, and a gate terminal connected to the internal gate node; and a voltage limiting element connected between the internal gate node and the internal source node. The driving stage voltage references the internal source node and drives switching of the bidirectional switch according to the first driving signal and the second driving signal, and has a driving transistor and a switching transistor connected to each other in an inverter configuration.

Description

Technical Field

[0001] The solution relates to a high voltage bidirectional switch device with improved electrical characteristics. Background Art

[0002] In some applications, it is beneficial to use a bidirectional high voltage switching device that can allow current to be transferred bidirectionally between a first high voltage terminal and a second high voltage terminal.

[0003] For example, high voltage switching devices are often used in charge recovery resonant drives.

[0004] These drivers base charge recovery on appropriate sharing between a first load capacitive element and a second load capacitive element (which may correspond to a capacitive actuator, such as a capacitive micromirror) by using a certain number of energy storage and storage capacitors.

[0005] In particular, charge sharing between capacitive elements is achieved according to a specific charge recovery algorithm through a bidirectional switching device connected between the same capacitive element and the storage capacitor, which is appropriately driven by a driving signal with a high voltage (in the order of tens of V) and an average frequency (up to tens of kHz).

[0006] These switching devices are used to manage (bidirectional) high voltages on two terminals. In particular, in order to exploit the charge recovery properties, the switching devices not only have a low on-state resistance, but also fast turn-on and turn-off times. In addition, the energy consumption for driving the switch and the area for forming the corresponding driver generally need to be minimized.

[0007] Figure 1 A known circuit embodiment of a high voltage bidirectional switch device is shown, generally indicated at 1.

[0008] The switching device 1 defines a bidirectional switch formed by a first switching element 2, in particular a high voltage MOS transistor M1, having a drain terminal connected to a first switch terminal A (e.g. designed to be connected to a first charge redistribution capacitive element), a source terminal connected to an internal node S and a gate terminal connected to an internal node G. The body terminal of the MOS transistor M1 is also connected to the source terminal so that a parasitic diode (e.g. Figure 1 as shown) to avoid improper conduction during operation (in some cases, the connection between the body terminal and the source terminal is inherent).

[0009] The bidirectional switch is also formed by a second switching element 4, in particular a high voltage MOS transistor M2, which has a drain terminal connected to the second switch terminal T (e.g. designed to be connected to the second charge redistribution capacitive element), a source terminal connected to the internal node S and a gate terminal connected to the internal node G. Figure 1 As shown, MOS transistor M2 also has a body terminal connected to the source terminal, as previously described.

[0010] The above-mentioned high voltage MOS transistors M1, M2 can withstand a high voltage (for example, having a value of the order of 40-60V) applied between the corresponding drain terminal and the source terminal and between the corresponding gate terminal and the drain terminal.

[0011] The switching device 1 also includes a voltage limiting element 5 connected between the internal nodes G and S, in particular formed by a Zener diode, which has an anode connected to the above-mentioned internal node S and a cathode connected to the above-mentioned external node G, and has the function of limiting the voltage between the same internal nodes G and S to a maximum value, for example equal to 5.5V (which can be borne by the above-mentioned MOS transistors M1, M2 between the gate terminal and the source terminal).

[0012] The switching device 1 also includes: a first current generator 6, which is configured to generate a first current I1, connected between a power terminal having a high power supply voltage VHV (for example, in the order of 40-60V) and an internal node G, with a first switch 7 inserted in between; a second current generator 8, which is configured to generate a second current I2, connected between an internal node S and a ground reference (GND), with a second switch 9 inserted in between; and a third switch 10 inserted between the above-mentioned internal node G and the ground reference GND.

[0013] Operation of the switching device 1 envisages that the first current I1 and the second current I2 are provided by closing the first switch 7 and the second switch 9, making the same switching device 1 conductive, wherein the above-mentioned voltage limiting element 5 defines and limits the voltage V between the gate and the source of the MOS transistors M1 and M2 GS ; Therefore, current transfer occurs between the first switch terminal A and the second switch terminal T (possibly in both directions).

[0014] By opening the first switch 7 and the second switch 9 and by connecting the internal node G (and therefore the gate terminals of the MOS transistors M1 and M2) to the ground reference GND by closing the third switch 10, the switching device 1 is turned off, thereby removing the first flow I1 and the second flow I2 (in a manner not shown here, the possibility of connecting the internal node S and therefore the source terminals of the same MOS transistors M1, M2 to the ground reference GND can also be envisaged); thus, the current transmission between the first switch terminal A and the second switch terminal T is interrupted.

[0015] However, such a switching device 1 has some disadvantages.

[0016] First, when the switching device 1 is turned off, the parasitic capacitances at the internal nodes G and S are fully discharged to the ground reference, causing the same capacitances to be recharged (with an associated increase in current consumption) each time it is turned on.

[0017] Furthermore, the on-currents (the above-mentioned first current I1 and second current I2 ) have high values ​​to ensure sufficiently fast charging time; therefore, circuits designed for their generation are usually complex, costly to manufacture, and require high area occupation in integrated manufacturing.

[0018] Furthermore, these on-currents are applied for a priori unknown lengths of time and vary according to variations in parameters such as process, voltage to be controlled and temperature; therefore the values ​​of these currents are usually too large to avoid operational problems.

[0019] The above problem is exacerbated by the fact that the on-resistance value of the switching devices (as mentioned above) is as low as possible in order to maximize efficiency (e.g., the associated charge recovery driver). This can be achieved by increasing their size and (especially in the high voltage domain) this requires a significant increase in parasitic capacitance.

[0020] Therefore, some solutions are proposed, aiming to at least partially overcome the problems of the switching device 1 described above.

[0021] For example, it has been proposed that, at turn-on, the application of the on-current is limited only to a short time interval (initial pre-charge) followed by a lower holding current. Furthermore, in addition to the above-mentioned MOS transistors M1 and M2, it has been proposed to use auxiliary switching elements, i.e. transistor switching elements, which can also operate during the initial pre-charge phase.

[0022] However, despite being able to reduce turn-on time, these solutions often come with greater complexity and higher power consumption, and in any case fail to address some of the issues highlighted previously. Summary of the invention

[0023] Embodiments of the present disclosure at least partially overcome the problems previously highlighted.

[0024] In one embodiment, a switching device includes a bidirectional switch. The bidirectional switch includes a first switch MOS transistor having a drain terminal connected to a first switch terminal, a source terminal connected to an internal source node, and a gate terminal connected to an internal gate node. The bidirectional switch includes a second switch MOS transistor having a drain terminal connected to a second switch terminal, a source terminal connected to an internal source node, and a gate terminal connected to an internal gate node. The bidirectional switch includes a voltage limiting element connected between the internal gate node and the internal source node. The switching device includes a driver stage, which is voltage-referenced to an internal source node and is configured to drive the switching of the bidirectional switch according to a first drive signal and a second drive signal, and the driver stage includes a drive transistor and a switch transistor connected to each other. The drive transistor is connected to a power supply terminal and driven by a first drive signal to charge the internal gate node and turn on the bidirectional switch in the on-interval of the switching device. The switch transistor is driven by a second drive signal to short-circuit the internal gate node and the internal source node in the off-interval of the switching device and turn off the bidirectional switch.

[0025] In one embodiment, a charge recovery resonant driver includes a first capacitive actuator and a second capacitive actuator, the first capacitive actuator is coupled to a first charge exchange terminal, the first charge exchange terminal can be selectively connected alternately to a power supply terminal with a high voltage and a ground reference terminal, and the second capacitive actuator is coupled to a second charge exchange terminal, the second charge exchange terminal can be selectively connected alternately to the power supply terminal and the ground reference terminal. The charge recovery resonant driver includes a plurality of energy storage capacitors, each energy storage capacitor is coupled to a corresponding device pair, and can be selectively connected to the first charge exchange device through a first switching device in the device pair, and can be selectively connected to the second charge exchange terminal through a second switching device in the device pair. Each switching device includes a bidirectional switch, the bidirectional switch has a first switching MOS transistor and a second switching MOS transistor, the first switching MOS transistor has a drain terminal connected to the first switching terminal, a source terminal connected to an internal source node, and a gate terminal connected to an internal gate node, and the second switching MOS transistor has a drain terminal connected to the second switching terminal, a source terminal connected to the internal source node, and a gate terminal connected to the internal gate node. The bidirectional switch includes a voltage limiting element connected between the internal gate node and the internal source node. Each switching device includes a driver stage voltage-referenced to an internal source node and configured to drive switching of the bidirectional switch according to a first drive signal and a second drive signal, the driver stage including a drive transistor and a switch transistor connected to each other.

[0026] In one embodiment, a method includes driving a bidirectional switch of a switching device with a driver stage based on a first drive signal and a second drive signal. The driver stage includes a driving transistor and a switching transistor connected to each other. The bidirectional switch includes a first switching MOS transistor and a second switching MOS transistor coupled together at an internal source node between a first switch terminal and a second switch terminal. The bidirectional switch includes an internal gate, which is coupled to an internal source, coupled to a gate terminal of the first switching MOS transistor, and coupled to an output of the driver stage through a voltage limiting device. The method includes providing a power supply voltage to a drain terminal of the driving transistor, charging the internal gate node and turning on the bidirectional switch in a conduction interval of the switching device by driving the driving transistor with a first drive signal, and short-circuiting the internal gate node and the internal source node and turning off the bidirectional switch in a turn-off interval of the switching device by driving the switching transistor with a second drive signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] For a better understanding of the invention, preferred embodiments thereof will now be described, by way of non-limiting example only, and with reference to the accompanying drawings, in which:

[0028] Figure 1 A circuit diagram showing a high voltage bidirectional switching device of a known type;

[0029] Figure 2 A circuit diagram of a high voltage bidirectional switch device according to an embodiment of the present solution is shown;

[0030] Figure 3 Shows Figure 2 A more detailed circuit diagram of a bidirectional switching device;

[0031] Figure 4A Shows Figure 3 A bidirectional switching device, with particular reference to the conduction phase;

[0032] Figure 4B shows a timing diagram for conducting and shutting off current in a switching device, with particular reference to the above-mentioned conduction phase;

[0033] Figure 5A Shows Figure 3 Bidirectional switching device, with particular reference to the turn-off phase;

[0034] Figure 5B shows a timing diagram for the conduction and shutdown of current in a switching device, with particular reference to the shutdown phase described above;

[0035] Figure 6 shows a schematic circuit diagram of a charge recovery resonant driver according to another aspect of the present solution, wherein a switching device may be used;

[0036] Figure 7 Shown with Figure 6 Voltage diagrams associated with the operation of the driver;

[0037] Figure 8 It is shown that compared with solutions of known type, Figure 6 The trend of the current consumption in the driver as a function of frequency; and

[0038] Figure 9-10 Corresponding circuit diagrams of bidirectional switch devices according to different embodiments of the present solution are shown. DETAILED DESCRIPTION

[0039] Figure 2 A high voltage bidirectional switch device, generally indicated at 20, is shown in accordance with the present solution.

[0040] The switch device 20 includes a bidirectional switch 21, which is connected to a reference Figure 1 The basically similar approach discussed is formed as follows:

[0041] a first switching element 22, in particular a high voltage MOS transistor M1, having a drain terminal connected to a first switching terminal A (e.g. designed to be connected to a first capacitive element, e.g. to a capacitive actuator), a source terminal connected to an internal node S and a gate terminal connected to an internal node G;

[0042] a second switching element 24, in particular a high voltage MOS transistor M2, having a drain terminal connected to a second switching terminal T (e.g. designed to be connected to a second capacitive element, in particular to a storage capacitor), a source terminal connected to an internal node S and a gate terminal connected to an internal node G; and

[0043] The voltage limiting element 25, connected between the internal nodes G and S, is particularly formed by a Zener diode, has an anode connected to the above-mentioned internal node S and a cathode connected to the above-mentioned external node G, and has the function of limiting the voltage between the same internal nodes G and S to a maximum tolerable value (for example, equal to 5.5V).

[0044] The high voltage MOS transistors M1 and M2 are capable of withstanding a high voltage (e.g., of the order of 40-60 V) applied between the corresponding drain and source terminals and between the corresponding gate and drain terminals; the voltage between the gate and source terminals is limited to a maximum value clamped by the voltage limiting element 25.

[0045] According to one aspect of the present solution, the switching device 20 further comprises a control and driver stage, generally indicated by 200 , which is voltage-referenced to an internal node S (with respect to a ground reference GND) and is configured to control and drive the switching of the bidirectional switch 21 .

[0046] The control and drive stage 200 includes a driver stage 26, which is referenced to an internal node S and is configured to receive at input a first drive signal drv_on and a second drive signal drv_off, the two voltage signals having logically opposite values, i.e., if drv_on is logically high, drv_off is logically low, and vice versa, and to implement switching of the bidirectional switch 21 according to these first drive signal drv_on and the second drive signal drv_off.

[0047] In detail, the driver stage 26 includes a driver transistor M ON and the switching transistor M OFF , both of which are NMOS type, driven by the above-mentioned first drive signal drv_on and second drive signal drv_off, and connected to each other in an inverter configuration.

[0048] In particular, the driving transistor M ON having a drain terminal connected to a power supply terminal having a high power supply voltage VHV (e.g., in the order of 40-60 V), a gate terminal receiving a first drive signal drv_on, and a source terminal connected to the above-mentioned internal node G (in addition, the source terminal is connected to a corresponding body terminal for correctly biasing the junction in each operating state).

[0049] Switching transistor M OFF It has a drain terminal connected to the internal node G, a gate terminal receiving the second drive signal drv_off, and a source terminal connected to the internal node S (the source terminal is also connected to the corresponding body terminal).

[0050] In more detail, the driving transistor M ON is in a source follower configuration and is driven by a first drive signal drv_on so as to charge the internal node G (and therefore the gate terminals of MOS transistors M1 and M2) in a fast and efficient manner, thereby turning on the bidirectional switch 21 (to allow current or charge transfer in both directions between the corresponding terminals A and T); this configuration is also advantageously self-limiting in current.

[0051] Switching transistor M OFFDriven by the second drive signal drv_off to short-circuit the internal nodes G and S (and therefore the gate terminals and source terminals of the MOS transistors M1 and M2) when driven in the on state, thereby turning off the bidirectional switch 21 (it should be noted that, unlike known solutions, in this case, during operation of the switching device 20, in particular in order to turn off the bidirectional switch 21, the gate terminals and / or source terminals of the same MOS transistors M1, M2 are not connected to the ground reference GND).

[0052] The control and drive stage 200 of the switching device 20 further comprises a load stage 30 which is also referenced to the internal node S and has an input terminal N1 which is selectively connectable via a first switch 32 to a load configured to generate a conduction current I ON The on-state current generator 34 is connected to the power supply terminal (and the high voltage VHV).

[0053] The load stage 30 is configured to conduct current I ON The first drive signal drv_on is generated as a voltage signal to cause the drive transistor M of the driver stage 26 to turn on. ON conduction.

[0054] The control and drive stage 200 of the switching device 20 also includes a switching logic stage 40, which is also referenced to the internal node S and has a corresponding input terminal N2, which can be selectively connected to a second switch 42 configured to generate an off current I OFF The shutdown current generator 44 is connected to the power supply terminal (and the high voltage VHV).

[0055] The switch logic stage 40 is configured to be based on the shutdown current I OFF The second drive signal drv_off is generated as a voltage signal by combining the value of the first drive signal drv_on to cause the switch transistor M of the driver stage 26 to OFF conduction.

[0056] As will also be discussed in detail below, the switch transistor M is allowed to OFF The second driving signal drv_off (when logic high) is turned on by turning off the current I OFF and generated by the first driving signal drv_on switching to a low logic value, which in turn conducts the current I ON Therefore, it is determined that the conducting transistor M ON and the switching transistor M OFF The on and off drive signals drv_on and drv_off are determined by the on current I ON and the shutdown current I OFFcontrol (which in turn is determined by the logically alternative activation of the corresponding switches 32, 42). Basically, when it is desired to turn on transistor M ON When the conduction current I ON is activated, and the shutdown current I OFF is disabled; therefore, the first drive signal drv_on becomes a high logic state and the second drive signal drv_off becomes a low logic state. Conversely, when it is desired to turn on the off transistor M OFF When the shutdown current I OFF is activated and conducts current I ON is disabled; therefore, the second drive signal drv_off becomes a high logic state and the first drive signal drv_on becomes a low logic state.

[0057] As mentioned above Figure 2 As shown, the control and driving stage 200 may further include an additional shutdown current generator 46, which is configured to generate a shutdown current I OFF and can be connected between the internal node S (via the third switch 47) and the ground reference GND. As will be discussed further below, the additional shutdown current generator 46 (if present) is configured to compensate for the shutdown current I used by the above-mentioned switching logic stage 40. OFF .

[0058] During operation, the driver stage 26 behaves like an N-type inverter which is referenced to an internal node S and thus operates in a floating manner with respect to the ground reference GND.

[0059] The conduction current I ON The small value (because this current only needs to turn on the transistor M ON and the parasitic capacitance of the load), which determines the generation of a suitable value of the first drive signal drv_on by the load stage 30, thereby causing the drive transistor M of the driver stage 26 to ON conduction.

[0060] The switch-off is obtained by short-circuiting the source and gate terminals of the MOS transistors M1 and M2, instead of (as in known solutions) bringing the same terminals to the ground reference GND. In the switch-off state, both the first switching element 22 and the second switching element 24 remain in a completely floating state, thereby following the dynamic characteristics of the capacitive elements connected to the switch terminals A and T. Basically, the parasitic capacitances are therefore not completely discharged towards ground, but at most a limited discharge, which corresponds to the voltage between gate and source (V GS )loss.

[0061] It should be noted that, in a manner not described in detail (but which is clear to a person skilled in the art), the above-mentioned switching device 20 is configured to receive suitable control signals from the outside (for example, from a control unit of an electronic device in which the same switching device 20 is used), in particular for driving the first switch 32, the second switch 42 and the third switch 47, for the timing of the above-mentioned turn-on and turn-off phases of the switching device 20 (as described above).

[0062] Reference now Figure 3 , a first embodiment of the control and drive stage 200 of the switching device 20 will now be described in more detail, in particular with respect to the above-mentioned load stage 30 and the above-mentioned switching logic stage 40.

[0063] In the illustrated embodiment, the load stage 30 comprises a low voltage NMOS type load transistor 50 and a load Zener diode 52 connected in series with the load transistor 50, the load Zener diode having an anode terminal connected to an internal node S and a cathode terminal connected to the source terminal of the above-mentioned load transistor 50. The load transistor 50 also has a gate terminal connected to a corresponding drain terminal (thus being diode-connected) and also connected to the input terminal N1 of the load stage 30, i.e., to the driver transistor M of the driver stage 26. ON A gate terminal of the load transistor 50 is provided at which a first drive signal drv_on is generated (the load transistor 50 also has a source terminal connected to the body terminal).

[0064] The switch logic stage 40 comprises a MOS latch 54 having input terminals N1, N2 as input / output terminals and referenced to an internal node S. The switch logic stage 40 is formed by a first latch transistor 55 and a second latch transistor 56 in a cross configuration, wherein:

[0065] a first latch transistor 55 of low voltage nMOS type having a drain terminal connected to an input terminal N1 of the load stage 30 (with a first drive signal drv_on), a source terminal connected to an internal node S, and a gate terminal connected to an input terminal N2 of the switch logic stage 40 (and a drain terminal of the second latch transistor 56); and

[0066] The second latch transistor 56 of low voltage nMOS type has a drain terminal connected to the input terminal N2 of the switch logic stage 40, a source terminal connected to the internal node S, and a gate terminal connected to the input terminal N1 of the load stage 30 (and the drain terminal of the first latch transistor 55).

[0067] The source terminals of the latch transistors 55 and 56 are also connected to the corresponding body terminals.

[0068] The switching logic stage 40 also includes a Zener diode 58 having an anode connected to the internal node S and a cathode connected to the input terminal N2 (and the gate terminal of the first latch transistor 55 and the drain terminal of the second latch transistor 56 ).

[0069] As emphasized below, the MOS latch 54 (referenced to the internal node S) allows for accelerated switching from the on state to the off state (and vice versa) and maintains the above-described on and off states of the bidirectional switch 21 with minimum current demand.

[0070] During operation, also refer to Figure 4A (which highlights the portion of the switching device 20 that is referenced to the on-state) and Figure 4B The timing diagram of the conduction current I at the first pre-charge value ON The pulse determines the generation of the drive signal drv_on by the load stage 30, which is used to turn on the drive transistor M of the drive stage 26. ON (and turns on the bidirectional switch 21).

[0071] Specifically, in the described embodiment, the value of the driving signal drv_on referenced to the internal node S is determined by the voltage V across the load Zener diode 52. ZD and the gate-source voltage V of the load transistor 50 (diode-connected) GS The sum of (50) gives:

[0072] V(drv_on)=V ZD +V GS (50)

[0073] Assuming the same drive transistor M ON Matching with the load transistor 50, the driving transistor M of the driving stage 26 ON Basically equal to V ZD The gate-source voltage V GS (M ON ) is turned on (it should be noted that to optimize this matching, load transistor 50 can be implemented as a high voltage transistor, where the penalty in terms of power and area consumption is minimized).

[0074] The second latch transistor 56 is also turned on, so that the second drive signal drv_off reaches the value of the internal node S, and thus turns off the switch transistor M. OFF (and the first latch transistor 55).

[0075] Advantageously, the turn-on time of the bidirectional switch 21 is very fast, in particular due to the drive transistor M ON The source follower configuration and the small charge required to charge the parasitic capacitance. ONDepends on the same drive transistor M ON The size of the on-state current I ON The current is “recirculated” across the capacitive elements (eg, load and storage elements) connected to the first switch terminal A and the second switch terminal T of the bidirectional switch 21 (in any case, for a finite time determined by the pre-charge pulse).

[0076] Subsequently, using the positive feedback provided by the MOS latch 54, the on state can be caused by the on current I ON The second value is maintained, and the second value is a holding value, which is lower than the first pre-charge value (such as the above Figure 4B This holding current is sufficient to enhance the positive feedback provided by the MOS latch 54 to compensate for parasitic effects (coupling, ground and reference shifts) that may result in improper switching of the same latch.

[0077] Reference now Figure 5A (which highlights the portion of the switching device 20 referenced to the off state) and Figure 5B The timing diagram of the bidirectional switch 21 is shown in FIG. 1 . The turn-off phase of the bidirectional switch 21 assumes that the conduction current I ON (which becomes zero value) and provides a shutdown current I OFF , which has a corresponding pulse of a first pre-charge value (followed by a holding value lower than the above-mentioned first value, which is maintained for the entire duration of the switch-off phase).

[0078] In providing the above shutdown current I OFF After that, the second driving signal drv_off increases to a value V relative to the internal node S. ZL , which is equal to the voltage across Zener diode 58.

[0079] Therefore, the switching transistor M OFF The voltage V between the gate terminal and the source terminal is turned on. GS (M OFF ) is equal to the same value V ZL In addition, the first latch transistor 55 is turned on to make the first drive signal drv_on reach the value of the internal node S and thereby turn off the drive transistor M. ON .

[0080] Generally, assuming that the off state has a longer duration than the on state, it is also conceivable that a current equal to the off current I OFF The matched current is used to compensate for the current used to maintain the state of the MOS latch 54 without affecting the voltage values ​​at the first switch terminal A and the second switch terminal T of the bidirectional switch 21.

[0081] refer to Figure 6 A possible application of the switching device 20 described above in a charge recovery resonant driver (generally indicated at 60) will now be described.

[0082] The resonant driver 60 operates to generate a first capacitive actuator C OUT(1) With the second capacitive actuator C OUT(2) The first capacitive actuator is coupled to a first charge exchange terminal A1, and the first charge exchange terminal can be selectively and alternately connected to a power supply terminal with a high voltage VHV and a ground reference terminal GND. The second capacitive actuator is coupled to a second charge exchange terminal A2, and the second charge exchange terminal can also be selectively and alternately connected to a power supply terminal with a high voltage VHV and a ground reference terminal GND.

[0083] The resonant driver 60 includes a C TANK (1)……C TANK (N) represents a plurality of (N) energy storage capacitors, which can be respectively connected through the first switching device 20a and the second switching device 20b (at the corresponding internal node C 1 ……C N are coupled to each other, having respective energy storage capacitors C connected thereto TANK (1)……C TANK (N)) is selectively connected to the first charge exchange terminal A1 or the second charge exchange terminal A2.

[0084] In particular, each of the above-mentioned first switching device 20 a and second switching device 20 b may advantageously be formed as previously described in detail with respect to the switching device 20 .

[0085] Advantageously, the floating state of the first switching element 22 and the second switching element 24 of each switching device 20 in the off state causes the gate terminal and the source terminal of the corresponding MOS transistors M1 and M2 to follow the trend of the switching terminals A and T, so as to maintain a bias state always close to the (next) turn-on. In terms of charge, this means that the parasitic capacitance of the switch "participates" in the charge redistribution (significantly reducing the lost charge). Therefore, the advantage of the proposed solution is twofold: by continuing to charge and discharge the parasitic capacitance, no charge is lost, and before turning on, the switch is brought close to the bias state that it would have during the same turn-on period, thereby minimizing the turn-on time.

[0086] By appropriately driving the first switching device 20a and the second switching device 20b, the charge present at the first charge exchange terminal A can be obtained in a manner known per se (not described in detail here). 1 and the second charge exchange terminal A 2 The voltage V(A1 )、V(A 2 ) a step increase or corresponding decrease, such as Figure 7 shown.

[0087] In particular, it has been demonstrated that the power consumption associated with the resonant drive 60 is reduced by a theoretical factor N (equal to ), where N is consistent with the number of intermediate levels generated on the rising and falling edges (the same number N is consistent with the number of energy storage capacitors mentioned above).

[0088] However, this factor N is usually reduced by the power consumption used to drive the switching devices 20a, 20b.

[0089] On the contrary, thanks to the use of the solution previously described in detail for providing the above-mentioned switching devices 20a, 20b, the Applicant has demonstrated the possibility of essentially achieving the above-mentioned ideal value of the factor N due to the possibility of minimizing the charge losses associated with the conduction of the switching devices and the possibility of accelerating the conduction and shutdown of the same switching devices.

[0090] in this regard, Figure 8 The trend of the current consumption associated with the resonant driver 60 is shown, for example, as a function of the frequency f (assuming that the high voltage VHV is equal to 32 V and the capacitance of the first capacitive actuator and the second capacitive actuator (here represented by C LOAD ) is equal to 2nF, and the number of energy storage capacitors N is equal to 8).

[0091] In particular, the ideal current consumption (equal to ) is indicated by a dotted line; by a solution of known type (in which conventional switching devices are used, such as Figure 1 The current consumption obtainable using the switching device 20 according to the present solution is represented by a solid line.

[0092] It is therefore clear that the solution described for the switching device 20 above allows achieving a current consumption substantially equal to the ideal consumption.

[0093] The advantages of the proposed solution can be clearly seen from the foregoing description.

[0094] In any case, it is emphasized that the solution described for the switching device 20 allows obtaining a fast turn-on time, in particular due to the fact that the parasitic capacitances are not fully discharged during the turn-off phase and also due to the fact that the drive current is provided by an n-type MOS in a source follower configuration (the aforementioned drive transistor M ON ) is provided to the bidirectional switch 21.

[0095] Furthermore, since the off state is obtained by making the voltage between the gate terminal and the source terminal of the MOS transistors M1, M2 zero instead of grounding the corresponding gate terminals, the off time is also fast.

[0096] At the same time, considering the efficiency of controlling parasitic capacitance, the size of MOS transistors M1 and M2 can be increased to reduce the on-state resistance (without excessively penalizing the on-time).

[0097] The described solution also allows an improvement in power consumption and efficiency, in particular due to the fact that a complete discharge of the parasitic capacitances to the ground reference GND is avoided at each switching of the switching device from the on state to the off state.

[0098] The described solution also reduces complexity and area occupation compared to solutions of known type.

[0099] Finally, it is evident that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

[0100] It is particularly important to emphasize that different circuit implementations are conceivable for both the load stage 30 and the switch logic stage 40 of the switch device 20 .

[0101] For example, Fig. 9 A switching device 20 is shown in which a different implementation is employed for the load stage 30 described above.

[0102] In the present embodiment, the load stage 30 includes a load Zener diode 52 having a cathode terminal connected to the input terminal N1 of the load stage 30 and an anode terminal connected to the source terminal of the load transistor 50 .

[0103] The above-mentioned load transistor 50 , also of the low voltage NMOS type in this case, also has a gate terminal connected to the input terminal N1 of the load stage 30 and a drain terminal connected to the internal node S.

[0104] In the on-state, the load transistor 50 operates, in this case in the linear region, to add a small voltage drop to the voltage drop across the load Zener diode 52 for generating the first drive signal drv_on.

[0105] This embodiment represents the advantage that the possibility of establishing a direct current path between the internal node S and the power supply terminal is avoided.

[0106] This embodiment may be advantageous, for example, in case the switching device 20 is used as an anti-ringing switch to short-circuit a corresponding inductor in a DC-DC converter (according to known solutions, not described in detail here).

[0107] in this regard, Fig.10 It is shown how the control and driver stage 200 of the switching device 20 is modified (simplified) for this specific application.

[0108] In particular, in this case, the switch terminal T is connected to the positive power supply PVCCA of the DC-DC converter, and the switch terminal A is connected to the switch node SW.

[0109] The switching logic stage 40 can be simplified by the presence of a single low voltage nMOS type transistor (denoted by 65) having its drain terminal connected to the input terminal N1 of the load stage 30 (with the first drive signal drv_on), its source terminal connected to the ground reference GND, and its gate terminal connected to the input terminal N2 of the switching logic stage 40 and receiving in this case the second drive signal drv_off. A further low voltage nMOS type transistor (denoted by 66) is connected between the internal node S and the same ground reference ground line GND and having its gate terminal connected to the input terminal N2.

[0110] In this case, the switch device 20 is turned on with respect to the positive power supply PVCCA and can be turned off at the ground reference GND. As previously mentioned, the presence of the load Zener diode 52 in series with the load transistor 50 avoids a DC path between the same positive power supply PVCCA and the ground reference GND in the off state.

[0111] Another implementation of the same load stage 30 may also envisage the absence of the load transistor 50, in which case the value of the first drive signal drv_on varies only as a function of the voltage drop across the load Zener diode 52. In this case, a larger SoA (Safe Operating Area) may be obtained at the expense of a lower switching speed.

[0112] In general, the same load stage 30 may be implemented with other different embodiments, such as with one or more series-connected resistors, with one or more diode-connected MOS transistors, or with other different implementations.

[0113] In one embodiment, a switching device (20) includes a bidirectional switch (21), the bidirectional switch being formed by a first switching MOS transistor (22), a second switching MOS transistor (24) and a voltage limiting element (25), the first switching MOS transistor having a drain terminal connected to a first switching terminal (A), a source terminal connected to an internal source node (S) and a gate terminal connected to an internal gate node (G); the second switching MOS transistor having a drain terminal connected to a second switching terminal (T), a source terminal connected to an internal source node (S) and a gate terminal connected to an internal gate node (G); the voltage limiting element being connected between the internal gate node and the internal source node (G, S), wherein the switching device (20) further includes a driving stage (26), the driving stage voltage being referenced to the internal source node (S) and being configured to drive the switching of the bidirectional switch (21) according to a first driving signal and a second driving signal (drv_on, drv_off), the driving stage (26) including driving transistors (M2) connected to each other in an inverter configuration ON ) and the switching transistor (M OFF ); wherein the driving transistor (M ON ) is connected to the power supply terminal and driven by the first drive signal (drv_on) to charge the internal gate node (G) and turn on the bidirectional switch (21) in the on-interval of the switching device (20); and the switching transistor (M OFF ) is driven by a second drive signal (drv_off) to short-circuit an internal gate node and an internal source node in an off interval of the switching device (20) and turn off the bidirectional switch (21).

[0114] Driver transistor (M ON ) can be an n-type MOS transistor in a source follower configuration.

[0115] Driver transistor (M ON ) may have a drain terminal connected to the power supply terminal, a gate terminal receiving the first drive signal (drv_on), and a source terminal connected to the above-mentioned internal gate node (G); and the switching transistor (M OFF ) may have a drain terminal connected to the internal gate node (G), a gate terminal receiving a second drive signal (drv_off), and a source terminal connected to the internal source node (S).

[0116] During the off interval of the switching device (20), the first and second switching MOS transistors (22, 24) of the bidirectional switch (21) may be in a floating state.

[0117] The device may also include a load stage (30) having a voltage referenced to the internal source node (S) and having an input terminal (N1) selectively connectable via a first switch (32) to a load stage configured to generate a conduction current (I ON ) of the on-state current generator (34); wherein the load stage (30) can be configured to pass the on-state current (I ON ) generates a first drive signal (drv_on) (which is a voltage signal) to cause the drive transistor (M) of the driver stage (26) to ON ) is turned on.

[0118] The load stage (30) may include a load transistor (50) and a load Zener diode (52) connected in series with the load transistor (50) and having an anode terminal connected to the internal source node (S) and a cathode terminal connected to the source terminal of the load transistor (50); the load transistor (50) having a gate terminal connected to a corresponding drain terminal, thereby being diode-connected and also connected to an input terminal (N1) of the load stage (30).

[0119] The load stage (30) may include a load transistor (50) and a load Zener diode (52), the load Zener diode having a cathode terminal connected to an input terminal (N1) of the load stage (30) and an anode terminal connected to a source terminal of the load transistor (50); wherein the load transistor (50) may have a gate terminal connected to the input terminal (N1) of the load stage (30) and a drain terminal connected to an internal source node (S).

[0120] The load transistor (50) may be of the low voltage NMOS type.

[0121] The device may also include a switch logic stage (40) voltage referenced to the internal source node (S) and having a corresponding input terminal (N2) selectively connectable via a second switch (42) to a circuit configured to generate an off current (I OFF ) of the off current generator (44); wherein the switch logic stage (40) can be configured to be based on the off current (I OFF ) and the value of the first drive signal (drv_on) to generate a second drive signal (drv_off) (which is a voltage signal) to cause the switch transistor (M) of the driver stage (26) to switch on. OFF ) is turned on.

[0122] The second driving signal with a high logic value can be designed to turn on the switching transistor (M OFF ), and can be based on the shutdown current (I OFF) and the first drive signal (drv_on) is switched to a low logic value, which is generated by the conduction current (I ON ) is turned off; used to determine the conduction transistor and the switch transistor (M ON 、M OFF ) of the first drive signal and the second drive signal (drv_on, drv_off) for turning on / off, thus the on current and the off current (I ON ,I OFF ), and the on-current and the off-current are determined by the logically replaceable activation of the corresponding first switch and the second switch (32, 42).

[0123] The switch logic stage (40) may include a MOS latch (54) having input terminals (N1, N2) as input / output terminals and referring to an internal source node (S); the MOS latch (54) is formed by a first latch transistor and a second latch transistor (55, 56) in a cross configuration, the first latch transistor and the second latch transistor being connected between the corresponding input terminal (N2) and the internal source node (S); and a Zener diode (58) having an anode connected to the internal source node (S) and a cathode connected to the corresponding input terminal (N2).

[0124] The MOS latch (54) may include a first latch transistor (55) and a second latch transistor (56), the first latch transistor having a drain terminal connected to the load stage (30) and on which a first drive signal (drv_on) is present, a source terminal connected to an internal source node (S), and a gate terminal connected to an input terminal (N2) of a switch logic stage (40); and the second latch transistor having a drain terminal connected to a corresponding input terminal (N2) of the switch logic stage (40), a source terminal connected to the internal source node (S), and a gate terminal connected to the drain terminal of the first latch transistor (55).

[0125] The first latch transistor and the second latch transistor (55, 56) may be low voltage nMOS type transistors.

[0126] The device may also include a circuit configured to generate a shutdown current (I OFF ) and selectively connects an additional off current generator (46) between the internal source node (S) and a ground reference (GND) via a third switch (47).

[0127] The switch logic stage (40) may include a low voltage nMOS transistor (65) having a drain terminal connected to an input terminal (N1) of the load stage (30), a source terminal connected to a ground reference (GND), and a gate terminal connected to a corresponding input terminal (N2) of the switch logic stage (40) and receiving a second drive signal (drv_off), wherein a further low voltage nMOS transistor (66) may be connected between an internal source node (S) and the ground reference (GND) and may have a gate terminal connected to the corresponding input terminal (N2).

[0128] In one embodiment, a charge recovery resonant driver (60) can be summarized as being configured to: OUT1 ) and the second capacitive actuator (C OUT2 ), the first capacitive actuator is coupled to the first charge exchange terminal (A 1 ), the first charge exchange terminal can be selectively and alternately connected to a power supply terminal having a high voltage (VHV) and a ground reference terminal (GND); the second capacitive actuator is coupled to the second charge exchange terminal (A 2 ), the second charge exchange terminal can be selectively and alternately connected to the power supply terminal and the ground reference terminal (GND); the resonant driver (60) includes a plurality of (N) energy storage capacitors (C TANK (1)……C TANK (N)), the energy storage capacitor is selectively connected to the first charge exchange terminal or the second charge exchange terminal (A) through the first switch device (20a) and the second switch device (20b) respectively. 1 , A 2 ); wherein each of the first switching device and the second switching device (20a, 20b) is implemented as a switching device (20).

[0129] In one embodiment, the first capacitive actuator and the second capacitive actuator (C OUT1 , C OUT2 ) can be a capacitive micromirror.

[0130] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A switching device, comprising: Bidirectional switch, including: a first switch MOS transistor having a drain terminal connected to the first switch terminal, a source terminal connected to the internal source node, and a gate terminal connected to the internal gate node; a second switch MOS transistor having a drain terminal connected to the second switch terminal, a source terminal connected to the internal source node, and a gate terminal connected to the internal gate node; and a voltage limiting element connected between the internal gate node and the internal source node; and a driver stage, the voltage of which is referenced to the internal source node and configured to drive switching of the bidirectional switch according to a first drive signal and a second drive signal, the driver stage comprising a drive transistor and a switch transistor connected to each other; wherein the driving transistor is connected to a power supply terminal and driven by the first driving signal to charge the internal gate node and turn on the bidirectional switch in a conduction interval of the switching device; and The switching transistor is driven by the second driving signal to short-circuit the internal gate node and the internal source node and turn off the bidirectional switch during an off interval of the switching device. 2 . The device according to claim 1 , wherein the driver transistor is an n-type MOS transistor in a source follower configuration.

3. The device according to claim 2, wherein: the drive transistor having a drain terminal connected to the power supply terminal, a gate terminal receiving the first drive signal, and a source terminal connected to the internal gate node; as well as The switching transistor has a drain terminal connected to the internal gate node, a gate terminal receiving the second drive signal, and a source terminal connected to the internal source node. 4 . The device of claim 1 , wherein during the turn-off interval of the switching device, the first switch MOS transistor and the second switch MOS transistor of the bidirectional switch are in a floating state.

5. The device of claim 1 , further comprising a load stage voltage-referenced to the internal source node and having an input terminal selectively connectable by a first switch to an on-current generator configured to generate an on-current, wherein the load stage is configured to generate the first drive signal via the on-current to cause conduction of the driver transistor of the driver stage, the first drive signal being a voltage signal.

6. The device of claim 5 , wherein the load stage comprises a load transistor and a load Zener diode connected in series with the load transistor and having an anode terminal connected to the internal source node and a cathode terminal connected to the source terminal of the load transistor, the load transistor having a gate terminal connected to the drain terminal of the load transistor and to the input terminal of the load stage.

7. The device of claim 5 , wherein the load stage comprises a load transistor and a load Zener diode having a cathode terminal connected to the input terminal of the load stage and an anode terminal connected to the source terminal of the load transistor, wherein the gate terminal of the load transistor is connected to the input terminal of the load stage and the drain terminal of the load transistor is connected to the internal source node.

8. The device of claim 6, wherein the load transistor is of a low voltage NMOS type.

9. The device of claim 5 , further comprising a switching logic stage voltage-referenced to the internal source node and having an input terminal selectively connectable by a second switch to a shutdown current generator, the shutdown current generator configured to generate a shutdown current, wherein the switching logic stage is configured to generate the second drive signal based on the shutdown current and a value of the first drive signal to cause conduction of the switching transistor of the driver stage, the second drive signal being a voltage signal.

10. The device according to claim 9 , wherein the second drive signal having a high logic value is designed to turn on the switching transistor and is generated based on the off current and the switching of the first drive signal to a low logic value, the low logic value being generated by the off current, the first drive signal and the second drive signal for determining the on / off of the pass transistor and the switching transistor being controlled by the on current and the off current, which are in turn determined by logically alternative activation of the corresponding first switch and the second switch.

11. The device of claim 9 , wherein the switch logic stage comprises a MOS latch having the input terminal as an input / output terminal and referenced to the internal source node, the MOS latch being formed by a first latch transistor and a second latch transistor in a cross configuration, the first latch transistor and the second latch transistor being connected between the respective input terminals and the internal source node; and a Zener diode having an anode connected to the internal source node and a cathode connected to the respective input terminal.

12. The device of claim 11, wherein the MOS latch comprises: a first latch transistor having a drain terminal connected to the load stage and having the first drive signal present at the drain terminal, a source terminal connected to the internal source node, and a gate terminal connected to the input terminal of the switching logic stage; as well as A second latch transistor has a drain terminal connected to the corresponding input terminal of the switching logic stage, a source terminal connected to the internal source node, and a gate terminal connected to the drain terminal of the first latch transistor. 13 . The device of claim 12 , wherein the first latch transistor and the second latch transistor are low voltage nMOS type transistors. 14 . The device of claim 9 , further comprising an additional off-current generator configured to generate the off-current and selectively connected between the internal source node and a ground reference via a third switch.

15. The device of claim 9 , wherein the switching logic stage comprises a low voltage nMOS transistor having a drain terminal, a source terminal, and a gate terminal, the drain terminal being connected to the input terminal of the load stage, the source terminal being connected to a ground reference, the gate terminal being connected to a corresponding input terminal of the switching logic stage and receiving the second drive signal, wherein a further low voltage nMOS transistor is connected between the internal source node and the ground reference and having a gate terminal connected to the input terminal.

16. A charge recovery resonant driver, comprising: a first capacitive actuator coupled to a first charge exchange terminal, the first charge exchange terminal being selectively and alternately connectable to a power supply terminal and a ground reference terminal, the power supply terminal having a high voltage; as well as a second capacitive actuator coupled to a second charge exchange terminal, the second charge exchange terminal being selectively and alternately connectable to the power supply terminal and the ground reference terminal; a plurality of energy storage capacitors, each energy storage capacitor being coupled to a respective device pair and selectively connectable to the first charge exchange device by a first switching device in the device pair and selectively connectable to the second charge exchange terminal by a second switching device in the device pair, wherein each switching device comprises: Bidirectional switch, including: a first switch MOS transistor having a drain terminal connected to the first switch terminal, a source terminal connected to the internal source node, and a gate terminal connected to the internal gate node; a second switch MOS transistor having a drain terminal connected to the second switch terminal, a source terminal connected to the internal source node, and a gate terminal connected to the internal gate node; and a voltage limiting element connected between the internal gate node and the internal source node; and A driver stage has a voltage reference to the internal source node and is configured to drive switching of the bidirectional switch according to a first drive signal and a second drive signal, the driver stage including a drive transistor and a switch transistor connected to each other.

17. The charge recovery resonant driver of claim 16, wherein: The driving transistor is connected to a power supply terminal and driven by the first driving signal to charge the internal gate node and turn on the bidirectional switch in a conduction interval of the switching device; and The switching transistor is driven by the second driving signal to short-circuit the internal gate node and the internal source node and turn off the bidirectional switch in an off interval of the switching device.

18. The charge recovery resonant driver of claim 17, wherein the first capacitive actuator and the second capacitive actuator are capacitive micromirrors.

19. A method comprising: a bidirectional switch for driving a switching device using a driver stage based on a first drive signal and a second drive signal, the driver stage including a driver transistor and a switch transistor connected to each other, the bidirectional switch including a first switch MOS transistor and a second switch MOS transistor, an internal gate, the first switch MOS transistor and the second switch MOS transistor being coupled together at an internal source node between a first switch terminal and a second switch terminal, the internal gate being coupled to the internal source, to gate terminals of the first switch MOS transistor and the second switch MOS transistor, and to an output of the driver stage by a voltage limiting device; providing a power supply voltage to a drain terminal of the driving transistor; charging the internal gate node and turning on the bidirectional switch in a conduction interval of the switching device by driving the driving transistor with the first driving signal; as well as By driving the switching transistor with the second drive signal, the internal gate node and the internal source node are short-circuited in an off interval of the switching device and the bidirectional switch is turned off. 20 . The method of claim 19 , wherein during the turn-off interval of the switching device, the first and second switch MOS transistors of the bidirectional switch are in a floating state.

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