High speed high voltage comparator

Abstract

The application provides a high-speed high-voltage comparator suitable for an analog-digital conversion circuit, comprising a front signal voltage conversion module, a middle signal amplification module and a rear signal latch module connected in sequence; the devices contained in the front signal voltage conversion module are high-voltage devices, receive a high-voltage input signal, convert the high-voltage input signal into a low-voltage input signal and send the low-voltage input signal to the middle signal amplification module; the middle signal amplification module comprises multiple cascaded amplifiers, the devices contained in the middle signal amplification module are low-voltage devices, the low-voltage input signal is amplified and processed to generate an intermediate analog signal which is sent to the rear signal latch module; the devices contained in the rear signal latch module are low-voltage devices, the intermediate analog signal is converted into a digital signal by the clock signal and outputted. The high-speed high-voltage comparator can meet the application requirement of high speed and high voltage, has small noise, small mismatch and strong anti-interference ability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a high-speed high-voltage comparator. BACKGROUND

[0002] Analog-to-digital conversion circuit seriously depends on high-speed comparators, but its application scenarios include processing of high-voltage (5V, 3V) input signals, and 5V, 3V devices cannot meet the requirements of 100MHz high-speed signal processing, only 1.1V devices can be used, so a new comparator structure needs to be proposed. SUMMARY

[0003] The purpose of the present application is to provide a high-speed high-voltage comparator that can meet the application requirements of high speed and high voltage.

[0004] To achieve the above purpose, the present application provides the following technical solutions:

[0005] The present application provides a high-speed high-voltage comparator, which comprises a pre-signal voltage conversion module, a middle-signal amplification module, a post-signal latch module connected in sequence, and a voltage generating circuit for providing low-voltage power supply for the middle-signal amplification module and the post-signal latch module; the devices contained in the pre-signal voltage conversion module are all high-voltage devices, which receive high-voltage input signals, convert them into low-voltage input signals, and send them to the middle-signal amplification module; the middle-signal amplification module comprises a plurality of cascaded amplifiers, and the devices contained therein are all low-voltage devices, which amplify and process the low-voltage input signals to generate intermediate-level analog signals and send them to the post-signal latch module; the devices contained in the post-signal latch module are all low-voltage devices, which are controlled by a clock signal to convert the intermediate-level analog signals into digital signals and output them.

[0006] In an embodiment, the pre-signal voltage conversion module comprises a zeroth PMOS tube, a first PMOS tube, a second PMOS tube, a first resistor, and a second resistor, the source end of the zeroth PMOS tube is connected to a high-voltage power supply, the gate end of the zeroth PMOS tube is connected to a zeroth bias voltage, the drain end of the zeroth PMOS tube is connected to the source end of the first PMOS tube and the source end of the second PMOS tube, the gate end of the first PMOS tube and the gate end of the second PMOS tube jointly constitute a first signal input end for receiving the high-voltage input signals, the drain end of the first PMOS tube is grounded via the first resistor, the drain end of the second PMOS tube is grounded via the second resistor, and the drain end of the first PMOS tube and the drain end of the second PMOS tube jointly constitute a first signal output end for outputting the low-voltage input signals.

[0007] In an embodiment, the middle signal amplification module comprises a first-stage amplifier, a second-stage amplifier,..., an Nth-stage amplifier, N being a positive integer greater than or equal to three, the first-stage amplifier comprising a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a third resistor, a fourth resistor, a source end of the third PMOS tube being connected to the low-voltage power supply, a gate end of the third PMOS tube being connected to a first bias voltage, a drain end of the third PMOS tube being connected to a source end of the fourth PMOS tube and a source end of the fifth PMOS tube, a gate end of the fourth PMOS tube and a gate end of the fifth PMOS tube together constituting a second signal input end for receiving a second input signal, a drain end of the fourth PMOS tube being connected to ground via the third resistor, a drain end of the fifth PMOS tube being connected to ground via the fourth resistor, and a drain end of the fourth PMOS tube and a drain end of the fifth PMOS tube together constituting a second signal output end for outputting a second output signal.

[0008] In an embodiment, the second stage amplifier comprises a sixth PMOS, a seventh PMOS, an eighth PMOS, a ninth PMOS, a tenth PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a source terminal of the sixth PMOS is connected to the low voltage power supply, a gate terminal of the sixth PMOS is connected to a second bias voltage, a drain terminal of the sixth PMOS is connected to a source terminal of the seventh PMOS, a source terminal of the eighth PMOS, a gate terminal of the seventh PMOS, a gate terminal of the eighth PMOS together form a third signal input terminal, connected to the second signal output terminal, receiving a third input signal, and the gate terminal of the seventh PMOS is connected to a drain terminal of the fifth PMOS via the first capacitor, the gate terminal of the eighth PMOS is connected to a drain terminal of the fourth PMOS via the second capacitor, and the gate terminal of the seventh PMOS is connected to a fifth bias voltage via a first switch, the gate terminal of the eighth PMOS is connected to the fifth bias voltage via a second switch, a drain terminal of the seventh PMOS is connected to a source terminal of the ninth PMOS, a drain terminal of the eighth PMOS is connected to a source terminal of the tenth PMOS, a gate terminal of the ninth PMOS, a gate terminal of the tenth PMOS is connected to a third bias voltage, a drain terminal of the ninth PMOS is connected to a drain terminal of the first NMOS, a drain terminal of the tenth PMOS is connected to a drain terminal of the second NMOS, the drain terminal of the ninth PMOS, the drain terminal of the tenth PMOS together form a third signal output terminal, outputting a third output signal, a gate terminal of the first NMOS, a gate terminal of the second NMOS is connected to a fourth bias voltage, a source terminal of the first NMOS is connected to a drain terminal of the third NMOS, a source terminal of the third NMOS is connected to ground, a source terminal of the second NMOS is connected to a drain terminal of the fourth NMOS, a source terminal of the fourth NMOS is connected to ground, the gate terminal of the third NMOS, the gate terminal of the fourth NMOS together are connected to the drain terminal of the ninth PMOS via the third capacitor, the gate terminal of the third NMOS, the gate terminal of the fourth NMOS together are connected to the drain terminal of the tenth PMOS via the fourth capacitor, the gate terminal of the third NMOS, the gate terminal of the fourth NMOS are connected to a sixth bias voltage via a third switch, a fourth switch in series, the drain terminal of the ninth PMOS is connected to a common mode voltage via a fifth switch, a sixth switch in series, the drain terminal of the tenth PMOS is connected to the common mode voltage via a seventh switch, an eighth switch in series, a connection point between the third switch, the fourth switch and a connection point between the fifth switch, the sixth switch are connected to the fifth capacitor,The connection point of the third switch and the fourth switch is connected with the connection point of the seventh switch and the eighth switch, and the sixth capacitor is connected between the connection point of the third switch and the fourth switch and the connection point of the seventh switch and the eighth switch.

[0009] In an embodiment, the Nth amplifier has the same structure as the second amplifier, and the Nth amplifier has a fourth signal input end, a fourth signal output end, a seventh capacitor and an eighth capacitor. The fourth signal input end receives a fourth input signal, and is connected with the third signal output end via the seventh capacitor and the eighth capacitor. The fourth signal output end outputs a fourth output signal.

[0010] In an embodiment, the post signal latch module comprises a sixteenth PMOS, a seventeenth PMOS, an eighteenth PMOS, a nineteenth PMOS, a twentieth PMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, a ninth capacitor, a tenth capacitor, the source of the sixteenth PMOS is connected to the low voltage power supply, the gate of the sixteenth PMOS is connected to a latch signal, the drain of the sixteenth PMOS is connected to the source of the seventeenth PMOS and the source of the eighteenth PMOS, the gate of the seventeenth PMOS and the gate of the eighteenth PMOS together form a fifth signal input end for receiving a fifth input signal, and the fifth signal input end is connected to the fourth signal output end via the ninth capacitor and the tenth capacitor, the gate of the seventeenth PMOS is connected to the fifth bias voltage via a ninth switch, the gate of the eighteenth PMOS is connected to the fifth bias voltage via a tenth switch, the drain of the seventeenth PMOS is connected to the source of the nineteenth PMOS and the drain of the ninth NMOS, the source of the ninth NMOS is grounded, the drain of the eighteenth PMOS is connected to the source of the twentieth PMOS and the drain of the fourteenth NMOS, the source of the fourteenth NMOS is grounded, the gate of the nineteenth PMOS is connected to the gate of the eleventh NMOS, the drain of the twelfth NMOS and the drain of the thirteenth NMOS, the source of the thirteenth NMOS is grounded, the gate of the twentieth PMOS is connected to the gate of the twelfth NMOS, the drain of the eleventh NMOS and the drain of the tenth NMOS, the source of the tenth NMOS is grounded, the drain of the nineteenth PMOS is connected to the drain of the eleventh NMOS, the drain of the twentieth PMOS is connected to the drain of the twelfth NMOS, the drain of the nineteenth PMOS and the drain of the twentieth PMOS together form a fifth signal output end for outputting a fifth output signal, and the drain of the eleventh NMOS and the source of the twelfth NMOS are grounded, the gate of the ninth NMOS, the gate of the tenth NMOS, the gate of the thirteenth NMOS and the gate of the fourteenth NMOS are all connected to the latch signal.

[0011] In an embodiment, the high-speed high-voltage comparator further comprises a digital logic circuit connected to the post signal latch module, receiving signals output by the post signal latch module and processing the signals to generate a comparison result.

[0012] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0013] The high-speed high-voltage comparator can meet the application requirement of high-speed high-voltage, has small noise, small mismatch and strong anti-interference ability. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0015] Figure 1 A structural block diagram of a high-speed high-voltage comparator provided in the first embodiment of the present application is shown in the figure.

[0016] Figure 2 A structural block diagram of a high-speed high-voltage comparator provided in the first embodiment of the present application is shown in the figure. Figure 1 An internal circuit schematic diagram of the pre-signal voltage conversion module in the first embodiment of the present application is shown in the figure.

[0017] Figure 3 An internal circuit schematic diagram of the pre-signal voltage conversion module in the first embodiment of the present application is shown in the figure. Figure 1 An internal circuit schematic diagram of the pre-signal voltage conversion module in the first embodiment of the present application is shown in the figure.

[0018] Figure 4 An internal circuit schematic diagram of the pre-signal voltage conversion module in the first embodiment of the present application is shown in the figure. Figure 1 An internal circuit schematic diagram of the pre-signal voltage conversion module in the first embodiment of the present application is shown in the figure.

[0019] Figure 5 A transmission process schematic of each signal involved in the high-speed high-voltage comparator of the present application is shown in the figure. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application. It should be noted that the description order of the following embodiments is not used to limit the preferred order of the embodiments of the present application. In the following embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0021] Please refer to Figure 1As shown, the first embodiment of the present application provides a high-speed high-voltage comparator suitable for an analog-to-digital conversion circuit, which comprises a pre-signal voltage conversion module 101, a middle-signal amplification module 200, a post-signal latch module 301 connected in sequence, and a voltage generation circuit 400 for providing a low-voltage power supply LVDD for the middle-signal amplification module 200 and the post-signal latch module 301; the pre-signal voltage conversion module 101 contains high-voltage devices, receives a high-voltage input signal, converts it into a low-voltage input signal, and sends it to the middle-signal amplification module 200; the middle-signal amplification module 200 comprises multiple cascaded amplifiers containing low-voltage devices, amplifies the low-voltage input signal, generates an intermediate analog signal, and sends it to the post-signal latch module 301; the post-signal latch module 301 contains low-voltage devices, is controlled by a clock signal, converts the intermediate analog signal into a digital signal, and outputs it.

[0022] First of all, the high voltage and low voltage mentioned in the present application are relative to each other. In a specific embodiment, the high voltage is 5V or 3V, and the low voltage is 1.1V. High speed means that the frequency of the signal to be processed reaches 80MHz or even higher.

[0023] Please refer to Figure 2 As shown, in an embodiment, the pre-signal voltage conversion module 101 comprises a zeroth PMOS tube PM0, a first PMOS tube PM1, a second PMOS tube PM2, a first resistor R1, and a second resistor R2. The source end of the zeroth PMOS tube PM0 is connected to a high-voltage power supply, the gate end of the zeroth PMOS tube PM0 is connected to a zeroth bias voltage, the drain end of the zeroth PMOS tube PM0 is connected to the source end of the first PMOS tube PM1 and the source end of the second PMOS tube PM2, the gate end of the first PMOS tube PM1 and the gate end of the second PMOS tube PM2 together constitute a first signal input end for receiving a high-voltage input signal, which can also be referred to as a first input signal ip1,in1, the drain end of the first PMOS tube PM1 is grounded via the first resistor R1, the drain end of the second PMOS tube PM2 is grounded via the second resistor R2, and the drain end of the first PMOS tube PM1 and the drain end of the second PMOS tube PM2 together constitute a first signal output end for outputting a low-voltage input signal, which can also be referred to as a first output signal op1,on1. In this description, the signals mentioned in the present application all include a pair of two paths, so each signal is represented using two element designations (a positive p and a negative n) to simplify the description throughout the text.

[0024] In a specific embodiment, the three PMOS of the front signal voltage conversion module 101 are 5V devices, which can withstand 5V input signal. The resistance of the first resistor R1 and the second resistor R2 are equal, both R. When the input voltage of the first input signal ip1, in1 is 5V, the corresponding input PMOS is off, and the voltage of the other path is 0V, the corresponding PMOS is on, so the current (Idd) flows into the load resistor (R) of the on PMOS. The parameter setting needs Idd*R <1.1V*(1+10%), to meet the voltage requirement of the devices used by the middle signal amplification module 200. Therefore, the voltage drop of this resistor is Idd*R≈1.1V, and the voltage drop of the load resistor of the other path is≈0*R≈0V. It is a continuous working amplifier, which is not affected by the system clock.

[0025] Please refer to Figure 1 , Figure 3 , in an embodiment, the middle signal amplification module 200 includes a first stage amplifier 201, a second stage amplifier 202, …, an Nth stage amplifier 203, N is a positive integer greater than or equal to three, the first stage amplifier 201 includes a third PMOS PM3, a fourth PMOS PM4, a fifth PMOS PM5, a third resistor R3, a fourth resistor R4, the source end of the third PMOS PM3 is connected to the low voltage power supply LVDD, the gate end of the third PMOS PM3 is connected to the first bias voltage bias1, the drain end of the third PMOS PM3 is connected to the source end of the fourth PMOS PM4 and the source end of the fifth PMOS PM5, the gate end of the fourth PMOS PM4 and the gate end of the fifth PMOS PM5 together constitute a second signal input end, which receives a second input signal, the drain end of the fourth PMOS PM4 is grounded through the third resistor R3, the drain end of the fifth PMOS PM5 is grounded through the fourth resistor R4, and the drain end of the fourth PMOS PM4 and the drain end of the fifth PMOS PM5 together constitute a second signal output end, which outputs a second output signal op2, on2.

[0026] The middle signal amplification module 200 is composed of several stages of open-loop amplification modules, which have the characteristics of large gain, small noise, and small mismatch. In a specific embodiment, all the active devices are 1.1V. The structure of the first stage amplifier 201 is the same as that of the front signal voltage conversion module 101, and the purpose is to generate an output with small noise. It is also a continuous working amplifier, which is not affected by the system clock. The structure of the following several stages can be determined according to the process parameters as long as the overall gain requirement is met.

[0027] Please continue to refer to Figure 3As shown, in an embodiment, the second stage amplifier 202 comprises a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a source terminal of the sixth PMOS transistor PM6 is connected to the low voltage power supply LVDD, a gate terminal of the sixth PMOS transistor PM6 is connected to a second bias voltage bias2, a drain terminal of the sixth PMOS transistor PM6 is connected to a source terminal of the seventh PMOS transistor PM7, a source terminal of the eighth PMOS transistor PM8, a gate terminal of the seventh PMOS transistor PM7, a gate terminal of the eighth PMOS transistor PM8 together form a third signal input terminal, connected to the second signal output terminal, receiving a third input signal ip3, in3, and a gate terminal of the seventh PMOS transistor PM7 is connected to a drain terminal of the fifth PMOS transistor PM5 via the first capacitor C1, a gate terminal of the eighth PMOS transistor PM8 is connected to a drain terminal of the fourth PMOS transistor PM4 via the second capacitor C2, and a gate terminal of the seventh PMOS transistor PM7 is connected to a fifth bias voltage bias5 via a first switch K1, a gate terminal of the eighth PMOS transistor PM8 is connected to the fifth bias voltage bias5 via a second switch K2, a drain terminal of the seventh PMOS transistor PM7 is connected to a source terminal of the ninth PMOS transistor PM9, a drain terminal of the eighth PMOS transistor PM8 is connected to a source terminal of the tenth PMOS transistor PM10, a gate terminal of the ninth PMOS transistor PM9, a gate terminal of the tenth PMOS transistor PM10 are connected to a third bias voltage bias3, a drain terminal of the ninth PMOS transistor PM9 is connected to a drain terminal of the first NMOS transistor NM1, a drain terminal of the tenth PMOS transistor PM10 is connected to a drain terminal of the second NMOS transistor NM2, a drain terminal of the ninth PMOS transistor PM9, a drain terminal of the tenth PMOS transistor PM10 together form a third signal output terminal, outputting a third output signal op3, on3, a gate terminal of the first NMOS transistor NM1, a gate terminal of the second NMOS transistor NM2 are connected to a fourth bias voltage bias4,

[0028] The source terminal of the first NMOS transistor NM1 is connected to the drain terminal of the third NMOS transistor NM3, the source terminal of the third NMOS transistor NM3 is connected to ground, the source terminal of the second NMOS transistor NM2 is connected to the drain terminal of the fourth NMOS transistor NM4, the source terminal of the fourth NMOS transistor NM4 is connected to ground, the gate terminal of the third NMOS transistor NM3 and the gate terminal of the fourth NMOS transistor NM4 are connected to the drain terminal of the ninth PMOS transistor PM9 through the third capacitor C3, the gate terminal of the third NMOS transistor NM3 and the gate terminal of the fourth NMOS transistor NM4 are connected to the drain terminal of the tenth PMOS transistor PM10 through the fourth capacitor C4, the gate terminal of the third NMOS transistor NM3 and the gate terminal of the fourth NMOS transistor NM4 are connected to the sixth bias voltage bias6 through the third switch K3 and the fourth switch K4, the drain terminal of the ninth PMOS transistor PM9 is connected to the common mode voltage through the fifth switch K5 and the sixth switch K6, the drain terminal of the tenth PMOS transistor PM10 is connected to the common mode voltage through the seventh switch K7 and the eighth switch K8, the fifth capacitor C5 is connected between the connection point of the third switch K3 and the fourth switch K4 and the connection point of the fifth switch K5 and the sixth switch K6, and the sixth capacitor C6 is connected between the connection point of the third switch K3 and the fourth switch K4 and the connection point of the seventh switch K7 and the eighth switch K8. Figure 3 In the specific embodiment shown, the common mode voltage is 0.55V.

[0029] The input terminal of the second stage amplifier 202 is in series with a capacitor for suppressing the output mismatch voltage (OS) of the previous stage. Before processing the signal, the gate terminals of the input MOS are biased with the same voltage, that is, the voltage of the third input signal ip3,in3 capacitor is the same. The output mismatch voltage (OS) of the previous two stages of amplifiers is stored in the other end of the capacitor, that is, the second output signal op2,on2. During the formal processing of the signal, the output mismatch voltage (OS) of the previous two stages of amplifiers will not affect the comparison result of this stage of amplifiers.

[0030] The second stage amplifier 202 adopts a capacitor switch type output stage common mode voltage clamping structure. Because it is processing high-speed signals, the output common mode voltage will not have a large deviation due to leakage.

[0031] Please continue to refer to Figure 1 , Figure 3As shown, in an embodiment, the Nth amplifier 203 has a fourth signal input end, a fourth signal output end, a seventh capacitor C7, and an eighth capacitor C8. The fourth signal input end receives a fourth input signal ip4, in4, and is connected to the third signal output end via the seventh capacitor C7 and the eighth capacitor C8. The fourth signal output end outputs a fourth output signal op4, on4.

[0032] The amplifiers behind the second amplifier 202 can have the same structure as the second amplifier 202. In Figure 3 In the specific embodiment shown, in order to shorten the transmission time of the signal, the middle signal amplification module 200 has a total of three amplifiers. According to the actual application scenario, the number of cascades, i.e., the number of amplifiers (i.e., the number of amplification stages) can be easily adjusted, and the structure of the amplifiers can be flexibly selected to trade off the corresponding signal conversion speed and design complexity. For example, the middle signal amplification module 200 can also have two amplifiers, and thus the input end (fifth signal input end) of the post-signal latch module 301 described below is not connected to the fourth signal output end, but is connected to the third signal output end.

[0033] Please refer to Figure 4As shown, in an embodiment, the back signal latch module 301 comprises a sixteenth PMOS PM16, a seventeenth PMOS PM17, an eighteenth PMOS PM18, a nineteenth PMOS PM19, a twentieth PMOS PM20, a ninth NMOS NM9, a tenth NMOS NM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a thirteenth NMOS NM13, a fourteenth NMOS NM14, a ninth capacitor C9, a tenth capacitor C10, a source terminal of the sixteenth PMOS PM16 is connected to the low voltage power supply LVDD, a gate terminal of the sixteenth PMOS PM16 is connected to a latch signal latch, a drain terminal of the sixteenth PMOS PM16 is connected to a source terminal of the seventeenth PMOS PM17 and a source terminal of the eighteenth PMOS PM18, a gate terminal of the seventeenth PMOS PM17 and a gate terminal of the eighteenth PMOS PM18 together form a fifth signal input terminal for receiving a fifth input signal ip5, in5, and the gate terminal of the seventeenth PMOS PM17 is connected to the fifth bias voltage bias5 through a ninth switch K9, the gate terminal of the eighteenth PMOS PM18 is connected to the fifth bias voltage bias5 through a tenth switch K10, a drain terminal of the seventeenth PMOS PM17 is connected to a source terminal of the nineteenth PMOS PM19 and a drain terminal of the ninth NMOS NM9, a source terminal of the ninth NMOS NM9 is grounded, a drain terminal of the eighteenth PMOS PM18 is connected to a source terminal of the twentieth PMOS PM20 and a drain terminal of the fourteenth NMOS NM14, a source terminal of the fourteenth NMOS NM14 is grounded, a gate terminal of the nineteenth PMOS PM19 is connected to a gate terminal of the eleventh NMOS NM11, a drain terminal of the twelfth NMOS NM12 and a drain terminal of the thirteenth NMOS NM13, a source terminal of the thirteenth NMOS NM13 is grounded, a gate terminal of the twentieth PMOS PM20 is connected to a gate terminal of the twelfth NMOS NM12, a drain terminal of the eleventh NMOS NM11 and a drain terminal of the tenth NMOS NM10, a source terminal of the tenth NMOS NM10 is grounded, a drain terminal of the nineteenth PMOS PM19 is connected to a drain terminal of the eleventh NMOS NM11, a drain terminal of the twentieth PMOS PM20 is connected to a drain terminal of the twelfth NMOS NM12, and a drain terminal of the nineteenth PMOS PM19 and a drain terminal of the twentieth PMOS PM20 together form a fifth signal output terminal for outputting a fifth output signal op5,The drain of the eleventh NMOS transistor NM11, the source of the twelfth NMOS transistor NM12, the gate of the ninth NMOS transistor NM9, the gate of the tenth NMOS transistor NM10, the gate of the thirteenth NMOS transistor NM13, and the gate of the fourteenth NMOS transistor NM14 are connected to the latch signal latch.

[0034] The post-signal latch module 301 is the last stage of the comparator of the present application, and the active devices thereof are all 1.1V. The analog signal is completely converted into a 1.1V digital signal and maintained under the control of the clock signal. In order to suppress the influence of the mismatch voltage of the termination signal amplifier, a pair of capacitors are also connected in series at the input end. Of course, the post-signal latch module 301 can also adopt a structure according to actual needs, as long as the required functions of the present application can be achieved.

[0035] The voltage generating circuit 400 (regulator) for providing a low-voltage (1.1V) power supply does not have a very strong precision requirement. The voltage generating circuit 400 provides a low-voltage power supply LVDD for the middle-signal amplification module 200 and the post-signal latch module 301, and improves the PSRR (power supply ripple rejection ratio) of this part of the circuit.

[0036] Finally, in an embodiment, the high-speed high-voltage comparator of the present application further comprises a digital logic circuit connected to the post-signal latch module 301, receiving the signal output by the post-signal latch module 301, i.e. the fifth output signal op5, on5, and processing it to generate a comparison result.

[0037] Below, please refer to Figure 5 The transmission process of the signals involved in the comparator of the present application is briefly described. In order to simplify the text, the element designations of the signals are directly used in the following description, and it is assumed that before TO, the potentials of the signals ip1, in1 are the same, =2.5V. op1-on1 = ip2-in2 = (0.55V+OS1)-0.55V. op2-on2 = (Vdc2+α*OS1+OS2)-Vdc2. Vdc2 is the common-mode voltage of the second stage output, and α is the gain of the second stage. ip3-in3 = bias5-bias5 = 0. op3-on3 = (bias6+OS3)-bias6. ip4-in4 = bias5-bias5 =0. op4-on4 = (bias6+OS4)-bias6. ip5-in5 = bias5-bias5 =0. op5-on5 = 0V-0V = 0V. OS1, OS2, OS3, and OS4 are the mismatch voltages of the amplifiers of the respective stages.

[0038] After T0, the input signal has changed, ip1-in1 = (2.5V+△)-(2.5V-△). op1-on1 = (0.55V+OS1+△1)-(0.55V-△1). ip2-in2 = OS1+2*△1. op2-on2 = (Vdc2+α*OS1+OS2+△2)-(Vdc2-△2). ip3-in3 = 2*△2. op3-on3 = (bias6+OS3+△3)-(bias6-△3). ip4-in4 = 2*△3. op4-on4 = (bias6+OS4+△4)-(bias6-△4). ip5-in5 = 2*△4. op5-on5 = 1.1V. Thus, the OS of each stage is suppressed and does not affect the next stage. However, because the cascade amplifier has a large gain, the maximum value of the intrinsic OS is limited. In the above description, △ represents the change in the single-ended input signal, and △1, △2, △3, and △4 represent the voltage of the signal after being amplified in the single-ended manner. Figure 5 In the above description, it is assumed that OS1 = OS2 = OS3 = OS4.

[0039] Each signal amplification circuit has a PMOS as the current source of the stage, and the gate end thereof is connected to a fixed voltage to ensure a stable and continuous supply current and a good power voltage noise suppression capability. The application environment of the comparator usually has two stages: a first stage of signal preparation, in which the comparator is set; and a second stage of signal input, in which the comparator compares. In the two stages, the pre-signal voltage conversion module 101 and the first stage of the middle signal amplification module 200 will accurately reflect the voltage change of the signal ip1, in1 to op1, on1 and op2, on2 in real time. At the same time, the mismatch voltage of the comparator itself will also be reflected to op2, on2 in real time. Because it is a multi-stage amplification, in order to reduce the interference of the mismatch voltage on the signal comparison result, the mismatch voltage elimination structure is used in the third, fourth, and fifth stages. For example, a series capacitor is inserted between the third stage input ip3, in3 and the second stage output op2, on2, and a series switch is arranged between ip3, in3 and bias5.

[0040] Usually in the first stage of the comparator, ip1, in1 is also set to the same voltage. Ideally, after the action of the pre-amplification circuit, it becomes op1 = on1 = 0.5*1.1V. After the first stage of the middle signal amplification module 200, op2 = on2 = 0.5*1.1V. However, in fact, op2, on2 contains the mismatch information of the two-stage amplification module. For example, Figure 5As shown, even if ip1 = in1, the voltages of op1, on1 and op2, on2 cannot be equal because of the mismatch effect. In the structure of the present application, the switch between ip3, in3 and bias5 is closed at this time, so that ip3 = in3 = bias5, eliminating the effect of the non-zero mismatch voltage on op2, on2 on the input signal of the present stage. Similarly, ip4, in4, ip5, in5 are eliminated in the same way, respectively, the effect of the non-zero mismatch voltage on op3, on3, op4, on4 of the present stage, that is, ip4 = in4 = bias5, ip5 = in5 = bias5. Even so, it is necessary to control the intrinsic mismatch voltage of each stage within a certain range. Therefore, under the premise of ensuring the function, the power consumption and area of each stage amplifier cannot be very small, and the gain cannot be too large. This needs to be ensured by using the corresponding structure according to different process parameters. The PM16 of the post signal latch module 301 is in the off state at this stage, and no current can flow from VDD through it to the source end of PM17, PM18. At the same time, NM9, NM10, NM13, NM14 are in the on state, pulling the voltages of op5, on5 and op5x, on5x (the middle node, the drain end of PM17, PM18) to 0 potential.

[0041] In the second stage of the comparator, first disconnect the switch between ip3, in3, ip4, in4, ip5, in5 and bias5, let them in the floating state. Because of the existence of these nodes parasitic capacitance, the voltage of these nodes will not change significantly in a short time, that is, do not affect the comparison results. Then the input signal ip1, in1 voltage has changed, the corresponding op1, on1 also changed. As described earlier, by controlling the current and load resistance, the maximum signal range of op1, on1 is 0V to 1.1V. Similarly, op2, on2 also has a corresponding change. This change is coupled to ip3, in3 through the series capacitor between op2, on2 and ip3, in3. Through the amplification function of this level, op3, on3 has a corresponding change. Similarly, this change is coupled to ip4, in4 through the series capacitor between op3, on3 and ip4, in4, and the op4, on4 has a new assigned voltage signal after the amplification module of this level. Similarly, this change process is also transmitted to ip5, in5. Because the previous stage amplification gain is sufficient, then the minimum input signal on ip1, in1, the voltage on ip5, in5 will be much larger than the equivalent input mismatch voltage of this level. After ip5, in5 reaches a stable voltage, the latch clock signal is started, and PM16 can provide a large enough current. At the same time, the gate voltage of NM9, NM10, NM13, NM14 is pulled to 0, so that these 4 NMOS enter the off state. At this moment, the voltage of op5, on5 and op5x, on5x still remains at 0V. Next, because ip5, in5 is not the same, the conduction resistance of PM17 and PM18 is not the same, so the current flowing through PM17, PM18 to op5x, on5x is also different, and the voltage of op5x, on5x is also different. During this voltage rising process, the node corresponding to PM19 or PM20 with a large Vgs will have a small Ron, resulting in a small Vds, that is, the node voltage of the PMOS drain end will also rise fast. While the voltage of the other node rises slowly. When the voltages of the two nodes are greater than the threshold voltage of the NMOS, the voltage difference will further cause the discharge capacity of NM11 and NM12 to be different, thereby accelerating the change rate of the voltage difference. As Figure 5As shown in the figure, (Vip5>Vin5)→(Vopx5>Vonx5)→(Vgs_PM20>Vgs_PM19)→(Vop5>Von5)→(Vgs_NM11>Vgs_NM12)→(Ids_NM11>Ids_NM12)→……→(PM20 on, NM12 off, PM9 off, NM11 on)→(Vop5≈1.1V, Von5=0)→the comparison process ends. At this time, the result can be stored and output by some digital logic circuits, and usually the output form is single-ended signal output, and a clock signal matched with the phase is output together to facilitate subsequent circuit processing.

[0042] Compared with the prior art, the technical scheme of the application has the following beneficial effects:

[0043] The high-speed high-voltage comparator can meet the application requirements of high speed and high voltage, has small noise, small mismatch, and strong anti-interference capability.

[0044] The above is only a specific embodiment of the application, but the protection scope of the application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered in the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims. In addition, the principles and embodiments of the application are described by applying specific examples in the specification, and the above example is only used to help understand the method and core idea of the application, and the content of the specification should not be understood as a limitation of the application.

Claims

1. A high-speed, high-voltage comparator suitable for analog-to-digital conversion circuits, characterized in that, The high-speed high-voltage comparator includes a pre-amplifier voltage conversion module, a mid-amplifier signal amplification module, a post-amplifier signal latching module, and a voltage generation circuit that provides low-voltage power to the mid-amplifier signal amplification module and the post-amplifier signal latching module, connected in sequence. The pre-amplifier voltage conversion module contains only high-voltage components, receives a high-voltage input signal, converts it into a low-voltage input signal, and sends it to the mid-amplifier signal amplification module. The mid-amplifier signal amplification module includes a multi-stage cascaded amplifier, containing only low-voltage components, amplifies the low-voltage input signal, generates an intermediate-stage analog signal, and sends it to the post-amplifier signal latching module. The post-amplifier signal latching module contains only low-voltage components, and is used by... The clock signal control converts the intermediate-stage analog signal into a digital signal and outputs it. The intermediate signal amplification module includes N amplifiers, namely the first-stage amplifier, the second-stage amplifier, and so on up to the Nth-stage amplifier, where N is a positive integer greater than or equal to three. The second-stage amplifier includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The source terminal of the sixth PMOS transistor is connected to the low-voltage power supply, the gate terminal of the sixth PMOS transistor is connected to the second bias voltage, and the drain terminal of the sixth PMOS transistor... The source terminals of the seventh and eighth PMOS transistors are connected, and the gate terminals of the seventh and eighth PMOS transistors together form a third signal input terminal, which is connected to the second signal output terminal to receive a third input signal. The gate terminal of the seventh PMOS transistor is connected to the drain terminal of the fifth PMOS transistor via the first capacitor, and the gate terminal of the eighth PMOS transistor is connected to the drain terminal of the fourth PMOS transistor via the second capacitor. The gate terminal of the seventh PMOS transistor is connected to a fifth bias voltage via a first switch, and the gate terminal of the eighth PMOS transistor is connected to the fifth bias voltage via a second switch. The drain terminal of the seventh PMOS transistor is connected to the source terminal of the ninth PMOS transistor, and the drain terminal of the eighth PMOS transistor is connected to... The source terminal of the tenth PMOS transistor, the gate terminal of the ninth PMOS transistor, and the gate terminal of the tenth PMOS transistor are connected to a third bias voltage. The drain terminal of the ninth PMOS transistor is connected to the drain terminal of the first NMOS transistor, and the drain terminal of the tenth PMOS transistor is connected to the drain terminal of the second NMOS transistor. The drain terminals of the ninth and tenth PMOS transistors together constitute a third signal output terminal, outputting a third output signal. The gate terminals of the first and second NMOS transistors are connected to a fourth bias voltage. The source terminal of the first NMOS transistor is connected to the drain terminal of the third NMOS transistor, and the source terminal of the third NMOS transistor is grounded. The source terminal of the second NMOS transistor is connected to the drain terminal of the fourth NMOS transistor.The source terminal of the fourth NMOS transistor is grounded. The gate terminals of the third and fourth NMOS transistors are connected to the drain terminal of the ninth PMOS transistor via the third capacitor. The gate terminals of the third and fourth NMOS transistors are connected to the drain terminal of the tenth PMOS transistor via the fourth capacitor. The gate terminals of the third and fourth NMOS transistors are connected to the sixth bias voltage via a series-connected third and fourth switch. The drain terminal of the ninth PMOS transistor is connected to the common-mode voltage via a series-connected fifth and sixth switch. The drain terminal of the tenth PMOS transistor is connected to the common-mode voltage via a series-connected seventh and eighth switch. The fifth capacitor is connected between the connection points of the third and fourth switches and the connection points of the fifth and sixth switches. The sixth capacitor is connected between the connection points of the third and fourth switches and the connection points of the seventh and eighth switches. The pre-amplifier signal voltage conversion module includes a zeroth PMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first resistor. The second resistor is used to connect the source of the zeroth PMOS transistor to a high-voltage power supply, the gate of the zeroth PMOS transistor to a zeroth bias voltage, and the drain of the zeroth PMOS transistor to the sources of the first and second PMOS transistors. The gates of the first and second PMOS transistors together form a first signal input terminal to receive the high-voltage input signal. The drain of the first PMOS transistor is grounded through the first resistor, and the drain of the second PMOS transistor is grounded through the second resistor. The drains of the first and second PMOS transistors together form a first signal output terminal to output the low-voltage input signal. The first resistor is configured such that when the first PMOS transistor is turned on, the product of the current flowing through the first resistor and the resistance of the first resistor is less than 1.1V. The second resistor is configured such that when the second PMOS transistor is turned on, the product of the current flowing through the second resistor and the resistance of the second resistor is less than 1.1V. The low voltage is 1.1V, and the high voltage is 5V or 3V.

2. The high-speed high-voltage comparator according to claim 1, characterized in that, The first-stage amplifier includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third resistor, and a fourth resistor. The source terminal of the third PMOS transistor is connected to the low-voltage power supply, the gate terminal of the third PMOS transistor is connected to a first bias voltage, and the drain terminal of the third PMOS transistor is connected to the source terminals of the fourth and fifth PMOS transistors. The gate terminals of the fourth and fifth PMOS transistors together form a second signal input terminal to receive a second input signal. The drain terminal of the fourth PMOS transistor is grounded through the third resistor, and the drain terminal of the fifth PMOS transistor is grounded through the fourth resistor. The drain terminals of the fourth and fifth PMOS transistors together form a second signal output terminal to output a second output signal.

3. The high-speed high-voltage comparator according to claim 1, characterized in that, The structure of the Nth stage amplifier is the same as that of the second stage amplifier. The Nth stage amplifier has a fourth signal input terminal, a fourth signal output terminal, a seventh capacitor, and an eighth capacitor. The fourth signal input terminal receives a fourth input signal and is connected to the third signal output terminal via the seventh capacitor and the eighth capacitor. The fourth signal output terminal outputs a fourth output signal.

4. The high-speed high-voltage comparator according to claim 3, characterized in that, The post-signal latching module includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a ninth capacitor, and a tenth capacitor. The source terminal of the sixteenth PMOS transistor is connected to the low-voltage power supply, the gate terminal of the sixteenth PMOS transistor is connected to the latching signal, and the drain terminal of the sixteenth PMOS transistor is connected to the source terminal of the seventeenth PMOS transistor and the eighteenth PMOS transistor. The source terminal of the transistor, the gate terminal of the seventeenth PMOS transistor, and the gate terminal of the eighteenth PMOS transistor together constitute the fifth signal input terminal, receiving the fifth input signal. This signal is connected to the fourth signal output terminal via the ninth capacitor and the tenth capacitor. The gate terminal of the seventeenth PMOS transistor is connected to the fifth bias voltage via the ninth switch, and the gate terminal of the eighteenth PMOS transistor is also connected to the fifth bias voltage via the tenth switch. The drain terminal of the seventeenth PMOS transistor is connected to the source terminal of the nineteenth PMOS transistor and the drain terminal of the ninth NMOS transistor. The source terminal of the ninth NMOS transistor is grounded. The drain of the eighteenth PMOS transistor is connected to the source of the twentieth PMOS transistor and the drain of the fourteenth NMOS transistor, with the source of the fourteenth NMOS transistor grounded. The gate of the nineteenth PMOS transistor is connected to the gate of the eleventh NMOS transistor, the drain of the twelfth NMOS transistor, and the drain of the thirteenth NMOS transistor, with the source of the thirteenth NMOS transistor grounded. The gate of the twentieth PMOS transistor is connected to the gate of the twelfth NMOS transistor, the drain of the eleventh NMOS transistor, and the drain of the tenth NMOS transistor, with the source of the tenth NMOS transistor grounded. The drain of the nineteenth PMOS transistor is connected to the drain of the eleventh NMOS transistor, and the drain of the twentieth PMOS transistor is connected to the drain of the twelfth NMOS transistor. The drains of the nineteenth PMOS transistor and the twentieth PMOS transistor together constitute the fifth signal output terminal, outputting the fifth output signal. The drain of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are grounded. The gates of the ninth NMOS transistor, the tenth NMOS transistor, the thirteenth NMOS transistor, and the fourteenth NMOS transistor are all connected to the latch signal.

5. The high-speed high-voltage comparator according to claim 1, characterized in that, The high-speed high-voltage comparator also includes a digital logic circuit, which is connected to the post-signal latch module, receives the signal output by the post-signal latch module, processes it, and generates a comparison result.

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