Multi-mode switching decoding method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a multi-mode switching decoding method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the coding of to-be-coded data, and obtaining coded data; in the low-power-consumption decoding mode, decoding the coded data according to the check matrix and the adaptive unit to obtain decoded data corresponding to the low-power-consumption decoding mode; the adaptive unit provides first verification data; if decoding of the coded data fails in the low-power-consumption decoding mode, switching the low-power-consumption decoding mode to a high-performance decoding mode; in the high-performance decoding mode, decoding the coded data according to the check matrix and the calculation unit to obtain decoded data corresponding to the high-performance decoding mode; and the calculation unit calculates to obtain second verification data, wherein the second verification data is used for updating the first verification data. According to the embodiment of the invention, different error code scenes are flexibly adapted through a low-power-consumption decoding mode and a high-performance decoding mode.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of wireless communication error correction, and in particular to a multi-mode switching decoding method, a multi-mode switching decoding device, an electronic device, and a computer-readable storage medium. Background Art

[0002] In the field of SSD (Solid State Dis) storage, the industry has generally begun to adopt an error correction code, which is a low-density parity check code (LDPC code). As a forward error correction technology, LDPC (Low Density Parity Check Code) has excellent error correction capabilities, and its error correction capability can approach the Shannon limit (also known as channel capacity). The excellent error correction capability of LDPC makes it a widely used error correction code in the current SSD storage field. However, with the continuous increase in the number of 3D FLASH (flash memory) stacking layers and the increase in storage unit density, the increase in the read and write error rate of NAND (a non-volatile storage unit), the error correction capability requirements for LDPC codewords are also increasing. In order to adapt to more demanding storage scenarios, the industry has begun to develop in the direction of high code rate and large codewords, and has begun to increase the code length of LDPC from 2KB to 4KB, 8KB, and even 16KB to improve the error correction capability of LDPC. However, as the LDPC codeword increases, the check matrix also increases, and the decoding power consumption and decoding delay of LDPC also increase significantly. The increase in decoding latency will seriously affect the system's decoding throughput and the SSD flash read performance. The increase in codewords will also increase decoding power consumption and hardware costs.

[0003] In actual application scenarios, in most cases, the error rate of SSD reading and writing is low, and only in very rare cases will a large number of errors appear in an LDPC codeword. However, during the decoding process, LDPC does not distinguish the number of input errors, which makes the error correction capability of LDPC codewords excessive in most cases, resulting in unnecessary consumption of power. Summary of the invention

[0004] The embodiments of the present invention provide a multi-mode switching decoding method, device, electronic device and computer-readable storage medium to solve the problem in the prior art that only a single decoding mode will lead to increased decoding power consumption and decoding delay.

[0005] The embodiment of the present invention discloses a multi-mode switching decoding method, the method comprising:

[0006] Encoding the data to be encoded to obtain encoded data;

[0007] In the low power decoding mode, the coded data is decoded according to the check matrix and the adaptive unit to obtain the decoded data corresponding to the low power decoding mode; the adaptive unit is used to provide the first check data in the low power decoding mode;

[0008] If the encoded data fails to be decoded in the low-power decoding mode, switching the low-power decoding mode to a high-performance decoding mode, and switching the adaptive unit to a computing unit;

[0009] In the high-performance decoding mode, the encoded data is decoded according to the check matrix and the calculation unit to obtain decoded data corresponding to the high-performance decoding mode; the calculation unit is used to calculate and obtain second check data in the high-performance decoding mode, and the second check data is used to update the first check data.

[0010] Optionally, the check matrix includes a plurality of variable nodes, and in the low power decoding mode, decoding the coded data according to the check matrix and the adaptive unit to obtain decoded data corresponding to the low power decoding mode includes:

[0011] Initializing the plurality of variable nodes according to the encoded data to obtain log-likelihood ratios corresponding to the plurality of variable nodes;

[0012] determining, in the adaptive unit, the first verification data;

[0013] Update the log-likelihood ratios corresponding to the plurality of variable nodes according to the first verification data to obtain first posterior log-likelihood ratios corresponding to the plurality of variable nodes;

[0014] The decoding data corresponding to the low power decoding mode is determined according to the first a posteriori log-likelihood ratios corresponding to the plurality of variable nodes.

[0015] Optionally, the check matrix further includes a plurality of check nodes, and in the high-performance decoding mode, decoding the coded data according to the check matrix and the calculation unit to obtain decoded data corresponding to the high-performance decoding mode includes:

[0016] After obtaining the log-likelihood ratios corresponding to the plurality of variable nodes, collecting the check messages sent by the target variable nodes connected to each check node in the check matrix;

[0017] Calculate the product of the symbol values ​​corresponding to the plurality of verification messages to obtain a target symbol value;

[0018] Determine the minimum value among the absolute values ​​corresponding to the plurality of verification messages as the target absolute value;

[0019] multiplying a normalization factor, the target symbol value and the target absolute value to obtain the second verification data;

[0020] Update the log-likelihood ratios corresponding to the plurality of variable nodes according to the second verification data to obtain second posterior log-likelihood ratios corresponding to the plurality of variable nodes;

[0021] The decoding data corresponding to the high-performance decoding mode is determined according to the second a posteriori log-likelihood ratios corresponding to the plurality of variable nodes.

[0022] Optionally, determining the decoding data corresponding to the low power decoding mode according to the first a posteriori log-likelihood ratios corresponding to the plurality of variable nodes includes:

[0023] When the first posterior log-likelihood ratio corresponding to the variable node is greater than the decision threshold, determining the decision result corresponding to the variable node as a first preset value;

[0024] When the first posterior log-likelihood ratio corresponding to the variable node is greater than the decision threshold, determining the decision result corresponding to the variable node as a second preset value;

[0025] The decision results corresponding to the plurality of variable nodes are concatenated to obtain decoding data corresponding to the low power decoding mode.

[0026] Optionally, after obtaining the decoded data corresponding to the high-performance mode, the method further includes:

[0027] determining an average value between the first verification data and the second verification data as updated verification data;

[0028] The updated verification data replaces the first verification data in the adaptive unit to update the first verification data.

[0029] Optionally, the low power consumption decoding mode is a default decoding mode, and after obtaining the decoding data corresponding to the high performance mode, the method further includes:

[0030] Increasing the number of failures corresponding to the low power decoding mode by one;

[0031] When the number of failures corresponding to the low power decoding mode is greater than a failure threshold, the default decoding mode is switched to the high performance decoding mode.

[0032] Optionally, encoding the data to be encoded to obtain the encoded data includes:

[0033] Performing operations on the check matrix and the data to be encoded to obtain a check bit;

[0034] The check bit is superimposed on the data to be encoded to obtain the encoded data.

[0035] The embodiment of the present invention further discloses a multi-mode switching decoding device, the device comprising:

[0036] An encoding module, used for encoding the data to be encoded to obtain encoded data;

[0037] A low-power decoding module, used for decoding the coded data according to the check matrix and the adaptive unit in the low-power decoding mode to obtain the decoded data corresponding to the low-power decoding mode; the adaptive unit is used for providing the first check data in the low-power decoding mode;

[0038] A switching module, configured to switch the low-power decoding mode to a high-performance decoding mode and switch the adaptive unit to a computing unit if the encoded data fails to be decoded in the low-power decoding mode;

[0039] A high-performance decoding module is used to decode the encoded data according to the check matrix and the calculation unit in the high-performance decoding mode to obtain decoded data corresponding to the high-performance decoding mode; the calculation unit is used to calculate and obtain second check data in the high-performance decoding mode, and the second check data is used to update the first check data.

[0040] The embodiment of the present invention further discloses an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0041] The memory is used to store computer programs;

[0042] The processor is used to implement the method described in the embodiment of the present invention when executing the program stored in the memory.

[0043] The embodiment of the present invention further discloses a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the embodiment of the present invention.

[0044] The embodiment of the present invention further discloses a computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the method described in the embodiment of the present invention.

[0045] The embodiments of the present invention include the following advantages:

[0046] In an embodiment of the present invention, the coded data is encoded to obtain the coded data; in a low-power decoding mode, the coded data is decoded according to a check matrix and an adaptive unit to obtain the decoded data corresponding to the low-power decoding mode; the adaptive unit is used to provide first verification data in the low-power decoding mode; if the decoding of the coded data fails in the low-power decoding mode, the low-power decoding mode is switched to a high-performance decoding mode, and the adaptive unit is switched to a calculation unit; in the high-performance decoding mode, the coded data is decoded according to the check matrix and the calculation unit to obtain the decoded data corresponding to the high-performance decoding mode; the calculation unit is used to calculate and obtain second verification data in the high-performance decoding mode, and the second verification data is used to update the first verification data.

[0047] The decoding method provided by the embodiment of the present invention provides two modes during decoding: a low-power decoding mode and a high-performance decoding mode, so as to flexibly adapt to different error scenarios. The low-power decoding mode can provide better power characteristics in low-error scenarios, and the high-performance decoding mode can ensure the error correction performance in high-error scenarios, wherein the low-power decoding mode is the default decoding mode, and in the case of decoding failure in the low-power decoding mode, it will automatically switch to the high-performance decoding mode to ensure the final decoding performance. Secondly, the first check data required in the low-power decoding mode can be updated adaptively, thereby optimizing the error correction performance of the low-power decoding mode, and on the basis of the low-power decoding mode, the second check data is calculated by the calculation unit, thereby achieving an improvement in error correction performance, and compared with a single high-performance decoding mode, the logic resources will be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a schematic diagram of an application environment provided in an embodiment of the present invention;

[0049] Figure 2 is a flowchart of a multi-mode switching decoding method provided in an embodiment of the present invention;

[0050] Figure 3 is a system block diagram of a decoding method for implementing multi-mode switching provided in an embodiment of the present invention;

[0051] Figure 4 is a processing flow chart of automatic switching of a decoding mode provided in an embodiment of the present invention;

[0052] Figure 5 is a structural block diagram of a multi-mode switching decoding device provided in an embodiment of the present invention;

[0053] Figure 6is a schematic diagram of the hardware structure of an electronic device for implementing various embodiments of the present invention;

[0054] Figure 7 is a schematic diagram of a computer-readable medium provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] Taking the SSD application scenario as an example, in order to adapt to scenarios with higher error correction requirements and improve the error correction capability of LDPC, the industry generally chooses a larger LDPC codeword. In the decoding stage, the existing technology usually uses a single decoding mode to decode the data read from the SSD. In this decoding process, after the encoded data (data to be decoded) is read from the storage module, it enters the LDPC decoder. The decoder has only one operating mode and does not distinguish between low power and high performance modes. The data to be decoded is decoded in the LDPC decoder according to a unified mode, and the decoded data is output after the decoding is completed.

[0057] Therefore, in the LDPC decoding scheme of the prior art, a single decoding mode is used for decoding. In order to cover the worst error scenario, the LDPC decoding capability needs to always work in a high-performance single mode. For most scenarios, the error rate of LDPC codewords is low, and the performance requirements for LDPC are not high. When decoding according to the worst scenario, the LDPC error correction capability is over-designed, which will cause unnecessary consumption of power consumption, thereby increasing the chip heat dissipation cost.

[0058] In view of the problem that the decoding mode in the prior art is single and the decoding mode cannot be flexibly switched to adapt to different bit error scenarios, causing the system to always work in the high-performance mode and resulting in high power consumption, the embodiment of the present invention proposes a multi-mode switching LDPC decoding method, which provides two modes of low power consumption and high performance during decoding to adapt to different bit error scenarios, wherein the low power consumption mode is the default working mode. In the low power consumption mode, the system decoding power consumption is low, which is more green and low-carbon. The high-performance mode is for a few high-bit error scenarios. In the case of decoding failure in the low power consumption mode, it automatically switches to the high-performance mode to ensure the final decoding performance. Because in the low power consumption mode, the decoding calculation is simple and the logic complexity is low, the power consumption is low. This scenario can adapt to most bit error scenarios, and the high-performance mode, as a performance guarantee solution, can ensure the final decoding performance of LDPC.

[0059] Reference Figure 1, shows a schematic diagram of an application environment provided in an embodiment of the present invention, which specifically includes three parts: an LDPC encoder, a data storage module and an LDPC decoder. The LDPC encoder is used to encode the data to be encoded to obtain the encoded data, the data storage module is used to store the encoded data and provide the encoded data to the LDPC decoder, and the LDPC decoder is used to decode the encoded data.

[0060] Reference Figure 2 , shows a flowchart of a multi-mode switching decoding method provided in an embodiment of the present invention, which may specifically include the following steps:

[0061] Step 201, encode the data to be encoded to obtain encoded data;

[0062] like Figure 1 As shown, in an embodiment of the present invention, the data to be encoded is read from the SSD, and the data to be encoded is input into the LDPC encoder for encoding to obtain encoded data, and the encoded data is transmitted to the data storage module through the channel for storage. Specifically, the LDPC encoder generates check bits using a predefined check matrix, and appends these check bits to the original data to form an LDPC codeword (encoded data).

[0063] In the actual encoding process, the coded data obtained includes the data to be encoded and the check bits. Subsequently, in the LDPC decoding process, the LDPC decoder will use the combination of these check bits and the data to be encoded (i.e., the coded data) to try to recover the data to be encoded that may be erroneous. If errors occur in the data during transmission, the LDPC decoder can identify and correct these errors through the check bits, thereby ensuring the accuracy and reliability of the data. Among them, the check bits are used to detect and correct errors that may occur during data transmission at the receiving end.

[0064] In the LDPC decoder in the embodiment of the present invention, there are two decoding modes, namely a low power decoding mode and a high performance decoding mode. The decoding algorithm adopted in the embodiment of the present invention is the normalized minimum sum algorithm (NMS algorithm).

[0065] In the NMS algorithm, each decoding iteration process involves the update calculation of the check node. It is necessary to calculate the minimum value of each row of check nodes and use the calculated minimum value to update the variable node. In decoding, it is also necessary to use the predefined check matrix. The specific calculation is as follows:

[0066] 1) Initialization: For each variable node i, L(P i ) for initialization (related to the noise variance, a fixed value is taken during hard decoding).

[0067] The initialization formula is shown in formula (1):

[0068] L(P i )=2a*y n / σ 2 (1)

[0069]

[0070] Among them, L(P i ) is the log-likelihood ratio (LLR) corresponding to variable node i, y n is the received value after noise superposition, σ 2 is the logarithmic standard deviation, a is obtained by the above formula (2), E s is the average energy of the signal.

[0071] 2) Check node update: Calculate the minimum value of each row of check nodes and use this minimum value to update the corresponding variable nodes.

[0072] The specific formula is as shown in formula (3):

[0073]

[0074] Among them, L (l) (r ji ) is used to represent the message sent by variable node i to check node j, α is the normalization factor, ∏ represents the product operation, sgn(L (l-1) (q i′j ) represents the message q from variable node i to check node j' at the (l-1)th iteration i′j The symbol of i′∈R j / i is used to indicate traversing all variable nodes i connected to check node j, min indicates taking the minimum value operation, |L (l-1) (q i′j )|is used to represent the message q from variable node i to check node j at the (l-1)th iteration i′j The absolute value of (l) represents the lth iteration, and (l-1) represents the (l-1)th iteration. For the normalization factor α, the value range is 0<α≤1. In the NMS algorithm, α=1.

[0075] 3) Update variable nodes, as shown in formulas (4) and (5):

[0076]

[0077] Among them, L (l) (q ij ) is used to represent the message sent by the verification node j to the variable node i, L(P i) is the log-likelihood ratio corresponding to variable node i, L (l) (r j′i ) is used to represent the message sent by variable node i to check node j', (l) is used to represent the lth iteration, C i It is used to represent the set of all check nodes connected to variable node i, C i\j It is used to represent the set of check nodes connected to the variable node i except the check node j; in the low-power decoding mode, L (l) (r ji ) and L (1) (r j，i ) is used to represent the first verification data, L (l) (Q i ) is used to represent the first a posteriori log-likelihood ratio corresponding to the variable node i; in the high-performance decoding mode, L (1) (r ji ) and L (1) (r j′i ) is used to represent the second verification data, L (l) (Q i ) is used to represent the second posterior log-likelihood ratio corresponding to variable node i.

[0078] 4) Judgment, as shown in formula (6):

[0079]

[0080] in, Used to indicate the decision result corresponding to variable node i.

[0081] Reference Figure 3 , shows a system block diagram of a decoding method for implementing multi-mode switching provided in an embodiment of the present invention.

[0082] Step 202: In the low power decoding mode, the coded data is decoded according to the check matrix and the adaptive unit to obtain the decoded data corresponding to the low power decoding mode; the adaptive unit is used to provide the first check data in the low power decoding mode;

[0083] In the embodiment of the present invention, the coded data is sent to the LDPC decoder and decoded using the low power decoding mode to obtain decoded data corresponding to the low power decoding mode. Specifically, in the low power decoding mode, Figure 3 As shown, a preset minimum value (first check data) can be provided by the adaptive unit to replace the traditional minimum value calculation, that is, the above formula (3), thereby reducing the calculation complexity and power consumption. At the same time, because there is no need to calculate the minimum value through loop iteration, the decoding delay is lower.

[0084] A check equation is defined in the check matrix. The check matrix is ​​used to detect and correct errors during the decoding process. The decoder needs to decode according to the check equation and the data provided by the adaptive unit to try to recover the encoded data.

[0085] In the LDPC encoding and decoding process, the same check matrix is ​​used. The check matrix is ​​usually a sparse matrix, that is, most of the elements are zero, and only a few elements are non-zero values. This sparsity is an important feature of LDPC codes, which makes the computational complexity of the encoding and decoding process relatively low. The check matrix plays a core role in both the encoding and decoding processes, but its use is different. Specifically, in the LDPC encoding process, the check matrix is ​​used to generate check bits. Specifically, the data to be encoded generates check bits by operating with the check matrix, and then these check bits are attached to the data to be encoded to form a complete LDPC codeword (data to be encoded). This process ensures that the codeword satisfies the check equation defined by the check matrix; in the LDPC decoding process, the check matrix is ​​used to detect and correct errors. The decoder uses the received codeword (which may contain errors) and the check matrix to perform the decoding algorithm. The decoder iteratively updates the messages of the variable nodes and the check nodes, and finally tries to recover the data to be encoded. The check matrix defines here which variable nodes and check nodes are connected, and how to pass messages and update through these connections.

[0086] Step 203: If the encoded data fails to be decoded in the low-power decoding mode, the low-power decoding mode is switched to a high-performance decoding mode, and the adaptive unit is switched to a computing unit;

[0087] In the embodiment of the present invention, if the decoder cannot successfully recover the data to be encoded (i.e., decoding fails) in the low-power decoding mode, the system will automatically switch to the high-performance decoding mode. Figure 3 As shown, the adaptive unit will be switched to the computing unit, and the computing unit will perform the complete check node update calculation, that is, the above formula (3). The calculation process is not simplified, ensuring that the system can still provide sufficient error correction performance in high bit error rate scenarios.

[0088] Step 204: In the high-performance decoding mode, the encoded data is decoded according to the check matrix and the calculation unit to obtain decoded data corresponding to the high-performance decoding mode; the calculation unit is used to calculate and obtain second check data in the high-performance decoding mode, and the second check data is used to update the first check data.

[0089] In the embodiment of the present invention, when switching from the low power consumption decoding mode to the high performance decoding mode, as shown in FIG. Figure 3As shown, the decoder uses the more accurate verification data (second verification data) provided by the calculation unit for decoding. The second verification data is obtained by performing a complete verification node update calculation, so it can provide higher error correction performance. The calculation unit not only calculates new verification data, but also uses these data to update the verification data (first verification data) in the low power mode to optimize the subsequent decoding process. Finally, the decoder outputs the accurate recovery of the data to be encoded, that is, the final decoded data.

[0090] Reference Figure 4 , showing a processing flow chart of automatic switching of a decoding mode provided by an embodiment of the present invention. The low-power decoding mode and the high-performance decoding mode are essentially serial modes. The low-power decoding mode is used as the default decoding mode. Low-power decoding is performed first. When the low-power decoding fails, high-performance decoding is started. Then, when the next codeword is decoded, it will switch back to the low-power decoding mode.

[0091] In the embodiment of the present invention, Figure 3 and Figure 4 The selector shown in is used to confirm which of the low-power decoding and the high-performance decoding is successful, and then output the decoding data corresponding to the successful decoding.

[0092] The multi-mode switching decoding method provided by the embodiment of the present invention provides two modes during decoding: a low-power decoding mode and a high-performance decoding mode, so as to flexibly adapt to different error scenarios. The low-power decoding mode can provide better power characteristics in low-error scenarios, and the high-performance decoding mode can ensure the error correction performance in high-error scenarios, wherein the low-power decoding mode is the default decoding mode, and in the case of decoding failure in the low-power decoding mode, it will automatically switch to the high-performance decoding mode to ensure the final decoding performance. Secondly, the first check data required in the low-power decoding mode can be updated adaptively, thereby optimizing the error correction performance of the low-power decoding mode, and on the basis of the low-power decoding mode, the second check data is calculated by the calculation unit, thereby achieving an improvement in error correction performance, and compared with a single high-performance decoding mode, the logic resources will be reduced.

[0093] In an embodiment of the present invention, the check matrix includes a plurality of variable nodes, and in the low power decoding mode, decoding the coded data according to the check matrix and the adaptive unit to obtain the decoded data corresponding to the low power decoding mode includes:

[0094] Initializing the plurality of variable nodes according to the encoded data to obtain log-likelihood ratios corresponding to the plurality of variable nodes;

[0095] determining, in the adaptive unit, the first verification data;

[0096] Update the log-likelihood ratios corresponding to the plurality of variable nodes according to the first verification data to obtain first posterior log-likelihood ratios corresponding to the plurality of variable nodes;

[0097] The decoding data corresponding to the low power decoding mode is determined according to the first a posteriori log-likelihood ratios corresponding to the plurality of variable nodes.

[0098] In the embodiment of the present invention, firstly, the multiple variable nodes are initialized according to the received coded data (the received coded data will be affected by noise at this time) to obtain the log-likelihood ratio (LLR) corresponding to each variable node, which is specifically obtained by the above formulas (1) and (2). These LLR values ​​reflect the reliability of the signal received by each variable node at the receiving end; it is also necessary to determine the first verification data in the adaptive unit, and the adaptive unit provides a preset minimum value to replace the minimum value calculation in the above formula (3), thereby reducing the calculation complexity and power consumption; then, the log-likelihood ratios corresponding to the multiple variable nodes are updated using the first verification data to obtain the first a posteriori log-likelihood ratio corresponding to each variable node, which is specifically obtained by the above formulas (4) and (5). By combining the data provided by the adaptive unit and the structure of the check matrix, the estimation of the variable node state is optimized; finally, according to the first a posteriori log-likelihood ratios corresponding to the multiple variable nodes, the decoding data corresponding to the low power decoding mode is determined, which is specifically determined by the above formula (6), that is, by comparing the signs of the a posteriori log-likelihood ratios, a final bit value decision is made to obtain the final decoding data.

[0099] Specifically, the log-likelihood ratio corresponding to the variable node is L(P i ), the encoded data is y n , the first verification data is L (1) (r ji ), the first posterior log-likelihood ratio corresponding to the variable node is L (1) (Q i ).

[0100] The embodiment of the present invention introduces an adaptive unit to replace the traditional minimum value calculation, and then provides the first check data, which can significantly reduce the computational complexity and power consumption in the LDPC decoding process, making the low-power decoding mode particularly suitable for most scenarios with low bit error rates, effectively reducing system energy consumption. At the same time, the design of the adaptive unit optimizes the decoding process, simplifies the calculation steps, and improves the decoding efficiency. Although the calculation is simplified in the low-power mode, the synergy of the check matrix and the adaptive unit ensures the performance of the decoder in detecting and correcting errors. By iteratively updating the log-likelihood ratio, the real original data is gradually approached, ensuring the accuracy and reliability of the decoding. In addition, the flexible design of the low-power decoding mode enables the system to automatically adjust the working mode according to different bit error scenarios. It can operate in low-power mode in most cases, and switch to high-performance mode in a few high-error scenarios, thereby fully guaranteeing the overall performance of the system.

[0101] Furthermore, the low-power decoding mode provided in the embodiment of the present invention can significantly reduce the decoding delay and increase the system throughput.

[0102] In an embodiment of the present invention, the check matrix further includes a plurality of check nodes, and in the high-performance decoding mode, decoding the coded data according to the check matrix and the calculation unit to obtain decoded data corresponding to the high-performance decoding mode includes:

[0103] After obtaining the log-likelihood ratios corresponding to the plurality of variable nodes, collecting the check messages sent by the target variable nodes connected to each check node in the check matrix;

[0104] Calculate the product of the symbol values ​​corresponding to the plurality of verification messages to obtain a target symbol value;

[0105] Determine the minimum value among the absolute values ​​corresponding to the plurality of verification messages as the target absolute value;

[0106] multiplying a normalization factor, the target symbol value and the target absolute value to obtain the second verification data;

[0107] Update the log-likelihood ratios corresponding to the plurality of variable nodes according to the second verification data to obtain second posterior log-likelihood ratios corresponding to the plurality of variable nodes;

[0108] The decoding data corresponding to the high-performance decoding mode is determined according to the second a posteriori log-likelihood ratios corresponding to the plurality of variable nodes.

[0109] In the embodiment of the present invention, the high-performance decoding mode is based on the low-power decoding mode, and the calculation unit replaces the adaptive unit to calculate the minimum value (second verification data). Therefore, after obtaining the log-likelihood ratio corresponding to each variable node, the decoder will collect the verification messages sent by the target variable node connected to each verification node in the check matrix, and these verification messages contain the variable node's estimation of its own state.

[0110] In the calculation unit, the symbol values ​​corresponding to the multiple verification messages are multiplied to obtain the target symbol value, the purpose of which is to provide a unified symbol judgment for the verification node by integrating the symbol information of all relevant variable nodes; then, among the absolute values ​​corresponding to the multiple verification messages, the minimum value is determined as the target absolute value, the purpose of which is to provide a key reference value for the verification node by finding the minimum absolute value; finally, the normalization factor, the target symbol value and the target absolute value are multiplied to obtain the second verification data, the purpose of which is to generate key data for updating the log-likelihood ratio of the variable node by combining the normalization factor and the target symbol value with the absolute value. The calculation unit specifically implements the calculation process of the above formula (3).

[0111] Specifically, the second posterior log-likelihood ratio corresponding to the variable node is L (l) (Q i ), the check message sent by the target variable node connected to each check node in the check matrix is ​​L (l-1) (q i′j ), the target symbol value is sgn(L (l-1) (q i′j ), the target absolute value is

[0112] In the high-performance decoding mode of the embodiment of the present invention, by introducing a calculation unit to accurately calculate the minimum value (the second check data), the error correction capability and decoding performance of LDPC decoding are significantly improved. The high-performance decoding mode is particularly effective when processing high bit error rate scenarios, and can ensure that the decoder can still accurately recover the data to be decoded in a complex environment, thereby enhancing the robustness and reliability of the system. At the same time, the flexible design of the high-performance decoding mode enables the system to automatically adjust the working mode according to different bit error scenarios, and can operate in low-power mode in most cases, and switch to high-performance mode in a few high-error scenarios, thereby comprehensively improving the overall performance and throughput of the system.

[0113] In the embodiment of the present invention, the first a posteriori log-likelihood ratio corresponding to the variable node or the second a posteriori log-likelihood ratio corresponding to the variable node is calculated by the above formulas (4) and (5).

[0114] In an embodiment of the present invention, determining the decoding data corresponding to the low power decoding mode according to the first a posteriori log-likelihood ratios corresponding to the plurality of variable nodes includes:

[0115] When the first posterior log-likelihood ratio corresponding to the variable node is greater than the decision threshold, determining the decision result corresponding to the variable node as a first preset value;

[0116] When the first posterior log-likelihood ratio corresponding to the variable node is greater than the decision threshold, determining the decision result corresponding to the variable node as a second preset value;

[0117] The decision results corresponding to the plurality of variable nodes are concatenated to obtain decoding data corresponding to the low power decoding mode.

[0118] In the decoding process of the embodiment of the present invention, a decision threshold is set to distinguish the positive and negative of the first a posteriori log-likelihood ratio corresponding to the variable node. This threshold is usually zero because the sign of the log-likelihood ratio (LLR) determines the bit value of the variable node. Specifically, when the first a posteriori log-likelihood ratio corresponding to the variable node is greater than the decision threshold (usually zero), the decision result corresponding to the variable node is determined as the first preset value. In a binary system, the first preset value is usually 0; when the first a posteriori log-likelihood ratio corresponding to the variable node is less than the decision threshold (usually zero), the decision result corresponding to the variable node is determined as the second preset value. In a binary system, the second preset value is usually 1. Subsequently, the decision results corresponding to all variable nodes are spliced ​​to obtain the decoding data corresponding to the low-power decoding mode, in order to combine the bit values ​​of each variable node to form a complete decoding data.

[0119] Specifically referring to the above formula (6), the decision result corresponding to the variable node is

[0120] When the log likelihood ratio is equal to zero, theoretically, the probability of the bit value corresponding to the variable node being 0 and 1 is equal. However, in practical applications, due to the uncertainty of noise and signal transmission, it is very rare for the log likelihood ratio to be exactly equal to zero. Therefore, in the judgment process of the embodiment of the present invention, even if the situation where the log likelihood ratio is equal to zero exists in theory, this situation is usually not handled separately in practical applications.

[0121] In another embodiment of the present invention, when P(0) / P(1), the decision is made in the above manner. If it is changed to P(1) / P(0), the decision is opposite to the above manner, wherein P(0) represents the probability of sending a bit value of 0, and P(1) represents the probability of sending a bit value of 1. By distinguishing different decision modes, the LDPC decoder can adapt to different channel conditions, optimize decoding performance, enhance flexibility and robustness, and improve decoding efficiency. The decoder can select the decision mode that best suits the current channel conditions, so that it can accurately and efficiently perform decoding in various environments, ensuring the reliability and performance of data transmission. This flexible decision strategy enables the decoder to dynamically adapt to channel changes, improving its adaptability and overall performance in practical applications.

[0122] The embodiment of the present invention simplifies the decision logic by setting the decision threshold (usually zero), improves the efficiency of the low-power decoding mode, and adapts to different probability ratios, reduces the probability of misjudgment, and optimizes the decoding performance. This design is not only intuitive and efficient in binary systems, but also can flexibly adjust the decision mode to ensure the integrity and consistency of the decoded data, thereby ensuring the accuracy of decoding while enhancing the flexibility and adaptability of the decoder, making the LDPC decoding method more efficient, reliable and adaptable in practical applications.

[0123] In an embodiment of the present invention, after obtaining the decoded data corresponding to the high performance mode, the method further includes:

[0124] determining an average value between the first verification data and the second verification data as updated verification data;

[0125] The updated verification data replaces the first verification data in the adaptive unit to update the first verification data.

[0126] In the embodiment of the present invention, after the high-performance decoding mode is ended each time, the minimum value data calculated by the above formula (3) will be used as correction data to update the minimum adaptive data in the low-power decoding mode, and the adaptive minimum value data update method is the average value of the original data and the correction data. Specifically, the average value between the first verification data and the second verification data is determined as the updated verification data, and then the updated verification data replaces the first verification data in the adaptive unit to update the first verification data.

[0127] The embodiment of the present invention combines the verification data of the low power mode and the high performance mode to generate a new verification data to optimize the performance of the adaptive unit, thereby adaptively optimizing the error correction performance in the low power decoding mode, and ensuring that the adaptive unit can be adjusted according to the latest decoding results, thereby improving the accuracy and reliability of decoding.

[0128] In an embodiment of the present invention, the low power consumption decoding mode is a default decoding mode, and after obtaining the decoding data corresponding to the high performance mode, the method further includes:

[0129] Increasing the number of failures corresponding to the low power decoding mode by one;

[0130] When the number of failures corresponding to the low power decoding mode is greater than a failure threshold, the default decoding mode is switched to the high performance decoding mode.

[0131] In the embodiment of the present invention, the initial default decoding mode is the low power decoding mode. After the decoding data corresponding to the high performance mode is obtained, that is, after the high performance decoding is completed, the number of decoding failures in the low power decoding mode is counted. When the number of failures exceeds the threshold, Figure 3 As shown, the decoding mode control unit switches the default decoding mode to the high-performance mode, and the low-power mode is no longer enabled. Specifically, the number of failures corresponding to the low-power decoding mode is increased by one, and when the number of failures corresponding to the low-power decoding mode is greater than the failure threshold, the default decoding mode is switched to the high-performance decoding mode.

[0132] The embodiment of the present invention records the number of failures in the low power mode and monitors its performance to ensure that when the performance of the low power mode is poor, the system can automatically switch to the high performance mode to ensure the accuracy and reliability of decoding. The error correction performance is guaranteed by the high performance decoding mode. Compared with the traditional method, the highest error correction capability of the decoding method provided in the embodiment of the present invention is unchanged.

[0133] In one embodiment of the present invention, encoding the data to be encoded to obtain the encoded data includes:

[0134] Performing operations on the check matrix and the data to be encoded to obtain a check bit;

[0135] The check bit is superimposed on the data to be encoded to obtain the encoded data.

[0136] In an embodiment of the present invention, the data to be encoded is raw data, which needs to be converted into encoded data through the LDPC encoding process. The check matrix defines how to generate check bits from the data to be encoded. During the encoding process, the data to be encoded generates check bits through operations with the check matrix (such as matrix multiplication), and then these check bits are attached to the data to be encoded to form encoded data. The encoded data must satisfy the check equation defined by the check matrix. For example, in the binary domain, the product of the encoded data and the check matrix should be zero. Specifically, the number of rows of the check matrix determines the number of check bits, and the number of columns usually matches the length of the data to be encoded.

[0137] The decoding method provided by the embodiment of the present invention provides two modes during decoding: a low-power decoding mode and a high-performance decoding mode, so as to flexibly adapt to different error scenarios. The low-power decoding mode can provide better power characteristics in low-error scenarios, and the high-performance decoding mode can ensure the error correction performance in high-error scenarios, wherein the low-power decoding mode is the default decoding mode, and in the case of decoding failure in the low-power decoding mode, it will automatically switch to the high-performance decoding mode to ensure the final decoding performance. Secondly, the first check data required in the low-power decoding mode can be updated adaptively, thereby optimizing the error correction performance of the low-power decoding mode, and on the basis of the low-power decoding mode, the second check data is calculated by the calculation unit, thereby achieving an improvement in error correction performance, and compared with a single high-performance decoding mode, the logic resources will be reduced.

[0138] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0139] Reference Figure 5 , shows a structural block diagram of a multi-mode switching decoding device provided in an embodiment of the present invention, which may specifically include the following modules:

[0140] The encoding module 501 is used to encode the data to be encoded to obtain encoded data;

[0141] A low power decoding module 502, configured to decode the coded data according to the check matrix and the adaptive unit in the low power decoding mode to obtain decoded data corresponding to the low power decoding mode; the adaptive unit is configured to provide first check data in the low power decoding mode;

[0142] A switching module 503, configured to switch the low power decoding mode to a high performance decoding mode and switch the adaptive unit to a computing unit if the encoded data fails to be decoded in the low power decoding mode;

[0143] The high-performance decoding module 504 is used to decode the encoded data according to the check matrix and the calculation unit in the high-performance decoding mode to obtain the decoded data corresponding to the high-performance decoding mode; the calculation unit is used to calculate and obtain the second check data in the high-performance decoding mode, and the second check data is used to update the first check data.

[0144] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0145] In addition, an embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; the memory is used to store computer programs; the processor is used to implement the various processes of the above-mentioned multi-mode switching decoding method embodiment when executing the program stored in the memory, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0146] The embodiment of the present invention further provides a computer-readable storage medium, on which instructions are stored, and when executed by one or more processors, the processors execute the various processes of the above-mentioned multi-mode switching decoding method embodiment, and can achieve the same technical effect, to avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0147] An embodiment of the present invention also provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned multi-mode switching decoding method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0148] Figure 6 A schematic diagram of the hardware structure of an electronic device for implementing various embodiments of the present invention.

[0149] The electronic device 600 includes but is not limited to: a radio frequency unit 601, a network module 602, an audio output unit 603, an input unit 604, a sensor 605, a display unit 606, a user input unit 607, an interface unit 608, a memory 609, a processor 610, and a power supply 611. Those skilled in the art will appreciate that Figure 6 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. In the embodiments of the present invention, the electronic device includes but is not limited to a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted terminal, a wearable device, and a pedometer.

[0150] It should be understood that in the embodiment of the present invention, the radio frequency unit 601 can be used for receiving and sending signals during information transmission or communication. Specifically, after receiving downlink data from the base station, it is sent to the processor 610 for processing; in addition, uplink data is sent to the base station. Generally, the radio frequency unit 601 includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, etc. In addition, the radio frequency unit 601 can also communicate with the network and other devices through a wireless communication system.

[0151] The electronic device provides users with wireless broadband Internet access through the network module 602, such as helping users to send and receive emails, browse web pages, and access streaming media.

[0152] The audio output unit 603 can convert the audio data received by the RF unit 601 or the network module 602 or stored in the memory 609 into an audio signal and output it as sound. Moreover, the audio output unit 603 can also provide audio output related to a specific function performed by the electronic device 600 (for example, a call signal reception sound, a message reception sound, etc.). The audio output unit 603 includes a speaker, a buzzer, a receiver, etc.

[0153] The input unit 604 is used to receive audio or video signals. The input unit 604 may include a graphics processor (GPU) 6041 and a microphone 6042, and the graphics processor 6041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The processed image frame can be displayed on the display unit 606. The image frame processed by the graphics processor 6041 can be stored in the memory 609 (or other storage medium) or sent via the radio frequency unit 601 or the network module 602. The microphone 6042 can receive sound and can process such sound into audio data. The processed audio data can be converted into a format output that can be sent to a mobile communication base station via the radio frequency unit 601 in the case of a telephone call mode.

[0154] The electronic device 600 also includes at least one sensor 605, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 6061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 6061 and / or the backlight when the electronic device 600 is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally three axes), and can detect the magnitude and direction of gravity when stationary, which can be used to identify the posture of the electronic device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; the sensor 605 can also include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be repeated here.

[0155] The display unit 606 is used to display information input by the user or information provided to the user. The display unit 606 may include a display panel 6061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0156] The user input unit 607 can be used to receive input digital or character information, and to generate key signal input related to user settings and function control of the electronic device. Specifically, the user input unit 607 includes a touch panel 6071 and other input devices 6072. The touch panel 6071, also known as a touch screen, can collect the user's touch operation on or near it (such as the user's operation on the touch panel 6071 or near the touch panel 6071 using any suitable object or accessory such as a finger, stylus, etc.). The touch panel 6071 may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the processor 610, receives the command sent by the processor 610 and executes it. In addition, the touch panel 6071 can be implemented in various types such as resistive, capacitive, infrared and surface acoustic waves. In addition to the touch panel 6071, the user input unit 607 may also include other input devices 6072. Specifically, other input devices 6072 may include but are not limited to a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be described in detail here.

[0157] Furthermore, the touch panel 6071 may be overlaid on the display panel 6061. When the touch panel 6071 detects a touch operation on or near it, it is transmitted to the processor 610 to determine the type of touch event. Then, the processor 610 provides corresponding visual output on the display panel 6061 according to the type of touch event. Figure 6 In the figure, the touch panel 6071 and the display panel 6061 are used as two independent components to realize the input and output functions of the electronic device. However, in some embodiments, the touch panel 6071 and the display panel 6061 can be integrated to realize the input and output functions of the electronic device, which is not limited here.

[0158] The interface unit 608 is an interface for connecting an external device to the electronic device 600. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, etc. The interface unit 608 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the electronic device 600 or may be used to transmit data between the electronic device 600 and an external device.

[0159] The memory 609 can be used to store software programs and various data. The memory 609 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory 609 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0160] The processor 610 is the control center of the electronic device. It uses various interfaces and lines to connect various parts of the entire electronic device. By running or executing software programs and / or modules stored in the memory 609 and calling data stored in the memory 609, it performs various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. The processor 610 may include one or more processing units; preferably, the processor 610 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 610.

[0161] The electronic device 600 may also include a power supply 611 (such as a battery) for supplying power to each component. Preferably, the power supply 611 may be logically connected to the processor 610 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system.

[0162] In addition, the electronic device 600 includes some functional modules not shown, which will not be described in detail here.

[0163] like Figure 7 As shown, in another embodiment provided by the present invention, a computer-readable storage medium 701 is also provided, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer executes the decoding method for multi-mode switching described in the above embodiment.

[0164] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0165] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0166] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

[0167] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0168] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0169] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0170] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0171] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0172] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical disks.

[0173] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A decoding method for multi-mode switching, It is characterized in that The method comprises: Encoding the data to be encoded to obtain encoded data; In the low power decoding mode, the coded data is decoded according to the check matrix and the adaptive unit to obtain the decoded data corresponding to the low power decoding mode; the adaptive unit is used to provide the first check data in the low power decoding mode; If the encoded data fails to be decoded in the low-power decoding mode, switching the low-power decoding mode to a high-performance decoding mode, and switching the adaptive unit to a computing unit; In the high-performance decoding mode, the encoded data is decoded according to the check matrix and the calculation unit to obtain decoded data corresponding to the high-performance decoding mode; the calculation unit is used to calculate and obtain second check data in the high-performance decoding mode, and the second check data is used to update the first check data.

2. The method according to claim 1, It is characterized in that The check matrix includes a plurality of variable nodes. In the low power decoding mode, the coded data is decoded according to the check matrix and the adaptive unit to obtain the decoded data corresponding to the low power decoding mode, including: Initializing the plurality of variable nodes according to the encoded data to obtain log-likelihood ratios corresponding to the plurality of variable nodes; determining, in the adaptive unit, the first verification data; Update the log-likelihood ratios corresponding to the plurality of variable nodes according to the first verification data to obtain first posterior log-likelihood ratios corresponding to the plurality of variable nodes; The decoding data corresponding to the low power decoding mode is determined according to the first a posteriori log-likelihood ratios corresponding to the plurality of variable nodes.

3. The method according to claim 2, It is characterized in that The check matrix further includes a plurality of check nodes. In the high-performance decoding mode, decoding the coded data according to the check matrix and the calculation unit to obtain decoded data corresponding to the high-performance decoding mode includes: After obtaining the log-likelihood ratios corresponding to the plurality of variable nodes, collecting the check messages sent by the target variable nodes connected to each check node in the check matrix; Calculate the product of the symbol values ​​corresponding to the plurality of verification messages to obtain a target symbol value; Determine the minimum value among the absolute values ​​corresponding to the plurality of verification messages as the target absolute value; multiplying a normalization factor, the target symbol value and the target absolute value to obtain the second verification data; Update the log-likelihood ratios corresponding to the plurality of variable nodes according to the second verification data to obtain second posterior log-likelihood ratios corresponding to the plurality of variable nodes; The decoding data corresponding to the high-performance decoding mode is determined according to the second a posteriori log-likelihood ratios corresponding to the plurality of variable nodes.

4. The method according to claim 3, It is characterized in that The step of determining the decoding data corresponding to the low power decoding mode according to the first a posteriori log-likelihood ratios corresponding to the plurality of variable nodes comprises: When the first posterior log-likelihood ratio corresponding to the variable node is greater than the decision threshold, determining the decision result corresponding to the variable node as a first preset value; When the first posterior log-likelihood ratio corresponding to the variable node is greater than the decision threshold, determining the decision result corresponding to the variable node as a second preset value; The decision results corresponding to the plurality of variable nodes are concatenated to obtain decoding data corresponding to the low power decoding mode.

5. The method according to claim 3, It is characterized in that After obtaining the decoded data corresponding to the high performance mode, the method further includes: determining an average value between the first verification data and the second verification data as updated verification data; The updated verification data replaces the first verification data in the adaptive unit to update the first verification data.

6. The method according to claim 3, It is characterized in that The low power consumption decoding mode is a default decoding mode. After obtaining the decoding data corresponding to the high performance mode, the method further includes: Increasing the number of failures corresponding to the low power decoding mode by one; When the number of failures corresponding to the low power decoding mode is greater than a failure threshold, the default decoding mode is switched to the high performance decoding mode.

7. The method according to claim 1, It is characterized in that The step of encoding the data to be encoded to obtain the encoded data includes: Performing operations on the check matrix and the data to be encoded to obtain a check bit; The check bit is superimposed on the data to be encoded to obtain the encoded data.

8. A decoding device with multi-mode switching, It is characterized in that The device comprises: An encoding module, used for encoding the data to be encoded to obtain encoded data; A low-power decoding module, used for decoding the coded data according to the check matrix and the adaptive unit in the low-power decoding mode to obtain the decoded data corresponding to the low-power decoding mode; the adaptive unit is used for providing the first check data in the low-power decoding mode; A switching module, configured to switch the low-power decoding mode to a high-performance decoding mode and switch the adaptive unit to a computing unit if the encoded data fails to be decoded in the low-power decoding mode; A high-performance decoding module is used to decode the encoded data according to the check matrix and the calculation unit in the high-performance decoding mode to obtain decoded data corresponding to the high-performance decoding mode; the calculation unit is used to calculate and obtain second check data in the high-performance decoding mode, and the second check data is used to update the first check data.

9. An electronic device, It is characterized in that It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; The memory is used to store computer programs; The processor is used to implement the method according to any one of claims 1 to 7 when executing the program stored in the memory.

10. A computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, cause the processors to perform the method according to any one of claims 1 to 7.

Images