Automatic gain control module, signal processing chip and optical receiver

Abstract

The invention discloses an automatic gain control module, a signal processing chip and an optical receiver, the automatic gain control module comprises a first integrator, a second integrator, a third integrator and a fourth integrator, the first integrator is used for converting pulse train signals into first level signals, converting signals among the pulse train signals into second level signals, and converting the second level signals into second level signals; the third integrator is used for converting a first level signal into a first control signal, the fourth integrator is used for converting a second level signal into a second control signal, and the second integrator is used for converting the first level signal into a first gain control signal under the control of the first control signal and converting the second level signal into a second gain control signal under the control of the second control signal. The first level signal is converted into the first gain control signal, the second level signal is converted into the second gain control signal, the voltage of the first gain control signal and the second gain control signal is gradually increased or decreased, and the voltage change rate is gradually increased, so that the response speed of the automatic gain control module can be improved, and the stability of the circuit system is ensured.

Description

Technical Field

[0001] The invention relates to the technical field of optical sensors, and in particular to an automatic gain control module, a signal processing chip and an optical receiver. Background Art

[0002] An infrared light receiver usually includes a photosensitive chip and a signal processing chip electrically connected to the photosensitive chip. The photosensitive chip is mainly used to convert the optical signal into an electrical signal, and the signal processing chip is mainly used to amplify and shape the electrical signal, so as to obtain the sensing information carried by the optical signal according to the electrical signal, and transmit the sensing information to the processor of the electronic device where the infrared light receiver is located, so that the processor can implement corresponding control functions according to the sensing information, such as the function of controlling the screen brightness of the electronic device. In order to amplify the electrical signal and suppress interference at the same time, the signal processing chip usually includes an automatic gain control module (AGC for short), but the traditional automatic gain control module cannot ensure the stability of the circuit system while responding quickly. Summary of the invention

[0003] The invention discloses an automatic gain control module, a signal processing chip and an optical receiver, so as to improve the response speed of the automatic gain control module and ensure the stability of the circuit system.

[0004] In the first aspect, the present invention discloses an automatic gain control module, comprising a first integrator, a second integrator, a third integrator and a fourth integrator; the first integrator is used to convert a pulse train signal in an input signal into a first level signal, convert a signal between pulse train signals in the input signal into a second level signal, and transmit the first level signal or the second level signal to the second integrator, the third integrator and the fourth integrator; the third integrator is used to convert the first level signal into a first control signal, and transmit the first control signal to the second integrator; the fourth integrator is used to convert the second level signal into a second control signal, and transmit the second control signal to the second integrator; the second integrator is used to convert the first level signal into a first gain control signal under the control of the first control signal, and convert the second level signal into a second gain control signal under the control of the second control signal; the voltage of the first gain control signal gradually increases or decreases, and the voltage change rate of the first gain control signal gradually increases; the voltage of the second gain control signal gradually decreases or increases, and the voltage change rate of the second gain control signal gradually increases.

[0005] In some embodiments of the present invention, the second integrator includes a first adjustable current source, a second adjustable current source, a second capacitor, a second transistor and a third transistor; the first end of the first adjustable current source is electrically connected to the reference voltage end, the control end of the first adjustable current source is connected to the output end of the third integrator, and the second end of the first adjustable current source is electrically connected to the first end of the second transistor; the second end of the second transistor is electrically connected to the first end of the third transistor, the second end of the third transistor is electrically connected to the first end of the second adjustable current source, the second end of the second adjustable current source is grounded, and the control end of the second adjustable current source is connected to the output end of the fourth integrator; the control ends of the second transistor and the third transistor are electrically connected to the output end of the first integrator; the second end of the second transistor is electrically connected to the first end of the second capacitor, and the second end of the second capacitor is grounded; the first end of the second capacitor is used to output the first gain control signal or the second gain control signal.

[0006] In some embodiments of the present invention, the first level signal is used to control the second transistor to be turned on and the third transistor to be turned off, so that the first adjustable current source charges the second capacitor, and the voltage of the first gain control signal output by the second capacitor gradually increases; the first control signal is used to control the current value of the first adjustable current source to gradually increase, so as to control the voltage change rate of the first gain control signal to gradually increase; the second level signal is used to control the third transistor to be turned on and the second transistor to be turned off, so that the second capacitor discharges to the second adjustable current source, and the voltage of the second gain control signal output by the second capacitor gradually decreases; the second control signal is used to control the current value of the second adjustable current source to gradually increase, so as to control the voltage change rate of the second gain control signal to gradually increase.

[0007] In some embodiments of the present invention, the voltage of the first control signal gradually increases to control the current value of the first adjustable current source to gradually increase; the voltage of the second control signal gradually increases to control the current value of the second adjustable current source to gradually increase.

[0008] In some embodiments of the present invention, the third integrator includes a fourth current source, a fourth transistor, a fifth transistor and a third capacitor; the first end of the fourth current source is electrically connected to the reference voltage end, the second end of the fourth current source is electrically connected to the first end of the fourth transistor, the second end of the fourth transistor is electrically connected to the first end of the fifth transistor, and the second end of the fifth transistor is grounded; the control ends of the fourth transistor and the fifth transistor are electrically connected to the output end of the first integrator; the first end of the third capacitor is electrically connected to the second end of the fourth transistor, and the second end of the third capacitor is grounded; the first end of the third capacitor is used to output the first control signal.

[0009] In some embodiments of the present invention, the fourth integrator includes an inverter, a fifth current source, a sixth transistor, a seventh transistor and a fourth capacitor; the first end of the inverter is electrically connected to the output end of the first integrator, and the second end of the inverter is electrically connected to the control ends of the sixth transistor and the seventh transistor; the first end of the fifth current source is electrically connected to the reference voltage end, the second end of the fifth current source is electrically connected to the first end of the sixth transistor, the second end of the sixth transistor is electrically connected to the first end of the seventh transistor, and the second end of the seventh transistor is grounded; the first end of the fourth capacitor is electrically connected to the second end of the sixth transistor, and the second end of the fourth capacitor is grounded; the first end of the fourth capacitor is used to output the second control signal.

[0010] In some embodiments of the present invention, the first integrator includes a first transistor, a first current source, a first capacitor and a Schmitt trigger; the first end of the first current source is electrically connected to the reference voltage end, the second end of the first current source is electrically connected to the first end of the first transistor, and the second end of the first transistor is grounded; the control end of the first transistor is used to receive the input signal; the first end of the first capacitor is electrically connected to the first end of the first transistor, the first end of the first capacitor is electrically connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is used to output the first level signal or the second level signal.

[0011] In a second aspect, the present invention discloses a signal processing chip, comprising the automatic gain control module as described in any one of the above items.

[0012] In some embodiments of the present invention, a current-to-voltage conversion module, an amplifier, a gain-adjustable amplifier, a bandpass filter, a comparator, a signal integration circuit and a shaping circuit are further included; the current-to-voltage conversion module is used to receive the current signal at the input end of the signal processing chip, and convert the current signal into a voltage signal and output it to the amplifier; the amplifier is used to amplify the voltage signal output by the current-to-voltage conversion module, and output the amplified voltage signal to the gain-adjustable amplifier; the gain-adjustable amplifier is used to receive the first gain control signal or the second gain control signal output by the automatic gain control module, and adjust the amplification gain multiple according to the first gain control signal or the second gain control signal, and The voltage signal output by the amplifier is amplified by a corresponding gain multiple and then output to the bandpass filter; the bandpass filter is used to receive the voltage signal output by the gain adjustable amplifier, filter it and then output it to the comparator; the comparator is used to compare the voltage signal output by the bandpass filter with its internal reference voltage signal, and output the signal representing the comparison result to the signal integration circuit; the signal integration circuit is used to integrate the signal output by the comparator, and output the converted demodulated useful signal to the shaping circuit; the shaping circuit is used to shape the signal output by the signal integration circuit, and output the shaped signal to the output end of the signal processing chip.

[0013] In a third aspect, the present invention discloses an optical receiver, comprising the signal processing chip as described above.

[0014] The automatic gain control module, signal processing chip and optical receiver disclosed in the present invention include a first integrator, a second integrator, a third integrator and a fourth integrator. The first integrator is used to convert a pulse train signal in an input signal into a first level signal, and convert a signal between pulse train signals in the input signal into a second level signal. The second integrator is used to convert a first level signal into a first control signal. The third integrator is used to convert a second level signal into a second control signal. The fourth integrator is used to convert a first level signal into a first gain control signal with a gradually increasing or decreasing voltage under the control of the first control signal, and convert a second level signal into a second gain control signal with a gradually decreasing or increasing voltage under the control of the second control signal. Because the voltage change rate of the first gain control signal gradually increases, and the voltage change rate of the second gain control signal gradually increases, the change rate of the voltage average value of the first gain control signal and the second gain control signal can also gradually increase. Not only can the change rate of the voltage average value of the first gain control signal and the second gain control signal be larger when the pulse width time and interval time of the interference signal are longer, so that the response speed of the automatic gain control module is faster, so that the automatic gain control module can quickly and effectively suppress the interference signal, but also the change rate of the voltage average value of the first gain control signal and the second gain control signal can be smaller when the pulse width time and interval time of the interference signal are shorter, so that the fluctuation of the voltage average value of the first gain control signal and the second gain control signal is smaller, and the gain fluctuation of the gain adjustable amplifier is smaller, thereby ensuring the stability of the circuit system of the signal processing chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0016] Figure 1 This is a schematic diagram of the circuit structure of a traditional infrared light receiver.

[0017] Figure 2 It is a schematic diagram of the circuit structure of a traditional automatic gain control module.

[0018] Figure 3 for Figure 2 The signal timing diagram of the automatic gain control module is shown.

[0019] Figure 4 The present invention is a schematic diagram of the structure of an automatic gain control module disclosed in an embodiment of the present invention.

[0020] Figure 5 It is a schematic diagram of the structure of a second integrator disclosed in an embodiment of the present invention.

[0021] Figure 6 A signal timing diagram of an automatic gain control module disclosed in an embodiment of the present invention.

[0022] Figure 7 It is a schematic diagram of the structure of a third integrator disclosed in an embodiment of the present invention.

[0023] Figure 8 It is a schematic structural diagram of a fourth integrator disclosed in an embodiment of the present invention.

[0024] Fig. 9 It is a schematic diagram of the structure of a first integrator disclosed in an embodiment of the present invention.

[0025] Fig.10 The present invention is a schematic diagram of the structure of a signal processing chip disclosed in an embodiment of the present invention.

[0026] Fig.11 A schematic diagram of the structure of an optical receiver disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] like Figure 1 As shown, Figure 1 This is a schematic diagram of the circuit structure of a traditional infrared light receiver. The infrared light receiver includes a photosensitive chip 001 and a signal processing chip 100. The signal processing chip 100 includes a current-to-voltage conversion module 002, an amplifier 003, a gain-adjustable amplifier 004, a bandpass filter 005, a comparator 006, a signal integration circuit 007, a shaping circuit 008 and an automatic gain control module 009.

[0029] Among them, the photosensitive chip 001 is used to convert the sensed light signal into an electrical signal, and output the electrical signal to the input terminal IN of the signal processing chip 100. The current-voltage conversion module 002 is used to receive the current signal input from the input terminal IN, and convert it into a voltage signal and output it to the amplifier 003. The amplifier 003 is used to amplify the voltage signal output by the current-voltage conversion module 002, and output the amplified voltage signal to the gain-adjustable amplifier 004. The gain-adjustable amplifier 004 is used to receive the gain control signal output by the automatic gain control module 009, adjust the amplification gain multiple according to the gain control signal, and amplify the voltage signal output by the amplifier 003 by the corresponding gain multiple and output it to the bandpass filter 005. The bandpass filter 005 is used to receive the voltage signal output by the gain-adjustable amplifier 004, and filter it and output it to the comparator 006. The comparator 006 is used to compare the voltage signal output by the bandpass filter 005 with the reference voltage signal inside it, and output the signal (high-level signal or low-level signal) representing the comparison result to the signal integration circuit 007. The signal integration circuit 007 is used to perform integration operation on the signal output by the comparator 006, and convert it into a demodulated useful signal and output it to the shaping circuit 008. The shaping circuit 008 is used to perform shaping processing on the signal output by the signal integration circuit 007, and output the shaped signal to the output terminal OUT.

[0030] like Figure 2 As shown, Figure 2 Schematic diagram of the circuit structure of a traditional automatic gain control module 009, which includes a first integrator 1 and a second integrator 2. The first integrator 1 includes a first transistor 101, a first current source 102, a first capacitor 103 and a Schmitt trigger 104, and the second integrator 2 includes a second current source 106, a third current source 107, a second capacitor 108, a second transistor 109 and a third transistor 110.

[0031] like Figure 3 As shown, Figure 3 for Figure 2As shown in the signal timing diagram of the automatic gain control module 009, when the signal output by the comparator 006, i.e., the input signal of the automatic gain control module 009, is a pulse train signal with continuous level flipping, the first integrator 1 outputs a high level signal to the second integrator 2, so that the third transistor 110 is turned off and the second transistor 109 is turned on, so that the second current source 106 charges the second capacitor 108, so that the gain control signal output by the second integrator 2 is a first gain control signal that increases at a certain rate; when the signal output by the comparator 006, i.e., the input signal of the automatic gain control module 009, is a low level signal between the pulse train signals, the first integrator 1 outputs a low level signal to the second integrator 2, so that the third transistor 110 is turned on and the second transistor 109 is turned off, so that the second capacitor 108 discharges to the third current source 107, so that the gain control signal output by the second integrator 2 is a second gain control signal that decreases at a certain rate.

[0032] The voltage average values ​​of the first gain control signal and the second gain control signal output by the automatic gain control module 009 are determined by the pulse width time d1 and the interval time d2. The pulse width time d1 refers to the time of the pulse train signal with continuous level flipping, and the interval time d2 refers to the time of the low level signal between the pulse train signals. Because the gain multiple of the gain adjustable amplifier 004 is inversely proportional to the voltage average values ​​of the first gain control signal and the second gain control signal output by the automatic gain control module 009, when the signal processing chip 100 receives an interference signal, and the pulse width time d1 of the interference signal is greater than the interval time d2, the voltage average values ​​of the first gain control signal and the second gain control signal output by the automatic gain control module 009 increase, and the gain multiple of the gain adjustable amplifier 004 decreases, so that the interference signal is suppressed and will not be transmitted to the output terminal OUT of the signal processing chip 100. When the interference signal received by the signal processing chip 100 disappears, the voltage averages of the first gain control signal and the second gain control signal output by the automatic gain control module 009 decrease, the gain multiple of the adjustable gain amplifier 004 increases, and the sensitivity of the signal processing chip 100 improves.

[0033] However, because the charging rate and the discharging rate of the second capacitor 108 are fixed, the voltage change rate of the first gain control signal output by the automatic gain control module 009 and the voltage change rate of the second gain control signal are also fixed, and the change rate of the voltage average value of the first gain control signal output by the automatic gain control module 009 and the second gain control signal is also fixed. In the case where the change rate of the voltage average value is small, if the pulse width time d1 and the interval time d2 of the interference signal are long, the automatic gain control module 009 needs to spend a long time to suppress the interference signal, resulting in the slow response speed of the automatic gain control module 009, and the interference signal cannot be quickly and effectively suppressed. In the case where the change rate of the voltage average value is large, if the pulse width time d1 and the interval time d2 of the interference signal are short, although the response speed of the automatic gain control module 009 is fast, the interference signal can be quickly suppressed, but the fluctuation of the voltage average value of the first gain control signal output by the automatic gain control module 009 and the second gain control signal is large, resulting in the gain fluctuation of the gain adjustable amplifier 004 being large, resulting in the poor stability of the circuit system of the signal processing chip 100.

[0034] Based on this, the present invention discloses an automatic gain control module, in which the voltage change rate of the first gain control signal output by the module and the voltage change rate of the second gain control signal output by the module gradually increase, so that the change rate of the voltage average values ​​of the first gain control signal and the second gain control signal gradually increases, so as to improve the response speed of the automatic gain control module while ensuring the stability of the circuit system.

[0035] As an optional implementation of the content disclosed in the present invention, the embodiment of the present invention discloses an automatic gain control module, such as Figure 4 As shown, Figure 4 It is a schematic diagram of the structure of an automatic gain control module disclosed in an embodiment of the present invention. The automatic gain control module includes a first integrator 1, a second integrator 2, a third integrator 3 and a fourth integrator 4.

[0036] Among them, the first integrator 1 is used to convert the pulse train signal in the input signal into a first level signal L1, convert the signal between the pulse train signals in the input signal into a second level signal L2, and transmit the first level signal L1 or the second level signal L2 to the second integrator 2, the third integrator 3 and the fourth integrator 4.

[0037] The third integrator 3 is used to convert the first level signal L1 into a first control signal K1 and transmit the first control signal K1 to the second integrator 2. The fourth integrator 4 is used to convert the second level signal L2 into a second control signal K2 and transmit the second control signal K2 to the second integrator 2.

[0038] The second integrator 2 is used to convert the first level signal L1 into the first gain control signal Z1 under the control of the first control signal K1, and to convert the second level signal L2 into the second gain control signal Z2 under the control of the second control signal K2. In addition, the voltage of the first gain control signal Z1 gradually increases or decreases, and the voltage change rate of the first gain control signal Z1 gradually increases; the voltage of the second gain control signal Z2 gradually decreases or increases, and the voltage change rate of the second gain control signal Z2 gradually increases.

[0039] Because the voltage change rate of the first gain control signal Z1 gradually increases, and the voltage change rate of the second gain control signal Z2 gradually increases, the change rate of the voltage average value of the first gain control signal Z1 and the second gain control signal Z2 can also gradually increase. Not only can the change rate of the voltage average value of the first gain control signal Z1 and the second gain control signal Z2 be larger when the pulse width time d1 and the interval time d2 of the interference signal are longer, so that the response speed of the automatic gain control module is faster, so that the automatic gain control module can quickly and effectively suppress the interference signal, but also the change rate of the voltage average value of the first gain control signal Z1 and the second gain control signal Z2 can be smaller when the pulse width time d1 and the interval time d2 of the interference signal are shorter, so that the fluctuation of the voltage average value of the first gain control signal Z1 and the second gain control signal Z2 is smaller, and the gain fluctuation of the gain adjustable amplifier is smaller, thereby ensuring the stability of the circuit system of the signal processing chip.

[0040] In some embodiments of the present invention, Figure 5 As shown, Figure 5 It is a structural schematic diagram of a second integrator 2 disclosed in an embodiment of the present invention. The second integrator 2 includes a first adjustable current source 206 , a second adjustable current source 207 , a second capacitor 108 , a second transistor 109 and a third transistor 110 .

[0041] The first end of the first adjustable current source 206 is electrically connected to the reference voltage terminal Vdd, the control end of the first adjustable current source 206 is connected to the output end of the third integrator 3, and the second end of the first adjustable current source 206 is electrically connected to the first end of the second transistor 109. The second end of the second transistor 109 is electrically connected to the first end of the third transistor 110, the second end of the third transistor 110 is electrically connected to the first end of the second adjustable current source 207, the second end of the second adjustable current source 207 is grounded, and the control end of the second adjustable current source 207 is connected to the output end of the fourth integrator 4. The control ends of the second transistor 109 and the third transistor 110 are electrically connected to the output end of the first integrator 1, the second end of the second transistor 109 is electrically connected to the first end of the second capacitor 108, the second end of the second capacitor 108 is grounded, and the first end of the second capacitor 108 is used to output the first gain control signal Z1 or the second gain control signal Z2.

[0042] In some embodiments of the present invention, the first level signal is a high level signal, the second level signal is a low level signal, the second transistor 109 is an NMOS transistor, and the third transistor 110 is a PMOS transistor. Figure 5 and Figure 6 As shown, Figure 6 The signal timing diagram of an automatic gain control module disclosed in an embodiment of the present invention, the first level signal L1 is used to control the second transistor 109 to be turned on and the third transistor 110 to be turned off, so that the first adjustable current source 206 charges the second capacitor 108, so that the voltage of the first gain control signal Z1 output by the second capacitor 108 gradually increases. The first control signal K1 is used to control the current value of the first adjustable current source 206 to gradually increase, so as to control the voltage change rate of the first gain control signal Z1 to gradually increase. The second level signal L2 is used to control the third transistor 110 to be turned on and the second transistor 109 to be turned off, so that the second capacitor 108 discharges to the second adjustable current source 207, so that the voltage of the second gain control signal Z2 output by the second capacitor 108 gradually decreases. The second control signal K2 is used to control the current value of the second adjustable current source 207 to gradually increase, so as to control the voltage change rate of the second gain control signal Z2 to gradually increase.

[0043] like Figure 5 and Figure 6As shown, when the input signal of the automatic gain control module or the first integrator 1 is a pulse train signal with continuous level flipping, the first integrator 1 outputs a high-level signal, so that the third transistor 110 is turned off and the second transistor 109 is turned on, so that the first adjustable current source 206 charges the second capacitor 108, so that the gain control signal output by the second integrator 2 is a gradually increasing first gain control signal Z1. In addition, as the current value of the first adjustable current source 206 gradually increases, the charging rate of the second capacitor 108 gradually increases, and the voltage change rate of the first gain control signal Z1 gradually increases.

[0044] When the input signal of the automatic gain control module or the first integrator 1 is a low-level signal between pulse train signals, the first integrator 1 outputs a low-level signal, so that the third transistor 110 is turned on and the second transistor 109 is turned off, so that the second capacitor 108 discharges to the second adjustable current source 207, so that the gain control signal output by the second integrator 2 is a gradually decreasing second gain control signal Z2. In addition, as the current value of the second adjustable current source 207 gradually increases, the discharge rate of the second capacitor 108 gradually increases, and the voltage change rate of the second gain control signal Z2 gradually increases.

[0045] Of course, the present invention is not limited to this. In other embodiments, the second transistor 109 may be a PMOS transistor and the third transistor 110 may be an NMOS transistor. In this case, the voltage of the first gain control signal Z1 gradually decreases and the voltage of the second gain control signal Z2 gradually increases. In other embodiments, the first level signal may be a low level signal and the second level signal may be a high level signal, which will not be described in detail here.

[0046] In some embodiments of the present invention, reference Figure 6 , the voltage of the first control signal K1 gradually increases to control the current value of the first adjustable current source 206 to gradually increase, thereby controlling the voltage change rate of the first gain control signal Z1 to gradually increase; the voltage of the second control signal K2 gradually increases to control the current value of the second adjustable current source 207 to gradually increase, thereby controlling the voltage change rate of the second gain control signal Z2 to gradually increase.

[0047] On this basis, in some embodiments of the present invention, Figure 7 As shown, Figure 7 1 is a schematic diagram of the structure of a third integrator 3 disclosed in an embodiment of the present invention. The third integrator 3 includes a fourth current source 111 , a fourth transistor 112 , a fifth transistor 113 and a third capacitor 114 .

[0048] The first end of the fourth current source 111 is electrically connected to the reference voltage terminal Vdd, and the second end of the fourth current source 111 is electrically connected to the first end of the fourth transistor 112. The second end of the fourth transistor 112 is electrically connected to the first end of the fifth transistor 113, and the second end of the fifth transistor 113 is grounded. The control ends of the fourth transistor 112 and the fifth transistor 113 are electrically connected to the output end of the first integrator 1, and are used to receive the first level signal L1 or the second level signal L2. The first end of the third capacitor 114 is electrically connected to the second end of the fourth transistor 112, and the second end of the third capacitor 114 is grounded. The first end of the third capacitor 114 is used to output the first control signal K1.

[0049] Taking the fourth transistor 112 as an NMOS transistor and the fifth transistor 113 as a PMOS transistor as an example, Figure 6 When the first integrator 1 outputs the first level signal L1 and the first level signal L1 is a high level signal, the fourth transistor 112 is turned on and the fifth transistor 113 is turned off, and the fourth current source 111 charges the third capacitor 114, so that the voltage at the first end of the third capacitor 114 gradually increases, so that the voltage of the first control signal K1 gradually increases. When the first integrator 1 outputs the second level signal L2 and the second level signal L2 is a low level signal, the fourth transistor 112 is turned off and the fifth transistor 113 is turned on, so that the voltage at the first end of the third capacitor 114 is pulled down.

[0050] In some embodiments of the present invention, Figure 8 As shown, Figure 8 Schematic diagram of the structure of a fourth integrator disclosed in an embodiment of the present invention. The fourth integrator 4 includes an inverter 115 , a fifth current source 116 , a sixth transistor 117 , a seventh transistor 118 and a fourth capacitor 119 .

[0051] The first end of the inverter 115 is electrically connected to the output end of the first integrator 1, and is used to receive the first level signal L1 or the second level signal L2. The second end of the inverter 115 is electrically connected to the control end of the sixth transistor 117 and the seventh transistor 118. The first end of the fifth current source 116 is electrically connected to the reference voltage end Vdd, the second end of the fifth current source 116 is electrically connected to the first end of the sixth transistor 117, the second end of the sixth transistor 117 is electrically connected to the first end of the seventh transistor 118, and the second end of the seventh transistor 118 is grounded. The first end of the fourth capacitor 119 is electrically connected to the second end of the sixth transistor 117, the second end of the fourth capacitor 119 is grounded, and the first end of the fourth capacitor 119 is used to output the second control signal K2.

[0052] Taking the sixth transistor 117 as an NMOS transistor and the seventh transistor 118 as a PMOS transistor as an example, Figure 6When the first integrator 1 outputs the first level signal L1 and the first level signal L1 is a high level signal, the inverter 115 outputs a low level signal, the sixth transistor 117 is turned off, the seventh transistor 118 is turned on, and the voltage at the first end of the fourth capacitor 119 is pulled down. When the first integrator 1 outputs the second level signal L2 and the second level signal L2 is a low level signal, the inverter 115 outputs a high level signal, the sixth transistor 117 is turned on, the seventh transistor 118 is turned off, and the fifth current source 116 charges the fourth capacitor 119, so that the voltage at the first end of the fourth capacitor 119 gradually increases, so that the voltage of the second control signal K2 gradually increases.

[0053] Of course, in the embodiment of the present invention, only Figure 7 and Figure 8 The structure shown is for explanation by way of example only and is not limited thereto.

[0054] In some embodiments of the present invention, Fig. 9 As shown, Fig. 9 1 is a schematic diagram of the structure of a first integrator 1 disclosed in an embodiment of the present invention. The first integrator 1 includes a first transistor 101 , a first current source 102 , a first capacitor 103 and a Schmitt trigger 104 .

[0055] Among them, the first end of the first current source 102 is electrically connected to the reference voltage terminal Vdd, the second end of the first current source 102 is electrically connected to the first end of the first transistor 101, and the second end of the first transistor 101 is grounded; the control end of the first transistor 101 is used to receive an input signal; the first end of the first capacitor 103 is electrically connected to the first end of the first transistor 101, the first end of the first capacitor 103 is electrically connected to the input end of the Schmitt trigger 104, and the output end of the Schmitt trigger 104 is used to output a first level signal L1 or a second level signal L2.

[0056] As another optional implementation of the content disclosed in the present invention, an embodiment of the present invention further discloses a signal processing chip, which includes the automatic gain control module disclosed in any of the above embodiments. Fig.10 As shown, Fig.10The structure diagram of a signal processing chip 100 disclosed in an embodiment of the present invention, the signal processing chip also includes a current-to-voltage conversion module 002, an amplifier 003, a gain-adjustable amplifier 004, a band-pass filter 005, a comparator 006, a signal integration circuit 007 and a shaping circuit 008. The current-to-voltage conversion module 002 is used to receive the current signal at the input end of the signal processing chip 100, and convert the current signal into a voltage signal and output it to the amplifier 003; the amplifier 003 is used to amplify the voltage signal output by the current-to-voltage conversion module 002, and output the amplified voltage signal to the gain-adjustable amplifier 004; the gain-adjustable amplifier 004 is used to receive the first gain control signal or the second gain control signal output by the automatic gain control module, and adjust the amplification gain multiple according to the first gain control signal or the second gain control signal, and amplify the voltage signal output by the amplifier 003 by the corresponding gain multiple and output it to the band-pass filter 00 5; the bandpass filter 005 is used to receive the voltage signal output by the gain adjustable amplifier 004, and output it to the comparator 006 after filtering; the comparator 006 is used to compare the voltage signal output by the bandpass filter 005 with the reference voltage signal inside it, and output the signal indicating the comparison result to the signal integration circuit 007; the signal integration circuit 007 is used to perform an integration operation on the signal output by the comparator 006, and output the converted demodulated useful signal to the shaping circuit 008; the shaping circuit 008 is used to perform shaping processing on the signal output by the signal integration circuit 007, and output the shaped signal to the output end of the signal processing chip 100.

[0057] As another optional implementation of the content disclosed in the present invention, an embodiment of the present invention further discloses an optical receiver, which includes a signal processing chip disclosed in any of the above embodiments. Fig.11 As shown, Fig.11 It is a schematic diagram of the structure of an optical receiver disclosed in an embodiment of the present invention. The optical receiver also includes a photosensitive chip 200. The photosensitive chip 200 is used to convert the sensed optical signal into an electrical signal and output the electrical signal to the signal processing chip 100.

[0058] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. An automatic gain control module, characterized in that: comprising a first integrator, a second integrator, a third integrator and a fourth integrator; The first integrator is used to convert a pulse train signal in the input signal into a first level signal, convert a signal between the pulse train signals in the input signal into a second level signal, and transmit the first level signal or the second level signal to the second integrator, the third integrator and the fourth integrator; The third integrator is used for converting the first level signal into a first control signal, and transmitting the first control signal to the second integrator; The fourth integrator is used for converting the second level signal into a second control signal, and transmitting the second control signal to the second integrator; The second integrator is used to convert the first level signal into a first gain control signal under the control of the first control signal, and to convert the second level signal into a second gain control signal under the control of the second control signal; the voltage of the first gain control signal gradually increases or decreases, and the voltage change rate of the first gain control signal gradually increases; the voltage of the second gain control signal gradually decreases or increases, and the voltage change rate of the second gain control signal gradually increases.

2. The automatic gain control module according to claim 1, characterized in that: The second integrator includes a first adjustable current source, a second adjustable current source, a second capacitor, a second transistor and a third transistor; The first terminal of the first adjustable current source is electrically connected to the reference voltage terminal, the control terminal of the first adjustable current source is connected to the output terminal of the third integrator, and the second terminal of the first adjustable current source is electrically connected to the first terminal of the second transistor; The second end of the second transistor is electrically connected to the first end of the third transistor, the second end of the third transistor is electrically connected to the first end of the second adjustable current source, the second end of the second adjustable current source is grounded, and the control end of the second adjustable current source is connected to the output end of the fourth integrator; The control ends of the second transistor and the third transistor are electrically connected to the output end of the first integrator; the second end of the second transistor is electrically connected to the first end of the second capacitor, and the second end of the second capacitor is grounded; the first end of the second capacitor is used to output the first gain control signal or the second gain control signal.

3. The automatic gain control module according to claim 2, characterized in that: The first level signal is used to control the second transistor to be turned on and the third transistor to be turned off, so that the first adjustable current source charges the second capacitor, and the voltage of the first gain control signal output by the second capacitor gradually increases; The first control signal is used to control the current value of the first adjustable current source to gradually increase, so as to control the voltage change rate of the first gain control signal to gradually increase; The second level signal is used to control the third transistor to be turned on and the second transistor to be turned off, so that the second capacitor discharges to the second adjustable current source, and the voltage of the second gain control signal output by the second capacitor gradually decreases; The second control signal is used to control the current value of the second adjustable current source to gradually increase, so as to control the voltage change rate of the second gain control signal to gradually increase.

4. The automatic gain control module according to claim 2 or 3, characterized in that: The voltage of the first control signal gradually increases to control the current value of the first adjustable current source to gradually increase; the voltage of the second control signal gradually increases to control the current value of the second adjustable current source to gradually increase.

5. The automatic gain control module according to claim 4, characterized in that: The third integrator includes a fourth current source, a fourth transistor, a fifth transistor and a third capacitor; The first end of the fourth current source is electrically connected to the reference voltage end, the second end of the fourth current source is electrically connected to the first end of the fourth transistor, the second end of the fourth transistor is electrically connected to the first end of the fifth transistor, and the second end of the fifth transistor is grounded; the control ends of the fourth transistor and the fifth transistor are electrically connected to the output end of the first integrator; the first end of the third capacitor is electrically connected to the second end of the fourth transistor, and the second end of the third capacitor is grounded; the first end of the third capacitor is used to output the first control signal.

6. The automatic gain control module according to claim 4, characterized in that: The fourth integrator includes an inverter, a fifth current source, a sixth transistor, a seventh transistor and a fourth capacitor; The first end of the inverter is electrically connected to the output end of the first integrator, and the second end of the inverter is electrically connected to the control ends of the sixth transistor and the seventh transistor; the first end of the fifth current source is electrically connected to the reference voltage end, the second end of the fifth current source is electrically connected to the first end of the sixth transistor, the second end of the sixth transistor is electrically connected to the first end of the seventh transistor, and the second end of the seventh transistor is grounded; the first end of the fourth capacitor is electrically connected to the second end of the sixth transistor, and the second end of the fourth capacitor is grounded; the first end of the fourth capacitor is used to output the second control signal.

7. The automatic gain control module according to claim 1, characterized in that: The first integrator includes a first transistor, a first current source, a first capacitor and a Schmitt trigger; The first end of the first current source is electrically connected to the reference voltage end, the second end of the first current source is electrically connected to the first end of the first transistor, and the second end of the first transistor is grounded; the control end of the first transistor is used to receive the input signal; the first end of the first capacitor is electrically connected to the first end of the first transistor, the first end of the first capacitor is electrically connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is used to output the first level signal or the second level signal.

8. A signal processing chip, characterized in that: It comprises the automatic gain control module as described in any one of claims 1 to 7.

9. The signal processing chip according to claim 8, characterized in that: It also includes a current-to-voltage conversion module, an amplifier, a gain-adjustable amplifier, a bandpass filter, a comparator, a signal integration circuit, and a shaping circuit; The current-to-voltage conversion module is used to receive the current signal at the input end of the signal processing chip, and convert the current signal into a voltage signal and then output it to the amplifier; The amplifier is used to amplify the voltage signal output by the current-voltage conversion module, and output the amplified voltage signal to the gain adjustable amplifier; The gain adjustable amplifier is used to receive the first gain control signal or the second gain control signal output by the automatic gain control module, and adjust the amplification gain multiple according to the first gain control signal or the second gain control signal, and amplify the voltage signal output by the amplifier by a corresponding gain multiple and then output it to the bandpass filter; The bandpass filter is used to receive the voltage signal output by the gain adjustable amplifier, and filter it before outputting it to the comparator; The comparator is used to compare the voltage signal output by the bandpass filter with the reference voltage signal inside the comparator, and output a signal representing the comparison result to the signal integration circuit; The signal integration circuit is used to perform integration operation on the signal output by the comparator, and convert the signal into a demodulated useful signal and output it to the shaping circuit; The shaping circuit is used to shape the signal output by the signal integration circuit, and output the shaped signal to the output end of the signal processing chip.

10. An optical receiver, characterized in that: Comprising the signal processing chip according to claim 8 or 9.

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