Clock source switching method and device, network equipment and medium
By setting the forced holdover mode on the main control board of the network device and switching the clock source after the timer timed out, the problem of unstable clock switching of the clock source is solved, ensuring the clock stability and time synchronization accuracy of the network device.
Patent Information
- Application Number
- CN202411336707.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2024-12-20
AI Technical Summary
In network equipment of distributed systems, clock instability is caused by inconsistent phase of clock signal when switching clock source, which affects the accuracy of time synchronization services and may lead to packet loss problems.
By setting the forced holdover mode on the main control board and switching the clock source after the timer timed out, ensure that the clock signal is switched in a stable state, avoiding the transition period of the unstable clock state.
It effectively avoids the problem of clock instability and degradation of time synchronization service accuracy caused by clock source switching, ensures the clock stability of network equipment, and prevents packet loss.
Smart Images
Figure CN119172030A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular to a clock source switching method, device, network equipment and medium. Background Art
[0002] In network devices of distributed systems, such as routers, Synchronous Ethernet (SYNCE) is usually used to synchronize the clock between the router and an external clock source. Figure 1 As shown, the router includes a backplane, a main control board, a service board 1 and a service board 2. Each service board has multiple backup clock links with different priorities. For example, service board 1 is connected to the backup clock link of external clock source 1 and external clock source 2, and can receive external clock signal 1 and external clock signal 2. Service board 2 is connected to the backup clock link of external clock source 3 and external clock source 4, and can receive external clock signal 3 and external clock signal 4. External clock sources 1, 2, 3, and 4 correspond to priorities 1, 2, 3, and 4, respectively. Each service board has a source selection switch and a clock chip. After the service board selects the optimal clock source of the service board through the timing task, the backup clock link of the optimal clock source is opened through the source selection switch, and then the clock chip converts the external clock signal corresponding to the optimal clock source into a clock signal of a specified frequency and sends it to the main control board. After receiving the clock signals of each service board, the main control board selects the clock signal of the clock source with the highest priority through the source selection switch, and converts the clock signal into clock signals of various frequencies required by the router through the clock chip.
[0003] However, the source selection switch of the main control board generally uses devices such as Field-Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD) to switch the hardware circuit. For example, the clock source with the highest priority selected by the main control board is the external clock source 3 of the service board 2, and the clock source currently used is the external clock source 1 of the service board 1. The source selection module switches the clock link from the link between the service board 1 to the link between the service board 2, and the clock signal received by the clock chip of the main control board is also switched from the clock signal of the external clock source 1 to the clock signal of the external clock source 3. Due to the inconsistency of the phases of different clock signals, the clock phase jump will occur in the process of switching the clock source, resulting in the clock signal output by the clock chip of the main control board having noise for about a few seconds, which in turn causes the clock to be unstable within these few seconds, affecting the time synchronization service accuracy of the router, and even causing packet loss problems. Summary of the invention
[0004] The purpose of the embodiments of the present application is to provide a clock source switching method, device, network device and medium to solve the problem of clock instability during the clock source switching process. The specific technical solution is as follows:
[0005] In a first aspect, an embodiment of the present application provides a clock source switching method, which is applied to a main control board of a network device, and the method includes:
[0006] Reselect the optimal clock source every preset period of time;
[0007] If the optimal clock source is inconsistent with the currently used clock source, the master clock state is set to a forced holdover mode and the first timer is started;
[0008] Turning on the clock link of the optimal clock source by means of a source selection switch;
[0009] After the first timer times out, releasing the forced holdover mode of the master clock state;
[0010] When the master clock state is not in the forced holdover mode, the currently used clock source is switched to the optimal clock source.
[0011] In a possible implementation, the method further includes:
[0012] Receiving a clock source change message sent by a service board, wherein the clock source change message includes a slot number of the service board and the validity of the changed clock source;
[0013] If the slot number of the service board is the same as the slot number of the service board to which the currently used clock source belongs, and the changed clock source is valid, the master clock state is set to the forced holdover mode, and the second timer is started;
[0014] After the second timer times out, the forced holdover mode of the master clock state is released.
[0015] In a possible implementation, before setting the master clock state to the forced holdover mode, the method further includes:
[0016] Determine whether the current count value of the forced holdover mode is 0, the initial value of the count value is 0;
[0017] If not, the count value is increased by 1, and it is determined that the master clock state has been successfully set to the forced holdover mode;
[0018] If yes, then the count value is increased by 1, and the step of setting the master clock state to the forced holdover mode is performed;
[0019] Before releasing the forced holdover mode of the master clock state, the method further includes:
[0020] Determine whether the count value of the current forced holdover mode is greater than 1;
[0021] If yes, then the count value is reduced by 1, and the master clock state is kept in the forced holdover mode;
[0022] If not, the step of releasing the forced holdover mode of the master clock state is performed.
[0023] In a possible implementation manner, before setting the master clock state to the forced holdover mode and starting the first timer, the method further includes:
[0024] Determine whether the optimal clock source is consistent with the currently used clock source;
[0025] If yes, the number of switching source protection times is set to a preset initial value, and the process returns to the step of reselecting the optimal clock source every preset time period;
[0026] If not, determine whether the number of source protection times is 0;
[0027] If the number of source protection switching times is not 0, the number of source protection switching times is reduced by 1, and the process returns to the step of reselecting the optimal clock source every preset time period;
[0028] If the number of source protection switching times is 0, the number of source protection switching times is set to the preset value, and the steps of setting the master clock state to the forced holdover mode and starting the first timer are performed.
[0029] In a possible implementation, the preset initial value is 2.
[0030] In a second aspect, an embodiment of the present application provides a clock source switching device, which is applied to a main control board of a network device, and the device includes:
[0031] A selection module is used to reselect the optimal clock source every preset time period;
[0032] A setting module, configured to set the master clock state to a forced holdover mode and start a first timer if the optimal clock source is inconsistent with the currently used clock source;
[0033] An enabling module, used for enabling a clock link of the optimal clock source through a source selection switch;
[0034] A release module, used for releasing the forced holdover mode of the master clock state after the first timer times out;
[0035] The switching module is used to switch the currently used clock source to the optimal clock source when the master clock state is not in the forced holdover mode.
[0036] In a possible implementation manner, the device further includes:
[0037] A receiving module, used to receive a clock source change message sent by a service board, wherein the clock source change message includes a slot number of the service board and the validity of the changed clock source;
[0038] The setting module is further configured to set the master clock state to a forced holdover mode and start a second timer if the slot number of the service board is the same as the slot number of the service board to which the currently used clock source belongs and the changed clock source is valid;
[0039] The release module is further configured to release the forced holdover mode of the master clock state after the second timer times out.
[0040] In a possible implementation, the setting module is further used to:
[0041] Determine whether the current count value of the forced holdover mode is 0, the initial value of the count value is 0;
[0042] If not, the count value is increased by 1, and it is determined that the master clock state has been successfully set to the forced holdover mode;
[0043] If yes, then the count value is increased by 1, and the step of setting the master clock state to the forced holdover mode is performed;
[0044] The release module is further used for:
[0045] Determine whether the count value of the current forced holdover mode is greater than 1;
[0046] If yes, then the count value is reduced by 1, and the master clock state is kept in the forced holdover mode;
[0047] If not, the step of releasing the forced holdover mode of the master clock state is performed.
[0048] In a possible implementation manner, the device further includes:
[0049] Source protection module, used for:
[0050] Determine whether the optimal clock source is consistent with the currently used clock source;
[0051] If yes, the number of source switching protection times is set to a preset initial value, and the selection module is triggered to reselect the optimal clock source every preset time period;
[0052] If not, determine whether the number of source protection times is 0;
[0053] If the number of source protection switching times is not 0, the number of source protection switching times is reduced by 1, and the selection module is triggered to reselect the optimal clock source every preset time period;
[0054] If the number of source protection switching times is 0, the number of source protection switching times is set to the preset value, and the setting module is triggered to set the master clock state to the forced holdover mode, and start the first timer.
[0055] In a possible implementation, the preset initial value is 2.
[0056] In a third aspect, an embodiment of the present application provides a network device, including a main control board and a service board, wherein the main control board is used to implement the method described in the first aspect above.
[0057] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in the first aspect is implemented.
[0058] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.
[0059] With the above technical solution, after selecting a new optimal clock source, the main control board will not directly switch the currently used clock source to the optimal clock source, but will first set the master clock state to the forced holdover mode, start the first timer, and turn on the clock link of the optimal clock source through the source selection switch. Since the master clock state is in the forced holdover mode at this time, the clock signal of the optimal clock source will not be used temporarily. After the first timer times out, the clock signal of the optimal clock source is already in a stable state. At this time, switching the currently used clock source to the optimal clock source is equivalent to shielding the transition period when the clock is in an unstable state, which can prevent network devices from using unstable clock signals, ensure the clock stability of network devices, and thus avoid the reduction in time synchronization service accuracy and packet loss caused by clock source switching.
[0060] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.
[0062] Figure 1 A schematic diagram of the structure of a network device provided in an embodiment of the present application;
[0063] Figure 2 A flowchart of a clock source switching method provided in an embodiment of the present application;
[0064] Figure 3 A flowchart of another clock source switching method provided in an embodiment of the present application;
[0065] Figure 4 A flowchart of a method for performing protection processing on a forced holdover mode provided in an embodiment of the present application;
[0066] Figure 5 A flow chart of a method for switching source protection during clock source switching provided in an embodiment of the present application;
[0067] Figure 6 A schematic diagram of the structure of a clock source switching device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0068] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.
[0069] In order to solve the problem of unstable clock signal obtained during the main control board switching clock source, the embodiment of the present application provides a clock source switching method, which is applied to the main control board of a network device, and the network device can be a distributed network device, such as a distributed router, such as Figure 2 As shown, the method includes:
[0070] S201. Reselect an optimal clock source every preset time period.
[0071] The CPU of the main control board runs a timing task. Whenever the timer of the timing task times out, the optimal clock source can be selected based on the clock signals sent from each service board.
[0072] S202: If the optimal clock source is inconsistent with the currently used clock source, the master clock state is set to a forced holdover mode, and a first timer is started.
[0073] Among them, the forced holdover mode is a clock synchronization mode. When the forced holdover mode is turned on, the clock stability can be maintained through the internal mechanism when the external clock signal is unavailable, that is, a relatively stable clock signal can still be output to ensure the normal operation of the system.
[0074] It is understandable that when the master clock state is in forced holdover mode, the main control board will not temporarily use the clock signal of the currently reselected optimal clock source. Instead, it will determine the average frequency of the clock signal within the historical preset time length, and continue to provide the clock signal to the entire network device according to the average frequency. For example, the clock source currently used by the mainboard is clock source 1, and the reselected clock source is clock source 2. After setting the master clock state to forced holdover mode, the main control board can determine the average frequency of the clock signal of clock source 1 in the previous two seconds, and generate a clock signal according to the average frequency to provide the clock signal to the network device.
[0075] S203: Enable the clock link of the optimal clock source through the source selection switch.
[0076] The main control board can switch the hardware circuit through devices such as FPGA or CPLD, that is, switch the clock link of the currently used clock source to the clock link of the optimal clock source, so as to receive the clock signal from the optimal clock source through the clock link of the optimal clock source.
[0077] S204: After the first timer times out, the forced holdover mode of the master clock state is released.
[0078] The timeout duration of the first timer can be set based on an empirical value. The timeout duration matches the duration that the clock signal is in an unstable state when the main control board switches the clock source. The locking performance of the clock chip and the clock frequency of the clock source are different, which will affect the duration that the clock signal is in an unstable state.
[0079] As an example, the timeout duration of the first timer may be 10 seconds.
[0080] S205: When the master clock state is not in the forced holdover mode, switch the currently used clock source to the optimal clock source.
[0081] It is understandable that after the forced holdover mode is released, the main control board can switch the clock source normally, switch the currently used clock source to the optimal clock source, and transmit the clock signal of the optimal clock source to the entire network device.
[0082] With this method, after selecting a new optimal clock source, the main control board will not directly switch the currently used clock source to the optimal clock source, but will first set the master clock state to the forced holdover mode, start the first timer, and turn on the clock link of the optimal clock source through the source selection switch. Since the master clock state is in the forced holdover mode at this time, the clock signal of the optimal clock source will not be used temporarily. After the first timer times out, the clock signal of the optimal clock source is already in a stable state. At this time, switching the currently used clock source to the optimal clock source is equivalent to shielding the transition period when the clock is in an unstable state, which can prevent network devices from using unstable clock signals, ensure the clock stability of network devices, and thus avoid the reduction in time synchronization service accuracy and packet loss caused by clock source switching.
[0083] In the related art, it takes about 10 seconds for the clock chip of the service board to switch from the old clock signal to the new clock signal and enter a stable state. During this period, the clock signal reported by the service board to the main control board is in an unstable state and there is clock noise. The main control board transmits the unstable clock signal to the clock of the entire router, which will affect the stability of the router and cause the clock of the entire router to have an error of hundreds to thousands of ns, affecting the accuracy of the router's time synchronization service and even causing packet loss problems.
[0084] In order to solve this problem, in some embodiments of the present application, the method further includes:
[0085] Receive the clock source change message sent by the service board, which includes the slot number of the service board and the validity of the changed clock source; if the slot number of the service board is the same as the slot number of the service board to which the currently used clock source belongs, and the changed clock source is valid, set the master clock state to the forced holdover mode and start the second timer; after the second timer times out, release the forced holdover mode of the master clock state. The validity of the changed clock source is used to indicate whether the service board can receive the signal of the changed clock source. If the service board can receive the signal of the changed clock source, it means that the changed clock source is valid.
[0086] Among them, the CPU of the service board will select the optimal clock source of the service board through the timer task. If the optimal clock source of the service board changes, the service board will send a clock source change message to the main control board. The clock source change message carries the slot number of the service board, the interface of the changed clock source, and the validity of the clock source connected to the interface. Then the main control board can determine whether the slot number is consistent with the slot number of the service board to which the currently used clock source belongs. If not, it means that the optimal clock source currently selected by the service board and the clock source currently used by the main control board are not from the same service board, and do not involve the switching of different clock sources on the same service board. Therefore, the main control board will not process it temporarily; if they are consistent and the changed clock source is valid, it means that the optimal clock source currently selected by the service board and the clock source currently used by the main control board are from the same service board, which will involve the switching of different clock sources on the same service board. Therefore, the main control clock state is set to the forced holdover mode and the second timer is started. That is, before the second timer times out, the main control board will not use the clock signal of the optimal clock source selected by the service board this time.
[0087] It can be understood that after the second timer times out, if the optimal clock source selected by the main control board through the timing task is the same as the optimal clock source selected by the business board this time, and the main control board determines that the master clock state is not in forced holdover mode, the currently used clock source can be switched to the optimal clock source.
[0088] The timeout period of the second timer can be set based on an empirical value. The timeout period matches the time that the clock signal is in an unstable state when the clock source of the service board is switched. Different clock chips of the service board and different clock frequencies of the clock source will affect the time that the clock signal is in an unstable state. As an example, the timeout period of the second timer can be 15 seconds.
[0089] When using this method, if the main control board determines that the currently used clock source and the optimal clock source currently selected by the business board are from the same business board, it may involve switching of different clock sources on the same business board. In this case, the main control board sets the master clock state to forced holdover mode, which can prevent the main control board from switching the clock source temporarily. After the second timer times out, the main control board will release the forced holdover mode, which is equivalent to shielding the transition period when the clock on the business board is in an unstable state. It can avoid the clock of the network device from generating excessive clock noise, ensure the clock stability of the network device, and thus avoid the reduction in time synchronization service accuracy and packet loss caused by clock source switching.
[0090] The method described in the above embodiment can be implemented by a service board master clock source selection processing module (referred to as source selection processing module for short), the functions of which include service board source selection processing and main control board source selection processing. Figure 3 As shown, the method comprises the following steps:
[0091] S301. The service board selects the best clock source in the board through a scheduled task.
[0092] Among them, the timing duration of the scheduled task is the duration pre-set in the business board, and the embodiment of the present application does not limit this duration.
[0093] S302: The service board determines whether the selected optimal clock source is consistent with the optimal clock source selected last time.
[0094] If yes, there is no change and no action is required.
[0095] If not, execute S303.
[0096] S303: The service board sends a clock source change message to the main control board.
[0097] Among them, the clock source change message includes the slot number of the business board, and optionally may also include the link information of the optimal clock source selected this time and the validity of the optimal clock source. The link information can specifically be the interface number of the interface on the business board used to connect to the clock link of the optimal clock source.
[0098] S304: The main control board performs clock protection judgment through the clock status protection module.
[0099] Optionally, after receiving the clock source change message, the main control board may first execute S304. Clock protection judgment refers to judging whether clock state protection is required at this time. If it is determined that clock state protection is not required, then continue to execute S305.
[0100] The specific method of clock protection determination will be introduced in subsequent embodiments.
[0101] S305: The main control board determines whether the current clock source switching belongs to the switching source within the same service board.
[0102] If not, it means that it does not involve the switching of different clock sources on the same service board, and no processing is performed; if so, execute S306.
[0103] The main control board can determine whether the current source slot number is consistent with the slot number of the service board to which the currently used clock source belongs. The current source slot number is the slot number carried in the clock source change message.
[0104] If they are inconsistent, it is determined that the current clock source switching does not belong to the switching within the same service board;
[0105] If they are consistent, the validity of the clock source corresponding to the interface number carried in the clock source change message is further determined. If the clock source is valid, it is determined that the current clock source switching belongs to the switching source within the same business board; if the clock source is invalid, it is determined that the current clock source switching does not belong to the switching within the same business board.
[0106] S306: The main control board calls the clock state protection module to set the current main control clock state to the forced holdover mode and starts a 15-second timer.
[0107] The 15-second timer is the second timer in the above embodiment.
[0108] S307, when the 15-second timer times out, the main control board calls the clock state protection module to release the forced holdover mode of the current main control clock state.
[0109] After S307 , S314 may be executed.
[0110] S308. The main control board selects the optimal clock source for all service boards through a scheduled task.
[0111] Among them, the timing duration of the scheduled task is the duration pre-set in the main control board, and the embodiment of the present application does not limit this duration.
[0112] S309: The main control board determines whether the selected optimal clock source is consistent with the currently used clock source.
[0113] It can be understood that the clock source currently used is the optimal clock source selected by the main control board last time.
[0114] If yes, it means that the optimal clock source has not changed and no processing is required; if no, execute S310.
[0115] S310. The main control board determines whether the clock source can be switched currently through the source switching protection module.
[0116] If yes, execute S311; if no, return to S308.
[0117] The method by which the source switching protection module determines whether the clock source can be switched will be introduced in subsequent embodiments.
[0118] S311. The main control board calls the clock state protection module to set the main control clock state to the forced holdover mode and starts a 10-second timer.
[0119] The 10-second timer is the first timer in the above embodiment.
[0120] S312, the FPGA or CPLD of the main control board is switched.
[0121] Among them, the FPGA or CPLD is the source selection switch of the main control board. The source selection switch can switch the clock link of the currently used clock source to the clock link of the optimal clock source, so that the clock chip of the main control board can receive the clock signal of the optimal clock source. However, since the main control clock state is set to forced holdover mode, the main control board temporarily does not use the clock signal of the optimal clock source.
[0122] S313, the 10-second timer times out, and the main control board calls the clock status protection module to release the forced holdover mode of the main control clock status.
[0123] S314: The main control board switches the currently used clock source to the currently selected optimal clock source.
[0124] By adopting this method, when different clock sources need to be switched on the business board, and when the optimal clock source needs to be switched on the main control board, the main control board will set the main control clock state to a forced holdover state and start a timer. After the timer times out, the main control board will actually switch the currently used clock source to the re-elected optimal clock source. This can avoid in advance the unstable clock signal generated when the business board is used to switch the clock source, and can avoid the unstable clock signal generated when the main control board is used to switch the clock source, thereby ensuring the clock stability of the entire distributed network equipment, avoiding the time jump problem caused by clock instability, and further avoiding the problem of reduced accuracy of time synchronization services and packet loss.
[0125] It is understandable that after the business board selects the optimal clock source within the board and the main control board selects the optimal clock source for all business boards, both may trigger the main control board to set the master clock state to the forced holdover state and start a timer respectively. If the master clock state is set to the forced holdover state multiple times in a short period of time, multiple timers may be started, which will cause clock state conflicts. The problem that the most recently set forced holdover state is released prematurely due to the timeout of the timer started first may occur. In order to avoid this problem, the clock protection module can perform protection processing on the forced holdover state of the master clock. Based on this, in some embodiments of the present application, before setting the master clock state to the forced holdover mode, the method also includes:
[0126] Determine whether the current forced holdover mode count value is 0, the initial value of the count value is 0; if not, add 1 to the count value, and determine that the master clock state has been successfully set to the forced holdover mode; if so, add 1 to the count value, and execute the step of setting the master clock state to the forced holdover mode.
[0127] The count value indicates the number of times the master clock state has been set to the forced holdover mode. If the count value is not 0, it means that the master clock state has been set to the forced holdover mode. There is no need to set it again. It is assumed that the setting has been successful. The count value can be directly increased by 1, indicating that the master clock state has been set to the forced holdover mode once. If the count value is 0, it means that the master clock state is not currently set to the forced holdover mode. In this case, the master clock state can be set to the forced holdover mode and the count value can be increased by 1.
[0128] Accordingly, before releasing the forced holdover mode of the master clock state, the method further includes:
[0129] It is determined whether the count value of the current forced holdover mode is greater than 1; if so, the count value is reduced by 1 and the master clock state is kept in the forced holdover mode; if not, the step of releasing the forced holdover mode of the master clock state is performed.
[0130] If the count value is greater than 1, it means that the master clock state has been set to the forced holdover mode for multiple times, that is, multiple timers have been started, and currently only one timer has timed out, and there are other timers started due to the setting of the forced holdover mode that have not timed out, so the forced holdover mode cannot be temporarily released, but the count value can be reduced by 1. If the count value is less than or equal to 1, it means that the timer that has timed out is the last timer, that is, there is only one forced holdover mode setting that has not been released, so the forced holdover mode of the master clock state can be released at this time, and the count value can be restored to 0.
[0131] The following describes the process of the clock protection module protecting the master clock in the forced holdover mode in combination with the specific process. Figure 4 As shown, the method includes:
[0132] S401 , initialize the count value of the forced holdover mode to 0.
[0133] When the master clock state needs to be set to the forced holdover mode, S402 is executed.
[0134] S402: Determine whether the current count value is 0.
[0135] If yes, execute S403; if no, execute S404.
[0136] S403: Set the master clock state to the forced holdover mode, and increase the count value by 1.
[0137] After S403, S405 is executed.
[0138] S404: Add 1 to the count value.
[0139] After S404, S405 is executed.
[0140] S405: Determine that the master clock state has been successfully set to the forced holdover mode.
[0141] S406: A timer has timed out and the forced holdover mode needs to be released.
[0142] S407: Determine whether the count value is greater than 1.
[0143] If yes, execute S408; if no, execute S409.
[0144] S408, reducing the count value by 1, and maintaining the master clock state in the forced holdover mode.
[0145] S409: Release the forced holdover mode of the master clock state, and set the count value to 0.
[0146] S410: Determine whether the forced holdover mode is successfully released.
[0147] By adopting this method, by maintaining the count value of the forced holdover mode, the operation of the master clock state can be locked. Each time the forced holdover mode needs to be set, the count value is increased by 1. Whenever the timer times out and the forced holdover mode needs to be released, the count value is reduced by 1. When the count value reaches 1, if the forced holdover mode needs to be released, the forced holdover mode will be truly released. Otherwise, the forced holdover mode of the master clock state will be maintained. In this way, the master clock state can be protected, avoiding the problem of premature release of the forced holdover state in the scenario where the priorities or availability of the clock sources of multiple service boards change at the same time, so that the main control board can avoid using unstable clock signals, and improve the clock stability when multiple clock sources change in a short period of time.
[0148] In addition, in the related art, the main control board selects the best clock source from the clock sources of each service board according to the priority of each clock source and the validity of the received clock signal. A service board has multiple clock sources, but the main control board can only receive one clock signal of the service board in the same time period. This clock signal is used to represent all the clock signals of the service board. At present, the main control board has a problem of misjudging the validity of the clock signal of the service board for a short time.
[0149] For example, a service board has multiple clock sources, and one of the clock sources is disconnected. The service board needs to switch to another clock source. During the clock source switching process, the service board cannot send a clock signal to the main control board, causing the main control board to believe that all the current clock sources of the service board are invalid. After the service board completes the clock source switching and the main control board receives the clock signal sent by the service board again, it will re-believe that the clock source of the service board is valid. When the main control board believes that all the current clock sources of the service board are invalid, it may select the clock source of other service boards with lower priority as the optimal clock source, resulting in a misjudgment problem.
[0150] by Figure 1For example, external clock sources 1, 2, 3, and 4 correspond to priorities 1, 2, 3, and 4 respectively. If external clock source 1 with a priority of 1 is disconnected, the main control board should theoretically select external clock source 2 with a priority of 2 as the optimal clock source. However, since both external clock source 1 and external clock source 2 are on service board 1, when external clock source 1 is disconnected, all clock sources of service board 1 are disconnected. Service board 1 needs to switch the clock link to the clock link of external clock source 2 before it can receive the clock signal of external clock source 2 and send the clock signal of external clock source 2 to the main control board.
[0151] During the clock source switching process of service board 1, service board 1 cannot send a clock signal to the main control board, but service board 2 will send a clock signal of external clock source 3 with priority 3 to the main control board. At this time, since the main control board does not receive the clock signal sent by service board 1, it will select external clock source 3 as the optimal clock source and switch the currently used clock source to external clock source 3. In this case, the optimal clock source selected by the service board is actually not the currently available clock source with the highest priority, that is, there is a misjudgment problem, resulting in an inaccurate selected clock source.
[0152] And after the business board 1 sends the clock signal of the external clock source 2 to the main control board, the main control board will use the external clock source 2 as the optimal clock source, and then switch the clock source again. The frequent switching of the clock source will also cause the problem of clock instability.
[0153] In order to solve this problem, in the embodiment of the present application, the master control source switching protection module can be used to delay the master control to switch the clock delay, that is, before the master control clock state is set to the forced holdover mode and the first timer is started, the method also includes the following steps:
[0154] Step 1: Determine whether the optimal clock source is consistent with the currently used clock source.
[0155] If yes, go to step 2; if no, go to step 3.
[0156] Step 2: Set the number of source switching protection times to a preset initial value, and return to the step of reselecting the optimal clock source every preset time period.
[0157] It can be understood that if the optimal clock source selected by the main control board is the same as the currently used clock source, it means that the current main control board does not need to switch the optimal clock source.
[0158] Step 3: Determine whether the number of times of switching source protection is 0.
[0159] If not, go to step 4; if so, go to step 5.
[0160] Step 4: If the number of source switching protection times is not 0, the number of source switching protection times is reduced by 1, and the process returns to the step of reselecting the optimal clock source every preset time period.
[0161] If the number of source switching protection times is not 0, it means that source switching protection is still needed at this time. In this case, even if the main control board has selected a new optimal clock source, the optimal clock source will not be switched.
[0162] Step 5: If the number of source protection switching times is 0, the number of source protection switching times is set to a preset initial value, and the master clock state is set to a forced holdover mode, and the first timer is started.
[0163] If the number of source switching protection times is 0, it means that there is no need to perform source switching protection at this time. In this case, the master clock state can be set to the forced holdover mode, and after the forced holdover mode is released, the optimal clock source can be switched.
[0164] Optionally, the initial value of the number of source switching protection times can be 2. Under normal circumstances, the service board can complete the switching of the clock source within two preset time periods. Setting the initial value of the number of source switching protection times to 2 can not only avoid the main control board from selecting the source incorrectly, but also enable the main control board to switch to the optimal clock source in time. The following takes the preset initial value of the number of source switching protection times as 2 as an example to introduce the process of source switching protection. Figure 5 As shown, the method includes:
[0165] S501: The main control board sets the preset initial value of the number of source switching protection times to 2.
[0166] S502: The timing task of the main control board selects the best clock source and saves the best clock source selected this time.
[0167] S503: Determine whether the optimal clock source selected this time is consistent with the currently used clock source.
[0168] If yes, execute S504; if no, execute S505.
[0169] It can be understood that the clock source currently used is the optimal clock source previously selected by the main control board and successfully switched.
[0170] S504: The main control board resets the number of source switching protection times to 2 and returns to S502.
[0171] S505: The main control board determines whether the number of times of switching source protection is 0.
[0172] If yes, execute S506; if no, execute S507.
[0173] S506: reset the number of switching source protection times to 2, and after the current master clock state is released from the forced holdover mode, switch the currently used clock source to the optimal clock source selected this time.
[0174] S507: Reduce the number of source protection times by 1, and return to S502.
[0175] By adopting this method, the processing of clock source switching by the main control board is delayed by setting the number of source switching protection times. The main control board can switch the clock source only when the number of source switching protection times is 0. That is, the main control board needs to delay the preset initial value of cycles for selecting the optimal clock source before it can perform the source switching process. In this way, even if a business board does not send a clock signal in a short period of time, the main control board will not switch to the wrong optimal clock source, but can wait for the business board to send a signal and then reselect the accurate optimal clock source. This can avoid the problem of inaccurate source selection caused by the disconnection of the clock source of a business board, improve the accuracy of source selection, and avoid frequent clock source switching of the main control board, which can improve the stability of the clock signal.
[0176] Corresponding to the above method embodiment, the present application embodiment also provides a clock source switching device, which is applied to a main control board of a network device, such as Figure 6 As shown, the device comprises:
[0177] A selection module 601 is used to reselect an optimal clock source every preset time period;
[0178] A setting module 602 is used to set the master clock state to a forced holdover mode and start a first timer if the optimal clock source is inconsistent with the currently used clock source;
[0179] An enabling module 603, configured to enable a clock link of the optimal clock source through a source selection switch;
[0180] A release module 604, configured to release the forced holdover mode of the master clock state after the first timer times out;
[0181] The switching module 605 is used to switch the currently used clock source to the optimal clock source when the master clock state is not in the forced holdover mode.
[0182] Optionally, the device further comprises:
[0183] A receiving module, used to receive a clock source change message sent by a service board, wherein the clock source change message includes a slot number of the service board and the validity of the changed clock source;
[0184] The setting module 602 is further used to set the master clock state to a forced holdover mode and start a second timer if the slot number of the service board is the same as the slot number of the service board to which the currently used clock source belongs and the changed clock source is valid;
[0185] The release module 604 is further configured to release the forced holdover mode of the master clock state after the second timer times out.
[0186] Optionally, the setting module 602 is further used for:
[0187] Determine whether the current count value of the forced holdover mode is 0, the initial value of the count value is 0;
[0188] If not, the count value is increased by 1, and it is determined that the master clock state has been successfully set to the forced holdover mode;
[0189] If yes, then the count value is increased by 1, and the step of setting the master clock state to the forced holdover mode is performed;
[0190] The release module 604 is further used for:
[0191] Determine whether the count value of the current forced holdover mode is greater than 1;
[0192] If yes, then the count value is reduced by 1, and the master clock state is kept in the forced holdover mode;
[0193] If not, the step of releasing the forced holdover mode of the master clock state is performed.
[0194] Optionally, the device further comprises:
[0195] Source protection module, used for:
[0196] Determine whether the optimal clock source is consistent with the currently used clock source;
[0197] If yes, the number of switching source protection times is set to a preset initial value, and the selection module 601 is triggered to reselect the optimal clock source every preset time period;
[0198] If not, determine whether the number of source protection times is 0;
[0199] If the number of source protection switching times is not 0, the number of source protection switching times is reduced by 1, and the selection module 601 is triggered to reselect the optimal clock source every preset time period;
[0200] If the number of source protection switching times is 0, the number of source protection switching times is set to the preset value, and the setting module 602 is triggered to set the master clock state to the forced holdover mode, and start the first timer.
[0201] Optionally, the preset initial value is 2.
[0202] An embodiment of the present application also provides a network device, which includes a main control board and a service board, and the main control board is used to implement the method steps in the above method embodiment.
[0203] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned clock source switching methods are implemented.
[0204] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any clock source switching method in the above embodiments.
[0205] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.
[0206] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0207] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0208] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims
1. A clock source switching method, characterized in that: Applied to a main control board of a network device, the method comprises: Reselect the optimal clock source every preset period of time; If the optimal clock source is inconsistent with the currently used clock source, the master clock state is set to a forced holdover mode and the first timer is started; Turning on the clock link of the optimal clock source by means of a source selection switch; After the first timer times out, releasing the forced holdover mode of the master clock state; When the master clock state is not in the forced holdover mode, the currently used clock source is switched to the optimal clock source.
2. The method according to claim 1, characterized in that The method further comprises: Receiving a clock source change message sent by a service board, wherein the clock source change message includes a slot number of the service board and the validity of the changed clock source; If the slot number of the service board is the same as the slot number of the service board to which the currently used clock source belongs, and the changed clock source is valid, the master clock state is set to the forced holdover mode, and the second timer is started; After the second timer times out, the forced holdover mode of the master clock state is released.
3. The method according to claim 1 or 2, characterized in that: Before setting the master clock state to the forced holdover mode, the method further includes: Determine whether the current count value of the forced holdover mode is 0, the initial value of the count value is 0; If not, the count value is increased by 1, and it is determined that the master clock state has been successfully set to the forced holdover mode; If yes, then the count value is increased by 1, and the step of setting the master clock state to the forced holdover mode is performed; Before releasing the forced holdover mode of the master clock state, the method further includes: Determine whether the count value of the current forced holdover mode is greater than 1; If yes, then the count value is reduced by 1, and the master clock state is kept in the forced holdover mode; If not, the step of releasing the forced holdover mode of the master clock state is performed.
4. The method according to claim 1, characterized in that: Before setting the master clock state to the forced holdover mode and starting the first timer, the method further includes: Determine whether the optimal clock source is consistent with the currently used clock source; If yes, the number of switching source protection times is set to a preset initial value, and the process returns to the step of reselecting the optimal clock source every preset time period; If not, determine whether the number of source protection times is 0; If the number of source protection switching times is not 0, the number of source protection switching times is reduced by 1, and the process returns to the step of reselecting the optimal clock source every preset time period; If the number of source protection switching times is 0, the number of source protection switching times is set to the preset value, and the steps of setting the master clock state to the forced holdover mode and starting the first timer are performed.
5. The method according to claim 4, characterized in that The preset initial value is 2.
6. A clock source switching device, characterized in that: Applied to a main control board of a network device, the device comprises: A selection module is used to reselect the optimal clock source every preset time period; A setting module, configured to set the master clock state to a forced holdover mode and start a first timer if the optimal clock source is inconsistent with the currently used clock source; An enabling module, used for enabling a clock link of the optimal clock source through a source selection switch; A release module, used for releasing the forced holdover mode of the master clock state after the first timer times out; The switching module is used to switch the currently used clock source to the optimal clock source when the master clock state is not in the forced holdover mode.
7. The device according to claim 6, characterized in that The device also includes: A receiving module, used to receive a clock source change message sent by a service board, wherein the clock source change message includes a slot number of the service board and the validity of the changed clock source; The setting module is further configured to set the master clock state to a forced holdover mode and start a second timer if the slot number of the service board is the same as the slot number of the service board to which the currently used clock source belongs and the changed clock source is valid; The release module is further configured to release the forced holdover mode of the master clock state after the second timer times out.
8. The device according to claim 6 or 7, characterized in that The setting module is also used for: Determine whether the current count value of the forced holdover mode is 0, the initial value of the count value is 0; If not, the count value is increased by 1, and it is determined that the master clock state has been successfully set to the forced holdover mode; If yes, then the count value is increased by 1, and the step of setting the master clock state to the forced holdover mode is performed; The release module is further used for: Determine whether the count value of the current forced holdover mode is greater than 1; If yes, then the count value is reduced by 1, and the master clock state is kept in the forced holdover mode; If not, the step of releasing the forced holdover mode of the master clock state is performed.
9. The device according to claim 6, characterized in that The device also includes: Source protection module, used for: Determine whether the optimal clock source is consistent with the currently used clock source; If yes, the number of source switching protection times is set to a preset initial value, and the selection module is triggered to reselect the optimal clock source every preset time period; If not, determine whether the number of source protection times is 0; If the number of source protection switching times is not 0, the number of source protection switching times is reduced by 1, and the selection module is triggered to reselect the optimal clock source every preset time period; If the number of source protection switching times is 0, the number of source protection switching times is set to the preset value, and the setting module is triggered to set the master clock state to the forced holdover mode, and start the first timer.
10. The device according to claim 9, characterized in that The preset initial value is 2.
11. A network device, characterized in that: It comprises a main control board and a business board, and the main control board is used to implement any method described in claims 1-5.
12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.