Signal detection circuit, signal detection method, chip and electronic equipment

Abstract

The invention discloses a signal detection circuit, a signal detection method, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The signal detection circuit comprises a comparison circuit used for outputting a comparison signal according to a comparison result of a voltage value of a target signal and a reference voltage value; and the auxiliary detection circuit is used for outputting a signal detection result based on the comparison signal and a signal characteristic, the signal characteristic is a characteristic possessed by the communication signal of the reference type, and the signal detection result is used for indicating whether the target signal is the communication signal of the reference type or not. Based on the signal detection circuit, even if the voltage value of the target signal exceeds the reference voltage value, the target signal can be further detected according to the signal characteristics of the communication signal of the reference type, so that the false detection phenomenon caused by directly using the target signal with the larger voltage value as the communication signal of the reference type can be reduced; and the signal detection accuracy is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular to a signal detection circuit, a signal detection method, a chip, and an electronic device. Background Art

[0002] In the field of integrated circuit technology, electronic devices generally include a signal detection circuit, which is used to detect whether a signal is a reference type communication signal. For example, a reference type communication signal may refer to a signal transmitted in the form of 8b10b (8 bits and 10 bits) encoding.

[0003] In the related art, the signal detection circuit includes a filter circuit and a comparison circuit connected to each other. The filter circuit is used to extract the DC component of the target signal; the comparison circuit is used to compare the DC component extracted by the filter circuit with the reference DC component, and when the DC component extracted by the filter circuit is greater than the reference DC component, the detection result indicating that the target signal is a reference type of communication signal is output, and when the DC component extracted by the filter circuit is less than or equal to the reference DC component, the detection result indicating that the target signal is not a reference type of communication signal is output.

[0004] The DC component of a signal is usually determined based on the voltage value (also called amplitude) of the signal. In some application scenarios, even if the target signal is not a reference type of communication signal (for example, the target signal is noise), the voltage value of the target signal may reach the order of magnitude of the voltage value of the reference type of communication signal, thereby making the DC component extracted by the filtering circuit greater than the reference DC component, thereby causing the target signal to be mistaken for a reference type of communication signal, reducing the accuracy of signal detection. Summary of the invention

[0005] The embodiments of the present application provide a signal detection circuit, a signal detection method, a chip and an electronic device, which can be used to improve the accuracy of signal detection. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present application provides a signal detection circuit, including:

[0007] A comparison circuit, used for outputting a comparison signal according to a comparison result between a voltage value of a target signal and a reference voltage value;

[0008] The auxiliary detection circuit is used to output a signal detection result based on the comparison signal and the signal characteristic, wherein the signal characteristic is a characteristic of a communication signal of a reference type, and the signal detection result is used to indicate whether the target signal is a communication signal of the reference type.

[0009] In a possible implementation manner, the signal characteristic includes at least one of a code pattern characteristic or a frequency characteristic.

[0010] In a possible implementation, the auxiliary detection circuit includes:

[0011] A trigger circuit, used for sampling the comparison signal according to a clock signal and outputting a sampling signal;

[0012] A logic circuit, used for performing a logic operation on the sampling signal according to the signal characteristics and outputting a counting processing control signal;

[0013] The counter is used to perform counting processing according to the counting processing control signal and output the signal detection result according to the counting processing result.

[0014] In a possible implementation, the signal characteristic includes a code type characteristic; the code type characteristic includes: in the communication signal of the reference type, the maximum number of consecutive high-level signals or consecutive low-level signals is a specific value n, where n is an integer greater than 1; the trigger circuit includes n+1 triggers connected in sequence, the sampling signal includes the latest sampled n+1 level signals, the logic circuit includes a first logic circuit, the counting processing control signal includes a reset signal, and the counter includes a first counter;

[0015] The n+1 triggers are used to sample the comparison signal according to the clock signal and output the n+1 level signals;

[0016] The first logic circuit is used to perform a logic operation on the n+1 level signals according to the code type characteristics and output the clear signal;

[0017] The first counter is used to perform counting processing according to the clear signal, and output the signal detection result according to the counting processing result.

[0018] In a possible implementation, the signal characteristic includes a frequency characteristic; the frequency characteristic includes: there are no less than k level signals satisfying the high frequency condition in the communication signal of the reference type, k is an integer greater than 1, wherein one level signal satisfying the high frequency condition is determined based on m level signals constituting a reference code pattern, m is an integer greater than 2; the trigger circuit includes m triggers connected in sequence, the sampling signal includes the latest sampled m level signals, the logic circuit includes a second logic circuit, the counting processing control signal includes an enable counting signal, and the counter includes a second counter;

[0019] The m triggers are used to sample the comparison signal according to the clock signal and output the m level signals;

[0020] The second logic circuit is used to perform a logic operation on the m level signals according to the frequency characteristics and output the enable counting signal;

[0021] The second counter is used to perform counting processing according to the enable counting signal, and output the signal detection result according to the counting processing result.

[0022] In a possible implementation, the signal characteristics include a code type characteristic and a frequency characteristic; the code type characteristic includes: in the communication signal of the reference type, the maximum number of continuously appearing high-level signals or continuously appearing low-level signals is a specific value n, where n is an integer greater than 1; the frequency characteristic includes: there are no less than k level signals that meet the high-frequency condition in the communication signal of the reference type, where k is an integer greater than 1, wherein one level signal that meets the high-frequency condition is determined based on m level signals constituting the reference code type, where m is an integer greater than 2; n+1 is greater than or equal to m;

[0023] The trigger circuit includes n+1 triggers connected in sequence, the sampling signal includes the latest sampled n+1 level signals, the logic circuit includes a first logic circuit and a second logic circuit, the counting processing signal includes a clear signal and an enable counting signal, and the counter includes a third counter;

[0024] The n+1 triggers are used to sample the comparison signal according to the clock signal and output the n+1 level signals;

[0025] The first logic circuit is used to perform a logic operation on the n+1 level signals according to the code type characteristics and output the clear signal;

[0026] The second logic circuit is used to perform a logic operation on the m level signals output by the m flip-flops connected in sequence among the n+1 flip-flops according to the frequency characteristics, and output the enable counting signal;

[0027] The third counter is used to perform counting processing according to the clear signal and the enable counting signal, and output the signal detection result according to the counting processing result.

[0028] In one possible implementation, the comparison circuit is also used to output the target signal based on a comparison result of a voltage value of the target signal input at the first input terminal and a ground voltage value input at the second input terminal when the signal detection result indicates that the target signal is a communication signal of the reference type.

[0029] In one possible implementation, the signal detection circuit further includes a first control circuit, and the first control circuit is used to control the second input terminal to input the ground voltage value when the signal detection result indicates that the target signal is a communication signal of the reference type.

[0030] On the other hand, the embodiment of the present application further provides a signal detection method, including:

[0031] Outputting a comparison signal according to a comparison result between the voltage value of the target signal and the reference voltage value;

[0032] Based on the comparison signal and the signal characteristic, a signal detection result is output, wherein the signal characteristic is a characteristic of a communication signal of a reference type, and the signal detection result is used to indicate whether the target signal is a communication signal of the reference type.

[0033] In a possible implementation manner, the signal characteristic includes at least one of a code pattern characteristic or a frequency characteristic.

[0034] On the other hand, an embodiment of the present application further provides a chip, which includes any of the signal detection circuits described above.

[0035] On the other hand, an embodiment of the present application further provides an electronic device, which includes any of the signal detection circuits described above.

[0036] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0037] The technical solution provided by the embodiment of the present application is that the signal detection circuit includes a comparison circuit and an auxiliary detection circuit. The comparison circuit is used to detect the target signal from the perspective of the voltage value, and the auxiliary detection circuit is used to perform auxiliary detection on the target signal from the perspective of the signal characteristics of the reference type of communication signal. Based on this, even if the voltage value of the target signal exceeds the reference voltage value, the target signal can be further detected according to the signal characteristics of the reference type of communication signal, thereby reducing the false detection phenomenon caused by directly using the target signal with a larger voltage value as the reference type of communication signal, and improving the accuracy of signal detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a structural schematic diagram of a signal detection circuit in the related art;

[0040] Figure 2 is a structural schematic diagram of a signal detection circuit provided in an embodiment of the present application;

[0041] Figure 3 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0042] Figure 4 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0043] Figure 5 is a structural schematic diagram of a first logic circuit provided in an embodiment of the present application;

[0044] Figure 6 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0045] Figure 7 is a structural schematic diagram of a second logic circuit provided in an embodiment of the present application;

[0046] Figure 8 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0047] Fig. 9 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0048] Fig.10 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0049] Fig.11 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0050] Fig.12 is a structural schematic diagram of another signal detection circuit provided in an embodiment of the present application;

[0051] Fig.13 is a flow chart of a signal detection method provided in an embodiment of the present application;

[0052] Fig.14 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0053] Fig.15 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0054] The reference numerals in the figures represent respectively:

[0055] 10-comparison circuit; 20-auxiliary detection circuit; 30-trigger circuit; 40-logic circuit; 50-counter; 31-trigger; 41-first logic circuit; 42-second logic circuit; 51-first counter; 52-second counter; 53-third counter; 411-first logic sub-circuit; 412-second logic sub-circuit; 413-first OR gate; 421-third logic sub-circuit; 422-fourth logic sub-circuit; 423-second OR gate; 60-first control circuit; 70-second control circuit. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0057] In the field of integrated circuit technology, electronic devices generally include a signal detection circuit, which is used to detect whether a signal is a reference type communication signal. A reference type communication signal may be any type of communication signal, and a communication signal refers to a signal that carries information that needs to be communicated. Exemplarily, if the signal is not a reference type communication signal, the signal may be another type of communication signal, or it may be noise. The reference type can be set based on experience, or it can be flexibly adjusted according to detection requirements, and the embodiments of the present application do not limit this. Exemplarily, a reference type communication signal may refer to a signal transmitted in the form of 8b10b encoding, in which case the reference type communication signal may also be referred to as an 8b10b signal.

[0058] The embodiment of the present application is described by taking the reference type communication signal as an 8b10b signal as an example, and the signal detection circuit provided by the embodiment of the present application can be applied to the high-speed serial data communication field in the field of analog integrated circuit technology. In the field of analog integrated circuits, several high-speed serial communication protocols require that signals be transmitted in the form of 8b10b encoding on a high-speed serial line. In the receiving chip of the electronic device of these protocols, it is necessary to include an 8b10b signal detection circuit to confirm whether the received signal is a normal communication signal (i.e., 8b10 signal) or noise, so as to set the receiving chip to different working states, such as high-speed communication or sleep state. Exemplarily, high-speed serial communication protocols may include, but are not limited to, protocols such as PCIE (Peripheral Component Interconnect Express, peripheral component interconnect fast bus), USB3.0 (Universal Serial Bus 3.0, Universal Serial Bus 3.0), Rapid IO (fast input / output), MIPI-APHY (Mobile Industry Processor Interface-Automotive Physical, mobile industry processor interface-automotive physical layer) and the like.

[0059] In the related art, the signal detection circuit includes a filter circuit and a comparison circuit connected to each other. The filter circuit is used to extract the DC component of the target signal; the comparison circuit is used to compare the DC component extracted by the filter circuit with the reference DC component, and when the DC component extracted by the filter circuit is greater than the reference DC component, the detection result indicating that the target signal is a reference type of communication signal is output, and when the DC component extracted by the filter circuit is less than or equal to the reference DC component, the detection result indicating that the target signal is not a reference type of communication signal is output.

[0060] The DC component of a signal is usually determined based on the voltage value of the signal. In some application scenarios, even if the target signal is not a reference type of communication signal (for example, the target signal is noise), the voltage value of the target signal may reach the order of magnitude of the voltage value of the reference type of communication signal, thereby making the DC component extracted by the filtering circuit greater than the reference DC component, thereby causing the target signal to be mistaken for a reference type of communication signal, reducing the accuracy of signal detection.

[0061] For example, taking the reference type communication signal as an 8b10b signal as an example, the structure of the signal detection circuit in the related art can be as follows: Figure 1 shown. Figure 1The signal detection circuit shown includes a filter circuit and a comparison circuit connected to each other, wherein the filter circuit is an RC filter circuit composed of a resistor R1 and a capacitor C1, and the comparison circuit is a comparator CMP1 having a positive input terminal, a negative input terminal and an output terminal.

[0062] Figure 1 The principle of the signal detection circuit shown is as follows: Vin is the signal to be detected. After Vin passes through the RC filter circuit composed of the resistor R1 and the capacitor C1, the RC filter circuit extracts the DC component of Vin, and inputs the DC component of Vin to the positive input terminal of the comparator CMP1. The comparator CMP1 compares the DC component of Vin input at the positive input terminal with the reference DC component Vref input at the negative input terminal.

[0063] When Vin is a normal 8b10b signal (assuming the voltage value of the 8b10b signal is A), the DC component of Vin is 0.5*A (because the distribution of 0 and 1 of the 8b10b signal is 50% each). The reference DC component Vref is set to a value slightly less than 0.5*A. When the DC component of Vin is greater than the reference DC component Vref, the output Vo of the output terminal of the comparator CMP1 is 1, indicating that Vin is a normal 8b10b signal, that is, a normal 8b10b signal is detected; when the DC component of Vin is less than or equal to the reference DC component Vref, the output Vo of the output terminal of the comparator CMP1 is 0, indicating that Vin is not a normal 8b10b signal, that is, a normal 8b10b signal is not detected.

[0064] In the case where Vin is not a normal 8b10b signal, it can be considered that Vin is noise. If the voltage value of the noise is low, the signal detection circuit in the relevant technology can be used to detect the signal more accurately. However, in some application scenarios, such as the vehicle-mounted application scenario of MIPI-APHY, the voltage value of the noise will reach the order of magnitude of the signal. Therefore, even if Vin is noise, the DC component of Vin will be greater than the reference DC component Vref, so that the output Vo of the output terminal of the comparator CMP1 is 1, thereby mistaking the noise for a normal 8b10b signal, reducing the accuracy of signal detection. Therefore, it is crucial to provide a signal detection circuit that can improve the accuracy of signal detection.

[0065] The embodiment of the present application provides a signal detection circuit, which can improve the accuracy of signal detection. Figure 2The signal detection circuit provided in the embodiment of the present application includes a comparison circuit 10 and an auxiliary detection circuit 20, and the comparison circuit 10 is connected to the auxiliary detection circuit 20. Among them, the comparison circuit 10 is used to output a comparison signal according to the comparison result between the voltage value of the target signal and the reference voltage value. The auxiliary detection circuit 20 is used to output a signal detection result based on the comparison signal and the signal characteristic. The signal characteristic is a characteristic of a reference type of communication signal, and the signal detection result is used to indicate whether the target signal is a reference type of communication signal.

[0066] The target signal refers to the signal to be detected. The voltage value of the target signal is used to characterize the amplitude of the target signal. The amplitude of the target signal is used to indicate the strength of the target signal. After the target signal is input into the comparison circuit 10, the comparison circuit 10 can detect the voltage value of the target signal. The reference voltage value is less than the voltage value of the reference type communication signal. The reference voltage value can be set based on experience or flexibly adjusted according to the signal detection scenario. The embodiments of the present application do not limit this. The reference type communication signal can be any type of communication signal. For example, the reference type communication signal can refer to an 8b10b signal.

[0067] Exemplarily, the target signal is a digital signal, and the target signal only includes two level signals, a high level signal (1) and a low level signal (0). The target signal has a voltage value only at the high level signal, and does not have a voltage value at the low level signal. When the voltage value of the target signal is greater than the reference voltage value, the arrangement of the high level signal and the low level signal in the comparison signal output by the comparison circuit 10 is the same as the arrangement of the high level signal and the low level signal in the target signal; when the voltage value of the target signal is less than or equal to the reference voltage value, the comparison signal output by the comparison circuit 10 is all low level signals. Therefore, according to the comparison signal output by the comparison circuit 10, it can be reflected whether the voltage value of the target signal is greater than the reference voltage value.

[0068] Exemplarily, taking the signal detection scenario of detecting whether the target signal is an 8b10b signal as an example, the reference voltage value can be set to a smaller voltage value, for example, 10mV (millivolts). By setting the reference voltage value to 10mV, a large amount of noise with a small voltage value (that is, noise with a voltage value less than 10mV) can be identified according to the comparison signal output by the comparison circuit 10. When the target signal is a normal 8b10b signal, the voltage value of the target signal is usually 1V, and the reference voltage value of 10mV will not affect the judgment of the level signal 1 and 0 of the comparison circuit 10, that is, the comparison circuit 10 will output a comparison signal that is consistent with the level signal arrangement in the target signal.

[0069] Although it is possible to determine whether the voltage value of the target signal is greater than the reference voltage value based on the comparison signal output by the comparison circuit 10, since even if the target signal is not a reference type communication signal, the voltage value of the target signal is likely to be greater than the reference voltage value, in order to improve the accuracy of signal detection, the signal detection circuit in the embodiment of the present application also includes an auxiliary detection circuit 20. The auxiliary detection circuit 20 can output a signal detection result based on the comparison signal and the characteristics of the reference type communication signal. Based on this, even if the voltage value of the target signal exceeds the reference voltage value, the target signal can be further detected based on the signal characteristics of the reference type communication signal, thereby reducing the false detection phenomenon caused by directly using the target signal with a larger voltage value as the reference type communication signal, and improving the accuracy of signal detection.

[0070] The signal characteristics refer to the specific unique characteristics of the communication signal of the reference type. The signal characteristics can be flexibly changed according to the changes of the reference type, and the embodiments of the present application are not limited to this.

[0071] In one possible implementation, the signal characteristic includes at least one of a code type characteristic or a frequency characteristic. That is, the signal characteristic may include only a code type characteristic, may include only a frequency characteristic, or may include both a code type characteristic and a frequency characteristic. Among them, the code type characteristic includes: in the communication signal of the reference type, the maximum number of continuously occurring high-level signals or continuously occurring low-level signals is a specific value n, and n is an integer greater than 1. The frequency characteristic includes: there are no less than k level signals that meet the high-frequency condition in the communication signal of the reference type, k is an integer greater than 1, and a level signal that meets the high-frequency condition is determined based on m level signals constituting the reference code type, and m is an integer greater than 2. By considering the code type characteristic and / or frequency characteristic of the communication signal of the reference type to assist in detecting the target signal, it is beneficial to improve the matching degree between the signal detection result and the code type characteristic and / or frequency characteristic of the communication signal of the reference type, thereby improving the accuracy of the signal detection result.

[0072] The value of n is related to the reference type of communication signal. For example, when the reference type of communication signal is an 8b10b signal, the value of n is 5. That is, the maximum number of continuous high level signals or continuous low level signals in the 8b10b signal is 5.

[0073] The existence of no less than k level signals satisfying the high-frequency condition in the communication signal of the reference type indicates that the communication signal of the reference type has a strong high-frequency component, and the value of k can be set according to experience, or it can be flexibly adjusted according to the signal detection scene, and the embodiment of the present application is not limited to this, for example, the value of k is 2048. The high-frequency condition can be set according to experience, or it can be flexibly adjusted according to the signal detection scene, and the embodiment of the present application is not limited to this. Exemplarily, the level signal satisfying the high-frequency condition refers to a level signal whose continuous period is one clock cycle when a level signal is transmitted in one clock cycle. For the level signal transmitted in a certain clock cycle, if the level signal is different from the level signal transmitted in the previous clock cycle and the level signal transmitted in the next clock cycle, it is considered that the continuous period of the level signal is one clock cycle.

[0074] The reference pattern is a pattern that can determine a level signal that meets the high frequency condition. Exemplarily, the level signal that meets the high frequency condition refers to the situation of a level signal whose duration does not exceed one clock cycle, and the situation of the reference pattern is related to the value of m. For example, when the value of m is 3, the reference pattern includes a first pattern ("101" pattern) consisting of a high level signal, a low level signal and a high level signal arranged in sequence, and a second pattern ("010" pattern) consisting of a low level signal, a high level signal and a low level signal arranged in sequence. The first pattern indicates that there is a low level signal whose duration is one clock cycle, and the second pattern indicates that there is a high level signal whose duration is one clock cycle.

[0075] In some embodiments, the value of m may also be other values, for example, the value of m may also be 4. When the value of m is different, the reference code pattern is different.

[0076] In one possible implementation, see Figure 3 The auxiliary detection circuit 20 includes a trigger circuit 30, a logic circuit 40 and a counter 50. The counter 50 is connected to the logic circuit 40, which is also connected to the trigger circuit 30, and the trigger circuit 30 is also connected to the comparison circuit 10. Among them, the trigger circuit 30 is used to sample the comparison signal according to the clock signal and output the sampling signal; the logic circuit 40 is used to perform a logical operation on the sampling signal according to the signal characteristics and output a counting processing control signal; the counter 50 is used to perform counting processing according to the counting processing control signal and output the signal detection result according to the counting processing result. The process of outputting the signal detection result according to the comparison signal and the signal characteristics is divided into three sub-processes, which are respectively executed by the trigger circuit 30, the logic circuit 40 and the counter 50, so that different circuits have different divisions of labor, which is conducive to improving the standardization of circuit operation and improving the reliability of signal detection.

[0077] The clock signal refers to a pulse signal with periodicity. The trigger circuit 30 samples the comparison signal according to the clock signal, which specifically refers to the trigger circuit 30 sampling the comparison signal according to the clock edge of the clock signal, that is, for each clock edge in the clock signal, a level signal is sampled from the comparison signal. The clock edge refers to the mark of the level signal transition in the clock signal, and the clock edge can be a rising edge or a falling edge. Among them, the rising edge is used to indicate that the level signal in the clock signal changes from a low level signal to a high level signal, and the falling edge is used to indicate that the level signal in the clock signal changes from a high level signal to a low level signal. In the embodiment of the present application, the frequency of the clock signal is the data transmission rate of the received target signal. For example, if the data transmission rate of the target signal is 6Gbps (gigabits per second), the frequency of the clock signal is 6GHz (gigahertz).

[0078] It should be noted that after the trigger circuit 30 outputs the first sampling signal, each time a clock edge appears in the clock signal, a new sampling signal is output. That is to say, before the signal detection is completed, the trigger circuit 30 continuously outputs the sampling signal. Each time the trigger circuit 30 outputs a sampling signal, the logic circuit 40 outputs a counting processing control signal. The counting processing control signal is a signal for controlling the counting processing method of the counter 50. Each time the logic circuit outputs a counting processing control signal, the counter 50 performs a counting process (clearing the count value, increasing the count value, or keeping the count value unchanged, etc.), and the counting process result is the count value obtained after one or more counting processes.

[0079] In different situations of signal characteristics, the structures of the trigger circuit 30, the logic circuit 40 and the counter 50 are different. Next, the structures of the trigger circuit 30, the logic circuit 40 and the counter 50 are introduced in combination with four situations of signal characteristics.

[0080] Case 1: The signal characteristics include only the pattern characteristics.

[0081] In this case, see Figure 4 , the trigger circuit 30 includes n+1 triggers 31 connected in sequence, the sampling signal includes the latest sampled n+1 level signals, the logic circuit 40 includes a first logic circuit 41, the counting process control signal includes a clear signal, and the counter 50 includes a first counter 51. The first trigger 31 of the n+1 triggers 31 is connected to the comparison circuit 10, the first logic circuit 41 is connected to the n+1 triggers 31, and the first counter 51 is connected to the first logic circuit 41. Among them, the clear signal is used to indicate that the count value is cleared or the count value is kept unchanged.

[0082] n+1 triggers 31 are used to sample the comparison signal according to the clock signal and output n+1 level signals; the first logic circuit 41 is used to perform logic operations on the n+1 level signals according to the code type characteristics and output a clear signal; the first counter 51 is used to perform counting processing according to the clear signal and output a signal detection result according to the counting processing result. On the basis of considering the voltage value of the target signal, by only additionally considering the code type characteristics to realize the signal detection, the matching degree between the signal detection result and the code type characteristics can be improved, and the accuracy of signal detection can be improved to a certain extent. In addition, since only one characteristic is additionally considered, the efficiency of signal detection can also be guaranteed.

[0083] The trigger circuit 30 includes n+1 triggers 31 connected in sequence, and the n+1 triggers 31 are used to output the latest sampled n+1 level signals. The latest sampled n+1 level signals refer to the n+1 sampled signals with the shortest sampled duration among the sampled level signals. Among them, the sampled duration of the level signal refers to the duration between the sampling time of the level signal and the current time. The sampling time of the level signal refers to the time when the level signal is sampled.

[0084] Each trigger 31 is used to output a level signal among the latest sampled n+1 level signals. Exemplarily, when the first trigger 31 among the n+1 triggers 31 is connected to the comparison circuit 10, the p-th trigger 31 among the n+1 triggers 31 is used to output the level signal at the p-th position in the order of the sampled time length from short to long among the latest sampled n+1 level signals, where p is an integer not less than 1 and not greater than n+1.

[0085] Exemplarily, n+1 flip-flops connected in sequence may be understood as n+1-stage cascaded flip-flops 31 .

[0086] The embodiment of the present application does not limit the type of trigger 31, as long as it can sample the signal according to the clock signal. Exemplarily, the trigger 31 is a D trigger. The D trigger is an information storage device with a memory function and two stable states. It is the most basic logic unit that constitutes a variety of timing circuits and is also an important unit circuit in digital logic circuits. The D trigger has two stable states and can flip from one stable state to another stable state under the action of certain external signals.

[0087] In a possible implementation, when n+1 level signals are all the same level signals, the clear signal is the first level signal; when n+1 level signals are not all the same level signals, the clear signal is the second level signal. That is, the clear signal is the first level signal or the second level signal, and the first logic circuit 41 determines whether to output the first level signal or the second level signal by judging whether the n+1 level signals are the same level signals during the process of performing logic operations on the n+1 level signals according to the code type characteristics.

[0088] The first level signal is used to indicate that the count value is cleared, and the second level signal is used to indicate that the count value is kept unchanged. Exemplarily, the first level signal and the second level signal are represented by two different level signals, for example, the first level signal is a high level signal, and the second level signal is a low level signal; or the first level signal is a low level signal, and the second level signal is a high level signal.

[0089] The embodiment of the present application does not limit the structure of the first logic circuit 41, as long as it can ensure that the first logic circuit 41 has the function of outputting a first level signal when n+1 level signals are the same level signal, and outputting a second level signal when n+1 level signals are not the same level signal. In a possible implementation, see Figure 5 The first logic circuit 41 includes a first logic sub-circuit 411, a second logic sub-circuit 412 and a first OR gate 413; the first OR gate 413 is connected to the first logic sub-circuit 411 and the second logic sub-circuit 412, the first logic sub-circuit 411 is also connected to n+1 triggers 31, and the second logic sub-circuit 412 is also connected to n+1 triggers 31.

[0090] The first logic subcircuit 411 is used to output a first level signal when n+1 level signals are all high level signals, and to output a second level signal when n+1 level signals are not all high level signals. The second logic subcircuit 412 is used to output a first level signal when n+1 level signals are all low level signals, and to output a second level signal when n+1 level signals are not all low level signals. The first OR gate 413 is used to perform an OR operation on the output result of the first logic subcircuit 411 and the output result of the second logic subcircuit 412.

[0091] The structures of the first logic subcircuit 411 and the second logic subcircuit 412 can be flexibly set. Exemplarily, in the case where the first level signal is a high level signal and the second level signal is a low level signal, the first logic subcircuit 411 may include at least one first AND gate, which is used to output a high level signal when n+1 level signals are all high level signals, and output a low level signal when n+1 level signals are not all high level signals. The second logic subcircuit 412 may include n+1 inverters and at least one second AND gate, the n+1 inverters are used to invert the n+1 level signals and output n+1 inverted signals, and at least one second AND gate is used to output a high level signal when n+1 inverted signals are all high level signals (that is, n+1 level signals are all low level signals), and output a low level signal when n+1 inverted signals are not all high level signals (that is, n+1 level signals are not all low level signals).

[0092] The process of the first OR gate 413 performing an OR operation on the output result of the first logic sub-circuit 411 and the output result of the second logic sub-circuit 412 means that the first OR gate 413 outputs a first-level signal when at least one of the first logic sub-circuit 411 or the second logic sub-circuit 412 outputs a first-level signal; and outputs a second-level signal when both the first logic sub-circuit 411 and the second logic sub-circuit 412 output second-level signals.

[0093] In a possible implementation, the first counter 51 is used to clear the count value when the first logic circuit 41 outputs a first level signal, and to keep the count value unchanged when the first logic circuit 41 outputs a second level signal; if the count value is not zero when the detection end condition is met, a signal detection result indicating that the target signal is a reference type communication signal is output; if the count value is zero when the detection end condition is met, a signal detection result indicating that the target signal is not a reference type communication signal is output; wherein the initial count value of the first counter 51 is not zero. That is, in the process of counting according to the clear signal, the first counter 51 determines whether to clear the count value or keep the count value unchanged by judging whether the clear signal is a first level signal or a second level signal.

[0094] Meeting the detection end condition is used to constrain the detection duration to avoid inaccurate signal detection results caused by too long detection duration. Meeting the detection end condition can be set according to experience, or it can be flexibly adjusted according to the signal detection scenario, and the embodiments of the present application are not limited to this. For example, meeting the detection end condition can refer to the detection duration reaching a duration threshold, or it can refer to the number of clock edges that have appeared in the clock signal reaching a number threshold.

[0095] If the count value is not zero when the detection end condition is met, it means that before the detection end condition is met, the first logic circuit 41 outputs the second level signal and has not output the first level signal. In other words, before the detection end condition is met, there have been no continuous n+1 high level signals or n+1 continuous low level signals in the comparison signal. In other words, the maximum number of continuous high level signals or continuous low level signals in the comparison signal is n, and the comparison signal meets the code characteristics of the reference type of communication signal.

[0096] Since, when the voltage value of the target signal is greater than the reference voltage value, the arrangement of the high-level signal and the low-level signal in the comparison signal is the same as the arrangement of the high-level signal and the low-level signal in the target signal, the code type characteristic of the comparison signal that conforms to the reference type of communication signal can be considered to be the code type characteristic of the target signal whose voltage value is greater than the reference voltage value that conforms to the reference type of communication signal. Since only the code type characteristic is considered in case 1, if the count value is not zero when the detection end condition is met, it can be considered that the voltage value of the target signal is greater than the reference voltage value and the target signal conforms to the code type characteristic of the reference type of communication signal, and the first counter 51 outputs a signal detection result indicating that the target signal is a reference type of communication signal.

[0097] If the count value is zero when the detection end condition is met, it means that before the detection end condition is met, the first logic circuit 41 has outputted a first level signal. That is to say, before the detection end condition is met, there have been continuous n+1 high level signals or continuous n+1 low level signals in the comparison signal. In other words, the maximum number of continuous high level signals or continuous low level signals in the comparison signal is greater than n, and the comparison signal does not conform to the code type characteristics of the reference type communication signal. The reason why the comparison signal does not conform to the code type characteristics of the reference type communication signal may be that the voltage value of the target signal is less than or equal to the reference voltage value, or it may be that the voltage value of the target signal is greater than the reference voltage value but the target signal does not conform to the code type characteristics of the reference type communication signal. Regardless of the reason, the target signal is not a reference type communication signal. Therefore, the first counter 51 outputs a signal detection result indicating that the target signal is not a reference type communication signal.

[0098] Case 2: The signal characteristics include only frequency characteristics.

[0099] In this case 2, see Figure 6, the trigger circuit 30 includes m triggers 31 connected in sequence, the sampling signal includes the latest sampled m level signals, the logic circuit 40 includes a second logic circuit 42, the count processing control signal includes an enable count signal, and the counter 50 includes a second counter 52. The first trigger 31 of the m triggers 31 is connected to the comparison circuit 10, the second logic circuit 42 is connected to the m triggers 31, and the second counter 52 is connected to the second logic circuit 42. Among them, the enable count signal is used to indicate to increase the count value or keep the count value unchanged.

[0100] The m triggers 31 are used to sample the comparison signal according to the clock signal and output m level signals; the second logic circuit 42 is used to perform logic operations on the m level signals according to the frequency characteristics and output an enable count signal; the second counter 52 is used to perform counting processing according to the enable count signal and output a signal detection result according to the counting processing result. On the basis of considering the voltage value of the target signal, by only additionally considering the frequency characteristics to realize the signal detection, the matching degree between the signal detection result and the frequency characteristics can be improved, and the accuracy of signal detection can be improved to a certain extent. In addition, since only one characteristic is additionally considered, the efficiency of signal detection can also be guaranteed.

[0101] The trigger circuit 30 includes m triggers 31 connected in sequence, and the m triggers 31 are used to output the latest sampled m level signals. The latest sampled m level signals refer to the m sampled signals with the shortest sampled duration among the sampled level signals. Each trigger 31 is used to output a level signal among the latest sampled m level signals. Exemplarily, when the first trigger 31 among the m triggers 31 is connected to the comparison circuit 10, the qth trigger 31 among the m triggers 31 is used to output the level signal at the qth position in the order of the sampled duration from short to long among the latest sampled m level signals, and q is an integer not less than 1 and not greater than m.

[0102] In a possible implementation, when the code pattern formed by the m level signals is a reference code pattern, the enable count signal is a third level signal; when the code pattern formed by the m level signals is not a reference code pattern, the enable count signal is a fourth level signal. That is, when the enable count signal is a third level signal or a fourth level signal, the second logic circuit 42 determines whether to output the third level signal or the fourth level signal by judging whether the code pattern formed by the m level signals is a reference code pattern during the process of performing logic operations on the m level signals according to the frequency characteristics.

[0103] The third level signal is used to indicate an increase in the count value, and the fourth level signal is used to indicate a maintenance of the count value. Exemplarily, the third level signal and the fourth level signal are represented by two different level signals, for example, the third level signal is a high level signal, and the fourth level signal is a low level signal; or, the third level signal is a low level signal, and the fourth level signal is a high level signal.

[0104] The embodiment of the present application does not limit the structure of the second logic circuit 42, as long as it can ensure that the second logic circuit 42 has the function of outputting a third level signal when the code pattern composed of m level signals is a reference code pattern, and outputting a fourth level signal when the code pattern composed of m level signals is not a reference code pattern. In a possible implementation, the value of m is 3, and the reference code pattern includes a first code pattern composed of a high level signal, a low level signal, and a high level signal arranged in sequence, and a second code pattern composed of a low level signal, a high level signal, and a low level signal arranged in sequence. In this case, see Figure 7 The second logic circuit 42 includes a third logic sub-circuit 421, a fourth logic sub-circuit 422 and a second OR gate 423; the second OR gate 423 is connected to the third logic sub-circuit 421 and the fourth logic sub-circuit 422, the third logic sub-circuit 421 is also connected to three triggers 31 connected in sequence, and the fourth logic sub-circuit 422 is also connected to three triggers 31.

[0105] The third logic sub-circuit 421 is used to output a third level signal when the third code type composed of three level signals output by three sequentially connected triggers 31 is the first code type, and output a fourth level signal when the third code type is not the first code type; the fourth logic sub-circuit 422 is used to output the third level signal when the third code type is the second code type, and output the fourth level signal when the third code type is not the second code type; the second OR gate 423 is used to perform an OR operation on the output result of the third logic sub-circuit 421 and the output result of the fourth logic sub-circuit 422.

[0106] The structures of the third logic subcircuit 421 and the fourth logic subcircuit 422 can be flexibly set. Exemplarily, in the case where the third level signal is a high level signal and the fourth level signal is a low level signal, the third logic subcircuit 421 may include a first inverter, a second inverter, and at least one third AND gate, wherein the first inverter is used to invert the first level signal among the three level signals and output the inverted signal of the first level signal; the second inverter is used to invert the third level signal among the three level signals and output the inverted signal of the third level signal; and the at least one third AND gate is used to output a high level signal when the inverted signal of the first level signal, the second level signal, and the inverted signal of the third level signal are all high level signals, and output a low level signal when the inverted signal of the first level signal, the second level signal, and the inverted signal of the third level signal are not all high level signals.

[0107] The fourth logic subcircuit 422 may include a third inverter and at least one fourth AND gate, the third inverter is used to invert the second level signal among the three level signals and output the inverted signal of the second level signal, and the at least one fourth AND gate is used to output a high level signal when the first level signal, the inverted signal of the second level signal and the third level signal are all high level signals, and output a low level signal when the first level signal, the inverted signal of the second level signal and the third level signal are not all high level signals.

[0108] The process of the second OR gate 423 performing an OR operation on the output result of the third logic sub-circuit 421 and the output result of the fourth logic sub-circuit 422 means that the second OR gate 423 outputs a third level signal when at least one of the third logic sub-circuit 421 or the fourth logic sub-circuit 422 outputs a third level signal; and outputs a fourth level signal when both the third logic sub-circuit 421 and the fourth logic sub-circuit 422 output fourth level signals.

[0109] In a possible implementation, the second counter 52 is used to increase the count value when the second logic circuit 42 outputs a third level signal, and to keep the count value unchanged when the second logic circuit 42 outputs a fourth level signal; if the count value reaches k+s before the detection end condition is met, a signal detection result indicating that the target signal is a communication signal of the reference type is output; if the count value does not reach k+s when the detection end condition is met, a signal detection result indicating that the target signal is not a communication signal of the reference type is output; wherein s is the initial count value of the second counter 52, and s is an integer. The value of s can be set based on experience, or can be flexibly adjusted based on the application scenario, and the embodiment of the present application does not limit this, for example, the value of s can be zero.

[0110] If the count value reaches k+s before the detection end condition is met, it means that before the detection end condition is met, the second logic circuit 42 outputs the third level signal for k times. That is to say, before the detection end condition is met, the m level signals that can constitute the reference pattern appear in the comparison signal k times, and since each appearance of the m level signals constituting the reference pattern indicates that there is a level signal that meets the high-frequency condition in the comparison signal, therefore, before the detection end condition is met, k level signals that meet the high-frequency condition appear in the comparison signal, and the comparison signal meets the frequency characteristics of the reference type communication signal.

[0111] Since, when the voltage value of the target signal is greater than the reference voltage value, the arrangement of the high-level signal and the low-level signal in the comparison signal is the same as the arrangement of the high-level signal and the low-level signal in the target signal, the comparison signal conforms to the frequency characteristics of the reference type of communication signal, which can be considered as the target signal whose voltage value is greater than the reference voltage value conforms to the frequency characteristics of the reference type of communication signal. Since only the frequency characteristic is considered as a signal characteristic in case 2, if the count value reaches k+s before the detection end condition is met, it can be considered that the voltage value of the target signal is greater than the reference voltage value and the target signal conforms to the frequency characteristics of the reference type of communication signal, and the second counter 52 outputs a signal detection result indicating that the target signal is a reference type of communication signal.

[0112] If the count value does not reach k+s when the detection end condition is met, it means that when the detection end condition is met, the number of times the second logic circuit 42 outputs the third level signal does not reach k times. That is to say, when the detection end condition is met, the number of level signals that meet the high-frequency condition in the comparison signal does not reach k, and the comparison signal does not meet the frequency characteristics of the reference type of communication signal. The reason why the comparison signal does not meet the frequency characteristics of the reference type of communication signal may be that the voltage value of the target signal is less than or equal to the reference voltage value, or it may be that the voltage value of the target signal is greater than the reference voltage value but the target signal does not meet the frequency characteristics of the reference type of communication signal. Regardless of the reason, the target signal is not a reference type of communication signal. Therefore, the second counter 52 outputs a signal detection result indicating that the target signal is not a reference type of communication signal.

[0113] Case 3: The signal characteristics include pattern characteristics and frequency characteristics, and n+1 is greater than or equal to m.

[0114] In this case 3, see Figure 8The trigger circuit 30 includes n+1 triggers 31 connected in sequence, the sampling signal includes the latest sampled n+1 level signals, the logic circuit 40 includes a first logic circuit 41 and a second logic circuit 42, the counting processing signal includes a clearing signal and an enabling counting signal, and the counter 50 includes a third counter 53; the first logic circuit 41 is connected to the n+1 triggers 31, the second logic circuit 42 is connected to the m triggers 31 connected in sequence among the n+1 triggers 31; the third counter 53 is connected to the first logic circuit 41 and the second logic circuit 42. The first trigger 31 among the n+1 triggers 31 is connected to the comparison circuit 10.

[0115] It should be noted that Figure 8 It is only shown that both the first logic circuit 41 and the second logic circuit 42 are connected to the trigger circuit 30. The connection relationship between the first logic circuit 41 and the trigger circuit 30 specifically refers to the connection between the first logic circuit 41 and n+1 triggers 31, and the connection relationship between the second logic circuit 42 and the trigger circuit 30 specifically refers to the connection between the first logic circuit 41 and m triggers 31 connected in sequence among the n+1 triggers 31.

[0116] The m flip-flops 31 connected in sequence among the n+1 flip-flops 31 may refer to the m flip-flops 31 connected in sequence at any positions among the n+1 flip-flops 31. For example, in the case where the first flip-flop 31 among the n+1 flip-flops 31 is connected to the comparison circuit 10, the m flip-flops 31 connected in sequence among the n+1 flip-flops 31 may refer to the first m flip-flops 31 among the n+1 flip-flops 31.

[0117] The n+1 triggers 31 are used to sample the comparison signal according to the clock signal and output n+1 level signals; the first logic circuit 41 is used to perform logic operations on the n+1 level signals according to the code characteristics and output a clear signal; the second logic circuit 42 is used to perform logic operations on the m level signals output by the m triggers 31 connected in sequence among the n+1 triggers 31 according to the frequency characteristics and output an enable count signal; the third counter 53 is used to perform counting processing according to the clear signal and the enable count signal, and output a signal detection result according to the counting processing result. On the basis of considering the voltage value of the target signal, the signal is detected by additionally considering the code characteristics and frequency characteristics, which can improve the matching degree of the signal detection result with the code characteristics and frequency characteristics, and greatly improve the accuracy of signal detection.

[0118] In one possible implementation, when n+1 level signals are all the same level signals, the clear signal is the first level signal; when n+1 level signals are not all the same level signals, the clear signal is the second level signal; when the code pattern formed by the m level signals is a reference code pattern, the enable count signal is the third level signal; when the code pattern formed by the m level signals is not the reference code pattern, the enable count signal is the fourth level signal.

[0119] The working principle of the first logic circuit 41 refers to the relevant introduction of the first logic circuit 42 under situation 1, and the working principle of the second logic circuit 42 refers to the relevant introduction of the second logic circuit 42 under situation 2, which will not be repeated here.

[0120] The third counter 53 is used to clear the count value when the first logic circuit 41 outputs a first level signal, increase the count value when the first logic circuit 41 outputs a second level signal and the second logic circuit 42 outputs a third level signal, and keep the count value unchanged when the first logic circuit 41 outputs a second level signal and the second logic circuit 42 outputs a fourth level signal; if the count value reaches k+r before the detection end condition is met, output a signal detection result indicating that the target signal is a reference type communication signal; if the count value does not reach k+r when the detection end condition is met, output a signal detection result indicating that the target signal is not a reference type communication signal; wherein r is the initial count value of the third counter 53, and r is an integer. The value of r can be set based on experience or flexibly adjusted based on the application scenario, which is not limited in the embodiment of the present application. For example, the value of r can be zero.

[0121] If the count value reaches k+r before the detection end condition is met, it means that before the detection end condition is met, the second logic circuit 42 outputs the third level signal for k times, and the first logic circuit 41 has not output the first level signal during the process of the second logic circuit 42 outputting the third level signal k times. In other words, it means that before the detection end condition is met, k level signals that meet the high-frequency condition appear in the comparison signal, and the maximum number of high-level signals or low-level signals that appear continuously in the comparison signal during the process of k level signals that meet the high-frequency condition appearing is n, and the comparison signal meets the code type characteristics and frequency characteristics of the reference type communication signal.

[0122] Since, when the voltage value of the target signal is greater than the reference voltage value, the arrangement of the high-level signal and the low-level signal in the comparison signal is the same as the arrangement of the high-level signal and the low-level signal in the target signal, the comparison signal conforms to the code type characteristics and frequency characteristics of the reference type of communication signal, which can be considered as the target signal whose voltage value is greater than the reference voltage value conforms to the code type characteristics and frequency characteristics of the reference type of communication signal. Since the two signal characteristics of the code type characteristics and the frequency characteristics are considered in case 3, if the count value reaches k+r before the detection end condition is met, it can be considered that the voltage value of the target signal is greater than the reference voltage value and the target signal conforms to the code type characteristics and frequency characteristics of the reference type of communication signal, and the third counter 53 outputs a signal detection result indicating that the target signal is a reference type of communication signal.

[0123] If the count value does not reach k+r when the detection end condition is met, it means that when the detection end condition is met, the number of times the second logic circuit 42 outputs the third level signal does not reach k times, or it means that in the process of the second logic circuit 42 outputting not less than k times of the third level signal, the first logic circuit 41 has output the first level signal. That is to say, when the detection end condition is met, the number of level signals that meet the high-frequency condition in the comparison signal does not reach k, or the maximum number of high-level signals that appear continuously or low-level signals that appear continuously in the comparison signal is greater than n, and the comparison signal does not conform to the code type characteristics or frequency characteristics of the reference type of communication signal. The reason why the comparison signal does not conform to the code type characteristics or frequency characteristics of the reference type of communication signal may be that the voltage value of the target signal is less than or equal to the reference voltage value, or it may be that the voltage value of the target signal is greater than the reference voltage value but the target signal does not conform to the code type characteristics or frequency characteristics of the reference type of communication signal. Regardless of the reason, the target signal is not a reference type of communication signal. Therefore, the third counter 53 outputs a signal detection result indicating that the target signal is not a reference type of communication signal.

[0124] Case 4: The signal characteristics include pattern characteristics and frequency characteristics, and n+1 is less than m.

[0125] In this case 4, the trigger circuit 30 includes m triggers 31 connected in sequence, the sampling signal includes the latest sampled m level signals, the logic circuit 40 includes a first logic circuit 41 and a second logic circuit 42, the counting processing signal includes a clear signal and an enable counting signal, and the counter 50 includes a third counter 53; the first logic circuit 41 is connected to the m triggers 31, the second logic circuit 42 is connected to n+1 triggers 31 connected in sequence among the m triggers 31; the third counter 53 is connected to the first logic circuit 41 and the second logic circuit 42.

[0126] The m triggers 31 are used to sample the comparison signal according to the clock signal and output m level signals; the first logic circuit 41 is used to perform logic operations on the n+1 level signals output by the n+1 triggers 31 according to the code characteristics and output a clear signal; the second logic circuit 42 is used to perform logic operations on the m level signals according to the frequency characteristics and output an enable counting signal; the third counter 53 is used to perform counting processing according to the clear signal and the enable counting signal, and output a signal detection result according to the counting processing result. The detection principle of the signal detection circuit in this case 4 is the same as the detection principle of the signal detection circuit in the above case 3, and will not be repeated here.

[0127] In a possible implementation, when the signal detection result indicates that the target signal is a reference type communication signal, the target signal is input to the first input terminal of the comparison circuit 10, and the ground voltage value is input to the second input terminal of the comparison circuit 10. The first input terminal and the second input terminal are two input terminals of the comparison circuit 10. In some embodiments, the comparison circuit 10 is a comparator, the first input terminal is the positive input terminal of the comparator, and the second input terminal is the negative input terminal of the comparator.

[0128] The comparison circuit 10 is further configured to output the target signal according to the comparison result between the voltage value of the target signal inputted at the first input terminal and the ground voltage value inputted at the second input terminal when the signal detection result indicates that the target signal is a reference type communication signal. Exemplarily, the ground voltage value is 0V.

[0129] In the case where the signal detection result indicates that the target signal is a reference type communication signal, since the second input terminal inputs a ground voltage value, the target signal input at the first input terminal enters the comparison circuit 10 without any attenuation, and since the comparison circuit 10 also has no additional bias, the comparison circuit 10 can be used as a normal data receiving circuit. That is to say, the signal detection circuit provided in the embodiment of the present application can be reused as a normal data receiving circuit after completing the signal detection, compared with the signal detection circuit in the related art that can only be used to detect signals (such as Figure 1 As shown, the signal detection circuit in the related art adds an RC filter circuit after Vin, and the RC filter circuit filters out the high-frequency information of the signal, so that the signal detection circuit can only be used for signal detection). The signal detection circuit provided in the embodiment of the present application can save circuit area and reduce power consumption.

[0130] Exemplarily, whether the comparison circuit 10 performs the operation of comparing the voltage value of the target signal with the ground voltage value can be controlled by controlling whether the second input terminal inputs the ground voltage value. That is, when the signal detection result indicates that the target signal is a reference type communication signal, the second input terminal is controlled to input the ground voltage value, so that the comparison circuit 10 performs the operation of comparing the voltage value of the target signal with the ground voltage value; when the signal detection result indicates that the target signal is not a reference type communication signal, the second input terminal is controlled to stop inputting the ground voltage value, so that the comparison circuit 10 stops performing the operation of comparing the voltage value of the target signal with the ground voltage value.

[0131] In an exemplary embodiment, see Fig. 9 The signal detection circuit further includes a first control circuit 60 connected to the comparison circuit 10 and the auxiliary detection circuit 20, respectively. The first control circuit 60 is used to control the second input terminal to input a ground voltage value when the signal detection result indicates that the target signal is a reference type communication signal. Exemplarily, the first control circuit 60 is also used to control the second input terminal to stop inputting a ground voltage value when the signal detection result indicates that the target signal is not a reference type communication signal.

[0132] The embodiment of the present application does not limit the structure of the first control circuit 60, as long as it can ensure that the first control circuit 60 has the function of controlling whether the second input terminal inputs the ground voltage value according to the signal detection result. In an exemplary embodiment, the structure of the first control circuit 60 can be a mechanical switch, a diode, a triode, a relay, a transistor, a field effect tube, etc.

[0133] Taking the structure of the first controller 60 as a mechanical switch as an example, the first control circuit 60 can be called a first mechanical switch, one end of the first mechanical switch is grounded, the other end of the first mechanical switch is connected to the second input end, and the first mechanical switch is closed when the signal detection result indicates that the target signal is a reference type of communication signal, and is opened when the signal detection result indicates that the target signal is not a reference type of communication signal.

[0134] Taking the structure of the first controller 60 as a field effect transistor as an example, the first control circuit 60 can be called a first field effect transistor. The first field effect transistor includes a first gate, a first channel, a first electrode, and a second electrode. The first gate is connected to the output end of the auxiliary detection circuit 20, the first electrode is grounded, the second electrode is connected to the second input end, and the first electrode and the second electrode are connected through the first channel. Among them, the first channel is turned on when the signal detection result indicates that the target signal is a reference type of communication signal, and is turned off when the signal detection result indicates that the target signal is not a reference type of communication signal. Exemplarily, for the case where the auxiliary detection circuit 20 includes a trigger circuit 30, a logic circuit 40 and a counter 50, the output end of the auxiliary detection circuit 20 refers to the output end of the counter 50, that is, the first gate is connected to the output end of the counter 50 in the auxiliary detection circuit 20.

[0135] When the first channel is turned on, the first electrode and the second electrode are connected. Since the first electrode is grounded, the ground voltage value can be applied to the second electrode. Since the second electrode is connected to the second input terminal, the ground voltage value can be input to the second input terminal. When the first channel is turned off, the first electrode and the second electrode are not connected, and the ground voltage value cannot be applied to the second electrode, resulting in the inability to input the ground voltage value to the second input terminal. Based on this structure, whether the ground voltage value is input to the second input terminal can be controlled by turning on and off the first channel of the first field effect transistor, thereby improving control reliability.

[0136] The first electrode and the second electrode are two electrodes of the first field effect transistor. Exemplarily, the first electrode is the source of the first field effect transistor, and the second electrode is the drain of the first field effect transistor; or, the first electrode is the drain of the first field effect transistor, and the second electrode is the source of the first field effect transistor.

[0137] The on and off of the first channel is controlled by a level signal applied to the first gate. When the signal detection result indicates that the target signal is a reference type communication signal, the signal detection result applied to the first gate is a level signal that can turn on the first channel; when the signal detection result indicates that the target signal is not a reference type communication signal, the signal detection result applied to the first gate is a level signal that can turn off the first channel.

[0138] In some embodiments, the signal detection result for indicating that the target signal is a reference type communication signal is a high level signal, and the signal detection result for indicating that the target signal is not a reference type communication signal is a low level signal. In this case, the first field effect transistor is an NMOS (N-Metal-Oxide-Semiconductor) field effect transistor.

[0139] In some embodiments, the signal detection result for indicating that the target signal is a reference type communication signal is a low-level signal, and the signal detection result for indicating that the target signal is not a reference type communication signal is a high-level signal. In this case, the first field effect transistor is a PMOS (P-Metal-Oxide-Semiconductor) field effect transistor.

[0140] In one possible implementation, when the signal detection result indicates that the target signal is not a reference type communication signal, the target signal is input to the first input terminal of the comparison circuit 10, and the reference voltage value is input to the second input terminal of the comparison circuit 10. The comparison circuit 10 is used to output a comparison signal according to the comparison result of the voltage value of the target signal input to the first input terminal and the reference voltage value input to the second input terminal when the signal detection result indicates that the target signal is not a reference type communication signal. That is to say, the comparison circuit 10 performs the operation of comparing the voltage value of the target signal with the reference voltage value only when it is detected that the target signal is not a reference type communication signal, and can stop the operation of comparing the voltage value of the target signal with the reference voltage value in time after detecting that the target signal is a reference type communication signal, thereby saving resources.

[0141] Exemplarily, whether the comparison circuit 10 performs the operation of comparing the voltage value of the target signal with the reference voltage value can be controlled by controlling whether the reference voltage value is input to the second input terminal. That is, when the signal detection result indicates that the target signal is not a reference type communication signal, the second input terminal is controlled to input the reference voltage value, so that the comparison circuit 10 performs the operation of comparing the voltage value of the target signal with the reference voltage value; when the signal detection result indicates that the target signal is a reference type communication signal, the second input terminal is controlled to stop inputting the reference voltage value, so that the comparison circuit 10 stops performing the operation of comparing the voltage value of the target signal with the reference voltage value.

[0142] In an exemplary embodiment, see Fig.10 The signal detection circuit also includes a second control circuit 70 connected to the comparison circuit 10 and the auxiliary detection circuit 20 respectively. The second control circuit 70 is used to control the second input terminal to input a reference voltage value when the signal detection result indicates that the target signal is not a reference type communication signal. The embodiment of the present application does not limit the structure of the second control circuit 70, as long as it can ensure that the second control circuit 70 has the function of controlling whether the second input terminal inputs a reference voltage value according to the signal detection result. In an exemplary embodiment, the structure of the second control circuit 70 can be a mechanical switch, a diode, a triode, a relay, a transistor, a field effect tube, etc.

[0143] Taking the structure of the second controller 70 as a mechanical switch as an example, the second control circuit 70 can be called a second mechanical switch, a reference voltage value is applied to one end of the second mechanical switch, the other end of the second mechanical switch is connected to the second input end, and the second mechanical switch is closed when the signal detection result indicates that the target signal is not a reference type of communication signal, and is opened when the signal detection result indicates that the target signal is a reference type of communication signal.

[0144] Taking the structure of the second controller 70 as a field effect transistor as an example, the second control circuit 70 can be called a second field effect transistor. The second field effect transistor includes a second gate, a second channel, a third electrode and a fourth electrode; the second gate is connected to the output end of the auxiliary detection circuit 20, the third electrode is applied with a reference voltage value, the fourth electrode is connected to the second input end, and the third electrode and the fourth electrode are connected through the second channel. The second channel is turned on when the signal detection result indicates that the target signal is not a reference type communication signal, and is turned off when the signal detection result indicates that the target signal is a reference type communication signal.

[0145] Exemplarily, for the case where the auxiliary detection circuit 20 includes a trigger circuit 30, a logic circuit 40 and a counter 50, the output end of the auxiliary detection circuit 20 refers to the output end of the counter 50, that is, the second gate is connected to the output end of the counter 50 in the auxiliary detection circuit 20.

[0146] When the second channel is turned on, the third electrode and the fourth electrode are connected, and the reference voltage value applied by the third electrode can be applied to the fourth electrode. Since the fourth electrode is connected to the second input terminal, the reference voltage value can be input to the second input terminal. When the second channel is turned off, the third electrode and the fourth electrode are not connected, and the reference voltage value applied by the third electrode cannot be applied to the fourth electrode, resulting in the inability to input the reference voltage value to the second input terminal. Based on this structure, whether the reference voltage value is input to the second input terminal can be controlled by turning on and off the second channel of the second field effect tube, thereby improving control reliability.

[0147] The third electrode and the fourth electrode are two electrodes of the second field effect transistor. Exemplarily, the third electrode is the source of the second field effect transistor, and the fourth electrode is the drain of the second field effect transistor; or, the third electrode is the drain of the second field effect transistor, and the fourth electrode is the source of the second field effect transistor.

[0148] The conduction and shutoff of the second channel are controlled by the level signal applied to the second gate. When the signal detection result indicates that the target signal is not a reference type communication signal, the signal detection result applied to the second gate is a level signal that can turn on the second channel; when the signal detection result indicates that the target signal is a reference type communication signal, the signal detection result applied to the second gate is a level signal that can turn off the second channel.

[0149] In some embodiments, the signal detection result for indicating that the target signal is a reference type communication signal is a high level signal, and the signal detection result for indicating that the target signal is not a reference type communication signal is a low level signal. In this case, the second field effect transistor is a PMOS field effect transistor.

[0150] In some embodiments, the signal detection result for indicating that the target signal is a reference type communication signal is a low level signal, and the signal detection result for indicating that the target signal is not a reference type communication signal is a high level signal. In this case, the second field effect transistor is an NMOS field effect transistor.

[0151] Taking n+1 greater than or equal to m as an example, the structure of the signal detection circuit provided in the embodiment of the present application can be as follows: Fig.11 As shown. The signal detection circuit includes a first control circuit 60, a second control circuit 70, a comparison circuit 10 and an auxiliary detection circuit 20. Among them, the auxiliary detection circuit 20 includes a trigger circuit 30, a logic circuit 40 and a counter 50. The trigger circuit 30 includes n+1 triggers 31, the logic circuit 40 includes a first logic circuit 41 and a second logic circuit 42, and the counter 50 includes a third counter 53. The working principles of the above-mentioned components and the connection relationship between the components have been described in detail in the previous text, and will not be repeated here.

[0152] For example, the reference type of communication signal is 8b10b signal, the value of n+1 is 6 (that is, the value of n is 5), and the value of m is 3. Fig.12 The structure shown is an overall description of the working principle of the signal detection circuit provided in the embodiment of the present application. The first input terminal of the comparison circuit 20 (CMP1) is used to input the target signal Vin, and the second input terminal is connected to the first control circuit 60 and the second control circuit 70. The first control circuit is a first field effect tube (M2), and the second control circuit 70 is a second field effect tube (M1). The first gate of the first field effect tube is connected to the output signal signal_ok of the third counter 53, the first electrode of the first field effect tube is grounded, and the second electrode of the first field effect tube is connected to the second input terminal of the comparison circuit 20. The second gate of the second field effect tube is connected to the output signal signal_ok of the third counter 53, the third electrode of the second field effect tube is applied with a reference voltage value Vref (10mV), and the fourth electrode of the second field effect tube is connected to the second input terminal of the comparison circuit 20.

[0153] When signal_ok is 1, it indicates that the 8b10b signal is detected, and when it is 0, it indicates that the 8b10b signal is not detected. The first field effect tube is an NMOS field effect tube, and the second field effect tube is a PMOS field effect tube. In the initial state, signal_ok is 0, at which time the first field effect tube is turned off, the second field effect tube is turned on, and the reference voltage value Vref is input to the second input terminal of the comparison circuit 20. After signal_ok is pulled high (that is, signal_ok is 1), the first field effect tube is turned on, the second field effect tube is turned off, and the second input terminal of the comparison circuit 20 inputs the ground voltage value (0V). At this time, the target signal Vin enters the comparison circuit 20 without any attenuation, and the comparison circuit 20 also has no additional bias, and can be used as a normal data receiving path. That is, the signal detection circuit provided in the embodiment of the present application can be reused as a normal data receiving path after completing the detection, which saves circuit area and power consumption compared to the related art.

[0154] The output end of the comparison circuit 20 is connected to the 6-stage cascaded trigger 31 (DFF1-DFF6) in sequence, and the clock input end Clk of the trigger 31 is connected to the system clock signal ck1, and the frequency of ck1 is the data transmission rate of the received target signal. Q1-Q6 are the output end signals of DFF1-DFF6 respectively, and Q1-Q6 are 6 level signals sampled continuously.

[0155] The first logic circuit 41 (Z2) is composed of 6 inverters, 6 AND gates and 1 OR gate, and its function is to detect whether Q1-Q6 are all 1 or all 0. When Q1-Q6 are all 1 or all 0, the clr1 signal output by the first logic circuit 41 is 1. The second logic circuit 42 (Z1) is composed of 3 inverters, 2 AND gates and 1 OR gate, and its function is to detect whether Q1-Q3 has a code pattern of "010" or "101", that is, whether there is a 1 or 0 with a continuous period of one clock cycle. When such a code pattern is found, the en1 signal output by the second logic circuit 42 is pulled high, that is, the en1 signal output by the second logic circuit 42 is 1.

[0156] The third counter 53 has three input terminals, namely, Cnt, En and Clr. The Cnt input terminal is connected to the clock signal ck1, the En input terminal is connected to the en1 signal output by the second logic circuit 42, and the Clr input terminal is connected to the clr1 signal output by the first logic circuit 41. If En=1 (i.e., en1 is 1), the rising edge of ck1 is counted, and the counting result of the counter increases. If En=0 (i.e., en1 is 0), the counting result remains unchanged. During the counting process, if Clr=1 (i.e., clr1 is 1), the counting result is immediately cleared. When the counting result of the counter increases to a certain amount (e.g., 2048), the output signal signal_ok of the third counter 53 is pulled high, i.e., the output signal signal_ok of the third counter 53 is 1, indicating that a normal 8b10b signal is detected.

[0157] In summary, the conditions for signal_ok to be pulled high can be summarized as receiving 2048 1s or 0s in one clock cycle, and no consecutive 6 1s or 6 0s appear in this process, and the voltage value of the signal is greater than 10mV. The fact that 2048 1s or 0s in one clock cycle can be received indicates that the received signal has a strong high-frequency component (that is, it meets the frequency characteristics of the 8b10b signal), and the voltage value of the high-frequency signal is greater than 10mV. Even if the noise has a high-frequency component, the voltage value of the high-frequency component of the noise is usually very small, much less than 10mV of Vref. On the other hand, during this period, no consecutive 6 1s or 6 0s were received, indicating the code characteristics of the signal symbol 8b10b (the longest 1 or 0 of the 8b10b signal does not exceed 5). That is, the embodiment of the present application can identify whether the received signal is an 8b10b signal from the characteristics of the three dimensions of frequency, voltage value and code type, which has better accuracy than the related art that only identifies by signal voltage value. Even if the voltage value of the noise is very large, exceeding Vref, the signal detection circuit provided in the embodiment of the present application can avoid misdetection of the noise as an 8b10b signal due to the excessively large voltage value of the noise from both frequency and code type aspects.

[0158] The technical solution provided by the embodiment of the present application is that the signal detection circuit includes a comparison circuit and an auxiliary detection circuit. The comparison circuit is used to detect the target signal from the perspective of the voltage value, and the auxiliary detection circuit is used to perform auxiliary detection on the target signal from the perspective of the signal characteristics of the reference type of communication signal. Based on this, even if the voltage value of the target signal exceeds the reference voltage value, the target signal can be further detected according to the signal characteristics of the reference type of communication signal, thereby reducing the false detection phenomenon caused by directly using the target signal with a larger voltage value as the reference type of communication signal, and improving the accuracy of signal detection.

[0159] The present application embodiment provides a signal detection method, see Fig.13 , the signal detection method includes the following steps 1301 and 1302.

[0160] Step 1301: Output a comparison signal according to a comparison result between a voltage value of a target signal and a reference voltage value.

[0161] In an exemplary embodiment, the signal detection method provided in the embodiment of the present application can be implemented by a signal detection circuit, and the signal detection circuit includes a comparison circuit and an auxiliary detection circuit. This step 1301 can be implemented by a comparison circuit, that is, the comparison circuit outputs a comparison signal according to the comparison result between the voltage value of the target signal and the reference voltage value.

[0162] In one possible implementation, the signal detection method further includes: when the signal detection result indicates that the target signal is a reference type communication signal, outputting the target signal according to a comparison result between a voltage value of the target signal and a ground voltage value.

[0163] In an exemplary embodiment, the comparison circuit has a first input terminal and a second input terminal. The process of outputting the target signal according to the comparison result of the voltage value of the target signal and the ground voltage value includes: outputting the target signal according to the comparison result of the voltage value of the target signal input at the first input terminal and the ground voltage value input at the second input terminal through the comparison circuit.

[0164] In an exemplary embodiment, the signal detection circuit further includes a first control circuit, and the signal detection method further includes: controlling the second input terminal of the comparison circuit to input a ground voltage value when the signal detection result indicates that the target signal is a reference type communication signal through the first control circuit.

[0165] In one possible implementation, the process of outputting a comparison signal based on a comparison result between a voltage value of a target signal and a reference voltage value includes: when a signal detection result indicates that the target signal is not a reference type communication signal, outputting a comparison signal based on a comparison result between the voltage value of the target signal and the reference voltage value.

[0166] In an exemplary embodiment, the comparison circuit has a first input terminal and a second input terminal, and the process of outputting a comparison signal based on the comparison result of the voltage value of the target signal and the reference voltage value includes: outputting a comparison signal through the comparison circuit based on the comparison result of the voltage value of the target signal input at the first input terminal and the reference voltage value input at the second input terminal.

[0167] In an exemplary embodiment, the signal detection circuit further includes a second control circuit, and the signal detection method further includes: controlling the second input terminal of the comparison circuit to input a reference voltage value when the signal detection result indicates that the target signal is not a reference type communication signal through the second control circuit.

[0168] Step 1302: Based on the comparison signal and the signal characteristic, a signal detection result is output, where the signal characteristic is a characteristic of a reference type of communication signal, and the signal detection result is used to indicate whether the target signal is a reference type of communication signal.

[0169] In an exemplary embodiment, for the case where the signal detection method provided in the embodiment of the present application is implemented by a signal detection circuit, step 1302 can be implemented by an auxiliary detection circuit, that is, the signal detection result is output by the auxiliary detection circuit based on the comparison signal and signal characteristics.

[0170] In one possible implementation, a signal detection result is output based on a comparison signal and a signal characteristic, including: sampling the comparison signal according to a clock signal and outputting a sampling signal; performing a logical operation on the sampling signal according to the signal characteristic and outputting a counting processing control signal; performing counting processing according to the counting processing control signal and outputting a signal detection result according to the counting processing result.

[0171] In an exemplary embodiment, the auxiliary detection circuit includes a trigger circuit, a logic circuit and a counter. The output process of the signal detection result includes: sampling the comparison signal according to the clock signal through the trigger circuit and outputting the sampling signal; performing a logic operation on the sampling signal according to the signal characteristics through the logic circuit and outputting a counting processing control signal; performing counting processing through the counter according to the counting processing control signal and outputting the signal detection result according to the counting processing result.

[0172] In one possible implementation, the signal characteristics include at least one of a code type characteristic or a frequency characteristic; the code type characteristic includes: in a reference type of communication signal, the maximum number of continuously occurring high-level signals or continuously occurring low-level signals is a specific value n, where n is an integer greater than 1; the frequency characteristics include: in the reference type of communication signal, there are no less than k level signals that meet the high-frequency condition, where k is an integer greater than 1, wherein a level signal that meets the high-frequency condition is determined based on m level signals that constitute the reference code type, where m is an integer greater than 2.

[0173] In a possible implementation, the signal characteristic includes a code characteristic; the sampling signal includes the latest sampled n+1 level signals, and the counting process control signal includes a clearing signal. The output process of the signal detection result includes: sampling the comparison signal according to the clock signal, and outputting n+1 level signals; performing a logical operation on the n+1 level signals according to the code characteristic, and outputting a clearing signal; performing counting processing according to the clearing signal, and outputting the signal detection result according to the counting processing result.

[0174] Exemplarily, the trigger circuit includes n+1 triggers connected in sequence, the logic circuit includes a first logic circuit, and the counter includes a first counter. The output process of the signal detection result includes: sampling the comparison signal according to the clock signal through the n+1 triggers, and outputting n+1 level signals; performing a logic operation on the n+1 level signals according to the code type characteristics through the first logic circuit, and outputting a clear signal; performing counting processing according to the clear signal through the first counter, and outputting the signal detection result according to the counting processing result.

[0175] In a possible implementation, when n+1 level signals are all the same level signals, the clear signal is a first level signal; when n+1 level signals are not all the same level signals, the clear signal is a second level signal. The process of performing counting processing according to the clear signal and outputting a signal detection result according to the counting processing result includes: clearing the count value when the clear signal is the first level signal, and keeping the count value unchanged when the clear signal is the second level signal; if the count value is not zero when the detection end condition is met, outputting a signal detection result for indicating that the target signal is a reference type communication signal; if the count value is zero when the detection end condition is met, outputting a signal detection result for indicating that the target signal is not a reference type communication signal; wherein the initial count value is not zero.

[0176] Exemplarily, the initial count value refers to the initial count value of the first counter, that is, the count value is cleared to zero by the first counter when the first logic circuit outputs a first-level signal, and the count value is kept unchanged when the first logic circuit outputs a second-level signal; if the count value is not zero when the detection end condition is met, a signal detection result indicating that the target signal is a reference type of communication signal is output; if the count value is zero when the detection end condition is met, a signal detection result indicating that the target signal is not a reference type of communication signal is output.

[0177] In an exemplary embodiment, the first logic circuit includes a first logic subcircuit, a second logic subcircuit and a first OR gate. The process of performing a logic operation on n+1 level signals according to the code type characteristics by the first logic circuit and outputting a clear signal includes: outputting a first level signal by the first logic subcircuit when n+1 level signals are all high level signals, and outputting a second level signal when n+1 level signals are not all high level signals; outputting a first level signal by the second logic subcircuit when n+1 level signals are all low level signals, and outputting a second level signal when n+1 level signals are not all low level signals; performing an OR operation on the output result of the first logic subcircuit and the output result of the second logic subcircuit by the first OR gate, and outputting a clear signal.

[0178] In a possible implementation, the signal characteristic includes a frequency characteristic; the sampling signal includes the latest sampled m level signals, and the counting process control signal includes an enable counting signal. The output process of the signal detection result includes: sampling the comparison signal according to the clock signal and outputting the m level signals; performing a logical operation on the m level signals according to the frequency characteristic and outputting the enable counting signal; performing counting processing according to the enable counting signal, and outputting the signal detection result according to the counting processing result.

[0179] Exemplarily, the trigger circuit includes m triggers connected in sequence, the logic circuit includes a second logic circuit, and the counter includes a second counter. The output process of the signal detection result includes: sampling the comparison signal according to the clock signal through the m triggers, and outputting m level signals; performing a logic operation on the m level signals according to the frequency characteristics through the second logic circuit, and outputting an enable count signal; performing a count process according to the enable count signal through the second counter, and outputting the signal detection result according to the count process result.

[0180] In a possible implementation, when the code pattern composed of m level signals is a reference code pattern, the enable count signal is a third level signal; when the code pattern composed of m level signals is not a reference code pattern, the enable count signal is a fourth level signal. The process of performing counting processing according to the enable count signal and outputting a signal detection result according to the counting processing result includes: increasing the count value when the enable count signal is a third level signal, and keeping the count value unchanged when the enable count signal is a fourth level signal; if the count value reaches k+s before the detection end condition is met, outputting a signal detection result indicating that the target signal is a reference type communication signal; if the count value does not reach k+s when the detection end condition is met, outputting a signal detection result indicating that the target signal is not a reference type communication signal; wherein s is an initial count value and s is an integer.

[0181] Exemplarily, s is the initial count value of the second counter, that is, the count value is increased by the second counter when the second logic circuit outputs a third level signal, and the count value is kept unchanged when the second logic circuit outputs a fourth level signal; if the count value reaches k+s before the detection end condition is met, a signal detection result indicating that the target signal is a reference type communication signal is output; if the count value does not reach k+s when the detection end condition is met, a signal detection result indicating that the target signal is not a reference type communication signal is output.

[0182] Exemplarily, the value of m is 3, the reference code pattern includes a first code pattern consisting of a high level signal, a low level signal and a high level signal arranged in sequence, and a second code pattern consisting of a low level signal, a high level signal and a low level signal arranged in sequence; the second logic circuit includes a third logic subcircuit, a fourth logic subcircuit and a second OR gate. The process of performing a logic operation on m level signals according to the frequency characteristics by the second logic circuit and outputting an enable counting signal includes: outputting a third level signal by the third logic subcircuit when the third code pattern consisting of three level signals output by three triggers connected in sequence is the first code pattern, and outputting a fourth level signal when the third code pattern is not the first code pattern; outputting a third level signal by the fourth logic subcircuit when the third code pattern is the second code pattern, and outputting a fourth level signal when the third code pattern is not the second code pattern; performing an OR operation on the output result of the third logic subcircuit and the output result of the fourth logic subcircuit by the second OR gate, and outputting an enable counting signal.

[0183] In a possible implementation, the signal characteristics include code characteristics and frequency characteristics, n+1 is greater than or equal to m; the sampling signal includes the latest sampled n+1 level signals, and the counting processing signal includes a clearing signal and an enabling counting signal. The output process of the signal detection result includes: sampling the comparison signal according to the clock signal, and outputting n+1 level signals; performing logical operations on the n+1 level signals according to the code characteristics, and outputting a clearing signal; performing logical operations on the continuous m level signals among the n+1 level signals according to the frequency characteristics, and outputting an enabling counting signal; performing counting processing according to the clearing signal and the enabling counting signal, and outputting the signal detection result according to the counting processing result.

[0184] In an exemplary embodiment, the trigger circuit includes n+1 triggers connected in sequence, the logic circuit includes a first logic circuit and a second logic circuit, and the counter includes a third counter. The output process of the signal detection result includes: sampling the comparison signal according to the clock signal through the n+1 triggers, and outputting n+1 level signals; performing a logic operation on the n+1 level signals according to the code type characteristics through the first logic circuit, and outputting a clear signal; performing a logic operation on the m level signals output by the m triggers connected in sequence among the n+1 triggers according to the frequency characteristics through the second logic circuit, and outputting an enable count signal; performing a counting process according to the clear signal and the enable count signal through the third counter, and outputting the signal detection result according to the counting process result.

[0185] In one possible implementation, when n+1 level signals are all the same level signals, the clear signal is the first level signal; when n+1 level signals are not all the same level signals, the clear signal is the second level signal; when the code pattern formed by the m level signals is a reference code pattern, the enable count signal is the third level signal; when the code pattern formed by the m level signals is not the reference code pattern, the enable count signal is the fourth level signal.

[0186] The process of performing counting processing according to a clear signal and an enable count signal and outputting a signal detection result according to the count processing result includes: clearing the count value when the clear signal is a first level signal, increasing the count value when the clear signal is a second level signal and the enable count signal is a third level signal, and keeping the count value unchanged when the clear signal is a second level signal and the enable count signal is a fourth level signal; if the count value reaches k+r before the detection end condition is met, outputting a signal detection result indicating that the target signal is a reference type communication signal; if the count value does not reach k+r when the detection end condition is met, outputting a signal detection result indicating that the target signal is not a reference type communication signal; wherein r is an initial count value and r is an integer.

[0187] Exemplarily, r is the initial count value of the third counter, that is, the third counter clears the count value when the first logic circuit outputs a first-level signal, increases the count value when the first logic circuit outputs a second-level signal and the second logic circuit outputs a third-level signal, and keeps the count value unchanged when the first logic circuit outputs a second-level signal and the second logic circuit outputs a fourth-level signal; if the count value reaches k+r before the detection end condition is met, a signal detection result indicating that the target signal is a reference type communication signal is output; if the count value does not reach k+r when the detection end condition is met, a signal detection result indicating that the target signal is not a reference type communication signal is output.

[0188] The description of the above signal detection method embodiment has similar beneficial effects as the above signal detection circuit embodiment. For technical details not disclosed in the signal detection method embodiment, please refer to the description of the signal detection circuit embodiment of this application for understanding.

[0189] See also Fig.14 In one embodiment, a chip is further provided, the chip comprising the signal detection circuit in any possible implementation manner described above. Optionally, the chip may be a signal receiving chip.

[0190] See also Fig.15In one embodiment, an electronic device is also provided, which includes the signal detection circuit in any possible implementation manner described above.

[0191] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the signals involved in this application are all obtained with full authorization.

[0192] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0193] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0194] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A signal detection circuit, characterized in that: include: A comparison circuit, used for outputting a comparison signal according to a comparison result between a voltage value of a target signal and a reference voltage value; The auxiliary detection circuit is used to output a signal detection result based on the comparison signal and the signal characteristic, wherein the signal characteristic is a characteristic of a communication signal of a reference type, and the signal detection result is used to indicate whether the target signal is a communication signal of the reference type.

2. The signal detection circuit according to claim 1, characterized in that: The signal characteristic includes at least one of a pattern characteristic or a frequency characteristic.

3. The signal detection circuit according to claim 1, characterized in that: The auxiliary detection circuit comprises: A trigger circuit, used for sampling the comparison signal according to a clock signal and outputting a sampling signal; A logic circuit, used for performing a logic operation on the sampling signal according to the signal characteristics and outputting a counting processing control signal; The counter is used to perform counting processing according to the counting processing control signal and output the signal detection result according to the counting processing result.

4. The signal detection circuit according to claim 3, characterized in that: The signal characteristic includes a code type characteristic; the code type characteristic includes: in the communication signal of the reference type, the maximum number of consecutive high-level signals or consecutive low-level signals is a specific value n, where n is an integer greater than 1; the trigger circuit includes n+1 triggers connected in sequence, the sampling signal includes the latest sampled n+1 level signals, the logic circuit includes a first logic circuit, the counting processing control signal includes a reset signal, and the counter includes a first counter; The n+1 triggers are used to sample the comparison signal according to the clock signal and output the n+1 level signals; The first logic circuit is used to perform a logic operation on the n+1 level signals according to the code type characteristics and output the clear signal; The first counter is used to perform counting processing according to the clear signal, and output the signal detection result according to the counting processing result.

5. The signal detection circuit according to claim 3, characterized in that: The signal characteristic includes a frequency characteristic; the frequency characteristic includes: there are no less than k level signals satisfying the high frequency condition in the communication signal of the reference type, k is an integer greater than 1, wherein one level signal satisfying the high frequency condition is determined based on m level signals constituting the reference code pattern, m is an integer greater than 2; the trigger circuit includes m triggers connected in sequence, the sampling signal includes the latest sampled m level signals, the logic circuit includes a second logic circuit, the counting processing control signal includes an enable counting signal, and the counter includes a second counter; The m triggers are used to sample the comparison signal according to the clock signal and output the m level signals; The second logic circuit is used to perform a logic operation on the m level signals according to the frequency characteristics and output the enable counting signal; The second counter is used to perform counting processing according to the enable counting signal, and output the signal detection result according to the counting processing result.

6. The signal detection circuit according to claim 3, characterized in that: The signal characteristics include pattern characteristics and frequency characteristics; the pattern characteristics include: in the communication signal of the reference type, the maximum number of continuously appearing high-level signals or continuously appearing low-level signals is a specific value n, where n is an integer greater than 1; the frequency characteristics include: there are no less than k level signals that meet the high-frequency condition in the communication signal of the reference type, where k is an integer greater than 1, wherein one level signal that meets the high-frequency condition is determined based on m level signals constituting the reference pattern, where m is an integer greater than 2; n+1 is greater than or equal to m; The trigger circuit includes n+1 triggers connected in sequence, the sampling signal includes the latest sampled n+1 level signals, the logic circuit includes a first logic circuit and a second logic circuit, the counting processing signal includes a clear signal and an enable counting signal, and the counter includes a third counter; The n+1 triggers are used to sample the comparison signal according to the clock signal and output the n+1 level signals; The first logic circuit is used to perform a logic operation on the n+1 level signals according to the code type characteristics and output the clear signal; The second logic circuit is used to perform a logic operation on the m level signals output by the m flip-flops connected in sequence among the n+1 flip-flops according to the frequency characteristics, and output the enable counting signal; The third counter is used to perform counting processing according to the clear signal and the enable counting signal, and output the signal detection result according to the counting processing result.

7. The signal detection circuit according to any one of claims 1 to 6, characterized in that: The comparison circuit is also used to output the target signal based on a comparison result between a voltage value of the target signal input at the first input terminal and a ground voltage value input at the second input terminal when the signal detection result indicates that the target signal is a communication signal of the reference type.

8. The signal detection circuit according to claim 7, characterized in that: The signal detection circuit further includes a first control circuit, and the first control circuit is used for controlling the second input terminal to input the ground voltage value when the signal detection result indicates that the target signal is a communication signal of the reference type.

9. A signal detection method, characterized in that: include: Outputting a comparison signal according to a comparison result between the voltage value of the target signal and the reference voltage value; Based on the comparison signal and the signal characteristic, a signal detection result is output, wherein the signal characteristic is a characteristic of a communication signal of a reference type, and the signal detection result is used to indicate whether the target signal is a communication signal of the reference type.

10. The signal detection method according to claim 9, characterized in that: The signal characteristic includes at least one of a pattern characteristic or a frequency characteristic.

11. A chip, characterized in that: The chip includes the signal detection circuit as described in any one of claims 1-8.

12. An electronic device, characterized in that: The electronic device comprises the signal detection circuit as described in any one of claims 1-8.

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