Circuit system, SPI communication switching method and electronic equipment

Abstract

The invention provides a circuit system, an SPI communication switching method and electronic equipment, and relates to the technical field of communication. The system comprises an SPI host, an SPI slave and a switching circuit, wherein a first data pin of the SPI host is in communication connection with a second data pin of the SPI slave through the switching circuit; the SPI host further comprises a control pin for controlling the switching circuit. And the SPI host is used for sending a handshake command to the SPI slave and judging whether the switching circuit needs to be controlled to switch the connection mode between the first data pin and the second data pin through the control pin according to a response result of the handshake command. Therefore, the connection mode between the data pins is switched through the switching circuit, so that the condition that a conventional SPI specification is not followed is adapted, and the circuit does not need to be modified manually.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a circuit system, an SPI communication switching method and an electronic device. Background Art

[0002] SPI (Serial Peripheral Interface) is a common PCB board-level communication bus, usually used for data transmission between controllers and external devices. For example, external devices such as sensors, flash memory, real-time clocks, AD converters, etc. SPI uses master-slave mode for communication, which generally consists of four signal lines: CS (chip select), CLK (clock), MOSI (master output slave input), and MISO (master input slave output). The SPI interface needs to determine the host and slave at the beginning of hardware design in order to connect the four signal lines of the host and slave, especially the data input and output signals of SPI. It is necessary to connect the data output of the host with the data input of the slave, and the data input of the host with the data output of the slave.

[0003] During the hardware design phase, it is necessary to correctly connect these signal lines, especially to ensure the consistency of data input and output signals. Specifically, the CS (chip select) line of the SPI master is connected to the chip select input of the SPI slave to select a specific SPI slave for communication; the CLK (clock) line of the SPI master is connected to the clock input of all SPI slaves to provide a synchronous clock signal for data transmission; the MOSI (master output slave input) line of the SPI master is connected to the MOSI input of all SPI slaves to send data from the SPI master to the SPI slave; and the MISO (master input slave output) line of the SPI slave is connected to the MISO input of the SPI master to send data from the SPI slave to the SPI master. In this way, through these four signal lines, bidirectional data transmission can be achieved between the master SPI slave.

[0004] However, in practice, it is found that not all chips follow the above specifications, which may involve differences in signal line naming, logic levels, timing requirements, etc. At this time, when an error in the connection is found, it can only be solved by modifying the hardware circuit, which not only increases manpower and material resources, but may also cause circuit damage due to repeated circuit modifications. Summary of the invention

[0005] In order to overcome at least one deficiency in the prior art, the present application provides a circuit system, an SPI communication switching method and an electronic device, specifically including:

[0006] In a first aspect, the present application provides a circuit system, the circuit system comprising an SPI host, an SPI slave, and a switching circuit, wherein a first data pin of the SPI host and a second data pin of the SPI slave establish a communication connection through the switching circuit;

[0007] The SPI host also includes a control pin for controlling the switching circuit;

[0008] The SPI host is used to send a handshake command to the SPI slave, and judge whether it is necessary to control the switching circuit to switch the connection mode between the first data pin and the second data pin through the control pin according to the response result of the handshake command.

[0009] In combination with the optional implementation manner of the first aspect, the connection mode includes a direct connection mode and a cross connection mode.

[0010] In combination with an optional implementation manner of the first aspect, the switching circuit includes a double-pole double-throw switch and a driving element of the double-pole double-throw switch;

[0011] The control end of the SPI host is connected to the driving element;

[0012] The SPI host outputs different control signals to the driving element through the control pin, so that the double-pole double-throw switch switches the connection mode between the first data pin and the second data pin.

[0013] In combination with the optional implementation manner of the first aspect, the driving element is a logic NOT gate.

[0014] In a second aspect, the present application provides an SPI communication switching method, which is applied to an SPI host in a circuit system, wherein the circuit system further includes an SPI slave and a switching circuit, wherein a first data pin of the SPI host and a second data pin of the SPI slave establish a communication connection through the switching circuit, and the SPI host further includes a control pin for controlling the switching circuit, wherein the method includes:

[0015] Sending a handshake command to the SPI slave;

[0016] According to the response result of the handshake command, it is determined whether it is necessary to control the switching circuit through the control pin to switch the connection mode between the first data pin and the second data pin.

[0017] In combination with an optional implementation manner of the second aspect, judging whether it is necessary to control the switching circuit to switch the connection mode between the first data pin and the second data pin through the control pin according to the response result of the handshake command includes:

[0018] If the response data of the SPI slave to the handshake command is not received through the first data pin, controlling the switching circuit to switch the connection mode between the first data pin and the second data pin;

[0019] Return to sending a handshake command to the SPI slave until the number of switching times of the connection mode between the first data pin and the second data pin is greater than a first alarm threshold or response data of the SPI slave to the handshake command is received through the first data pin.

[0020] In combination with the optional implementation manner of the second aspect, the method further includes:

[0021] If the switching times are greater than the first alarm threshold, an alarm message indicating an abnormality of the SPI bus is output.

[0022] In combination with the optional implementation manner of the second aspect, the connection mode includes a direct connection mode and a cross connection mode.

[0023] The third aspect. The present application also provides an SPI communication switching method, which is applied to an SPI slave in a circuit system, wherein the circuit system further includes an SPI host and a switching circuit, wherein a first data pin of the SPI host and a second data pin of the SPI slave establish a communication connection through the switching circuit, the SPI host further includes a control pin for controlling the switching circuit, and the SPI slave includes a detection pin connected to the control pin, and the method includes:

[0024] Receive a handshake command sent by the SPI host;

[0025] In response to the handshake command, sending response data to the SPI host;

[0026] If the response data is sent successfully, enter the communication mode for communicating with the SPI host;

[0027] If the response data is not sent successfully, the number of level changes of the detection pin is accumulated, and when the number of level changes is greater than a second alarm threshold, an alarm message indicating an abnormality of the SPI bus is output.

[0028] In a fourth aspect, the present application also provides an electronic device, which includes the circuit system.

[0029] Compared with the prior art, this application has the following beneficial effects:

[0030] The present application provides a circuit system, an SPI communication switching method and an electronic device. The system includes an SPI host, an SPI slave and a switching circuit, wherein a first data pin of the SPI host and a second data pin of the SPI slave establish a communication connection through the switching circuit; the SPI host also includes a control pin for controlling the switching circuit. The SPI host is used to send a handshake command to the SPI slave, and according to the response result of the handshake command, it is determined whether it is necessary to control the switching circuit to switch the connection mode between the first data pin and the second data pin through the control pin. In this way, the connection mode between the data pins is switched by the switching circuit, thereby adapting to the situation where the conventional SPI specification is not followed without manually modifying the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of the structure of a circuit system provided in an embodiment of the present application;

[0033] Figure 2 One of the schematic diagrams of the connection method provided in the embodiment of the present application;

[0034] Figure 3 A second schematic diagram of the connection method provided in the embodiment of the present application;

[0035] Figure 4 A schematic diagram of the structure of a switching circuit provided in an embodiment of the present application;

[0036] Figure 5 A flow chart of the SPI communication switching method implemented by the SPI host provided in an embodiment of the present application;

[0037] Figure 6 A flowchart of the SPI communication switching method implemented by the SPI slave provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0041] In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. In addition, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0042] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0043] Based on the above statement, as introduced in the background technology, it is found in practice that not all chips follow the conventional SPI specification, that is, the MOSI (master output slave input) line of the SPI host is connected to the MOSI input terminal of all SPI slaves, which is used for the SPI host to send data to the SPI slave; and the MISO (master input slave output) line of the SPI slave is connected to the MISO input terminal of the SPI host. This may involve differences in the naming of signal lines, logic levels, timing requirements, etc. When an error in the connection is found, it can only be solved by modifying the hardware circuit, which not only increases manpower and material resources, but also may cause circuit damage due to repeated circuit modifications.

[0044] For example, some chips do not name the data pins of the SPI bus as MISO or MOSI, but as SDI (Serial Data Input), SDO (Serial Data Output) or SO (Serial Out), SI (Serial In). The corresponding relationship between the naming of these pins and MISO and MOSI varies from chip to chip, which may lead to connection errors when the chip is not familiar.

[0045] In addition, in some scenarios where the SPI master-slave relationship needs to be switched flexibly, for example, during the software debugging phase, the SPI master-slave relationship between the SOC and the MCU may be adjusted according to the application situation. If the physical pins of the data input signal and the data output signal are swapped after the SPI interface of one party switches between the master and slave modes, it will also cause errors in the data input and data output connection of the master-slave SPI interface, resulting in SPI communication abnormalities.

[0046] Based on the discovery of the above technical problems, the inventors have proposed the following technical solutions to solve or improve the above problems through creative work. It should be noted that the defects in the solutions in the above prior art are the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of the present application for the above problems below should all be the contributions made by the inventors to the present application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0047] In view of this, this embodiment provides a circuit system. Figure 1 As shown, the system includes an SPI host, an SPI slave, and a switching circuit, wherein the first data pin (MOSI, MISO) of the SPI host and the second data pin (MOSI, MISO) of the SPI slave establish a communication connection through the switching circuit; the SPI host also includes a control pin (Out) for controlling the switching circuit, wherein the control pin can be a certain I / O pin of the SPI host. The SPI host is used to send a handshake command to the SPI slave, and according to the response result of the handshake command, it is determined whether it is necessary to control the switching circuit to switch the connection mode between the first data pin and the second data pin through the control pin. In this way, the connection mode between the data pins is switched by the switching circuit, thereby adapting to the situation that does not follow the conventional SPI specification without manually modifying the circuit.

[0048] Continue to see Figure 1The SPI slave also includes a detection pin IN connected to the control pin. The SPI slave can detect the level change when the SPI host applies a control instruction to the control pin through the detection pin, and send out an SPI bus abnormality alarm when the preset conditions are met. Similarly, the control pin can be an I / O pin of the SPI slave.

[0049] In this embodiment, the connection method between the first data pin of the SPI host and the second data pin of the SPI slave includes a direct connection method and a cross connection method. Figure 1 The circuit system shown in Figure 2 As shown, in the direct connection mode, the MISO pin of the SPI master is connected to the MISO pin of the SPI slave, and the MOSI pin of the SPI master is connected to the MOSI pin of the SPI slave. Figure 1 The circuit system shown in Figure 3 As shown, in the cross connection mode, the MISO pin of the SPI host is connected to the MOSI pin of the SPI slave, and the MOSI pin of the SPI host is connected to the MISO pin of the SPI slave. It should be noted that, as described in the above embodiment, not all chips follow the conventional SPI specification. Figure 1 , Figure 2 , Figure 3 The data pins marked in are conventional naming methods, but they do not represent the actual pin functions. Therefore, it is necessary to control the switching circuit to adjust the connection method between the pins according to the actual communication situation.

[0050] based on Figure 1 The circuit system shown in Figure 4 As shown, the switching circuit includes a double-pole double-throw switch 11 and a driving element 12 of the double-pole double-throw switch 11, and the control end of the SPI host is connected to the driving element 12. The SPI host outputs different control signals to the driving element 12 through the control pin, so that the double-pole double-throw switch 11 switches the connection mode between the first data pin and the second data pin. Among them, the double-pole double-throw switch 11 can be in a mechanical form, that is, the double-pole double-throw function is realized by a mechanical structure. For example, the double-pole double-throw function is realized based on a relay. In addition, the double-pole double-throw switch 11 can also be in a non-mechanical form, that is, electronic components (such as transistors or relays) are used to realize the switching of the circuit, without physical contact, and relying on electrical signals to control the on and off of the circuit.

[0051] When the double-pole double-throw switch 11 is in a non-mechanical form, the driving element 12 is a logic NOT gate. It should be understood that the logic NOT gate can invert the signal output by the control pin, so that the non-mechanical switch (such as a transistor) can accurately and stably switch the circuit state, thereby realizing reliable switching of the connection mode between the first data pin and the second data pin.

[0052] Based on the introduction of the circuit system in the above embodiment, this embodiment also provides an SPI communication switching method. The method is applied to the SPI host in the above circuit system, the circuit system also includes an SPI slave and a switching circuit, the circuit system also includes an SPI slave, the first data pin of the SPI host and the second data pin of the SPI slave establish a communication connection through the switching circuit, and the SPI host also includes a control pin for controlling the switching circuit.

[0053] To make the solution provided by this embodiment clearer, Figure 5 Each step of the method is described in detail. However, it should be understood that the operations of the flowchart may not be implemented in order, and steps without logical contextual relationships may be reversed in order or implemented simultaneously. In addition, those skilled in the art may add one or more other operations to the flowchart, or remove one or more operations from the flowchart under the guidance of the content of this application. Figure 5 As shown, the method includes:

[0054] S1A, send handshake command to SPI slave.

[0055] S2A, judging whether it is necessary to switch the connection mode between the first data pin and the second data pin by controlling the switching circuit through the control pin according to the response result of the handshake command.

[0056] In this embodiment, if the response data of the SPI slave to the handshake command is not received through the first data pin, the switching circuit is controlled to switch the connection mode between the first data pin and the second data pin; then, the process returns to execute step S1A until the number of switching times of the connection mode between the first data pin and the second data pin is greater than the first alarm threshold or the response data of the SPI slave to the handshake command is received through the first data pin.

[0057] It can be understood that when the number of switching times of the connection mode between the first data pin and the second data pin is greater than the first alarm threshold, and a normal communication connection with the SPI slave is still not established, it means that an abnormality may have occurred. Therefore, if the SPI host detects that the number of switching times is greater than the first alarm threshold, it outputs an alarm message indicating an abnormality of the SPI bus.

[0058] For example, for an SPI master, its control pin is called an OUT pin, and the steps for attempting to establish communication with an SPI slave are as follows:

[0059] (1) After the SPI host is powered on, the host is in handshake mode;

[0060] (2) The SPI master sends a handshake command to the SPI slave and receives the slave's response data at the same time;

[0061] (3) If the SPI host sends the handshake command and receives the response data correctly, the host OUT pin signal remains unchanged, and the host enters the communication mode;

[0062] (4) If the SPI master does not receive the response data from the slave after sending the handshake command, or the received response data is incorrect, the SPI master controls the OUT pin level to flip, so that the switching circuit changes the connection status of the data input and data output lines between the master and the slave;

[0063] (5) Determine the number of times the SPI host OUT pin level flips. If it is not greater than the first alarm threshold of 3 times, return to step 2. If it exceeds 3 times, the SPI host shuts down the SPI bus communication and reports an error, and the process ends.

[0064] In addition, this embodiment also provides an SPI communication switching method, which is applied to the SPI slave in the above circuit system, wherein the circuit system also includes an SPI host and a switching circuit, wherein a first data pin of the SPI host and a second data pin of the SPI slave establish a communication connection through the switching circuit, the SPI host also includes a control pin for controlling the switching circuit, and the SPI slave includes a detection pin connected to the control pin. Figure 6 As shown, the method includes:

[0065] S1B, receives the handshake command sent by the SPI host;

[0066] S2B, in response to the handshake command, sends response data to the SPI host;

[0067] S3B, judging whether the response data is sent successfully. If it is sent successfully, executing step S4B, otherwise, executing step S5B.

[0068] S4B, enter the communication mode for communicating with the SPI master.

[0069] In communication mode, the SPI slave and SPI master can communicate normally according to the SPI communication protocol.

[0070] S5B, accumulating the number of level changes of the detection pin, and when the number of level changes is greater than a second alarm threshold, outputting alarm information indicating an abnormality of the SPI bus.

[0071] For example, for an SPI slave, the detection pin to which its control pin is connected is called an IN pin, and the steps for attempting to establish communication with the SPI master are as follows:

[0072] (1) After the SPI slave is powered on, it is in handshake mode, waiting to receive the handshake command from the host;

[0073] (2) The SPI slave receives the SPI master handshake command and sends response data to the SPI master;

[0074] (3) If the SPI slave receives the handshake command from the host and sends the response data correctly, and recognizes that the IN pin status has not changed, the SPI slave enters the communication mode;

[0075] (4) If the SPI slave receives the SPI master handshake command and sends the response data incorrectly, or detects that the IN pin level has changed, it determines whether the number of IN pin level changes exceeds 3 times. If not, it returns to step 2. If more than 3 times, the slave closes the SPI communication and reports an error, and the process ends.

[0076] In this way, based on the switching circuit between the SPI master and the SPI slave, the SPI communication switching method enables the SPI master and the SPI slave to adapt to non-standardized data pins.

[0077] Finally, this embodiment also provides an electronic device, which includes the above circuit system. The SPI master or SPI slave in the circuit system may include a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the above SPI communication switching method is implemented.

[0078] In addition, the SPI master or the SPI slave may also include a communication unit. The memory, the processor and the communication unit are electrically connected to each other directly or indirectly through a system bus to achieve data transmission or interaction.

[0079] The memory may be an information recording device based on any electronic, magnetic, optical or other physical principle, used to record execution instructions, data, etc. In some embodiments, the memory may be, but is not limited to, a volatile memory, a non-volatile memory, a storage drive, etc.

[0080] In some embodiments, the volatile memory may be a random access memory (RAM); in some embodiments, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), a flash memory, etc.; in some embodiments, the storage drive may be a disk drive, a solid-state drive, any type of storage disk (such as a CD, a DVD, etc.), or a similar storage medium, or a combination thereof, etc.

[0081] The communication unit is used to send and receive data through a network. In some embodiments, the network may include a wired network, a wireless network, a fiber optic network, a telecommunication network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network (WAN), a public switched telephone network (PSTN), a Bluetooth network, a ZigBee network, or a near field communication (NFC) network, or any combination thereof. In some embodiments, the network may include one or more network access points. For example, the network may include a wired or wireless network access point, such as a base station and / or a network switching node, and one or more components of the service request processing system may be connected to the network through the access point to exchange data and / or information.

[0082] The processor may be an integrated circuit chip having a signal processing capability, and the processor may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor may include a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), or a microprocessor, or any combination thereof.

[0083] It should be understood that the apparatus and method disclosed in the above-mentioned embodiments can also be implemented in other ways. The apparatus embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0084] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A circuit system, characterized in that: The circuit system comprises an SPI host, an SPI slave and a switching circuit, wherein a first data pin of the SPI host and a second data pin of the SPI slave establish a communication connection through the switching circuit; The SPI host also includes a control pin for controlling the switching circuit; The SPI host is used to send a handshake command to the SPI slave, and judge whether it is necessary to control the switching circuit to switch the connection mode between the first data pin and the second data pin through the control pin according to the response result of the handshake command.

2. The circuit system according to claim 1, characterized in that: The connection mode includes a direct connection mode and a cross connection mode.

3. The circuit system according to claim 1, characterized in that: The switching circuit includes a double-pole double-throw switch and a driving element of the double-pole double-throw switch; The control end of the SPI host is connected to the driving element; The SPI host outputs different control signals to the driving element through the control pin, so that the double-pole double-throw switch switches the connection mode between the first data pin and the second data pin.

4. The circuit system according to claim 3, characterized in that: The driving element is a logic NOT gate.

5. A SPI communication switching method, characterized in that: An SPI host applied to a circuit system, the circuit system further comprising an SPI slave and a switching circuit, a first data pin of the SPI host and a second data pin of the SPI slave establishing a communication connection through the switching circuit, the SPI host further comprising a control pin for controlling the switching circuit, the method comprising: Sending a handshake command to the SPI slave; According to the response result of the handshake command, it is determined whether it is necessary to control the switching circuit through the control pin to switch the connection mode between the first data pin and the second data pin.

6. The SPI communication switching method according to claim 5, characterized in that: The determining, according to the response result of the handshake command, whether it is necessary to control the switching circuit to switch the connection mode between the first data pin and the second data pin through the control pin includes: If the response data of the SPI slave to the handshake command is not received through the first data pin, controlling the switching circuit to switch the connection mode between the first data pin and the second data pin; Return to sending a handshake command to the SPI slave until the number of switching times of the connection mode between the first data pin and the second data pin is greater than a first alarm threshold or response data of the SPI slave to the handshake command is received through the first data pin.

7. The SPI communication switching method according to claim 6, characterized in that: The method further comprises: If the switching times are greater than the first alarm threshold, an alarm message indicating an abnormality of the SPI bus is output.

8. The SPI communication switching method according to claim 5 or 6, characterized in that: The connection mode includes a direct connection mode and a cross connection mode.

9. A SPI communication switching method, characterized in that: An SPI slave device applied to a circuit system, the circuit system further comprising an SPI host device and a switching circuit, a first data pin of the SPI host device and a second data pin of the SPI slave device establishing a communication connection through the switching circuit, the SPI host device further comprising a control pin for controlling the switching circuit, the SPI slave device comprising a detection pin connected to the control pin, the method comprising: Receive a handshake command sent by the SPI host; In response to the handshake command, sending response data to the SPI host; If the response data is sent successfully, then enter the communication mode for communicating with the SPI host; If the response data is not sent successfully, the number of level changes of the detection pin is accumulated, and when the number of level changes is greater than a second alarm threshold, an alarm message indicating an abnormality of the SPI bus is output.

10. An electronic device, characterized in that: The electronic device comprises the circuit system according to any one of claims 1 to 4.

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