Optical switching matrix and photoelectric switching system

Abstract

The invention relates to the technical field of photoelectric switching, and particularly discloses an optical switching matrix and a photoelectric switching system. According to the technical scheme, the optical switching matrix comprises 2n (n is greater than or equal to 3 and n is a positive integer) single-input and double-output 1 * 2 optical switch basic units, 2n double-input and single-output 2 * 1 optical switch basic units and 2n (2n-3) double-input and double-output 2 * 2 optical switch basic units, through a specific connection relationship, the number of the required optical switch basic units is greatly reduced, and the optical switch can be segmented into cascade connection of a plurality of small-scale optical chips, thereby reducing the complexity and cost of the optical switch chips, and avoiding the problem that a control circuit is too complicated due to excessive number of the optical switch basic units. Mass production and high-reliability use are realized; and maintenance and replacement are more difficult.

Description

Technical Field

[0001] The present application relates to the field of optoelectronic switching, and in particular to an optical switching matrix and an optoelectronic switching system. Background Art

[0002] For an N×N strictly non-blocking optical switching matrix, a network with both input and output in a binary tree structure can reduce the number of 2x2 optical switch basic units to 2*Log2N, effectively reducing the number of basic units in series and, in turn, reducing insertion loss. However, the number of optical switch basic units required is 2*(N-1)*N, which is too large. Therefore, large-capacity optical switching systems are still difficult to put into practical use. In addition, there are too many control signals, the control circuits are too complex, and the design of non-standard products is difficult. Mass production, high-reliability use, and maintenance and replacement are even more difficult. Summary of the invention

[0003] The main purpose of the present application is to provide an optical switching matrix and an optoelectronic switching system, aiming to solve the technical problem that the connection mode of the optical switching matrix in the prior art leads to an excessive number of optical switch basic units required.

[0004] To achieve the above object, the present application provides an optical switching matrix, the optical switching matrix comprising: n (n≥3, n is a positive integer) single-input, dual-output 1×2 optical switch basic units, 2 n Dual-input, single-output 2×1 optical switch basic unit and 2 n (2n-3) dual-input, dual-output 2×2 optical switch basic units;

[0005] Each of the 1×2 optical switch basic units constitutes the first column of the optical switching matrix. n The last column of the optical switching matrix is ​​composed of two dual-input, single-output 2×1 optical switch basic units, and the 2×2 optical switch basic units constitute the middle 2n-3 columns of the optical switching matrix, with 2 n 2×2 optical switch basic unit;

[0006] The optical switching matrix has 2n-1 columns, and the connection relationship between the columns of the optical switching matrix includes: 1 span 1 / 2 m-1 (At this time, m is 1 or 2) domain connection relationship and 2 spans 1 / 2 m-1 (In this case, m is any positive integer from 3 to n) domain connection relationships, a total of 2n-2 connection relationships; when the n-1th connection relationship is a connection relationship across 1 / 2 domains, the nth connection relationship is a connection relationship across 1 domain; when the n-1th connection relationship is a connection relationship across 1 domain, the nth connection relationship is a connection relationship across 1 / 2 domains; the xth and 2n-x-1th connection relationships are connections across 1 / 2 n-xdomain connection (x is any positive integer from 1 to n-2); the span 1 / 2 m-1 The domain connection relationship indicates that when Q 1 Column and Q 2 The connection relationship of the column is across 1 / 2 m-1 When two domains are connected (m is any positive integer from 1 to n), Q 1 Column and Q 2 The columns are divided into 2 equal parts by rows m-1 optical switch array chips, each of which has 2 n-m+1 The connection relationship of the optical switch basic units in each optical switch array chip is the same; let X (N,1) represents the optical switch basic unit in the first column of the Nth row in any optical switch array chip, X (N,2) represents the optical switch basic unit in the Nth row and the second column of the optical switch array chip. When 1≤N≤2 n-m When X (N,1) Connect X separately (N,2) and When 2 n-m <N≤2 n-m+1 When X (N,1) Connect X separately (N,2) and

[0007] In one embodiment, the structure of the optical switching matrix further includes: forming an optical switching matrix deformation structure by exchanging positions of any optical switch basic unit of the optical switching matrix with any optical switch basic unit in the same column, so as to cut the entire optical switch matrix into small-scale arrays, and cascade them with optical fibers;

[0008] The optical switch basic unit includes: a 1x2 optical switch with a single input and dual output, a 2x1 optical switch with dual inputs and a single output, and a 2x2 optical switch with dual outputs and dual inputs;

[0009] Selecting any one of the two input optical fibers will result in an array of 1x2 optical switch basic units with single input and dual output in the first column; selecting any one of the two output optical fibers will result in an array of 2x1 optical switch basic units with dual input and single output in the last column; selecting all optical fibers will result in an array of 2x2 optical switches for all basic units in the intermediate stage.

[0010] In one embodiment, the connection relationship of the optical switch basic units in each of the optical switch array chips is the same, and the other connection of all 2×2 optical switch basic units is a local domain connection.

[0011] In one embodiment, all cross-domain connections and local domain connections keep the lower-order addresses unchanged.

[0012] The present application also provides an optoelectronic switching system, the optoelectronic switching system comprising: an electrical switching chip module, a sealed cable module, an optical module, an optical switching matrix deformation structure as described above, and a field programmable gate array;

[0013] The electrical exchange chip module is connected to the sealed cable module;

[0014] The sealed cable module is connected to the optical module via an optical fiber;

[0015] The optical module is connected to the optical exchange matrix deformation structure;

[0016] The field programmable gate array is connected to the optical switching matrix deformation structure;

[0017] The electrical exchange chip module is used to send electrical signal data to the sealed cable module;

[0018] The optical module is used to receive the electrical signal data sent by the electrical switching chip module, convert the electrical signal data into optical signal data, perform wavelength division multiplexing on the optical signal data, and input the wavelength division multiplexed optical signal data into the optical switching matrix;

[0019] The optical switching matrix is ​​used to transmit the optical signal data.

[0020] The field programmable gate array is used for decoding control signals of blocking avoidance routing of a high-speed optical switching matrix.

[0021] In one embodiment, the sealed cable module further comprises: a transmission chip;

[0022] The transmission chip is used to relay, regenerate and reduce the speed of the electrical signal data received by the sealed cable module.

[0023] In one embodiment, the optoelectronic exchange system further includes: a central control unit;

[0024] The central control unit is connected to the optical switching matrix;

[0025] The central control unit is used to control the transmission of the optical signal data in the optical switching matrix.

[0026] In one embodiment, the optoelectronic switching system further comprises: a semiconductor optical amplifier;

[0027] The semiconductor optical amplifier is connected to the optical switching matrix;

[0028] The semiconductor optical amplifier is used to amplify optical signal data.

[0029] The technical solution of the present application proposes an optical switching matrix, wherein the optical switching matrix comprises: n (n≥3, n is a positive integer) single-input, dual-output 1×2 optical switch basic units, 2 n Dual-input, single-output 2×1 optical switch basic unit and 2 n (2n-3) dual-input, dual-output 2×2 optical switch basic units; through a specific connection relationship, the number of required optical switch basic units is greatly reduced, and can be divided into a cascade of multiple small-scale optical chips, reducing the complexity and cost of the optical switch chip, avoiding the technical problems of too complex control circuits caused by too many optical switch basic units, and making mass production, high-reliability use, and maintenance and replacement more difficult. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a first structural schematic diagram of the first embodiment of the optical switching matrix of the present application;

[0031] Figure 2 This is a second structural schematic diagram of the first embodiment of the optical switching matrix of the present application;

[0032] Figure 3 This is a connection diagram of the optical switch basic unit in the first embodiment of the optical switching matrix of the present application;

[0033] Figure 4 This is a third structural schematic diagram of the first embodiment of the optical switching matrix of the present application;

[0034] Figure 5 This is a fourth structural schematic diagram of the first embodiment of the optical switching matrix of the present application;

[0035] Figure 6 This is a first structural schematic diagram of the second embodiment of the optoelectronic switching system of the present application;

[0036] Figure 7 A second structural schematic diagram of the second embodiment of the optoelectronic switching system of the present application;

[0037] Figure 8 A third structural schematic diagram of the second embodiment of the optoelectronic switching system of the present application;

[0038] Fig. 9 This is a fourth structural diagram of the second embodiment of the optoelectronic switching system of the present application.

[0039] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0043] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0044] Reference Figure 1 , Figure 1 This is a first structural schematic diagram of the first embodiment of the optical switching matrix of the present application.

[0045] In this embodiment, the optical switching matrix includes: 5 A single-input, dual-output 1×2 optical switch basic unit, 2 5 Dual-input, single-output 2×1 optical switch basic unit and 2 5 (2*5-3) dual-input, dual-output 2×2 optical switch basic units;

[0046] Each of the 1×2 optical switch basic units constitutes the first column of the optical switching matrix. 5 The last column of the optical switching matrix is ​​composed of two dual-input, single-output 2×1 optical switch basic units, and the 2×2 optical switch basic units constitute the middle 7 columns of the optical switching matrix, with 2 5 A 2×2 optical switch basic unit constitutes a 32×32 optical switching matrix.

[0047] The 32×32 optical switching matrix has 2*5-1=9 columns, and the connection relationship between the columns of the optical switching matrix includes: 1 span 1 / 2m-1 (At this time, m is 1 or 2) domain connections and 2 spans 1 / 2 m-1 (At this time, m is any positive integer from 3 to 5) domain connections, a total of 2*5-2=8 connection relationships; when the 4th connection relationship is a connection across 1 / 2 domain, the 5th connection relationship is a connection across 1 domain; when the 4th connection relationship is a connection across 1 domain, the 5th connection relationship is a connection across 1 / 2 domain, and the xth and 9-xth connection relationships are connections across 1 / 2 5-x domain connection (x is any positive integer from 1 to 3); the span 1 / 2 m-1 The domain connection relationship indicates that when Q 1 Column and Q 2 The connection relationship of the column is across 1 / 2 m-1 (m is any positive integer from 1 to 5) domains are connected, Q 1 Column and Q 2 The columns are divided into 2 equal parts by rows m-1 optical switch array chips, each of which has 2 5-m+1 The connection relationship of the optical switch basic units in each optical switch array chip is the same; let X (N,1) represents the optical switch basic unit in the first column of the Nth row in any optical switch array chip, X (N,2) represents the optical switch basic unit in the Nth row and the second column of the optical switch array chip. When 1≤N≤2 5-m When X (N,1) Connect X separately (N,2) and When 2 5-m <N≤2 5-m+1 When X (N,1) Connect X separately (N,2) and

[0048]

[0049] It should be noted that the 4th connection relationship is a connection across 1 / 2 domain, and the 5th connection relationship is a connection across 1 domain. That is, the 4th connection relationship is a connection across 1 domain, and the 5th connection relationship is a connection across 1 / 2 domain. The 4th connection relationship and the 5th connection relationship can also be interchanged. The 1st and 8th connection relationships are across 1 / 2 domains. 4 If the fields are connected, the 1st and 2nd columns and the 8th and 9th columns are divided into 2 equal rows. 4 The connection relationship between the second and seventh optical switch array chips is 1 / 2 3 The 2nd and 3rd columns and the 7th and 8th columns are divided into 2 equal parts by row. 3 The connection relationship between the third and sixth optical switch array chips is 1 / 2 2The 3rd and 4th columns and the 6th and 7th columns are divided into 2 equal parts by row. 3 Taking the 2nd and 3rd columns and the 7th and 8th columns as examples, the 2nd and 3rd columns and the 7th and 8th columns are divided into 2 rows. 3 The internal connection relationship of each optical switch array chip is the same. Taking any optical switch array chip as an example, since its connection relationship spans 1 / 2 3 domains are connected, so m = 4, then when 1 ≤ N ≤ 2, for the optical switch basic unit X (N,1) The two output terminals of (N,2) , the other end is connected to X (N+2,2) ; When 2<N≤4, X (N,1) The two output terminals of (N,2) , the other end is connected to X (N-2,2) At this time, the connection relationship between the second column and the third column and between the seventh column and the eighth column is formed by eight such optical switch array chips.

[0050] Based on the above implementation, in another feasible implementation, referring to Figure 2 , Figure 2 This is a second structural diagram of the first embodiment of the optical switching matrix of the present application. The structure of the above 32×32 optical switching matrix also includes: any optical switch basic unit of the 32×32 optical switching matrix forms an optical switching matrix deformation structure by exchanging positions with any optical switch basic unit in the same column any number of times, so as to facilitate cutting the entire optical switch matrix into small-scale arrays and cascading them with optical fibers. The three types of optical switch basic units involved: 1x2 optical switch with single input and dual output, 2x1 optical switch with dual input and single output, and 2x2 optical switch with dual output and dual input, can all adopt a unified design. Refer to Figure 3 , Figure 3 This is a connection diagram of the optical switch basic units in the first embodiment of the optical switching matrix of the present application. The design of the optical chip array composed of these optical switch basic units can be optimized: the one with better performance among the two input optical fibers is selected, that is, the first column is an array of 1x2 optical switch basic units with single input and dual output; the one with better performance among the two output optical fibers is selected, that is, the last column is an array of 2x1 optical switch basic units with dual input and single output; the one with all optical fibers is selected, that is, the array of all basic units in the intermediate level are 2x2 optical switches.

[0051] Taking the above 32×32 optical switching matrix as an example, based on the original connection, only the optical switch basic units in the 4th, 5th and 6th columns are now row-swapped, and each row in the 4th, 5th and 6th columns (three optical switch basic units in total) is regarded as a whole. The original 9th, 17th and 25th rows are moved to the 2nd, 3rd and 4th rows respectively; the original 2nd, 10th, 18th and 26th rows are moved to the 5th, 6th, 7th and 8th rows respectively; the original 3rd, 11th, 19th and 27th rows are moved to the 9th, 10th, 11th and 12th rows respectively; the original 4th, 12th, 20th and 28th rows are moved to the The 13th, 14th, 15th and 16th rows are moved; the original 5th, 13th, 21st and 29th rows are moved to the 17th, 18th, 19th and 20th rows respectively; the original 6th, 14th, 22nd and 30th rows are moved to the 21st, 22nd, 23rd and 24th rows respectively; the original 7th, 15th, 23rd and 31st rows are moved to the 25th, 26th, 27th and 28th rows respectively; the original 8th, 16th and 24th rows are moved to the 29th, 30th and 31st rows respectively; this does not contradict the above-mentioned arbitrary optical switch basic unit of the optical switching matrix through any number of exchange positions with any optical switch basic unit in the same column. After such changes, the optical switching matrix can be divided into 24 small optical switch array chips, each chip including four rows and three columns of optical switch basic units.

[0052] In another possible implementation, reference Figure 4 , Figure 4 This is a third structural diagram of the first embodiment of the optical switching matrix of the present application.

[0053] In this embodiment, the optical switching matrix includes: 6 A single-input, dual-output 1×2 optical switch basic unit, 2 6 Dual-input, single-output 2×1 optical switch basic unit and 2 6 (2*6-3) dual-input, dual-output 2×2 optical switch basic units;

[0054] Each of the 1×2 optical switch basic units constitutes the first column of the optical switching matrix. 6 The last column of the optical switching matrix is ​​composed of two dual-input, single-output 2×1 optical switch basic units, and the 2×2 optical switch basic units constitute the middle 9 columns of the optical switching matrix, with 2 6 A 2×2 optical switch basic unit constitutes a 64×64 optical switching matrix.

[0055] The 64×64 optical switching matrix has 2*6-1=11 columns, and the connection relationship between the columns of the optical switching matrix includes: 1 span 1 / 2 m-1 (At this time, m is 1 or 2) domain connections and 2 spans 1 / 2 m-1(At this time, m is any positive integer from 3 to 6) domain connections, a total of 2*6-2=10 connection relationships; when the 5th connection relationship is a connection across 1 / 2 domain, the 6th connection relationship is a connection across 1 domain; when the 5th connection relationship is a connection across 1 domain, the 6th connection relationship is a connection across 1 / 2 domain, and the xth and 11-xth connection relationships are connections across 1 / 2 6-x domain connection (x is any positive integer from 1 to 4); the span 1 / 2 m-1 The domain connection relationship indicates that when Q 1 Column and Q 2 The connection relationship of the column is across 1 / 2 m-1 (m is any positive integer from 1 to 6) domains are connected, Q 1 Column and Q 2 The columns are divided into 2 equal parts by rows m-1 optical switch array chips, each of which has 2 6-m+1 The connection relationship of the optical switch basic units in each optical switch array chip is the same; let X (N,1) represents the optical switch basic unit in the first column of the Nth row in any optical switch array chip, X (N,2) represents the optical switch basic unit in the Nth row and the second column of the optical switch array chip. When 1≤N≤2 6-m When X (N,1) Connect X separately (N,2) and When 2 6-m <N≤2 6-m+1 When X (N,1) Connect X separately (N,2) and

[0056]

[0057] Based on the above implementation, in another feasible implementation, referring to Figure 5 , Figure 5 The fourth structural diagram of the first embodiment of the optical switching matrix of the present application. The structure of the above 64×64 optical switching matrix also includes: any optical switch basic unit of the 64×64 optical switching matrix forms an optical switching matrix deformation structure by exchanging positions with any optical switch basic unit in the same column any number of times.

[0058] Taking the above 64×64 optical switching matrix as an example, based on the original connection, only the optical switch basic units in the 4th, 5th, 6th, 7th and 8th columns are now row-swapped, and each row in the 4th, 5th, 6th, 7th and 8th columns (a total of 5 optical switch basic units) is regarded as a whole. The original 9th, 17th, 25th, 33rd, 41st, 49th and 57th rows are moved to the 2nd, 3rd, 4th, 5th, 6th, 7th and 8th rows respectively; the original 2nd, 10th, Move lines 18, 26, 34, 42, 50 and 58 to lines 9, 10, 11, 12, 13, 14, 15 and 16 respectively; move lines 3, 11, 19, 27, 35, 43, 51 and 59 to lines 17, 18, 19, 20, 21, 22, 23 and 24 respectively; move lines 4, 12, 20, 28, 36, 44, 52 and 60 to lines 25, 26, 27, 28 8, 29, 30, 31 and 32; move the original 5, 13, 21, 29, 37, 45, 53 and 61 to 33, 34, 35, 36, 37, 38, 39 and 40 respectively; move the original 6, 14, 22, 30, 38, 46, 54 and 62 to 41, 42, 43, 44, 45, 46, 47 and 48 respectively; move the original 7, 15, 23, 31, 39, The 47th, 55th and 63rd rows are moved to the 49th, 50th, 51st, 52nd, 53rd, 54th, 55th and 56th rows respectively; the original 8th, 16th, 24th, 32nd, 40th, 48th, 56th and 64th rows are moved to the 57th, 58th, 59th, 60th, 61st, 62nd, 63rd and 64th rows respectively; this does not contradict the fact that any optical switch basic unit of the optical switching matrix can exchange positions with any optical switch basic unit in the same column any number of times. After such changes, the optical switching matrix can be divided into 32 optical switch array chips with three rows and four columns and 8 optical switch array chips with eight rows and five columns.

[0059] It should be noted that at this time, the 5th connection relationship is connected across 1 / 2 domains, and the 6th connection relationship is connected across 1 domain. That is, the 5th connection relationship is connected across 1 domain, and the 6th connection relationship is connected across 1 / 2 domains. The 5th connection relationship and the 6th connection relationship can also be interchanged. The 1st and 10th connection relationships are connected across 1 / 2 domains. 5 The 1st and 2nd columns and the 10th and 11th columns are divided into 2 equal rows. 5 The connection relationship between the second and the ninth optical switch array chips is 1 / 2 4 The 2nd and 3rd columns and the 9th and 10th columns are divided into 2 equal rows. 4 The connection relationship between the third and the eighth optical switch array chips is 1 / 2 3 The 3rd and 4th columns and the 8th and 9th columns are divided into 2 equal parts by row. 3The connection relationship between the 4th and 7th optical switch array chips is 1 / 2 2 The 4th and 5th columns and the 7th and 8th columns are divided into 2 equal parts by row. 2 Taking the 4th and 5th columns and the 7th and 8th columns as examples, the 4th and 5th columns and the 7th and 8th columns are divided into 2 equal rows. 2 The internal connection relationship of each optical switch array chip is the same. Taking any optical switch array chip as an example, since its connection relationship spans 1 / 2 2 domains are connected, so m = 3, then when 1 ≤ N ≤ 2 3 When the optical switch basic unit X (N,1) The two output terminals of (N,2) , the other end is connected When 2 3 <N≤2 4 When X (N,1) The two output terminals of (N,2) , the other end is connected At this time, the connection relationship between the 4th column and the 5th column and between the 7th column and the 8th column is formed by 4 such optical switch array chips.

[0060] In this embodiment, the optical switching matrix includes: n (n≥3, n is a positive integer) single-input, dual-output 1×2 optical switch basic units, 2 n Dual-input, single-output 2×1 optical switch basic unit and 2 n (2n-3) dual-input, dual-output 2×2 optical switch basic units;

[0061] Each of the 1×2 optical switch basic units constitutes the first column of the optical switching matrix. n The last column of the optical switching matrix is ​​composed of two dual-input, single-output 2×1 optical switch basic units, and the 2×2 optical switch basic units constitute the middle 2n-3 columns of the optical switching matrix, with 2 n 2×2 optical switch basic unit;

[0062] The optical switching matrix has 2n-1 columns, and the connection relationship between the columns of the optical switching matrix includes: 1 span 1 / 2 m-1 (At this time, m is 1 or 2) domain connections and 2 spans 1 / 2 m-1(In this case, m is any positive integer from 3 to n) domain connections, with a total of 2n-2 connection relationships; when the n-1th connection relationship is a connection across 1 / 2 domain, the nth connection relationship is a connection across 1 domain; when the n-1th connection relationship is a connection across 1 domain, the nth connection relationship is a connection across 1 / 2 domain; the xth and 2n-x-1th connection relationships are connections across 1 / 2 n-x domain connection (x is any positive integer from 1 to n-2); the span 1 / 2 m-1 The domain connection indicates that when Q 1 Column and Q 2 The connection relationship of the column is across 1 / 2 m-1 When two domains are connected (m is any positive integer from 1 to n), Q 1 Column and Q 2 The columns are divided into 2 equal parts by rows m-1 optical switch array chips, each of which has 2 n-m+1 The connection relationship of the optical switch basic units in each optical switch array chip is the same; let X (N,1) represents the optical switch basic unit in the first column of the Nth row in any optical switch array chip, X (N,2) represents the optical switch basic unit in the Nth row and the second column of the optical switch array chip. When 1≤N≤2 n-m When X (N,1) Connect X separately (N,2) and When 2 n-m <N≤2 n-m+1 When X (N,1) Connect X separately (N,2) and Through this connection relationship, the number of required optical switch basic units is greatly reduced, avoiding the technical problems caused by too many control signals, too complicated control circuits, high difficulty in designing non-standard products, and more difficult mass production, high-reliability use, and maintenance and replacement.

[0063] Reference Figure 6 , Figure 6 This is a first structural diagram of the optoelectronic switching system of this application. Figure 5 A second embodiment of the present application is proposed.

[0064] In this embodiment, the optoelectronic exchange system includes: an electrical exchange chip module, a sealed cable module, an optical module, an optical exchange matrix deformation structure as described above, and a field programmable gate array; the electrical exchange chip module is connected to the sealed cable module; the sealed cable module is connected to the optical module through an optical fiber; the optical module is connected to the optical exchange matrix deformation structure; the field programmable gate array is connected to the optical exchange matrix deformation structure; the electrical exchange chip module is used to send electrical signal data to the sealed cable module; the optical module is used to receive the electrical signal data sent by the electrical exchange chip module, and convert the electrical signal data into optical signal data, and perform wavelength division multiplexing on the optical signal data, and input the wavelength division multiplexed optical signal data into the optical exchange matrix; the optical exchange matrix is ​​used to transmit the optical signal data. The field programmable gate array is used for decoding the control signal of the blocking avoidance routing of the high-speed optical exchange matrix.

[0065] It should be noted that, in this embodiment, the electrical switching chip module includes 256 electrical switching chips and 64 256×256 optical switching matrices. The 256×256 optical switching matrix is ​​a matrix with 2 8 A single-input, dual-output 1×2 optical switch basic unit, 2 8 Dual-input, single-output 2×1 optical switch basic unit and 2 8 (2*8-3) dual inputs, each of the 1×2 optical switch basic units constitutes the first column of the optical switching matrix, each of the 2 8 The last column of the optical switching matrix is ​​composed of two dual-input, single-output 2×1 optical switch basic units, and the 2×2 optical switch basic units constitute the middle 13 columns of the optical switching matrix, with 2 8 2×2 optical switch basic units; forming a 256×256 optical switching matrix. The 256×256 optical switching matrix has 2*8-1=15 columns, and the connection relationship between the columns of the optical switching matrix includes: 1 span 1 / 2 m-1 (At this time, m is 1 or 2) domain connections and 2 spans 1 / 2 m-1 (At this time, m is any positive integer from 3 to 8) domain connections, a total of 2*8-2=14 connection relationships; when the 7th connection relationship is a connection across 1 / 2 domain, the 8th connection relationship is a connection across 1 domain; when the 7th connection relationship is a connection across 1 domain, the 8th connection relationship is a connection across 1 / 2 domain, and the xth and 15-xth connection relationships are connections across 1 / 2 8-x domain connection (x is any positive integer from 1 to 6); the span 1 / 2 m-1 The domain connection relationship indicates that when Q 1 Column and Q 2 The connection relationship of the column is across 1 / 2 m-1(m is any positive integer from 1 to 8) domains are connected, Q 1 Column and Q 2 The columns are divided into 2 equal parts by rows m-1 optical switch array chips, each of which has 2 8-m+1 The connection relationship of the optical switch basic units in each optical switch array chip is the same; let X (N,1) represents the optical switch basic unit in the first column of the Nth row in any optical switch array chip, X (N,2) represents the optical switch basic unit in the Nth row and the second column of the optical switch array chip. When 1≤N≤2 8-m When X (N,1) Connect X separately (N,2) and When 2 8-m <N≤2 8-m+1 When X (N,1) Connect X separately (N,2) and Any optical switch basic unit of the 256×256 optical switching matrix can also obtain a new structure of the 256×256 optical switching matrix by exchanging positions with any optical switch basic unit in the same column any number of times, which is not limited in this example. The optical module can be a 400G QSFP112 ER4 optical module. The 400G QSFP112 ER4 optical module is a high-performance optical communication module, which is mainly used to achieve a data transmission rate of 400Gbps. ER4 (Extended Range 4) type optical modules are suitable for longer distance transmission applications and can usually support a single-mode optical fiber transmission distance of at least 40 kilometers. In this embodiment, there are 64 256×256 optical switching matrices in total, which together with 256 Leaf layer electrical switching chips and each of their 64-port upstream optical modules and 64-port downstream optical modules form a two-layer Leaf-Spine non-convergence fat tree switching network, and the traditional Spine electrical switching chip is replaced by the optical switching matrix. Optimally, in order to meet the full-bandwidth non-blocking interconnection of the switching system, each channel of the 256-channel optical switching matrix is ​​connected to an optical module on the upstream of a Leaf electrical switching chip, and the 64 upstream ports of each Leaf electrical switching chip are respectively connected to an upstream port of one of the 64 sets of optical switching matrices.

[0066] A two-layer low-latency, high-capacity optoelectronic hybrid switching network consisting of a 256×256 optical switching matrix and 256 electrical switching chips. This network architecture is not only suitable for future high-speed optical switching optical burst switching OBS, but also for the currently more mature low-speed optical switching optical line switching OCS system. Its characteristics are that the first layer of switching consists of electrical switching chips and uplink and downlink optical modules connected to them at high speed, and the second layer is optical switching. The total capacity of this optoelectronic hybrid two-layer network = B*N*M / 2, where B is the switching particle, that is, the rate of the optical module 400Gbps, M is the number of channels of the first layer of electrical switching chips = 51.2Tbps / 400Gbps = 128, and N is the number of channels of the second layer of optical switching matrix, that is, 256, and the total capacity is 6553.6Tbps.

[0067] For the optical line switching OCS system, all 2*log 2 The sources of the control signals a, b, c, d, e, f, g, h, i, j, k, l, m, n, z of 256-1=15 columns of optical switch basic units are uniformly from the central control unit.

[0068] In another feasible implementation manner, the photoelectric exchange system further comprises a central control unit; the central control unit is connected to the optical exchange matrix;

[0069] For the optical burst switching OBS system, as shown in Figure b, c, d, e, g, h, i, k, the log 2 256=8 columns of control signals are controlled by the addresses of the source routes of the 256 transmitting optical signals, and there is no need to introduce FPGA (field programmable gate array); for the control signals of the 7 columns of optical switch basic units a, f, j, l, m, n, z, it is necessary to introduce FPGA (field programmable gate array) to provide high-speed decoding control signals to avoid all blocked routes in real time.

[0070] Based on the above implementation, in another feasible implementation, refer to Figure 7 , Figure 7 This is a second structural diagram of the second embodiment of the optoelectronic switching system of the present application.

[0071] It should be noted that, in this embodiment, the electrical switching chip module includes 16*64=1024 groups, each group includes 8 electrical switching chips, and 256 1024×1024 optical switching matrices. The 1024×1024 optical switching matrix is ​​210 single-input, dual-output 1×2 optical switch basic units, 210 dual-input, single-output 2×1 optical switch basic units, and 210 dual-input, dual-output 2×2 optical switch basic units; each of the 1×2 optical switch basic units constitutes the first column of the optical switching matrix, and each of the 2 10The last column of the optical switching matrix is ​​composed of two dual-input, single-output 2×1 optical switch basic units, and the 2×2 optical switch basic units constitute the middle 17 columns of the optical switching matrix, with 2 10 2×2 optical switch basic units; constitute a 1024×1024 optical switching matrix. The 1024×1024 optical switching matrix has 2*10-1=19 columns, and the connection relationship between the columns of the optical switching matrix includes: 1 span 1 / 2 m-1 (At this time, m is 1 or 2) domain connections and 2 spans 1 / 2 m-1 (At this time, m is any positive integer from 3 to 10) domain connections, a total of 2*10-2=18 connection relationships; when the 9th connection relationship is a connection across 1 / 2 domain, the 10th connection relationship is a connection across 1 domain; when the 9th connection relationship is a connection across 1 domain, the 10th connection relationship is a connection across 1 / 2 domain, and the xth and 19-xth connection relationships are connections across 1 / 2 10-x domain connection (x is all positive integers from 1 to 10); the span 1 / 2 m-1 The domain connection relationship indicates that when Q 1 Column and Q 2 The connection relationship of the column is across 1 / 2 m-1 (m is any positive integer from 1 to 10) domains are connected, Q 1 Column and Q 2 The columns are divided into 2 equal parts by rows m-1 optical switch array chips, each of which has 2 10-m+1 The connection relationship of the optical switch basic units in each optical switch array chip is the same; let X (N,1) represents the optical switch basic unit in the first column of the Nth row in any optical switch array chip, X (N,2) represents the optical switch basic unit in the Nth row and the second column of the optical switch array chip. When 1≤N≤2 10-m When X (N,1) Connect X separately (N,2) and When 2 10-m <N≤2 10-m+1 When X (N,1) Connect X separately (N,2) and Any optical switch basic unit of the 1024×1024 optical switch matrix may be exchanged with any optical switch basic unit in the same column any number of times to obtain a new structure of the 1024×1024 optical switch matrix, which is not limited in this example.

[0072] A two-layer optical burst OBS switching network consisting of 256 sets of 1024x1024 optical switching matrices and 16*64=1024 groups of 8 Leaf electrical switching chips in each group. The packaged cable module includes multiple packaged cables. Each Leaf electrical switching chip in each group aggregates its 256 50G signals into 256 8*50G=400G ER8 optical modules through 32 packaged cables, and enters an optical fiber through wavelength division multiplexing in the module, and enters a channel of the 256 1024×1024 optical switching matrices respectively. Each channel of each 1024×1024 optical switching matrix is ​​connected to one group of the 1024 groups of Leaf electrical switching chips, and is demultiplexed and aggregated into 8 50G signals through wavelength division multiplexing inside the optical module and packaged cables, and then returns to the 8 Leaf switches in the same group. This ensures that the two-layer optical-electrical hybrid switching system forms a Leaf-Spine non-convergent fat tree switching network.

[0073] The total capacity of this optical-electrical hybrid two-layer network = B*N*M / 2, where B is the aggregated switching particles of 8 parallel Leaf electrical switching chips, that is, the rate of the optical module is 400Gbps, M is the number of channels of the Leaf layer electrical switching chip = 25.6Tbps / 50Gbps = 512, and N is the number of channels of the Spine layer optical switching matrix, that is, 1024. The total capacity is 400Gbps*1024*512 / 2=104857.6Tbps.

[0074] The Log21024=10 control signals of b, c, d, e, g, h, i, j, k and p are controlled by the addresses of the source routes of the 1024 transmitting optical signals, and there is no need to introduce FPGA control. For the control signals of the 9 optical switch basic units of a, f, l, m, n, o, q, r and z, it is necessary to introduce FPGA to provide high-speed decoding control signals to avoid all blocked routes in real time.

[0075] In another feasible implementation of this embodiment, refer to Figure 8 , Figure 8 This is a third structural diagram of the second embodiment of the optoelectronic switching system of the present application.

[0076] The photoelectric exchange system further comprises: a semiconductor optical amplifier; the semiconductor optical amplifier is connected to the optical exchange matrix;

[0077] It should be noted that, considering the relatively large optical insertion loss of the 1024×1024 optical switching matrix, it may be necessary to introduce a semiconductor optical amplifier to amplify the optical signal. This can be packaged together with the array chip on the receiving end side, and the optical power information feedback can be provided by the optical switch basic unit of the subsequent stage to control the semiconductor optical amplifier, so that it is always in the best working state.

[0078] Considering that the power switching chip has many peripheral components such as power supply, the chip itself occupies a large space, and factors such as heat dissipation and high-speed signal fan-out, generally only 1 to 2 large-capacity switching chips can be placed on a circuit board. More, such as 8 parallel switching chips, cannot be placed on the same circuit board. The physical distance between them may even be far, but Fig. 9 The network architecture requires each chip to fan out one path separately, and then aggregate into a single particle and enter the same optical module. The electrical insertion loss of the circuit board and its high-speed connectors is too large to support such long-distance high-speed signal transmission. Fortunately, the 32 pairs of cables of the sealed cable can transmit high-speed signals to a longer distance. Each electrical switching chip can transmit the signal to the same optical module on the same circuit board through the sealed cable, becoming a switching particle and entering a pair of optical fibers for the next optical switching. Similarly, the downstream optical module or electrical module also synthesizes 400G switching particles to connect to the large-bandwidth computing chip. In this way, the two dimensions of switching particles and the number of channels reach or even exceed the traditional two-layer Leaf-Spine electrical switching system. Not only can it achieve a larger system switching capacity with a relatively backward process, but it can also inherit other advantages of optical switching: low latency, low cost, low power consumption, transparent protocol upgrade friendliness, etc.

[0079] Although silicon-based optical switch chips have high reliability, considering the large scale of the switching matrix and the many optical coupling links, it is still necessary to consider the response plan for channel failure. In addition, the failure rate of the 400G QSFP-DD ER8 optical module with high optical output and high sensitivity may also be higher than that of ordinary short-distance optical modules or electrical modules. Reserving sufficient redundant channels is one of the necessary measures to maintain the long-term normal operation of the system. As shown in the figure, after considering the 1 / 32 redundant backup for the downlink, the maximum number of ports M / 2 of the L1 layer electrical switching ASIC chip is reduced to 248; the maximum number of ports N of the L2 layer optical switching matrix is ​​512; the switching particle of this two-layer hybrid system is 400Gbps, so it can support low-latency full-bandwidth non-blocking interconnection of N*M / 2=126976 high-computing power (GPU) cards. The downlink network of the L1 layer electrical switching chip is the same as that of traditional data centers, which are highly reliable short-distance optical modules. The uplink port is fully populated with 131072pcs optical modules with high link budget (400G ER8 QSFP-DD example in the figure); 256*Tx / M1 / M2 (1~64) silicon optical switch modules in 5*16OSFP-XD package; 256*Rx (1~128) silicon optical switch modules in QSFP-DD package packaged with semiconductor optical amplifiers; all these two types of pluggable standard package modules can also be hot-swapped and replaced. More importantly, when an optical module fails and there is no time to replace the hardware, the software can control the routing of the optical switch so that the transmitting optical fiber of the optical module always returns to its receiving optical fiber, and controls it to work in low power consumption mode without affecting other ports. Of course, the spare port and optical module can also be operated in this way. When a failed optical module appears, the spare port and optical module will be activated to replace the failed one. When there is a failed optical switch unit in the optical switching matrix, similar operations can also be performed without manual intervention in time.

[0080] In order to meet the GPU's requirements for data burstiness and real-time performance, and to give full play to the advantages of high-speed switching of silicon optical switches, OPS / OBS optical switching technology has been put on the agenda, requiring the upstream optical module to have the ability to receive bursts, which is difficult for single-wavelength 100G or even higher rates. However, if the single-wave rate can be reduced to 50Gbps PAM4, or NRZ, or even 25Gbps NRZ to achieve the burst receiving function, it will be much simpler. At the same time, for optical wavelength division multiplexing, it is not difficult to transmit and exchange 4, 8 or even more wavelengths into the same optical fiber. Therefore, we can borrow the mature supporting technologies and series chips of 50G PON and even 25G PON OLT.

[0081] Because of the inherent protocol transparency of optical switching, this technology can be used for various switching protocols in addition to large-capacity Ethernet: InfiniBand, NVLink, PCIe, CML, etc. The optical switching chips used for various protocols are the same, and there may be requirements of various scales. Optimally, standardized two-level 4×8 and 3×4 optical switching array chips can form a 16×16 strictly non-blocking matrix; standardized three-level 3×4 optical switching chips can form a 32×32 strictly non-blocking matrix; 4×8, 5×8, 4×8 three-level can form a 64×64 strictly non-blocking matrix. Until larger scale.

[0082] In another feasible implementation of this embodiment, refer to Fig. 9 , Fig. 9 This is a fourth structural diagram of the second embodiment of the optoelectronic switching system of the present application.

[0083] The sealed cable module further includes: a transmission chip;

[0084] Traditional sealed cables are generally passive, or only have a retimer, that is, the 32 pairs of high-speed transceiver signals at the switch end are consistent with the 32 transceiver signal rates in the cable. This is fine for short-distance high-speed signal transmission between the switching chip and the sealed cable, but it is difficult to support higher-speed transmission to distant optical modules through longer-distance cables. Active sealed cables can regenerate and reduce the speed of the 32 high-speed transceiver signals at the switch end through the internal gearbox chip, and increase the total bandwidth by doubling the number of channels instead of increasing the signal rate in the cable, so as to achieve the purpose of larger switching particles B and further expand the capacity of the switching system (B*N*M / 2).

[0085] The 32 pairs of transceiver signals at the switch end are input through the interface 21 defined by the CPO standard, sent to the transmission gearbox chip 1 through the step circuit board 2, converted into a lower rate transceiver signal, and then soldered together with the high-speed transceiver cable 3 through the front and back pads 22 of the step circuit board. The appearance size, mechanical / electrical / heat dissipation and other specifications of the entire sealed cable module 4 meet the CPO standard. The significance of this is that the rate of higher rate signals can be reduced and transmitted to the distant optical module with double the number of cable pairs. For example, 32*100G can be converted to 64*50G; 32*200G can be converted to 64*100G, 16*400G can be converted to 64*100G, 32*400G can be converted to 128*100G, and so on.

[0086] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0087] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An optical switching matrix, characterized in that: The optical switching matrix comprises: n (n≥3, n is a positive integer) single-input, dual-output 1×2 optical switch basic units, 2 n Dual-input, single-output 2×1 optical switch basic unit and 2 n (2n-3) dual-input, dual-output 2×2 optical switch basic units; Each of the 1×2 optical switch basic units constitutes the first column of the optical switching matrix. n The last column of the optical switching matrix is ​​composed of two dual-input, single-output 2×1 optical switch basic units, and the 2×2 optical switch basic units constitute the middle 2n-3 columns of the optical switching matrix, with 2 n 2×2 optical switch basic unit; The optical switching matrix has 2n-1 columns, and the connection relationship between the columns of the optical switching matrix includes: 1 span 1 / 2 m-1 (At this time, m is 1 or 2) domain connections and 2 spans 1 / 2 m-1 (In this case, m is any positive integer from 3 to n) domain connections, with a total of 2n-2 connection relationships; when the n-1th connection relationship is a connection across 1 / 2 domain, the nth connection relationship is a connection across 1 domain; when the n-1th connection relationship is a connection across 1 domain, the nth connection relationship is a connection across 1 / 2 domain; the xth and 2n-x-1th connection relationships are connections across 1 / 2 n-x domain connection (x is any positive integer from 1 to n-2); the span 1 / 2 m-1 A domain connection means that when the connection relationship between Q1 and Q2 columns spans 1 / 2 m-1 When two fields are connected (m is any positive integer from 1 to n), the Q1 column and Q2 column are divided into two equal parts by row. m-1 optical switch array chips, each of which has 2 n-m+1 Row and 2 columns of optical switch basic unit.

2. The optical switching matrix according to claim 1, characterized in that: The structure of the optical switching matrix further includes: forming an optical switching matrix deformation structure by exchanging positions of any optical switch basic unit of the optical switching matrix with any optical switch basic unit in the same column any number of times, so as to cut the entire optical switch matrix into small-scale arrays, and cascade them with optical fibers; The optical switch basic unit includes: a 1x2 optical switch with a single input and dual output, a 2x1 optical switch with dual inputs and a single output, and a 2x2 optical switch with dual outputs and dual inputs; Selecting any one of the two input optical fibers will result in an array of 1x2 optical switch basic units with single input and dual output in the first column; selecting any one of the two output optical fibers will result in an array of 2x1 optical switch basic units with dual input and single output in the last column; selecting all optical fibers will result in an array of 2x2 optical switches for all basic units in the intermediate stage.

3. The optical switching matrix according to claim 1, characterized in that: The connection relationship of the optical switch basic units in each optical switch array chip is the same, and the other connection of all 2×2 optical switch basic units is a local domain connection.

4. The optical switching matrix according to claim 3, characterized in that: All cross-domain connections and local domain connections keep the lower-order addresses unchanged.

5. A photoelectric switching system, characterized in that: The optoelectronic switching system comprises: an electrical switching chip module, a sealed cable module, an optical module, an optical switching matrix deformation structure as claimed in claim 2, and a field programmable gate array; The electrical exchange chip module is connected to the sealed cable module; The sealed cable module is connected to the optical module via an optical fiber; The optical module is connected to the optical exchange matrix deformation structure; The field programmable gate array is connected to the optical switching matrix deformation structure; The electrical exchange chip module is used to send electrical signal data to the sealed cable module; The optical module is used to receive the electrical signal data sent by the electrical switching chip module, convert the electrical signal data into optical signal data, perform wavelength division multiplexing on the optical signal data, and input the wavelength division multiplexed optical signal data into the optical switching matrix; The optical switching matrix is ​​used to transmit the optical signal data; The field programmable gate array is used for decoding control signals of blocking avoidance routing of a high-speed optical switching matrix.

6. The sealed cable module according to claim 5, characterized in that: The sealed cable module further includes: a transmission chip; The transmission chip is used to relay, regenerate and reduce the speed of the electrical signal data received by the sealed cable module.

7. The photoelectric switching system according to claim 5, characterized in that: The photoelectric exchange system further comprises: a central control unit; The central control unit is connected to the optical switching matrix; The central control unit is used to control the transmission of the optical signal data in the optical switching matrix.

8. The photoelectric switching system according to claim 5, characterized in that: The photoelectric exchange system further comprises: a semiconductor optical amplifier; The semiconductor optical amplifier is connected to the optical switching matrix; The semiconductor optical amplifier is used to amplify optical signal data.

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