Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure. The preparation method comprises the following steps: forming a plurality of first grooves arranged at intervals in a substrate and strip-shaped structures located between adjacent first grooves; a plurality of first semiconductor layers and a plurality of second semiconductor layers are alternately formed on the bottom surfaces of the first grooves and the top surfaces of the strip-shaped structures in the second direction, and the adjacent second semiconductor layers which are located above the first grooves, located above the strip-shaped structures and located in the third direction are staggered in the second direction, wherein the number of the second semiconductor layers is the same as that of the first grooves; forming a second groove penetrating through each first semiconductor layer and each second semiconductor layer along a second direction; removing the first semiconductor layers in the target region along the second direction and forming a support structure wrapping the second semiconductor layers in the target region; and removing the first semiconductor layer on one side of the support structure along the first direction, so that the exposed second semiconductor layer forms a semiconductor column. The preparation method can be applied to preparation of the memory to improve the storage capacity of the obtained structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, in order to further improve the integration of semiconductor devices and increase storage performance, three-dimensional (3D) structure semiconductor devices have been proposed. The 3D structure expands the structure of semiconductor devices in the vertical direction, which is of great help to the development of dynamic random access memory (DRAM) and other memories.

[0003] However, the integration density and storage performance of current 3D structured semiconductor devices still need to be improved. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure.

[0005] In one aspect, the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate, forming a plurality of first grooves arranged at intervals in the substrate, and a strip structure located between adjacent first grooves; the first grooves extend along a first direction;

[0007] A plurality of first semiconductor layers and a plurality of second semiconductor layers are alternately formed on the bottom surface of the first trench and the top surface of the strip structure respectively along a second direction; the second direction intersects with the first direction; wherein the second semiconductor layers located above the first trench and having the same number of layers located above the strip structure and adjacent in a third direction are staggered in the second direction; the third direction intersects with the first direction and the second direction;

[0008] forming a second groove penetrating each of the first semiconductor layers and each of the second semiconductor layers along the second direction; the second groove extends along the first direction, and the orthographic projection of the second groove on the substrate partially overlaps with the first groove and the strip structure;

[0009] removing each of the first semiconductor layers in a target area along the second direction, and forming a support structure wrapping each of the second semiconductor layers in the target area;

[0010] The first semiconductor layers on one side of the support structure along the first direction are removed, so that the exposed second semiconductor layers form a plurality of semiconductor pillars arranged in parallel and at intervals.

[0011] In some embodiments, the first semiconductor layer and the second semiconductor layer are respectively grown along the second direction by using an epitaxial process;

[0012] The first semiconductor layer is made of silicon germanium; the second semiconductor layer is made of silicon.

[0013] In some embodiments, the top surfaces of the first semiconductor layer and the second semiconductor layer parallel to the bottom surface of the first trench are (100) crystal planes; the side walls of the first semiconductor layer and the second semiconductor layer parallel to the second direction are (110) crystal planes.

[0014] In some embodiments, the first semiconductor layers located above the first trench and the first semiconductor layers with the same number of layers located above the strip structures and adjacent in the third direction have the same growth thickness;

[0015] The second semiconductor layers located above the first trench and having the same number of layers located above the strip structures and adjacent to each other in the third direction have the same growth thickness.

[0016] In some embodiments, growing the second semiconductor layer along the second direction on the top surface of the first semiconductor layer using an epitaxial process includes:

[0017] Using an epitaxial process, growing an initial second semiconductor layer along the second direction on the exposed surface of the first semiconductor layer;

[0018] The initial second semiconductor layer on the side wall of the first semiconductor layer along the second direction is removed, and the initial second semiconductor layer remaining on the top surface of the first semiconductor layer constitutes the second semiconductor layer.

[0019] In some embodiments, a thickness of the first semiconductor layer in the second direction is greater than a depth of the first trench.

[0020] In some embodiments, the thickness of the first semiconductor layer is 2√3 times the distance between adjacent first trenches.

[0021] In some embodiments, a depth of the first trench is √3 times a distance between adjacent first trenches; and a thickness of the second semiconductor layer is 1 / 2 of a distance between adjacent first trenches.

[0022] In some embodiments, the bottom surface of the second groove is located above the bottom surface of the first groove, and the distance from the bottom surface of the second groove to the bottom surface of the first groove is greater than or equal to 1 / 2 of the depth of the first groove.

[0023] On the other hand, the present disclosure further provides a semiconductor structure, which is prepared by using the method for preparing a semiconductor structure provided by any of the aforementioned embodiments.

[0024] The semiconductor structure preparation method and semiconductor structure provided by the present disclosure have at least the following beneficial effects:

[0025] In the embodiment of the present disclosure, by forming a plurality of second semiconductor layers arranged at intervals in the second direction, forming a second groove penetrating the second semiconductor layer, and forming a support structure wrapping each second semiconductor layer, the plurality of second semiconductor layers arranged at intervals can form a plurality of semiconductor pillars arranged in parallel and at intervals, thereby forming a semiconductor structure with a three-dimensional structure, so as to facilitate the realization of three-dimensional storage, and solve the density limitation of the planar semiconductor structure in the related art. Therefore, the embodiment of the present disclosure can be applied to the preparation of a memory to improve the storage capacity of the obtained structure.

[0026] At the same time, in the embodiment of the present disclosure, the multiple first semiconductor layers and the multiple second semiconductor layers are alternately formed along the second direction, so after removing each first semiconductor layer, the second semiconductor layers adjacent in the third direction are dislocated in the second direction, so that the semiconductor pillars adjacent in the third direction can be dislocated in the second direction, which is beneficial to reduce the required spacing between adjacent semiconductor pillars in the second direction and reduce the occupied area of ​​the semiconductor structure. Therefore, the embodiment of the present disclosure can also improve the integration density and storage performance of the resulting structure when applied to the preparation process of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 It is a schematic diagram of a process for preparing a semiconductor structure in some embodiments of the present disclosure;

[0029] Figure 2 is a schematic flow chart of step S200 in the method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0030] Figure 3 It is a schematic diagram of the cross-sectional structure of a structure obtained after forming a patterned photoresist layer in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0031] Figure 4A schematic diagram of a cross-sectional structure of a structure obtained after forming a first trench in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0032] Figure 5 A schematic diagram of a cross-sectional structure of a structure obtained after a first semiconductor layer is formed on a bottom surface of a first trench and a top surface of a strip structure along a second direction in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0033] Figure 6 A graph showing epitaxial growth rates of SiGe on different crystal planes in some embodiments of the present disclosure;

[0034] Figure 7 A schematic diagram of a cross-sectional structure of a structure obtained after growing an initial second semiconductor layer in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0035] Figure 8 A graph showing epitaxial growth rates of Si on different crystal planes in some embodiments of the present disclosure;

[0036] Fig. 9 A schematic diagram of a cross-sectional structure of a structure obtained after alternately forming multiple first semiconductor layers and multiple second semiconductor layers in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0037] Fig.10 It is a schematic diagram of the cross-sectional structure of a structure obtained after forming a second trench in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0038] Fig.11 A schematic diagram of a cross-sectional structure of a structure obtained after forming a support structure in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0039] Fig.12 A schematic diagram of a cross-sectional structure of a structure obtained after forming a semiconductor column in a method for preparing a semiconductor structure in some embodiments of the present disclosure;

[0040] Fig.13 It is a schematic diagram of the cross-sectional structure of a structure obtained after forming a capacitor in a method for preparing a semiconductor structure in some embodiments of the present disclosure.

[0041] Description of reference numerals:

[0042] 1. substrate; 10. patterned photoresist layer; 11. strip structure; 21. first semiconductor layer; 21a. first semiconductor layer located above the first groove; 21b. first semiconductor layer located above the strip structure and adjacent to the first semiconductor layer in the third direction; 22. second semiconductor layer; 22'. initial second semiconductor layer; 22a. first semiconductor layer located above the first groove; 22b. second semiconductor layer located above the strip structure and adjacent to the second semiconductor layer in the third direction; 221. semiconductor column; 23. patterned mask layer; 23'. mask material layer; 3. support structure; 41. capacitor dielectric layer; 42. upper electrode; T1. first groove; T2. second groove. DETAILED DESCRIPTION

[0043] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0045] It should be understood that when an element or layer is referred to as being "above" or "adjacent to...", it may be directly above or adjacent to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first direction may be referred to as a second direction, and similarly, a second direction may be referred to as a first direction; the first direction and the second direction are different directions.

[0046] Spatial relationship terms such as "located above..." may be used here to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "located above..." will be oriented "below" other elements or features. Therefore, the exemplary term "located above..." can include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0047] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the features, integers, steps, operations, elements and / or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded.

[0048] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0049] At present, the integration density and storage performance of 3D structured semiconductor devices still need to be improved.

[0050] Based on this, the present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure, which can improve integration density and storage performance. The details will be described in the subsequent embodiments.

[0051] According to some embodiments, the present disclosure provides a method for preparing a semiconductor structure.

[0052] The preparation method provided in the embodiments of the present disclosure can be used, but is not limited to, for preparing various types of memories, such as DRAM.

[0053] See also Figure 1 In some embodiments, the method for preparing the semiconductor structure may specifically include the following steps:

[0054] S100: providing a substrate, forming a plurality of first grooves arranged at intervals in the substrate, and a strip structure located between adjacent first grooves; the first grooves extend along a first direction.

[0055] S200: Multiple layers of first semiconductor layers and multiple layers of second semiconductor layers are alternately formed along the second direction on the bottom surface of the first groove and the top surface of the strip structure respectively; the second direction intersects with the first direction; wherein the second semiconductor layers located above the first groove and having the same number of layers located above the strip structure and adjacent in the third direction are staggered in the second direction; the third direction intersects with the first direction and the second direction.

[0056] S300: forming a second trench penetrating each first semiconductor layer and each second semiconductor layer along a second direction; the second trench extends along the first direction, and an orthographic projection of the second trench on the substrate partially overlaps with the first trench and the strip structure.

[0057] S400: removing each first semiconductor layer in the target area along the second direction, and forming a support structure encapsulating each second semiconductor layer in the target area.

[0058] S500: removing each first semiconductor layer on one side of the support structure along the first direction, so that each exposed second semiconductor layer forms a plurality of semiconductor pillars arranged in parallel and spaced apart.

[0059] In the preparation method provided in the above embodiment, by forming a plurality of second semiconductor layers arranged at intervals in the second direction, forming a second groove penetrating the second semiconductor layer, and forming a support structure wrapping each second semiconductor layer, the plurality of second semiconductor layers arranged at intervals can form a plurality of semiconductor pillars arranged in parallel and at intervals, thereby forming a semiconductor structure with a three-dimensional structure, so as to facilitate the realization of three-dimensional storage, and solve the density limitation of the planar semiconductor structure in the related art. Therefore, the above preparation method can be applied to the preparation of a memory to improve the storage capacity of the obtained structure.

[0060] At the same time, in the preparation method provided in the above embodiment, the multiple first semiconductor layers and the multiple second semiconductor layers are alternately formed along the second direction, so after removing each first semiconductor layer, the second semiconductor layers adjacent in the third direction are dislocated in the second direction, so that the semiconductor pillars adjacent in the third direction can be dislocated in the second direction, which is beneficial to reduce the required spacing between adjacent semiconductor pillars in the second direction and reduce the occupied area of ​​the semiconductor structure. Therefore, the above preparation method can be applied to the preparation of memory to improve the integration density and storage performance of the obtained structure.

[0061] See also Figure 2 In some embodiments, in step S200, the second semiconductor layer is grown on the top surface of the first semiconductor layer along the second direction using an epitaxial process, which may specifically include the following steps:

[0062] S210: growing an initial second semiconductor layer along a second direction on an exposed surface of the first semiconductor layer using an epitaxial process.

[0063] S220: removing the initial second semiconductor layer on the sidewall of the first semiconductor layer along the second direction, and making the initial second semiconductor layer remaining on the top surface of the first semiconductor layer form the second semiconductor layer.

[0064] It should be understood that although Figure 1 to Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 to Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0065] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 3 to 13 Understand some embodiments of the present disclosure.

[0066] See also Figure 3 to Figure 4 In step S100 , a substrate 1 is provided. A plurality of first trenches T1 arranged at intervals are formed in the substrate 1 , and a strip structure 11 is located between adjacent first trenches T1 .

[0067] The first trench T1 extends along the first direction. That is, in the embodiment of the present disclosure, the extending direction of the first trench T1 is defined as the first direction.

[0068] The embodiment of the present disclosure does not specifically limit the method for forming the first trench T1 in the substrate 1. As an example, the following steps may be used to form a plurality of first trenches T1 arranged at intervals in the substrate 1, for example:

[0069] like Figure 3 As shown, a patterned photoresist layer 10 is formed on one side surface of the substrate 1 ; the patterned photoresist layer 10 has a first mask pattern P1 , and the first mask pattern P1 can be used to define the position and shape of the first trench T1 .

[0070] like Figure 4 As shown, a photolithography (PH) and etching (ET) process is performed on the substrate 1 based on the patterned photoresist layer 10 to transfer the first mask pattern P1 into the substrate 1 to form a first trench T1.

[0071] It is understood that after obtaining the first trench T1 and the strip structure 11, the preparation method may further include a step of removing the patterned photoresist layer 10. As an example, the patterned photoresist layer 10 may be removed by wet cleaning or vapor etching.

[0072] See also Figures 5 to 9 In step S200, multiple layers of first semiconductor layers 21 and multiple layers of second semiconductor layers 22 are alternately formed along the second direction on the bottom surface of the first trench T1 and the top surface of the strip structure 11. The second semiconductor layers 22 located above the first trench T1 and having the same number of layers and located above the strip structure 11 and adjacent in the third direction are staggered in the second direction.

[0073] It should be noted that, in the embodiment of the present disclosure, the first direction, the second direction and the third direction intersect with each other. For ease of understanding, the following description is made by taking the second direction being perpendicular to the upper surface of the substrate 1 (e.g., the Z direction) and the third direction being parallel to the upper surface of the substrate 1 and intersecting with the first direction (e.g., the X direction) as an example.

[0074] As an example, Fig. 9 As shown, the first second semiconductor layer 22a located above the first trench T1 is offset in the second direction (eg, Z direction) from the first second semiconductor layer 22b located above the strip structure 11 and adjacent thereto in the third direction (eg, X direction).

[0075] It can be understood that the number of first semiconductor layers 21 and second semiconductor layers 22 stacked on the bottom surface of the first trench T1 and the top surface of the strip structure 11 can be adaptively set according to the requirements of the actual embodiment, and the present disclosure has no specific limitation on this.

[0076] In some embodiments, the first semiconductor layers 21 located above the first trench T1 and the first semiconductor layers 21 with the same number of layers located above the strip structures 11 and adjacent in the third direction (eg, the X direction) have the same growth thickness.

[0077] As an example, the first semiconductor layer 21 a located above the first trench T1 has the same growth thickness as the first semiconductor layer 21 b located above the strip structure 11 and adjacent thereto in the third direction (eg, X direction).

[0078] In some embodiments, the second semiconductor layers 22 located above the first trench T1 and the second semiconductor layers 22 with the same number of layers located above the strip structures 11 and adjacent in the third direction (eg, X direction) have the same growth thickness.

[0079] As an example, the first second semiconductor layer 22 a located above the first trench T1 has the same growth thickness as the first second semiconductor layer 22 b located above the strip structure 11 and adjacent thereto in the third direction (eg, X direction).

[0080] The present disclosure does not specifically limit the constituent material of the first semiconductor layer 21. As an example, the constituent material of the first semiconductor layer 21 may include but is not limited to silicon germanium (SiGe).

[0081] The present disclosure also does not specifically limit the constituent material of the second semiconductor layer 22. As an example, the constituent material of the second semiconductor layer 22 may include but is not limited to silicon (Si).

[0082] In some embodiments, the first semiconductor layer 21 and the second semiconductor layer 22 are respectively grown along the second direction (eg, the Z direction) by using an epitaxy (EPI) process.

[0083] Taking the first semiconductor layer 21 as an example in which the constituent material includes SiGe, the first semiconductor layer 21 can be formed by epitaxial growth in the following manner, for example: using germanium hydride (Ge2H2) gas, hydrogen (H2) and dichlorosilane (SiH2Cl2) to react at a suitable temperature and pressure to generate SiGe, and the generated SiGe is used as the first semiconductor layer 21.

[0084] During the epitaxial growth process, the temperature of the reaction chamber or the reaction area can be maintained between 700°C and 800°C to achieve an appropriate reaction rate; for example, during the epitaxial growth process, the temperature of the reaction chamber or the reaction area can be maintained at 700°C, 725°C, 750°C, 775°C or 800°C, etc.

[0085] During the epitaxial growth process, the gas pressure in the reaction chamber can be maintained at a level of 10 Torr to 50 Torr to control the reaction rate and gas diffusion; for example, the gas pressure in the reaction chamber during the epitaxial growth process can be 10 Torr, 20 Torr, 30 Torr, 40 Torr or 30 Torr, etc.

[0086] During the epitaxial growth process, the flow ratio of Ge2H2 and H2 can be 0.00045-0.00055; for example, the flow ratio of Ge2H2 and H2 can be 0.00045, 0.00048, 0.0005 or 0.00055, etc., to control the growth rate and quality of SiGe.

[0087] Taking the second semiconductor layer 22 as an example, the second semiconductor layer 22 can be formed by epitaxial growth in the following manner, for example: using dichlorosilane gas and hydrogen (H2) to react at a suitable temperature and pressure to generate Si, and the generated Si is used as the second semiconductor layer 22.

[0088] During the epitaxial growth process, the temperature of the reaction chamber or the reaction area can be maintained between 700°C and 800°C to achieve an appropriate reaction rate; for example, during the epitaxial growth process, the temperature of the reaction chamber or the reaction area can be maintained at 700°C, 725°C, 750°C, 775°C or 800°C, etc.

[0089] During the epitaxial growth process, the gas pressure in the reaction chamber can be maintained at a level of 10 Torr to 50 Torr to control the reaction rate and gas diffusion; for example, the gas pressure in the reaction chamber during the epitaxial growth process can be 10 Torr, 20 Torr, 30 Torr, 40 Torr or 30 Torr, etc.

[0090] During the epitaxial growth process, the flow ratio of SiH2Cl2 and H2 can be 0.005-0.02; for example, the flow ratio of SiH2Cl2 and H2 can be 0.005, 0.01, 0.015 or 0.02, etc., to control the growth rate and quality of Si.

[0091] The following describes some embodiments of the present disclosure in which a first semiconductor layer 21 (eg, a first semiconductor layer 21 ) is formed on the bottom surface of the first trench T1 and the top surface of the strip structure 11 along the second direction (eg, the Z direction). Figure 5 The process of the first semiconductor layer 21a) shown in FIG. 1 is further explained.

[0092] In some embodiments, the top surface of the first semiconductor layer 21 parallel to the bottom surface of the first trench T1 is formed as a (100) crystal plane; meanwhile, the sidewall of the first semiconductor layer 21 parallel to the second direction (eg, Z direction) is formed as a (110) crystal plane.

[0093] For example, the constituent material of the first semiconductor layer 21 includes SiGe, the temperature T of the reaction chamber or the reaction area during the SiGe epitaxial growth process is 700° C., and the gas pressure P in the reaction chamber is 20 Torr. Figure 6As shown, the growth rate of SiGe (SiGegrowth rate) is positively correlated with the flow ratio F(Ge2H2) / F(H2) of Ge2H2 and H2, and the growth rate of SiGe on the (100) crystal plane is greater than its growth rate on the (110) crystal plane. Based on this, in the preparation method provided in the above embodiment, since the top surface of the first semiconductor layer 21 parallel to the bottom surface of the first trench T1 is formed as the (100) crystal plane, and the side wall of the first semiconductor layer 21 parallel to the second direction (for example, the Z direction) is formed as the (110) crystal plane, in the process of preparing the first semiconductor layer 21, the growth rate of the first semiconductor layer 21 in the thickness direction (that is, the second direction described in the embodiment of the present disclosure) is greater than its growth rate in the plane direction (that is, the direction parallel to the substrate 1 in the embodiment of the present disclosure). For example, the difference between the growth rate of SiGe on the (100) crystal plane and the growth rate of SiGe on the (110) crystal plane can reach 1.7nm / min. Therefore, the first semiconductor layer 21 formed on the bottom surface of the first trench T1 and the top surface of the strip structure 11 is thicker, and the first semiconductor layer 21 formed on the side wall of the first trench T1 and the side wall of the strip structure 11 is thinner. This is beneficial for retaining the first semiconductor layer 21 formed on the bottom surface of the first trench T1 and the top surface of the strip structure 11 during the subsequent etching process, ensuring that the first semiconductor layer 21 can accurately grow along the second direction (for example, the Z direction).

[0094] It can be understood that in the embodiment of the present disclosure, the flow ratio of SiH2Cl2 and H2 during the epitaxial growth process can be adjusted to make the growth rate of the first semiconductor layer 21 on the (100) crystal plane have a larger difference from the growth rate of the first semiconductor layer 21 on the (110) crystal plane, so as to facilitate the first semiconductor layer 21 to grow more accurately along the second direction (for example, the Z direction) to form a better morphology.

[0095] The following further describes the process of growing the second semiconductor layer 22 along the second direction (for example, the Z direction) on the top surface of the first semiconductor layer 21 using an epitaxial process in some embodiments of the present disclosure.

[0096] In some embodiments, the process of growing the second semiconductor layer 22 along the second direction (eg, the Z direction) on the top surface of the first semiconductor layer 21 by using an epitaxial process can be specifically performed as follows: steps S210 - S220 .

[0097] In step S210, Figure 7 As shown, an initial second semiconductor layer 22 ′ is grown along a second direction (eg, Z direction) on the exposed surface of the first semiconductor layer 21 by using an epitaxial process.

[0098] In step S220, Fig. 9As shown, the initial second semiconductor layer 22 ′ on the sidewall of the first semiconductor layer 21 along the second direction (eg, the Z direction) is removed, and the initial second semiconductor layer 22 ′ remaining on the top surface of the first semiconductor layer 21 forms the second semiconductor layer 22 .

[0099] In some embodiments of the present disclosure, the first semiconductor layer 21 (for example Figure 7 The top surface of the first semiconductor layer 21a) shown in FIG. 1 forms a first second semiconductor layer 22 (eg Fig. 9 The process of forming the second semiconductor layer 22a) shown in FIG. 1 is further described.

[0100] In some embodiments, the top surface of the second semiconductor layer 22 parallel to the bottom surface of the first trench T1 is also formed as a (100) crystal plane; meanwhile, the sidewall of the second semiconductor layer 22 parallel to the second direction (eg, Z direction) is also formed as a (110) crystal plane.

[0101] For example, the constituent material of the second semiconductor layer 22 includes Si, and the temperature T of the reaction chamber or reaction area during the Si epitaxial growth process is 750° C. Figure 8 As shown, the growth rate of Si (Si growth rate) is positively correlated with the flow ratio F(SiH2Cl2) / F(H2) of SiH2Cl2 and H2, and when the growth rate of Si on the (100) crystal plane is greater than its growth rate on the (110) crystal plane. Based on this, in the preparation method provided in the above embodiment, since the top surface of the second semiconductor layer 22 parallel to the bottom surface of the first trench T1 is formed as the (100) crystal plane, and the side wall of the second semiconductor layer 22 parallel to the second direction (for example, the Z direction) is formed as the (110) crystal plane, in the process of preparing the first layer of the second semiconductor layer 22, the growth rate of the second semiconductor layer 22 in the thickness direction (that is, the second direction described in the embodiment of the present disclosure) is greater than its growth rate in the plane direction (that is, the direction parallel to the substrate 1 in the embodiment of the present disclosure). For example, the difference between the growth rate of Si on the (100) crystal plane and the growth rate of Si on the (110) crystal plane can reach 28nm / min. Therefore, the second semiconductor layer 22 formed on the top surface of the first semiconductor layer 21 is thicker, while the second semiconductor layer 22 formed on the side wall of the first semiconductor layer 21 is thinner. This is beneficial for retaining the second semiconductor layer 22 formed on the top surface of the first semiconductor layer 21 during the subsequent etching process, ensuring that the second semiconductor layer 22 can accurately grow along the second direction (for example, the Z direction).

[0102] It can be understood that in the embodiment of the present disclosure, the flow ratio of SiH2Cl2 and H2 during the epitaxial growth process can be adjusted to make the growth rate of the second semiconductor layer 22 on the (100) crystal plane have a larger difference from the growth rate of the second semiconductor layer 22 on the (110) crystal plane, so as to facilitate the second semiconductor layer 22 to grow more accurately along the second direction (for example, the Z direction) to form a better morphology.

[0103] Please continue reading Figure 5 In some embodiments, a thickness h1 of the first semiconductor layer 21 in the second direction (eg, the Z direction) is greater than a depth h2 of the first trench T1.

[0104] Please continue reading Figure 5 In some embodiments, the thickness h1 of the first semiconductor layer 21 in the second direction (eg, the Z direction) is equal to the distance a between adjacent first trenches T1. times.

[0105] It can be understood that the thickness h1 of the first semiconductor layer 21 in the second direction (for example, the Z direction) can be used to define the spacing between the second semiconductor layers 22 corresponding to the same first semiconductor layer 21 and adjacent in the second direction (for example, the Z direction), and the spacing a between adjacent first trenches T1 can be used to define the spacing between the second semiconductor layers 22 located at the same height and adjacent in the third direction (for example, the X direction). In the preparation method provided in the above embodiment, the thickness h1 of the first semiconductor layer 21 in the second direction (for example, the Z direction) is formed to be 1 / 2 of the spacing a between adjacent first trenches T1. times, so that the spacing between the second semiconductor layers 22 corresponding to the same first semiconductor layer 21 and adjacent in the second direction (for example, the Z direction) can be formed to be the spacing between the second semiconductor layers 22 located at the same height and adjacent in the third direction (for example, the X direction). times, so that the second semiconductor layer 22 can form a honeycomb arrangement in the direction perpendicular to the substrate 1, which is beneficial to reducing the distance between adjacent second semiconductor layers 22, increasing the arrangement density of the second semiconductor layer 22, and further improving the integration density of the semiconductor structure obtained by the preparation method.

[0106] Please continue reading Figure 5 In some embodiments, the depth h2 of the first trench T1 is equal to the distance a between adjacent first trenches T1. times.

[0107] In some embodiments, the thickness h3 of the second semiconductor layer 22 is ½ of the interval a between adjacent first trenches T1 .

[0108] In some embodiments, after forming the multi-layer first semiconductor layer 21 and the multi-layer second semiconductor layer 22 in step S200 and before step S300, the top surface of the obtained structure may be subjected to a surface planarization process. This is beneficial for forming the obtained structure into a better flat state, thereby improving the production yield of the preparation method.

[0109] See also Figures 9 and 10 In step S300, a second trench T2 is formed along a second direction (for example, the Z direction) penetrating each first semiconductor layer 21 and each second semiconductor layer 22. The second trench T2 extends along the first direction, and the orthographic projection of the second trench T2 on the substrate 1 partially overlaps with the first trench T1 and the strip structure 11.

[0110] The embodiment of the present disclosure does not specifically limit the method for forming the second trench T2 in step S300. As an example, the second trench T2 penetrating each first semiconductor layer 21 and each second semiconductor layer 22 along the second direction (for example, the Z direction) may be formed by the following steps, for example:

[0111] like Fig. 9 As shown, a mask material layer 23 ′ is formed on the top surface of the structure obtained in step S200 .

[0112] like Fig.10 As shown, a second mask pattern P2 is formed in the mask material layer 23 ′. The second mask pattern P2 can be used to define the position and shape of the second trench T2 . The remaining mask material layer 23 ′ serves as the patterned mask layer 23 .

[0113] like Fig.10 As shown, a photolithography process is performed on each first semiconductor layer 21 and each second semiconductor layer 22 along a second direction (for example, the Z direction) based on the patterned mask layer 23 to form a second trench T2 that penetrates each first semiconductor layer 21 and each second semiconductor layer 22 along the second direction (for example, the Z direction).

[0114] It can be understood that after obtaining the second trench T2, the preparation method may further include a step of removing the patterned mask layer 23. As an example, the patterned mask layer 23 may be removed by wet cleaning or steam etching.

[0115] In some embodiments, the bottom surface of the second trench T2 is located above the bottom surface of the first trench T1, and the distance d from the bottom surface of the second trench T2 to the bottom surface of the first trench T1 is greater than or equal to 1 / 2 of the depth h2 of the first trench T1. In this way, after the second trench T2 is formed, it can be ensured that each second semiconductor layer 22 closest to the substrate 1 is completely isolated from the strip structure 11.

[0116] See also Fig.11In step S400 , each first semiconductor layer 21 in the target area is removed along a second direction (eg, Z direction), and a support structure 3 wrapping each second semiconductor layer 22 is formed in the target area.

[0117] It should be noted that for the sake of illustration, Fig.11 The substrate 1 is omitted.

[0118] For ease of understanding, the following takes the first direction as Fig.11 The Y direction shown in FIG. 1 is used as an example for explanation.

[0119] Please continue reading Figure 11 to Figure 12 In step S500, the first semiconductor layers 21 on one side of the support structure 3 along the first direction (eg, the Y direction) are removed so that the exposed second semiconductor layers 22 form a plurality of semiconductor pillars 221 that are arranged in parallel and spaced apart.

[0120] It should be noted that Fig.12 The resulting structure is shown in Fig.11 Schematic diagram of the cross-sectional structure along the aa' direction.

[0121] The embodiment of the present disclosure does not specifically limit the method of removing the first semiconductor layer 21 in step S500. As an example, each first semiconductor layer 21 on one side of the support structure 3 along the first direction (for example, the Y direction) can be removed by wet etching (Wet Etch) or dry etching (Dry Etch).

[0122] It can be understood that when the first semiconductor layer 21 is removed by wet etching, an etching solution with a high selectivity ratio for the first semiconductor layer 21 and the second semiconductor layer 22 can be used to complete the wet etching process. In this way, different etching rates can be achieved for the first semiconductor layer 21 and the second semiconductor layer 22 during the wet etching process, so that when the first semiconductor layer 21 is removed by wet etching, the second semiconductor layer 22 will not be affected, which is conducive to improving the production yield of the preparation method.

[0123] The dry etching process may be, for example, steam etching. Steam etching can be used to remove the first semiconductor layer 21 through a gas chemical reaction. Compared with other dry etching processes (e.g., plasma etching), steam etching does not generate plasma during the process, which is beneficial to avoid irreversible changes or damages (also called film damage) to the structure, performance and / or surface quality of the second semiconductor layer 22 during the etching process, thereby reducing the risk of increased lattice defects, stress accumulation and interface roughness of the resulting structure due to film damage.

[0124] Taking the example that the constituent material of the first semiconductor layer 21 includes SiGe and the constituent material of the second semiconductor layer 22 includes Si, the first semiconductor layer 21 can be removed in the following manner, for example: using hydrogen chloride (HCl) gas and hydrogen to react with SiGe at a suitable temperature and pressure to remove SiGe.

[0125] During the SiGe removal process, the temperature of the reaction chamber or reaction area can be maintained between 700°C and 800°C to achieve an appropriate reaction rate; for example, during the SiGe removal process, the temperature of the reaction chamber or reaction area can be maintained at 700°C, 725°C, 750°C, 775°C or 800°C, etc.

[0126] During the SiGe removal process, the gas pressure in the reaction chamber can be maintained at a level of 10 Torr to 50 Torr to control the reaction rate and gas diffusion; for example, during the SiGe removal process, the gas pressure in the reaction chamber can be 10 Torr, 20 Torr, 30 Torr, 40 Torr or 30 Torr, etc.

[0127] During the SiGe removal process, the flow ratio of HCl to H2 may be 0.0002 to 0.00035; for example, the flow ratio of HCl to H2 may be 0.0002, 0.00025, 0.0003 or 0.00035, etc., to control the SiGe removal rate.

[0128] The manufacturing method provided in the embodiment of the present disclosure can be applied to the manufacturing process of a memory, for example, to the manufacturing process of a DRAM, wherein the capacitor can be used to constitute the part of the memory for storing data.

[0129] Based on this, see Fig.13 In some embodiments, the capacitor in the memory may be prepared by the following steps, for example:

[0130] The semiconductor structure is manufactured by the manufacturing method provided in the above embodiment; wherein the semiconductor pillar 221 manufactured in step S500 by the manufacturing method is used as the lower electrode of the capacitor.

[0131] A capacitor dielectric layer 41 is formed on the surface of the semiconductor column 221 parallel to the substrate 1, and an upper electrode 42 is formed on the surface of the capacitor dielectric layer 41 parallel to the substrate 1. The semiconductor column 221 (lower electrode), the capacitor dielectric layer 41 and the upper electrode 42 can together form a capacitor.

[0132] As an example, the semiconductor column 221 may be subjected to metal silicide treatment, and the semiconductor column 221 after the metal silicide treatment serves as the lower electrode of the capacitor.

[0133] The disclosed embodiment does not specifically limit the manner of forming the capacitor dielectric layer 41 on the surface of the semiconductor column 221 and the upper electrode 42 on the surface of the capacitor dielectric layer 41. As an example, a deposition (Deposition, Dep for short) process may be used to form the capacitor dielectric layer 41 on the surface of the semiconductor column 221 and the upper electrode 42 on the surface of the capacitor dielectric layer 41. The deposition process may be, for example, an atomic layer deposition (Atomic Layer Deposition, ALD for short) process.

[0134] The present embodiment of the disclosure does not specifically limit the constituent material of the capacitor dielectric layer 41. As an example, the constituent material of the capacitor dielectric layer 41 may include, but is not limited to, aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxide (SiO2), zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof. The present embodiment of the disclosure does not specifically limit the constituent material of the upper electrode 42. As an example, the constituent material of the upper electrode 42 may include, but is not limited to, titanium (Ti), titanium nitride (TiN) or tungsten (W).

[0135] Based on this, in some embodiments, the spacing a between adjacent first trenches T1 formed in the preparation method provided by the embodiment of the present disclosure can be set according to the requirements for the spacing between adjacent capacitors in the preparation process of the memory, so as to maximize the capacitor arrangement density. The required spacing between adjacent capacitors refers to: the spacing a' between the geometric centers of adjacent capacitors in the direction perpendicular to the substrate 1, such as Fig.13 shown.

[0136] As an example, combine Figure 4 and Fig.13 It is understood that the spacing a between adjacent first trenches T1 may be 1 / 2 of the spacing a′ required between adjacent capacitors.

[0137] As an example, combine Figure 4 and Fig.13 It is understood that the depth h2 of the first trench T1 can be a desired spacing a' between adjacent capacitors.

[0138] As an example, combine Figures 5 to 13 It is understood that the thickness h1 of the first semiconductor layer 21 in the second direction (eg, the Z direction) may be 1 / 100 of the required spacing a' between adjacent capacitors. times.

[0139] Since in step S200, the multiple layers of first semiconductor layers 21 and the multiple layers of second semiconductor layers 22 are alternately stacked, the thickness h1 of the first semiconductor layer 21 in the second direction (for example, the Z direction) is the spacing of the second semiconductor layer 22 in the second direction (for example, the Z direction). The semiconductor pillars 221 are composed of the second semiconductor layer 22, so the spacing of the semiconductor pillars 221 in the second direction (for example, the Z direction) is the spacing of the second semiconductor layer 22 in the second direction (for example, the Z direction); that is, the spacing of the semiconductor pillars 221 in the second direction (for example, the Z direction) can be determined according to the thickness h1 of the first semiconductor layer 21 in the second direction (for example, the Z direction). The thickness h1 of the first semiconductor layer 21 in the second direction (for example, the Z direction) is 1 / 4 of the spacing a' required between adjacent capacitors. times, the spacing of the semiconductor pillars 221 prepared in step S500 in the second direction (for example, the Z direction) can be 1 / 4 of the spacing a' required between adjacent capacitors. In this way, the semiconductor pillars 221 can be arranged in a honeycomb shape in a direction perpendicular to the substrate 1, and the capacitors formed by the semiconductor pillars 221 can also be arranged in a honeycomb shape, reducing the distance between adjacent capacitors to maximize the capacitor arrangement density in the memory.

[0140] As an example, combine Fig. 9 and Fig.13 It is understood that the thickness h3 of the second semiconductor layer 22 may be ¼ of the required spacing a′ between adjacent capacitors.

[0141] According to some embodiments, the present disclosure also provides a semiconductor structure. The semiconductor structure is prepared by a method for preparing a semiconductor structure provided by any of the above embodiments. Therefore, the semiconductor structure can also achieve the technical effects that can be achieved by the above preparation method, which will not be described in detail here.

[0142] Furthermore, the methods for preparing semiconductor structures provided in the embodiments of the present disclosure can all be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that those skilled in the art can understand the technical content of the present disclosure.

[0143] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that include: Providing a substrate, forming a plurality of first grooves arranged at intervals in the substrate, and a strip structure located between adjacent first grooves; The first groove extends along a first direction; Alternatingly forming multiple first semiconductor layers and multiple second semiconductor layers along a second direction on the bottom surface of the first trench and the top surface of the strip structure; The second direction intersects with the first direction; wherein the second semiconductor layers located above the first trench and having the same number of layers located above the strip structure and adjacent in the third direction are staggered in the second direction; the third direction intersects with the first direction and the second direction; forming a second groove penetrating each of the first semiconductor layers and each of the second semiconductor layers along the second direction; the second groove extends along the first direction, and the orthographic projection of the second groove on the substrate partially overlaps with the first groove and the strip structure; removing each of the first semiconductor layers in a target area along the second direction, and forming a support structure wrapping each of the second semiconductor layers in the target area; The first semiconductor layers on one side of the support structure along the first direction are removed, so that the exposed second semiconductor layers form a plurality of semiconductor pillars arranged in parallel and at intervals.

2. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The first semiconductor layer and the second semiconductor layer are respectively grown along the second direction by using an epitaxial process; The first semiconductor layer is made of silicon germanium; the second semiconductor layer is made of silicon.

3. The method for preparing a semiconductor structure according to claim 2, It is characterized in that The top surfaces of the first semiconductor layer and the second semiconductor layer parallel to the bottom surface of the first trench are (100) crystal planes; the side walls of the first semiconductor layer and the second semiconductor layer parallel to the second direction are (110) crystal planes.

4. The method for preparing a semiconductor structure according to claim 2, It is characterized in that The first semiconductor layers located above the first trench and the first semiconductor layers with the same number of layers located above the strip structures and adjacent to each other in the third direction have the same growth thickness; The second semiconductor layers located above the first trench and having the same number of layers located above the strip structures and adjacent to each other in the third direction have the same growth thickness.

5. The method for preparing a semiconductor structure according to claim 2, It is characterized in that Growing the second semiconductor layer along the second direction by using an epitaxial process on the top surface of the first semiconductor layer, comprising: Using an epitaxial process, growing an initial second semiconductor layer along the second direction on the exposed surface of the first semiconductor layer; The initial second semiconductor layer on the side wall of the first semiconductor layer along the second direction is removed, and the initial second semiconductor layer remaining on the top surface of the first semiconductor layer constitutes the second semiconductor layer.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that A thickness of the first semiconductor layer in the second direction is greater than a depth of the first trench.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The thickness of the first semiconductor layer is 2√3 times the distance between adjacent first trenches.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The depth of the first trench is √3 times the distance between adjacent first trenches; the thickness of the second semiconductor layer is 1 / 2 of the distance between adjacent first trenches.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The bottom surface of the second groove is located above the bottom surface of the first groove, and the distance from the bottom surface of the second groove to the bottom surface of the first groove is greater than or equal to 1 / 2 of the depth of the first groove.

10. A semiconductor structure, It is characterized in that The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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