A method for manufacturing a semiconductor memory
By forming a bitline material layer on the first region of the substrate and the shallow trench isolation structure and removing part of the capping layer, the bitline structure tilting problem is solved, and the performance of the semiconductor device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-08-02
- Publication Date
- 2026-06-23
AI Technical Summary
As the height of three-dimensional semiconductor memories increases, the bit line structure, especially the portion near the peripheral region, often experiences tilting problems.
A bitline material layer is formed on the first region of the substrate and the shallow trench isolation structure, and a portion of the first capping layer is removed from the shallow trench isolation structure to form a groove. Then, a second capping layer is formed on the bitline material layer to reduce the height of the bitline structure and prevent it from tipping over.
By reducing the height of the bitline structure, tipping is avoided, thus improving the performance of semiconductor devices.
Smart Images
Figure CN119173033B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor memory. Background Technology
[0002] Dynamic random access memory (DRAM) is a type of volatile memory, comprising an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage and release of charge in the capacitor to store data. The control circuitry addresses each memory cell and controls data access to that cell via word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.
[0003] To reduce the size of memory cells and manufacture chips with higher density, memory cell structures have evolved towards three-dimensional designs, such as using buried word lines and stacked capacitors. Stacked capacitors are vertically positioned above the substrate, thereby saving substrate area occupied by the capacitors and allowing for larger capacitances by easily increasing the electrode height. However, with increased height, the bit line structure, especially the portion near the peripheral region, often experiences tilting. Summary of the Invention
[0004] The purpose of this invention is to provide a method for fabricating a semiconductor memory that can solve the problem in the prior art where the bit line structure, especially the portion near the periphery (near the edge of the first region), often tilts as the height increases.
[0005] To address the above problems, the present invention provides a method for fabricating a semiconductor memory, which may include at least:
[0006] A substrate is provided, the substrate comprising a first region and a second region;
[0007] A shallow trench isolation structure is formed in the substrate, located between the first region and the second region, the shallow trench isolation structure defining the first region and the second region;
[0008] A bit line material layer is formed on the first region of the substrate and the shallow trench isolation structure, and the bit line material layer includes a semiconductor layer, a metal layer and a first capping layer from bottom to top;
[0009] Remove a portion of the first capping layer of the bitline material layer located on the shallow trench isolation structure to form a groove;
[0010] A second capping layer is formed on the remaining bitline material layer.
[0011] In some optional examples, forming the bit line material layer further includes forming the bit line material layer in a second region of the substrate to form a gate structure.
[0012] In some optional examples, after forming the gate structure located on the second region of the substrate, the method further includes:
[0013] An etch barrier layer is formed on the bit line material layer in the first region of the substrate and the shallow trench isolation structure, as well as on the gate structure in the second region of the substrate.
[0014] In some optional examples, after forming the etch barrier layer, the following steps are also included:
[0015] An insulating dielectric layer is formed on the second region of the substrate and the etch barrier layer on the shallow trench isolation structure, and a portion of the insulating dielectric layer in the second region of the substrate buries the gate structure.
[0016] In some optional examples, after forming the insulating dielectric layer, the following steps are also included:
[0017] A photoresist layer is formed on the first region and part of the shallow trench isolation structure and on the gate structure of the second region of the substrate.
[0018] In some optional examples, the step of forming the groove includes:
[0019] Remove all of the first capping layers on the shallow trench isolation structure that are not covered by the photoresist layer to form a groove with the bottom exposed below the metal layer located on the shallow trench isolation structure.
[0020] In some optional examples, the step of forming the groove includes:
[0021] The portion of the first capping layer not covered by the photoresist layer on the shallow trench isolation structure is removed to form a groove at the bottom of which the remaining first capping layer on the shallow trench isolation structure is exposed, and the upper surface of the exposed remaining first capping layer has an arc shape that is concave towards the surface of the substrate.
[0022] In some alternative examples, after the groove is formed, the sidewalls of the remaining bit line material layer are stepped in a descending manner in the horizontal direction from the first region of the substrate to the shallow trench isolation structure.
[0023] In some alternative examples, after the groove is formed, the sidewalls of the remaining bit line material layer form a gradually decreasing slope in the horizontal direction from the first region of the substrate to the shallow trench isolation structure.
[0024] In some optional examples, the step of forming the groove further includes:
[0025] Remove the etching barrier layer.
[0026] In some alternative examples, the distance between the upper and lower surfaces of the second capping layer located on the first region of the substrate is less than the distance between the upper and lower surfaces of the second capping layer located on the shallow trench isolation structure.
[0027] In some alternative examples, the distance between the upper and lower surfaces of the second capping layer on the shallow trench isolation structure is greater than the distance between the upper and lower surfaces of the second capping layer on the gate structure in the second region of the substrate.
[0028] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:
[0029] In the semiconductor memory fabrication method provided by this invention, a bit line material layer including a first capping layer is first formed on a first region of the substrate and a shallow trench isolation structure. A gate structure is formed in a second region of the substrate. Then, a portion of the first capping layer of the bit line material layer located on the shallow trench isolation structure is removed so that the top surface of the bit line material layer on the shallow trench isolation structure between the first and second regions of the substrate is lower than the top surface of the bit line material layer in the first and second regions (manifested by a groove). Afterward, a second capping layer is formed in a conformal manner on the first region and the shallow trench isolation structure with the groove. This ensures that the height of the bit line structure in the first region meets the product design requirements while reducing the height of the bit line structure formed on the shallow trench isolation structure near the edge of the first region, preventing the bit line structure formed on the shallow trench isolation structure from tilting and improving the performance of the semiconductor device. Attached Figure Description
[0030] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0031] Figure 1This is a schematic flowchart of a method for fabricating a semiconductor memory according to an embodiment of the present invention;
[0032] Figures 2-8 This is a schematic diagram of the structure during the fabrication process of the semiconductor memory fabrication method provided in one embodiment of the present invention;
[0033] The attached figures are labeled as follows:
[0034] 100 - Substrate, 101 - Shallow trench isolation structure, 11 - First region of the substrate, 12 - Second region of the substrate, 251 - Gate structure in the second region, 110 - Word line structure, 120 - Insulating layer, 130 - Bit line material layer, 131 - Semiconductor layer, 132 - Metal layer, 133 - Interlayer dielectric layer, 134 - First capping layer, 102 - Trench, 141 - Sidewall structure, 140 - Etching barrier layer, 150 - Insulating dielectric layer, 160 - Photoresist layer, 170 - Second capping layer.
[0035] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0036] The method for manufacturing the semiconductor device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.
[0037] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the fabrication method of the semiconductor memory provided in this embodiment. Figure 1 As shown, the semiconductor memory fabrication method provided in this embodiment includes at least the following steps:
[0038] Step S101: Provide a substrate, the substrate including a first region and a second region.
[0039] Step S102: A shallow trench isolation structure is formed in the substrate between the first region and the second region, the shallow trench isolation structure defining the first region and the second region.
[0040] Step S103: A bit line material layer is formed on the first region of the substrate and the shallow trench isolation structure. The bit line material layer includes a semiconductor layer, a metal layer and a first capping layer from bottom to top.
[0041] Step S104: Remove a portion of the first capping layer of the bitline material layer located on the shallow trench isolation structure to form a groove.
[0042] Step S105: A second capping layer is formed on the remaining bit line material layer.
[0043] In order to enable those skilled in the art to easily understand the semiconductor device fabrication method in the embodiments of the present invention, the following will further explain the semiconductor device fabrication method proposed in the present invention with reference to the various structural schematic diagrams in the fabrication process.
[0044] Figures 2-8 This is a schematic diagram of the semiconductor memory fabrication method provided in this embodiment of the invention during the fabrication process.
[0045] Please see Figure 2 Performing steps S101 to S102 above, a substrate 100 is provided. The substrate 100 includes a plurality of shallow trench isolation structures 101 arranged sequentially at intervals. One of the shallow trench isolation structures 101 has a wider width than the other shallow trench isolation structures 101 and is located on one side of all the other shallow trench isolation structures. This shallow trench isolation structure 101 defines the substrate 100 as a first region 11 and a second region 12. The first region 11 of the substrate 100 includes a plurality of word line structures 110. An insulating layer 120 is formed on the entire surface of the first region 11 and the second region 12 of the substrate 100. In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate or a substrate made of other suitable materials, but is not limited thereto. The shallow trench isolation structure 101 may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, nitrogen-doped silicon carbide, low dielectric constant dielectric materials such as fluorosilicone glass, silicon carbide oxide, spin-coated silicon glass, porous low dielectric constant dielectric materials, or combinations of the above materials, but are not limited thereto. For example, the shallow trench isolation structure 101 is elongated. The substrate 100 also includes multiple word line structures 110. The word line structures 110 may include a gate dielectric layer, a work function layer, a conductive layer, and a capping layer, but are not limited thereto. The insulating layer 120 may be made of oxides or nitrides, but is not limited thereto.
[0046] Continue reading Figure 2Next, step S103 is performed, using deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition to form a bit line material layer 130 on the first region 11 of the substrate 100, part of the shallow trench isolation structure 101, and the insulating layer 120 of the second region 12. In one embodiment, the bit line material layer 130 is a multilayer material structure, such as the bit line material layer 130 including, from bottom to top, a semiconductor layer 131, a barrier layer 132, a metal layer 133, and a first capping layer 134. The material of the semiconductor layer 131 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The barrier layer 132 may be made of metal, metal silicide, or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), and tungsten nitride (WN), but is not limited thereto. The metal layer 133 may be made of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. The first capping layer 134 may be made of dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but is not limited thereto. Preferably, in this embodiment of the invention, the semiconductor layer 131 is made of polycrystalline silicon, the barrier layer 132 is made of titanium nitride (TiN), the metal layer 133 is made of tungsten (W), and the first capping layer 134 is made of silicon nitride (SiN).
[0047] It should be understood that the process of performing step S103 also includes etching away a portion of the bit line material layer 130 on the second region 12 of the substrate 100 using at least one of a dry etching process or a wet etching process to form at least one discrete gate structure 251 within the second region 12. Subsequently, sidewall structures 141 are formed on the sidewalls of the gate structure 251 and on the sidewalls of the bit line material layer 130 located on the shallow trench isolation structure 101. The sidewall structures 141 may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto.
[0048] Please see Figure 3Following step S103 above, the above deposition process can be used to form an etch barrier layer 140 and an insulating dielectric layer 150 on the bit line material layer 130 on the first region 11 of the substrate 100 and the shallow trench isolation structure 101, and on the gate structure 251 of the second region 12 of the substrate 100. Then, etching or chemical mechanical polishing processes are used to ensure that the insulating dielectric layer 150 is located only on the shallow trench isolation structure 101 and the second region 12 of the substrate 100. Specifically, the insulating dielectric layer 150 is located on the etch barrier layer 140 on the shallow trench isolation structure 101, and the gate structure 251 in the second region 12 of the substrate 100 is buried. In one embodiment, the materials of the etch barrier layer 140 and the insulating dielectric layer 150 may both include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), or combinations thereof, but are not limited thereto. Preferably, the material of the etch barrier layer 140 is silicon carbide (SiCN), and the material of the insulating dielectric layer 150 is silicon nitride (SiN).
[0049] Subsequently, a photoresist layer 160 is formed on the first region 11 of the substrate 100, a portion of the shallow trench isolation structure 101, and the gate structure 251 of the second region 12 of the substrate 100. The photoresist layer 160 has an opening, the bottom of which exposes a portion of the etch barrier layer 140 and the insulating dielectric layer 150 on the shallow trench isolation structure 101.
[0050] Please see Figure 4 and Figure 5 In step S104 above, at least one etching process, either dry or wet etching, can be used. Using the photoresist layer 160 as a mask, a portion of the first capping layer 134 of the etching barrier layer 140 and the bit line material layer 130 located on the shallow trench isolation structure 101 is etched away along the opening of the photoresist layer 160 to form a groove 102. Since the inventive concept of this invention is to make the top surface of the bit line material layer 130 on the shallow trench isolation structure 101 between the first region 11 and the second region 12 of the substrate 100 lower than the top surface of the bit line material layer 130 in the first region 11 and the second region 12, when forming the groove 102 using the etching process in step S104, a portion of the height of the first capping layer 134 can be removed along the opening; alternatively, the entire first capping layer 134 can be removed along the opening.
[0051] As a preferred example, such as Figure 4As shown, the etch barrier layer 140 not covered by the photoresist layer 160 (i.e. the opening) and all the first capping layers 134 on the shallow trench isolation structure 101 can be removed to form a groove 102 with the bottom exposed below the metal layer 133 located on the shallow trench isolation structure 101.
[0052] As another preferred example, such as Figure 5 As shown, the etch barrier layer 140 not covered by the photoresist layer 160 (i.e. the opening) and part of the first capping layer 134 on the shallow trench isolation structure 101 can be removed to form a groove 102 with the bottom exposed on the remaining first capping layer 134 on the shallow trench isolation structure 101. The upper surface of the exposed remaining first capping layer 134 has an arc shape that is recessed towards the surface of the substrate 100. The arc shape that is recessed towards the surface of the substrate 100 includes a slope that gradually decreases in the horizontal direction from the first region 11 of the substrate 100 to the shallow trench isolation structure 101.
[0053] It should be understood that, since the photoresist layer 160 is also formed simultaneously in the second region 12 of the substrate 100 during the etching process of forming the groove 102 in step S104 of the present invention, the etching process of step S104 will not cause any loss to the height of the gate structure 251 in the second region 12.
[0054] Please see Figure 6 or Figure 7 In step S104 above, at least one deposition process, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition, can be used to form the aforementioned... Figure 4 or Figure 5A second capping layer 170 is formed conformally on the substrate 100 of the groove 102 shown. The material of the second capping layer 170 is the same as that of the first capping layer 134 in the bit line material layer 130, such as silicon nitride (SiN). Since the bit line material layer 130 on the shallow trench isolation structure 101 in this embodiment has a groove 102, when the second capping layer 170 is formed conformally using a deposition process, the distance between the upper and lower surfaces of the second capping layer 170 located on the first region 11 of the substrate 100 is smaller than the distance between the upper and lower surfaces of the second capping layer 170 located on the shallow trench isolation structure 101, while the distance between the upper and lower surfaces of the second capping layer 170 located on the shallow trench isolation structure 101 is larger than the distance between the gate in the second region 12 of the substrate 100. The distance between the upper and lower surfaces of the second capping layer 170 on structure 251 is such that the top surface of the bitline structure, which is located in the first region 11 of the substrate 100 and consists of the second capping layer 170, the first capping layer 134, the metal layer 133, the barrier layer 132, and the semiconductor layer 131, is higher than the top surface of the bitline structure, which is located on the shallow trench isolation structure 101 adjacent to the first region 11 of the substrate 100 and consists of the second capping layer 170, the first capping layer 134 (which may not be present), the metal layer 133, the barrier layer 132, and the semiconductor layer 131, thus achieving the inventive objective of the present invention.
[0055] It should be understood that after performing step S104 to form the groove 102 and before performing step S105 to form the second capping layer 170, the embodiments of the present invention may also include the step of removing the photoresist layer 160 and the etching barrier layer 140 located below the photoresist layer 160 in the first region 11 and the second region 12 of the substrate 100, but are not limited thereto.
[0056] It should be understood that, as above Figures 2-7 In the illustrated embodiment, the top surface of the bit line material layer 130 in the first region 11 of the substrate 100 is flush with the top surface of the gate structure 251 in the second region 12 of the substrate 100. However, in other embodiments, those skilled in the art will readily recognize that before forming the bit line material layer 130 on the first region 11 of the substrate 100, a portion of the shallow trench isolation structure 101, and the insulating layer 120 of the second region 12 using a deposition process in step S103, the process may further include forming an ONO stack structure, such as an oxide layer, a nitride layer, and an oxide layer, on the first region 11 of the substrate 100 and a portion of the shallow trench isolation structure 101, while forming a single-layer material structure, such as silicon oxide, on the second region 12 of the substrate 100. Figure 8As shown, under this configuration, the height of the ONO stack structure is greater than that of the single-layer material structure, such that the top surface of the bit line material layer 130 formed on the first region 11 and the shallow trench isolation structure 101 of the substrate 100 is higher than the top surface of the gate structure 251 (formed by etching the bit line material layer) of the second region 12 of the substrate 100, i.e., the height difference is as follows. Figure 8 As shown in the diagram, D1. In subsequent processes, due to this height difference D1, the etch stop layer 140 located in the first region 11 will be etched away, while the etch stop layer 140 located in the second region 12 will remain, as shown in the diagram. Figure 6 As shown.
[0057] Subsequently, based on the bit line material layer 130 and gate structure 251 with a height difference D1, steps S104 to S105 as described above can be performed, namely, forming the etch barrier layer 140, the insulating dielectric layer 150, the photoresist layer 160, etching at least a portion of the first capping layer 134 to form the groove 102, and forming the second capping layer 170, as detailed above. Figures 3-7 Accordingly, the present invention will not repeat the description.
[0058] It should be understood that “conformal” formation in this article refers to the shape along the surface of the membrane layer. For example, “conformal” coverage means that one membrane layer is attached along the shape of the surface of another membrane layer, and the surface shapes of the two membrane layers are consistent.
[0059] In summary, in the semiconductor memory fabrication method provided by this invention, a bit line material layer including a first capping layer is first formed on a first region of the substrate and a shallow trench isolation structure, and a gate structure is formed in a second region of the substrate. Then, a portion of the first capping layer of the bit line material layer located on the shallow trench isolation structure is removed so that the top surface of the bit line material layer on the shallow trench isolation structure between the first and second regions of the substrate is lower than the top surface of the bit line material layer in the first and second regions (manifested by a groove). Afterward, a second capping layer is formed conformally on the first region and the shallow trench isolation structure with the groove. This ensures that the height of the bit line structure in the first region meets the product design requirements while reducing the height of the bit line structure formed on the shallow trench isolation structure near the edge of the first region, preventing the bit line structure on the shallow trench isolation structure from tilting, thereby improving the performance of the semiconductor device.
[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A method for fabricating a semiconductor memory, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A shallow trench isolation structure is formed in the substrate, located between the first region and the second region, the shallow trench isolation structure defining the first region and the second region; A bit line material layer is formed on the first region of the substrate and the shallow trench isolation structure, and the bit line material layer includes a semiconductor layer, a metal layer and a first capping layer from bottom to top; At least a portion of the first capping layer of the bitline material layer located on the shallow trench isolation structure is removed to form a groove; A second capping layer is formed on the remaining bitline material layer; The thickness of the first cover layer located on the shallow trench isolation structure is less than the thickness of the first cover layer located in the first region.
2. The method for fabricating a semiconductor memory as described in claim 1, characterized in that, The formation of the bit line material layer further includes forming the bit line material layer in a second region of the substrate to form a gate structure.
3. The method for fabricating a semiconductor memory as described in claim 2, characterized in that, After forming the gate structure located on the second region of the substrate, the method further includes: An etch barrier layer is formed on the bit line material layer in the first region of the substrate and the shallow trench isolation structure, as well as on the gate structure in the second region of the substrate.
4. The method for fabricating a semiconductor memory as described in claim 3, characterized in that, After forming the etching barrier layer, the method further includes: An insulating dielectric layer is formed on the second region of the substrate and the etch barrier layer on the shallow trench isolation structure, and a portion of the insulating dielectric layer in the second region of the substrate buries the gate structure.
5. The method for fabricating a semiconductor memory as described in claim 4, characterized in that, After forming the insulating dielectric layer, the method further includes: A photoresist layer is formed on the first region and part of the shallow trench isolation structure and on the gate structure of the second region of the substrate.
6. The method for fabricating a semiconductor memory as described in claim 5, characterized in that, The steps for forming the groove include: Remove all of the first capping layers on the shallow trench isolation structure that are not covered by the photoresist layer to form a groove with the bottom exposed below the metal layer located on the shallow trench isolation structure.
7. The method for fabricating a semiconductor memory as described in claim 5, characterized in that, The steps for forming the groove include: The portion of the first capping layer not covered by the photoresist layer on the shallow trench isolation structure is removed to form a groove at the bottom of which the remaining first capping layer on the shallow trench isolation structure is exposed, and the upper surface of the exposed remaining first capping layer has an arc shape that is concave towards the surface of the substrate.
8. The method for fabricating a semiconductor memory as described in claim 6, characterized in that, After the groove is formed, the sidewalls of the remaining bit line material layer are stepped in a lower horizontal direction on the first region of the substrate to the shallow trench isolation structure.
9. The method for fabricating a semiconductor memory as described in claim 7, characterized in that, After the groove is formed, the sidewalls of the remaining bit line material layer form a gradually decreasing slope in the horizontal direction from the first region of the substrate to the shallow trench isolation structure.
10. The method for fabricating a semiconductor memory as described in claim 4 or 5, characterized in that, The step of forming the groove further includes: Remove the etching barrier layer.
11. The method for fabricating a semiconductor memory as described in claim 8 or 9, characterized in that, The distance between the upper and lower surfaces of the second capping layer located on the first region of the substrate is less than the distance between the upper and lower surfaces of the second capping layer located on the shallow trench isolation structure.
12. The method for fabricating a semiconductor memory as described in claim 8 or 9, characterized in that, The distance between the upper and lower surfaces of the second capping layer located on the shallow trench isolation structure is greater than the distance between the upper and lower surfaces of the second capping layer located on the gate structure in the second region of the substrate.