Active universal programmable silicon adapter plate with self-adaptive function

Abstract

The invention provides an active universal programmable silicon pinboard with a self-adaption function, the silicon pinboard is an active universal programmable silicon pinboard, and a universal programmable switch matrix, an SRAM (Static Random Access Memory) unit array, an SRAM unit array read-write control circuit, a core particle interconnection module and a universal interconnection line are integrated in the silicon pinboard; micro convex points are uniformly arranged on the upper layer of the silicon adapter plate; the lower layer of the silicon adapter plate is provided with salient points which are used for mounting an organic substrate; a TSV channel is arranged in the silicon adapter plate and is used for packaging and leading out a power supply, the ground and a signal; the universal programmable switch matrixes are distributed in the silicon adapter plate in a two-dimensional array mode, each universal programmable switch matrix corresponds to one core particle interconnection module, connection between different micro convex points is achieved through configuration of SRAM unit value control, and therefore connection and communication between different core particles attached to the silicon adapter plate are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit chip integration, and in particular to an active universal programmable silicon adapter board with a self-adaptive function. Background Art

[0002] As integrated circuit technology enters the 10nm and below process nodes, the cost of chip manufacturing has increased dramatically, the yield of single chips has continued to decrease as the chip scale increases, and the design time and money costs have increased dramatically. To solve this problem, the core particle technology has developed rapidly, and single-chip performance can be achieved by assembling multiple core particles. Multiple core particles are connected through silicon adapters, which can realize the assembly of core particles of different process nodes, different materials, and different types, and achieve miniaturization and efficient connection.

[0003] Currently, silicon adapter boards are usually passive and only realize the interconnection between chiplets and the TSV connection between chiplets and substrates. In this way, each product needs to customize the silicon adapter board and cannot be modified later, which has the disadvantages of high cost and long design cycle. Summary of the invention

[0004] The present application provides an active universal programmable silicon adapter board with self-adaptation function, which can be used to solve the technical problem that passive adapter boards need to be customized and developed.

[0005] The present application provides an active universal programmable silicon adapter board with self-adaptation function, the silicon adapter board is an active universal programmable silicon adapter board, which internally integrates a universal programmable switch matrix, an SRAM cell array, an SRAM cell array read-write control circuit, a core particle interconnection module and a universal interconnection line;

[0006] Micro-bumps are evenly placed on the upper layer of the silicon transfer board, with a size of less than 25 microns, for mounting various types of core particles;

[0007] The lower layer of the silicon adapter board is C4 bumps, which are used for mounting with the organic substrate;

[0008] A TSV channel is set inside the silicon adapter board to realize the package extraction of power, ground and signal;

[0009] The universal programmable switch matrix is ​​distributed in the silicon adapter board in the form of a two-dimensional array. Each universal programmable switch matrix corresponds to a chip interconnection module. The connection between different micro-bumps is realized by configuring the SRAM cell value control, thereby realizing the connection and communication between different chiplets mounted on the silicon adapter board.

[0010] Furthermore, the upper layer of the silicon transfer board is evenly distributed with M rows and N columns of micro-bumps, and each core interconnect module has X*Y programmable input and output IO pins, which are connected to each micro-bump through RDL wiring, and some signals are connected to the package pins through TSV as needed;

[0011] Chips of different sizes are mounted on the silicon adapter board according to their sizes, and configuration information is generated according to the system connection and written into the internal configuration SRAM of the silicon adapter board.

[0012] Furthermore, the OUT signal of the universal programmable switch matrix is ​​connected to the input IN terminal of other universal programmable switch matrices through different interconnection lines, or connected to the chiplet interconnection module to transmit the signal to the mounting chiplet;

[0013] The programmable switch matrix controls the on and off of each switch inside the switch matrix by configuring the SRAM value, thereby realizing the corresponding function; when the corresponding configuration SRAM value of the switch is 1, the switch is connected, and when the configuration SRAM value is 0, the switch is disconnected.

[0014] Furthermore, in an SRAM unit, data is lost after power failure, and reconfiguration and download are required after each power-on; or a flash storage unit or an anti-fuse storage unit is used, and no reconfiguration and download are required after power failure.

[0015] Furthermore, the X*Y programmable input and output IO pins in each chip interconnection module are configured as input ports, output ports, constant high level, and constant low level as required;

[0016] When there are multiple core sizes or lead-out terminals, one core can be connected to the corresponding micro-bumps of multiple core interconnect modules.

[0017] Furthermore, the universal programmable switch matrix and universal interconnection lines in the active universal programmable silicon adapter board device with self-adaptive function can realize the connection between all interconnection modules inside the adapter board. The interconnection switch matrix is ​​realized by NMOS transistors or transmission gates, and the silicon adapter board includes universal interconnection lines of different types, i.e., different spans and different directions;

[0018] The interconnection wires connect the input and output ports of each programmable interconnection switch array inside the silicon adapter board, and realize the connectivity between all programmable switch arrays inside the silicon adapter board through programming;

[0019] Universal interconnects are divided into three types according to their length: short, medium, and long. They are characterized by span, which represents the number of programmable switch arrays they cross. Short interconnects are used to connect adjacent switch arrays and have a span of 1; medium interconnects have a span of 2-3; and long interconnects have a span of 6.

[0020] Universal interconnects include horizontal interconnects, vertical interconnects, and diagonal interconnects to achieve efficient and flexible connections.

[0021] Furthermore, the core particle interconnection module is used to realize the access of the core particle input and output signals to the internal universal interconnection network of the active universal programmable silicon adapter board, and the configuration realizes that the micro-bumps are connected to the input port, the output port, the power supply, and the grounding mode;

[0022] In order to increase the operating frequency of the system, registers are inserted into the chip interconnect module to realize pipeline design; or a general chip interconnect protocol module is integrated inside the chip interconnect module to realize high-speed communication between different chiplets.

[0023] The chip interconnection module realizes input and output control by configuring SRAM. When configured as input, the micro-bump PAD is connected to the chip output end, and is connected to the corresponding programmable switch matrix Inx port through the OUT output port of the chip interconnection module to access the general interconnection network; when configured as output, the micro-bump PAD is connected to the chip input end, and the signal comes from the OUTx port of the programmable switch matrix corresponding to the chip interconnection module, and is connected to the IN port of the chip interconnection module. At this time, the input selection is realized by controlling the MUX to use the configuration SRAM value to select the corresponding mode among direct input, DFF insertion, interface protocol module connection, VCC connection, and GND connection.

[0024] The active silicon adapter board supports channel self-testing and redundant replacement, which can avoid production failures and improve the yield of the active silicon adapter board.

[0025] Furthermore, the DFF inside the core particle interconnect module is a DFF with a scan path. All DFFs are connected in series, and all interconnection connection states are obtained by shifting, so that faults such as open circuit, short circuit, fixed 1, and fixed 0 caused by manufacturing defects of the general interconnect line can be detected;

[0026] Adjust the configuration SRAM value according to the detected phenomenon to avoid the defective path and implement redundant replacement.

[0027] The active silicon adapter board provided in the present application is a silicon adapter board with integrated active devices, which can overcome the shortcomings of passive silicon adapter boards. It has an internally integrated self-adaptive universal programmable interconnect switch matrix and a programmable core interconnect module, which can be flexibly adjusted as needed to support subsequent upgrades. It also has the advantages of short design cycle, low design cost, and support for subsequent upgrades. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of a self-adaptive active universal programmable silicon adapter board device provided in an embodiment of the present application;

[0029] Figure 2 A top view of a self-adaptive active universal programmable silicon adapter board device provided in an embodiment of the present application;

[0030] Figure 3A simplified diagram of the structure of the programmable switch matrix inside the active universal programmable silicon adapter board provided in the embodiment of the present application;

[0031] Figure 4 A schematic diagram of the structure of a chip interconnection module in an adaptive active universal programmable silicon adapter board device provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the structure of universal programmable interconnect lines inside the adaptive active universal programmable silicon adapter board device provided in an embodiment of the present application;

[0033] Figure 6 A schematic diagram of a universal interconnect self-test structure in a self-adaptive active universal programmable silicon adapter board device provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of placing different cores in the self-adaptive active universal programmable silicon adapter board device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0036] like Figure 1 As shown, 1 is an organic substrate, 2 is a silicon adapter board device which is an adaptive active universal programmable silicon adapter board device, 3 is a micro-bump of the silicon adapter board for realizing mounting with a core particle, 4 is a TSV channel inside the silicon adapter board for realizing power, ground and signal package lead-out terminals, 5 is a C4 bump under the silicon adapter board for realizing mounting with an organic substrate, and 6 is a universal interconnection line inside the active universal programmable silicon adapter board for realizing connection between programmable interconnection switch arrays of different spans.

[0037] The silicon adapter board has built-in universal programmable switch matrix, SRAM cell array, SRAM cell array read and write control circuit, core particle interconnection module, universal interconnection line and self-test redundant replacement module.

[0038] Micro-bumps are evenly placed on the upper layer of the silicon transfer board, with a size of less than 25 microns, for mounting with various types of core particles;

[0039] The lower layer of the silicon adapter plate is a C4 bump for mounting with the organic substrate 1;

[0040] The silicon adapter board is equipped with abundant TSV channels to realize the package extraction of power, ground and signals.

[0041] The universal programmable switch matrix is ​​distributed in the silicon adapter device in the form of a two-dimensional array. Each universal programmable switch matrix corresponds to a core interconnection module. The connection between different micro-bumps is realized by configuring the SRAM unit value control, thereby realizing the connection and communication between different cores mounted on the silicon adapter. According to the size of the core and the number of lead-out shorts, the core is configured to correspond to multiple core interconnection modules. A self-test redundant replacement module is added for manufacturing defect detection and replacement.

[0042] Figure 2 This is a top view of the self-adaptive active universal programmable silicon adapter board device of the present application. The input port or output port of each core particle interconnection module is fanned out through RDL, connected to micro-convex balls, and evenly distributed on the surface of the silicon adapter board. The core particles can be directly mounted together with the micro-convex balls.

[0043] Figure 3 The figure shows a simplified diagram of the programmable switch matrix structure inside the active universal programmable silicon adapter board, which contains multiple illustrated switch matrices. The input IN0-IN7 part in the figure connects universal interconnection lines of different spans and directions, which are used to realize the connection between all programmable switch matrices inside the active universal programmable silicon adapter board. The other part comes from the output of the core grain connection module, and the core grain signal is connected to the silicon adapter board interconnection network through the core grain connection module. The switch matrix OUT signal is connected to the input IN end of other switch matrices through different interconnection lines, or connected to the core grain interconnection module to transmit the signal to the mounted core grain. The programmable switch matrix can control the on and off of each switch inside the switch matrix by configuring the SRAM value, thereby realizing the corresponding function. When the corresponding configuration SRAM value of the switch is 1, the switch is connected, and when the configuration SRAM value is 0, the switch is disconnected. The switch is realized by a transmission gate. In order to achieve a smaller area, it is realized by an NMOS tube. At this time, it is necessary to pay attention to the threshold loss.

[0044] Figure 4 It is a schematic diagram of the structure of the core particle interconnection module in the self-adaptive active universal programmable silicon adapter device of the present application. PAD is a micro-bump on the silicon adapter board. Different types of core particles can be directly mounted on the micro-bump to achieve connection with the silicon adapter board. The core particle interconnection module can be programmed, and input / output control is realized by configuring SRAM. When configured as input, the micro-bump PAD connects the core particle output end, and is connected to the corresponding programmable switch matrix Inx port through the OUT output port of the core particle interconnection module to access the universal interconnection network; when configured as output, the micro-bump PAD connects the core particle input end, and the signal comes from the programmable switch matrix OUTx port corresponding to the core particle interconnection module, and is connected to the IN port of the core particle interconnection module. At this time, the input selection is realized by controlling the MUX pair to use the configuration SRAM value, and several modes such as direct input, inserting DFF, connecting the interface protocol module, fixing 1 (connecting to VCC), and fixing 0 (connecting to GND) are selected to adapt to different application requirements.

[0045] Figure 5 This is a schematic diagram of the structure of universal programmable interconnect lines inside the adaptive active universal programmable silicon adapter board device of the present application. The silicon adapter board is designed with universal interconnect lines of different types, i.e., different spans and different directions. The interconnect lines connect the input and output ports of each programmable interconnect switch array inside the silicon adapter board, and the connection between all programmable switch arrays inside the silicon adapter board is achieved through programming. Universal interconnect lines are divided into three types according to their length: short, medium, and long. They are characterized by spans, which represent the number of programmable switch arrays spanned. Short interconnect lines are used to connect adjacent switch arrays, and the span is 1. Figure 5 As shown in 4, it is flexible and efficient; the interconnection line span is 2-3, such as Figure 5 The long interconnection line has a span of 6 (which can be adjusted as needed), as shown in Figure 3, which can be used to achieve fast communication over long distances. General interconnection lines include horizontal interconnection lines, vertical interconnection lines, and diagonal interconnection lines. Figure 5 As shown in 1, two switch arrays at diagonal positions can be directly connected to improve the transmission speed.

[0046] Figure 6 This is a schematic diagram of the general interconnect self-test structure in the self-adaptive active universal programmable silicon adapter device of the present application. The internal DFF of each core interconnect module is a DFF with a scan path. All DFFs can be connected in series. All interconnect connection states can be obtained by shifting. It can detect open circuits, short circuits, fixed 1s, fixed 0s and other faults caused by manufacturing defects in general interconnect lines. According to the detection phenomenon, the configuration SRAM value is adjusted to avoid defective paths and achieve redundant replacement. For example, when it is detected that the current path of IN0 is fixed to 1 due to a manufacturing defect, the path Inn is selected by configuring SRAM to replace the path IN0 to achieve redundant replacement.

[0047] Figure 7 This is a schematic diagram of placing different cores in the adaptive active universal programmable silicon adapter device of the present application. Cores of different sizes are mounted according to the micro-bumps corresponding to multiple core interconnection modules according to their area sizes, and the internal connections of the corresponding core interconnection modules are configured as input ports, output ports, power supply, grounding, etc. according to the input and output states of the core lead-out ports to meet the system connection requirements.

[0048] The active silicon adapter board device provided by the present application internally integrates a universal programmable switch matrix, a configuration SRAM cell array, a configuration SRAM cell array read-write control circuit, a core interconnection module and a universal interconnection line. The universal programmable switch matrix is ​​distributed in the silicon adapter board device in the form of a two-dimensional array. Each universal programmable switch matrix corresponds to a core interconnection module. The connection between different cores on the silicon adapter board can be realized by configuring the SRAM cell value control. Different types of cores can be flexibly mounted on the active silicon adapter board device according to the core size, and the corresponding configuration SRAM cell value of the universal programmable switch matrix is ​​generated according to the system connection self-adaptation to realize the interconnection between different cores; the lead-out end of the core interconnection module can be adapted according to the core size and the number of core ports to support the integration of different cores; the universal interconnection network supports diagonal interconnection, shortens the path delay, and supports redundant replacement function to avoid short circuit or open circuit of the interconnection path caused by manufacturing defects; the active silicon adapter board device has the characteristics of self-adaptation, programmability, high redundancy, etc., supports the rapid integration of different process nodes and different types of integrated circuit cores, can speed up the integration speed of multi-core systems, and reduce development costs.

[0049] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. An active universal programmable silicon adapter board with self-adaptive function, characterized in that: The silicon adapter board is an active universal programmable silicon adapter board, which integrates a universal programmable switch matrix, an SRAM cell array, an SRAM cell array read-write control circuit, a core particle interconnection module and a universal interconnection line; Micro-bumps are evenly placed on the upper layer of the silicon transfer board, with a size of less than 25 microns, for mounting various types of core particles; The lower layer of the silicon adapter board is C4 bumps, which are used for mounting with the organic substrate; A TSV channel is set inside the silicon adapter board to realize the package extraction of power, ground and signal; The universal programmable switch matrix is ​​distributed in the silicon adapter board in the form of a two-dimensional array. Each universal programmable switch matrix corresponds to a chip interconnection module. The connection between different micro-bumps is realized by configuring the SRAM cell value control, thereby realizing the connection and communication between different chiplets mounted on the silicon adapter board.

2. The silicon adapter plate according to claim 1, characterized in that: The upper layer of the silicon transfer board is evenly distributed with M rows and N columns of micro-bumps. Each core interconnect module has X*Y programmable input and output IO pins, which are connected to each micro-bump through RDL wiring. Some signals are connected to the package pins through TSV as needed. Chips of different sizes are mounted on the silicon adapter board according to their sizes, and configuration information is generated according to the system connection and written into the internal configuration SRAM of the silicon adapter board.

3. The silicon adapter plate according to claim 1, characterized in that: The OUT signal of the universal programmable switch matrix is ​​connected to the input IN terminal of other universal programmable switch matrices through different interconnection lines, or connected to the chip interconnection module to transmit the signal to the mounting chip; The programmable switch matrix controls the on and off of each switch inside the switch matrix by configuring the SRAM value, thereby realizing the corresponding function; when the corresponding configuration SRAM value of the switch is 1, the switch is connected, and when the configuration SRAM value is 0, the switch is disconnected.

4. The silicon adapter plate according to claim 1, characterized in that: SRAM unit, data is lost after power failure, and reconfiguration and download are required after each power-on; or flash storage unit or anti-fuse storage unit is used, and no reconfiguration and download are required after power failure.

5. The silicon adapter plate according to claim 1, characterized in that: The X*Y programmable input and output IO pins in each core interconnect module can be configured as input ports, output ports, constant high level, and constant low level as needed; When there are multiple core sizes or lead-out terminals, one core can be connected to the corresponding micro-bumps of multiple core interconnect modules.

6. The silicon adapter plate according to claim 1, characterized in that: The silicon adapter board includes different types of universal interconnects, i.e., different spans and different directions; The interconnection wires connect the input and output ports of each programmable interconnection switch array inside the silicon adapter board, and realize the connectivity between all programmable switch arrays inside the silicon adapter board through programming; Universal interconnects are divided into three types according to their length: short, medium, and long. They are characterized by span, which represents the number of programmable switch arrays they cross. Short interconnects are used to connect adjacent switch arrays and have a span of 1; medium interconnects have a span of 2-3; and long interconnects have a span of 6. Common interconnects include horizontal interconnects, vertical interconnects, and diagonal interconnects.

7. The silicon adapter plate according to claim 1, characterized in that: The core particle interconnection module is used to realize the access of the core particle input and output signals to the internal universal interconnection network of the active universal programmable silicon adapter board, and configure the corresponding connection of the micro-bumps to be configured as input ports, output ports, power supply, and grounding modes; A register is inserted inside the chiplet interconnect module; or a general chiplet interconnect protocol module is integrated inside the chiplet interconnect module to achieve high-speed communication between different chiplets. The chip interconnection module realizes input and output control by configuring SRAM. When configured as input, the micro-bump PAD is connected to the chip output end, and is connected to the corresponding programmable switch matrix Inx port through the OUT output port of the chip interconnection module to access the general interconnection network; when configured as output, the micro-bump PAD is connected to the chip input end, and the signal comes from the OUTx port of the programmable switch matrix corresponding to the chip interconnection module, and is connected to the IN port of the chip interconnection module. At this time, the input selection is realized by controlling the MUX to use the configuration SRAM value to select the corresponding mode among direct input, DFF insertion, interface protocol module connection, VCC connection, and GND connection.

8. The silicon adapter plate according to claim 1, characterized in that: The DFF inside the core-grain interconnect module is a DFF with a scan path. All DFFs are connected in series, and all interconnection connection states are obtained by shifting. This can detect faults such as open circuit, short circuit, fixed 1, and fixed 0 caused by manufacturing defects in general interconnect lines. Adjust the configuration SRAM value according to the detected phenomenon to avoid the defective path and implement redundant replacement.

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