NAND flash memory storage device and electronic equipment

Abstract

The invention relates to the technical field of semiconductor devices, and particularly discloses an NAND flash memory storage device and electronic equipment. The peripheral circuit includes a plurality of hybrid transistor block structures each including a first conductivity type transistor region and a second conductivity type transistor region; the first conduction type transistor region comprises a first conduction type transistor structure and a first conduction type transistor parasitic structure, and the second conduction type transistor region comprises a second conduction type transistor structure and a second conduction type transistor parasitic structure; the first conductive type transistor structure and the first conductive type transistor parasitic structure share the same second conductive type electrode active layer, and the second conductive type transistor structure and the second conductive type transistor parasitic structure share the same first conductive type electrode active layer. According to the NAND flash memory storage device provided by the invention, the electrostatic capacity of the capacitor can be improved in a set area.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a NAND flash memory storage device and an electronic device. Background Art

[0002] As the integration level of semiconductor devices of NAND flash memory increases and the device size decreases, it becomes increasingly difficult to satisfy the electrostatic capacity of capacitors required for device operation.

[0003] Currently, with the reduction in chip size and the increase in the integration of memory devices, capacitors with larger capacities are needed, that is, the capacitance value of the capacitor needs to be increased within a given area. However, in the prior art, if a capacitor is to achieve the required performance within a specific circuit field, the area occupied by the capacitor will increase, thereby leading to the problem of increased chip size.

[0004] Therefore, how to provide a capacitor that can improve the electrostatic capacitance of the capacitor within a given area to achieve the required performance has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The present invention provides a NAND flash memory storage device and an electronic device, which solves the problem in the related art that the electrostatic capacity of a capacitor cannot be increased within a given area.

[0006] As a first aspect of the present invention, a NAND flash memory storage device is provided, comprising: A semiconductor substrate, wherein the semiconductor substrate is divided into a storage area and a peripheral area, wherein the storage area is used to form a storage unit, and the peripheral area is used to form a peripheral circuit, and the peripheral circuit is used to drive the operation of the storage unit; The peripheral circuit includes a plurality of hybrid transistor block structures formed on the semiconductor substrate, each hybrid transistor block structure including a first conductivity type transistor region and a second conductivity type transistor region; The first conductive type transistor region includes a first conductive type transistor structure and a first conductive type transistor parasitic structure, the second conductive type transistor region includes a second conductive type transistor structure and a second conductive type transistor parasitic structure, the first conductive type transistor structure and the second conductive type transistor structure are symmetrically arranged, the first conductive type transistor parasitic structure and the second conductive type transistor structure are symmetrically arranged, the first conductive type transistor structure and the first conductive type transistor parasitic structure share the same second conductive type electrode active layer, and the second conductive type transistor structure and the second conductive type transistor parasitic structure share the same first conductive type electrode active layer; The first conductive type transistor structure can form a first group of capacitor structures when connected to a voltage, and the first conductive type transistor parasitic structure can form a first group of parasitic capacitor structures when connected to a voltage, and the capacitance of the first group of capacitor structures and the capacitance of the first group of parasitic capacitor structures form the capacitance of the first conductive type transistor region; The second conductive type transistor structure can form a second group of capacitor structures when a voltage is connected, and the second conductive type transistor parasitic structure can form a second group of parasitic capacitor structures when a voltage is connected. The capacitance of the second group of capacitor structures and the capacitance of the second group of parasitic capacitor structures form the capacitance of the second conductive type transistor region.

[0007] Further, the first conductive type transistor structure includes a second conductive type electrode active layer formed on the semiconductor substrate, a first conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a first control electrode layer formed on the second conductive type electrode active layer; The first conductive type transistor parasitic structure includes a second conductive type electrode active layer formed on the semiconductor substrate, a second conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a second control electrode layer formed on the second conductive type electrode active layer; The second conductive type transistor structure includes a first conductive type electrode active layer formed on the semiconductor substrate, a second conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the inside of the first conductive type electrode active layer, and a first control electrode layer formed on the first conductive type electrode active layer; The second conductive type transistor parasitic structure includes a first conductive type electrode active layer formed on the semiconductor substrate, a first conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the interior of the first conductive type electrode active layer, and a second control electrode layer formed on the first conductive type electrode active layer.

[0008] Further, the second conductive type electrode active layer is formed as a second conductive type first bulk electrode terminal of the first conductive type transistor structure and a second conductive type second bulk electrode terminal of the first conductive type transistor parasitic structure respectively; The first conductive type first input-output electrode layer is formed as a first conductive type first source electrode terminal and a first conductive type first drain electrode terminal of the first conductive type transistor structure, and the first control electrode layer on the second conductive type electrode active layer is formed as a control gate electrode terminal of the first conductive type transistor structure; The second conductive type first input-output electrode layer is formed as the second conductive type first source electrode terminal and the second conductive type first drain electrode terminal of the first conductive type transistor parasitic structure, and the second control electrode layer on the second conductive type electrode active layer is formed as the control gate electrode terminal of the first conductive type transistor parasitic structure.

[0009] Further, when the first conductive type transistor structure and the first conductive type transistor parasitic structure are both connected to a voltage: A voltage difference is formed between the first conductive type first source electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, between the first conductive type first drain electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, and between the second conductive type first bulk electrode terminal and the control gate electrode terminal of the first conductive type transistor structure to generate a first group of capacitor structures; A voltage difference is formed between the first source electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, between the first drain electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, and between the second bulk electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor to generate a first group of parasitic capacitance structures.

[0010] Further, the first conductive type first source electrode terminal, the first conductive type first drain electrode terminal and the second conductive type first bulk electrode terminal are all connected to a high level voltage, and the control gate electrode terminal of the first conductive type transistor structure is connected to a low level voltage; The second conductivity type first source electrode terminal, the second conductivity type first drain electrode terminal and the second conductivity type second bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the first conductivity type transistor parasitic structure is connected to a high level voltage.

[0011] Further, the first conductive type electrode active layer is formed as a first conductive type first bulk electrode terminal of the second conductive type transistor structure and a first conductive type second bulk electrode terminal of the second conductive type transistor structure respectively; The second conductive type second input-output electrode layer is formed as a second conductive type second source electrode terminal and a second conductive type second drain electrode terminal of the second conductive type transistor structure, and the first control electrode layer on the first conductive type electrode active layer is formed as a control gate electrode terminal of the second conductive type transistor structure; The first conductive type second input-output electrode layer forms a first conductive type second source electrode terminal and a first conductive type second drain electrode terminal of the second conductive type transistor parasitic structure, and the second control electrode layer on the first conductive type electrode active layer forms a control gate electrode terminal of the second conductive type transistor parasitic structure.

[0012] Further, when the second conductive type transistor structure and the second conductive type transistor parasitic structure are both connected to a voltage: a voltage difference is formed between the second conductive type second source electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, between the second conductive type second drain electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, and between the first conductive type first bulk electrode terminal and the control gate electrode terminal of the second conductive type transistor structure to generate a second group of capacitor structures; A voltage difference is formed between the second source electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, between the second drain electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, and between the second bulk electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor to generate a second group of parasitic capacitance structures.

[0013] Further, the second conductive type second source electrode terminal, the second conductive type second drain electrode terminal and the first conductive type first bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the second conductive type transistor structure is connected to a high level voltage; The first conductive type second source electrode terminal, the first conductive type second drain electrode terminal and the first conductive type second bulk electrode terminal are all connected to a high level voltage, and the control gate electrode terminal of the second conductive type transistor parasitic structure is connected to a low level voltage.

[0014] Further, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0015] As another aspect of the present invention, there is provided an electronic device, comprising the NAND flash memory storage device as described above.

[0016] The NAND flash memory storage device provided by the present invention can maximize the area of ​​the capacitor within a given area by additionally adding a parasitic structure within the same active layer area of ​​the semiconductor substrate, thereby achieving the purpose of improving the integration of the chip's storage devices and the electrostatic capacitance of the capacitor without increasing the chip size. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0018] Figure 1 This is a structural block diagram of the NAND flash memory storage device provided by the present invention.

[0019] Figure 2 A schematic diagram of the layout of a hybrid transistor block structure in a NAND flash memory storage device provided by the present invention.

[0020] Figure 3 This is a schematic diagram of the layout of the bulk electrode provided by the present invention.

[0021] Figure 4a The present invention provides Figure 2 Schematic diagram of the vertical structure of the P-type transistor parasitic structure N100 after the A-A' region is cut.

[0022] Figure 4b A cross-sectional view of a P-type transistor structure provided by the present invention.

[0023] Figure 5a The present invention provides Figure 2 Schematic diagram of the vertical structure of the N-type transistor parasitic structure P100 after the BB' region is cut.

[0024] Figure 5b A cross-sectional view of an N-type transistor structure provided by the present invention. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] In the prior art, as chip size decreases and the integration of memory devices increases, more capacitors are needed, that is, the capacitance of the capacitor needs to be increased within a given area. However, capacitors that currently achieve the required performance in a specific circuit field usually increase the area occupied by the capacitor, which in turn increases the chip size.

[0029] Based on this, a NAND flash memory storage device is provided in this embodiment, such as Figure 1 and Figure 2 As shown, the NAND flash memory storage device 10 includes: A semiconductor substrate, wherein the semiconductor substrate is divided into a storage area 110 and a peripheral area 120, wherein the storage area is used to form a storage unit, and the peripheral area is used to form a peripheral circuit, wherein the peripheral circuit is used to drive the storage unit to work; The peripheral circuit includes a plurality of hybrid transistor block structures 200 formed on the semiconductor substrate, each hybrid transistor block structure 200 includes a first conductive type transistor region 210 and a second conductive type transistor region 220; The first conductive type transistor region 210 includes a first conductive type transistor structure 211 and a first conductive type transistor parasitic structure 212, the second conductive type transistor region 220 includes a second conductive type transistor structure 221 and a second conductive type transistor parasitic structure 222, the first conductive type transistor structure 211 and the second conductive type transistor structure 221 are symmetrically arranged, the first conductive type transistor parasitic structure 212 and the second conductive type transistor structure 222 are symmetrically arranged, the first conductive type transistor structure 211 and the first conductive type transistor parasitic structure 212 share the same second conductive type electrode active layer, and the second conductive type transistor structure 221 and the second conductive type transistor parasitic structure 222 share the same first conductive type electrode active layer; The first conductive type transistor structure 211 can form a first group of capacitor structures when connected to a voltage, and the first conductive type transistor parasitic structure 212 can form a first group of parasitic capacitor structures when connected to a voltage, and the capacitance of the first group of capacitor structures and the capacitance of the first group of parasitic capacitor structures form the capacitance of the first conductive type transistor region; The second conductive type transistor structure 221 can form a second group of capacitor structures when a voltage is connected, and the second conductive type transistor parasitic structure 222 can form a second group of parasitic capacitor structures when a voltage is connected. The capacitance of the second group of capacitor structures and the capacitance of the second group of parasitic capacitor structures form the capacitance of the second conductive type transistor region.

[0030] In an embodiment of the present invention, a first conductive type transistor structure 211 and a first conductive type transistor parasitic structure 212 are arranged in the first conductive type transistor region 210. The first conductive type transistor parasitic structure 212 shares the same second conductive type electrode active layer with the first conductive type transistor structure 211. Specifically, it can be understood that the first conductive type transistor parasitic structure 212 is arranged on the second conductive type electrode active layer where the first conductive type transistor structure 211 is located, that is, a first group of parasitic capacitance structures is formed without increasing the area of ​​the first conductive type transistor region 210, so that the first conductive type transistor region 210 adds the capacitance of the first group of parasitic capacitance structures on the basis of the capacitance of the current first group of capacitance structures, thereby achieving the purpose of increasing the capacitance of the capacitor within a given area.

[0031] Similarly, a second conductive type transistor structure 221 and a second conductive type transistor parasitic structure 222 are arranged in the second conductive type transistor region 220. The second conductive type transistor parasitic structure 222 shares the same first conductive type electrode active layer with the second conductive type transistor structure 221. Specifically, it can be understood that the second conductive type transistor parasitic structure 222 is arranged on the first conductive type electrode active layer where the second conductive type transistor structure 221 is located, that is, a second group of parasitic capacitance structures is formed without increasing the area of ​​the second conductive type transistor region 220, so that the second conductive type transistor region 220 adds the capacitance of the second group of parasitic capacitance structures on the basis of the capacitance of the current second group of capacitance structures, thereby achieving the purpose of increasing the capacitance of the capacitor within a given area.

[0032] Therefore, the NAND flash memory storage device provided in the embodiment of the present invention can maximize the area of ​​the capacitor within a given area by additionally adding a parasitic structure within the same active layer area of ​​the semiconductor substrate, thereby achieving the purpose of improving the integration of the chip's storage devices and the electrostatic capacitance of the capacitor without increasing the chip size.

[0033] In the embodiment of the present invention, the first conductive type transistor structure 211 includes a second conductive type electrode active layer formed on the semiconductor substrate, a first conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a first control electrode layer formed on the second conductive type electrode active layer; The first conductive type transistor parasitic structure 212 includes a second conductive type electrode active layer formed on the semiconductor substrate, a second conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a second control electrode layer formed on the second conductive type electrode active layer; The second conductive type transistor structure 221 includes a first conductive type electrode active layer formed on the semiconductor substrate, a second conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the inside of the first conductive type electrode active layer, and a first control electrode layer formed on the first conductive type electrode active layer; The second conductive type transistor parasitic structure 222 includes a first conductive type electrode active layer formed on the semiconductor substrate, a first conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the interior of the first conductive type electrode active layer, and a second control electrode layer formed on the first conductive type electrode active layer.

[0034] It should be understood that the first conductive type transistor structure 211 and the first conductive type transistor parasitic structure 212 share the same second conductive type electrode active layer, that is, the first conductive type transistor parasitic structure 212 is arranged on the existing second conductive type electrode active layer to realize a first group of capacitor parasitic structures, and the capacitance is increased without increasing the current chip area. The second conductive type transistor structure 221 and the second conductive type transistor parasitic structure 222 share the same first conductive type electrode active layer, that is, the second conductive type transistor parasitic structure 222 is arranged on the existing first conductive type electrode active layer to realize a second group of capacitor parasitic structures, and the capacitance is increased without increasing the current chip area.

[0035] Specifically, the second conductive type electrode active layer is formed as a second conductive type first bulk electrode terminal of the first conductive type transistor structure and a second conductive type second bulk electrode terminal of the first conductive type transistor parasitic structure respectively; The first conductive type first input-output electrode layer is formed as a first conductive type first source electrode terminal and a first conductive type first drain electrode terminal of the first conductive type transistor structure, and the first control electrode layer on the second conductive type electrode active layer is formed as a control gate electrode terminal of the first conductive type transistor structure; The second conductive type first input-output electrode layer is formed as the second conductive type first source electrode terminal and the second conductive type first drain electrode terminal of the first conductive type transistor parasitic structure, and the second control electrode layer on the second conductive type electrode active layer is formed as the control gate electrode terminal of the first conductive type transistor parasitic structure.

[0036] It should be noted that, in the embodiment of the present invention, the bulk electrode can play a role in maintaining the threshold voltage of each device after being applied with different voltages. Figure 3 The transistor structure includes a source electrode 1-1 that provides carriers, a drain electrode 1-2 that attracts carriers to a high electric field, a control gate electrode 1-3 that acts as a switch, and a bulk electrode 1-4 that fixes the body to stabilize the transistor channel. In normal operation, the bulk electrode of the N-type transistor is connected to 0V or VSS, i.e., a low voltage, while the bulk electrode of the P-type transistor is connected to VDD, i.e., a high voltage. The voltage applied to the above-mentioned bulk electrodes is different according to the N-type and P-type devices, thereby playing a role in maintaining the threshold voltage of each device.

[0037] Therefore, based on the role of the bulk electrode in maintaining the threshold voltage of the transistor operation, when laying out in a NAND flash memory storage device, the bulk electrode needs to be set within a safe distance that can meet the normal operation of the transistor. This safe distance can ensure that the threshold voltage adjustment will not be affected when the transistor operates. This safe distance is usually within tens of microns, for example, usually less than 30μm.

[0038] In the embodiment of the present invention, when the first conductive type transistor structure 211 and the first conductive type transistor parasitic structure 212 are both connected to a voltage: A voltage difference is formed between the first conductive type first source electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, between the first conductive type first drain electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, and between the second conductive type first bulk electrode terminal and the control gate electrode terminal of the first conductive type transistor structure to generate a first group of capacitor structures; A voltage difference is formed between the first source electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, between the first drain electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, and between the second bulk electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor to generate a first group of parasitic capacitance structures.

[0039] In an embodiment of the present invention, when forming a first group of capacitor structures, the first conductive type first source electrode terminal, the first conductive type first drain electrode terminal, and the second conductive type first bulk electrode terminal are all connected to a high level voltage, and the control gate electrode terminal of the first conductive type transistor structure is connected to a low level voltage: When forming the first group of parasitic capacitance structures, the second conductive type first source electrode terminal, the second conductive type first drain electrode terminal and the second conductive type second bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the first conductive type transistor parasitic structure is connected to a high level voltage.

[0040] It should be understood that if Figure 2 As shown, by placing the control gate electrode terminal wiring of the first conductive type transistor parasitic structure onto the second conductive type electrode active layer that generates the second conductive type first bulk electrode terminal of the first conductive type transistor structure and the second conductive type second bulk electrode terminal of the first conductive type transistor parasitic structure, an additional semiconductor device is generated in the same area, that is, a first parasitic capacitor structure is formed, thereby achieving an improvement in the capacity of the current capacitor structure.

[0041] It should be noted that, in the embodiment of the present invention, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0042] In the embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type as an example.

[0043] The parasitic structure of the P-type transistor may specifically be composed of a source electrode N41 , a drain electrode N42 , and a control gate electrode N4G of an N-type bulk electrode active layer.

[0044] In this structure, a high voltage (usually VDD) is applied to the N-type source electrode terminal N41 and the drain electrode terminal N42, and a low voltage (usually VSS) is applied to the N-type control gate electrode terminal N4G, forming a first parasitic capacitance structure.

[0045] It should be noted that the high voltage is usually a power supply voltage, such as 5V; the low voltage may be, for example, a ground terminal, such as 0V.

[0046] Specifically, the P-type transistor parasitic structure N100 in the P-type region is connected along Figure 2 The vertical structure diagram after cutting the A-A' region is as follows Figure 4a As shown, in the P-type transistor parasitic structure N100, the control gate electrode N4G is placed on the N-type bulk electrode wiring N43 with a low doping concentration, so that the electrode generated is a device composed of an N+ type source electrode terminal N41 with a high doping concentration, an N+ type drain electrode terminal N42 with a high doping concentration, and an N-type control gate electrode terminal N4G. Therefore, the P-type transistor structure can realize a parasitic capacitance structure by additionally configuring the P-type transistor parasitic structure N100, so that when a low voltage VSS is applied to the N-type control gate electrode terminal N4G, and when a high voltage VDD is applied to the N+ type source electrode terminal N41 and the N+ type drain electrode terminal N42, three parasitic capacitance devices AC1, AC2 and AC3 can be realized, thereby obtaining the capacitance required by the semiconductor device.

[0047] like Figure 4b As shown, it is a cross-sectional view of a P-type transistor structure, connecting a high-doping concentration P+ type source electrode terminal 3-1, a high-doping concentration P+ type drain electrode terminal 3-2 and a low-doping concentration N-type bulk electrode terminal 3-4 to the VDD voltage, and connecting the control gate electrode terminal 3-3 of the P-type transistor structure to the VSS voltage. Due to the voltage difference, a first group of capacitor structures C3, C1 and C2 are generated. Based on Figure 4a and Figure 4bFrom the formed capacitor structure, it can be seen that the capacitance of the first conductive type transistor region is the capacitance of C3, C1 and C2 plus the capacitance of three parasitic capacitors AC1, AC2 and AC3, thereby achieving the purpose of increasing the capacitance within a given area.

[0048] It should be noted that the N-type bulk electrode wiring N43 is generated within a certain interval (usually less than 30 μm) as in the embodiment of the present invention. Figure 4a The P-type transistor parasitic structure N100 with the structure can form a structure in which the electrostatic capacity of the capacitor is increased to the maximum in a specific area or a required specific circuit area.

[0049] As a specific embodiment of the present invention, the first conductive type electrode active layer is formed as a first conductive type first bulk electrode terminal of the second conductive type transistor structure and a first conductive type second bulk electrode terminal of the second conductive type transistor structure respectively; The second conductive type second input-output electrode layer is formed as a second conductive type second source electrode terminal and a second conductive type second drain electrode terminal of the second conductive type transistor structure, and the first control electrode layer on the first conductive type electrode active layer is formed as a control gate electrode terminal of the second conductive type transistor structure; The first conductive type second input-output electrode layer forms a first conductive type second source electrode terminal and a first conductive type second drain electrode terminal of the second conductive type transistor parasitic structure, and the second control electrode layer on the first conductive type electrode active layer forms a control gate electrode terminal of the second conductive type transistor parasitic structure.

[0050] In the embodiment of the present invention, when the second conductive type transistor structure 221 and the second conductive type transistor parasitic structure 222 are both connected to a voltage: a voltage difference is formed between the second conductive type second source electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, between the second conductive type second drain electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, and between the first conductive type first bulk electrode terminal and the control gate electrode terminal of the second conductive type transistor structure to generate a second group of capacitor structures; A voltage difference is formed between the second source electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, between the second drain electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, and between the second bulk electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor to generate a second group of parasitic capacitance structures.

[0051] In an embodiment of the present invention, when forming the second group of capacitor structures, the second conductive type second source electrode terminal, the second conductive type second drain electrode terminal, and the first conductive type first bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the second conductive type transistor structure is connected to a high level voltage; When forming the second group of parasitic capacitance structures, a high level voltage is connected between the first conductive type second source electrode terminal, the first conductive type second drain electrode terminal and the first conductive type second bulk electrode terminal, and a low level voltage is connected to the control gate electrode terminal of the second conductive type transistor parasitic structure.

[0052] Specifically, Figure 2 As shown, in the embodiment of the present invention, taking the first conductivity type as P type and the second conductivity type as N type as an example, the parasitic structure of the N type transistor can specifically be composed of a source electrode terminal P41 of the P type bulk electrode active layer, a drain electrode terminal P42 of the P type bulk electrode active layer, and a control gate electrode terminal P4G of the bulk electrode active layer.

[0053] In the transistor parasitic structure of the above structure, a low voltage (usually VSS) is applied to the source electrode terminal P41 of the P-type bulk electrode active layer and a drain electrode terminal P42 of the P-type bulk electrode active layer, and a high voltage (usually VDD) is applied to the control gate electrode terminal P4G of the bulk electrode active layer, forming a second parasitic capacitor structure.

[0054] It should be noted that the high voltage is usually a power supply voltage, such as 5V; the low voltage may be, for example, a ground terminal, such as 0V.

[0055] Specifically, the N-type transistor parasitic structure P100 in the N-type region is connected along Figure 2 The vertical schematic diagram after cutting the B-B' region is as follows Figure 5a As shown, in the N-type transistor parasitic structure P100, the control gate electrode is placed on the P-type bulk electrode wiring P43 with a low doping concentration, so that the electrode generated is a device composed of a P+ type source electrode terminal P41 with a high doping concentration, a P+ type drain electrode terminal P42 with a high doping concentration, and a P-type control gate electrode terminal P4G. Therefore, the N-type transistor structure can realize a parasitic capacitance structure by additionally configuring the N-type transistor parasitic mechanism P100. When a low voltage VSS is applied to the P-type control gate electrode terminal P4G, and a high voltage VDD is applied to the P+ type source electrode terminal P41 and the P+ type drain electrode terminal P42, three parasitic capacitance devices having AC4, AC5 and AC6 can be formed, so that the capacitance required by the semiconductor device can be obtained.

[0056] like Figure 5b As shown, the high doping concentration N+ type source electrode terminal 3-6, the high doping concentration N+ type drain electrode terminal 3-7 and the low doping concentration P-type bulk electrode terminal 3-8 are connected to the VSS voltage, and the control gate electrode terminal 3-5 of the N-type transistor structure is connected to the VDD voltage. Due to the voltage difference, a second group of capacitor structures C4, C5 and C6 are generated. Based on Figure 5a and Figure 5b From the capacitor structure formed, it can be seen that the capacitance of the second conductive type transistor area is the capacitance of C4, C5 and C6 plus the capacitance of three parasitic capacitors AC4, AC5 and AC6, thereby achieving the purpose of increasing the capacitance within a given area.

[0057] It should be noted that the P-type bulk electrode wiring P43 is generated within a certain interval (usually less than 30 μm) as in the embodiment of the present invention. Figure 5a The N-type transistor parasitic structure P100 can be formed to maximize the electrostatic capacitance of the capacitor in a specific area or a required specific circuit area.

[0058] In summary, the NAND flash memory storage device provided by the present invention can increase the capacitance of the current transistor structure by adding a transistor parasitic structure to the given area of ​​the current first conductive type electrode active layer and the second conductive type electrode active layer, and further can realize a capacitor with the required performance in the current circuit area, thereby improving the safety of chip operation and achieving the purpose of increasing the electrostatic capacitance of the capacitor without increasing the chip size.

[0059] As another aspect of the present invention, there is provided an electronic device, comprising the NAND flash memory storage device as described above.

[0060] In an embodiment of the present invention, an electronic device adopts the aforementioned NAND flash memory storage device. By additionally adding a parasitic structure within the same active layer area of ​​a semiconductor substrate, the area of ​​the capacitor can be maximized within a given area, thereby achieving the purpose of improving the integration of the chip's storage devices and the electrostatic capacitance of the capacitor without increasing the chip size, thereby enhancing the competitive advantage of the NAND flash memory storage device. Similarly, an electronic device adopting the NAND flash memory storage device also has the advantages of a higher level of integration and a higher electrostatic capacitance.

[0061] Specifically, the electronic device may include a communication device or other electronic devices that need to use a stored startup code, such as a set-top box, a smart camera, a smart home, and the like.

[0062] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A NAND flash memory storage device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate is divided into a storage area and a peripheral area, wherein the storage area is used to form a storage unit, and the peripheral area is used to form a peripheral circuit, and the peripheral circuit is used to drive the operation of the storage unit; The peripheral circuit includes a plurality of hybrid transistor block structures formed on the semiconductor substrate, each hybrid transistor block structure including a first conductivity type transistor region and a second conductivity type transistor region; The first conductive type transistor region includes a first conductive type transistor structure and a first conductive type transistor parasitic structure, the second conductive type transistor region includes a second conductive type transistor structure and a second conductive type transistor parasitic structure, the first conductive type transistor structure and the second conductive type transistor structure are symmetrically arranged, the first conductive type transistor parasitic structure and the second conductive type transistor structure are symmetrically arranged, the first conductive type transistor structure and the first conductive type transistor parasitic structure share the same second conductive type electrode active layer, and the second conductive type transistor structure and the second conductive type transistor parasitic structure share the same first conductive type electrode active layer; The first conductive type transistor structure can form a first group of capacitor structures when connected to a voltage, and the first conductive type transistor parasitic structure can form a first group of parasitic capacitor structures when connected to a voltage, and the capacitance of the first group of capacitor structures and the capacitance of the first group of parasitic capacitor structures form the capacitance of the first conductive type transistor region; The second conductive type transistor structure can form a second group of capacitor structures when a voltage is connected, and the second conductive type transistor parasitic structure can form a second group of parasitic capacitor structures when a voltage is connected. The capacitance of the second group of capacitor structures and the capacitance of the second group of parasitic capacitor structures form the capacitance of the second conductive type transistor region.

2. The NAND flash memory storage device according to claim 1, wherein: The first conductive type transistor structure includes a second conductive type electrode active layer formed on the semiconductor substrate, a first conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a first control electrode layer formed on the second conductive type electrode active layer; The first conductive type transistor parasitic structure includes a second conductive type electrode active layer formed on the semiconductor substrate, a second conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a second control electrode layer formed on the second conductive type electrode active layer; The second conductive type transistor structure includes a first conductive type electrode active layer formed on the semiconductor substrate, a second conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the inside of the first conductive type electrode active layer, and a first control electrode layer formed on the first conductive type electrode active layer; The second conductive type transistor parasitic structure includes a first conductive type electrode active layer formed on the semiconductor substrate, a first conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the interior of the first conductive type electrode active layer, and a second control electrode layer formed on the first conductive type electrode active layer.

3. The NAND flash memory storage device according to claim 2, wherein: The second conductive type electrode active layer is formed as a second conductive type first bulk electrode terminal of the first conductive type transistor structure and a second conductive type second bulk electrode terminal of the first conductive type transistor parasitic structure respectively; The first conductive type first input-output electrode layer is formed as a first conductive type first source electrode terminal and a first conductive type first drain electrode terminal of the first conductive type transistor structure, and the first control electrode layer on the second conductive type electrode active layer is formed as a control gate electrode terminal of the first conductive type transistor structure; The second conductive type first input-output electrode layer is formed as the second conductive type first source electrode terminal and the second conductive type first drain electrode terminal of the first conductive type transistor parasitic structure, and the second control electrode layer on the second conductive type electrode active layer is formed as the control gate electrode terminal of the first conductive type transistor parasitic structure.

4. The NAND flash memory storage device according to claim 3, wherein: When the first conductive type transistor structure and the first conductive type transistor parasitic structure are both connected to a voltage: A voltage difference is formed between the first conductive type first source electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, between the first conductive type first drain electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, and between the second conductive type first bulk electrode terminal and the control gate electrode terminal of the first conductive type transistor structure to generate a first group of capacitor structures; A voltage difference is formed between the first source electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, between the first drain electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, and between the second bulk electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor to generate a first group of parasitic capacitance structures.

5. The NAND flash memory storage device according to claim 4, wherein: The first conductive type first source electrode terminal, the first conductive type first drain electrode terminal and the second conductive type first bulk electrode terminal are all connected to a high level voltage, and the control gate electrode terminal of the first conductive type transistor structure is connected to a low level voltage; The second conductivity type first source electrode terminal, the second conductivity type first drain electrode terminal and the second conductivity type second bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the first conductivity type transistor parasitic structure is connected to a high level voltage.

6. The NAND flash memory storage device according to claim 2, wherein: The first conductive type electrode active layer is formed as a first conductive type first bulk electrode terminal of the second conductive type transistor structure and a first conductive type second bulk electrode terminal of the second conductive type transistor structure respectively; The second conductive type second input-output electrode layer is formed as a second conductive type second source electrode terminal and a second conductive type second drain electrode terminal of the second conductive type transistor structure, and the first control electrode layer on the first conductive type electrode active layer is formed as a control gate electrode terminal of the second conductive type transistor structure; The first conductive type second input-output electrode layer forms a first conductive type second source electrode terminal and a first conductive type second drain electrode terminal of the second conductive type transistor parasitic structure, and the second control electrode layer on the first conductive type electrode active layer forms a control gate electrode terminal of the second conductive type transistor parasitic structure.

7. The NAND flash memory storage device according to claim 6, wherein: When the second conductive type transistor structure and the second conductive type transistor parasitic structure are both connected to a voltage: a voltage difference is formed between the second conductive type second source electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, between the second conductive type second drain electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, and between the first conductive type first bulk electrode terminal and the control gate electrode terminal of the second conductive type transistor structure to generate a second group of capacitor structures; A voltage difference is formed between the second source electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, between the second drain electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, and between the second bulk electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor to generate a second group of parasitic capacitance structures.

8. The NAND flash memory storage device according to claim 7, wherein: The second conductive type second source electrode terminal, the second conductive type second drain electrode terminal and the first conductive type first bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the second conductive type transistor structure is connected to a high level voltage; The first conductive type second source electrode terminal, the first conductive type second drain electrode terminal and the first conductive type second bulk electrode terminal are all connected to a high level voltage, and the control gate electrode terminal of the second conductive type transistor parasitic structure is connected to a low level voltage.

9. The NAND flash memory storage device according to any one of claims 1 to 8, characterized in that: When the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.

10. An electronic device, characterized in that: A NAND flash memory storage device comprising any one of claims 1 to 9.

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