NAND Flash Memory Storage Device and Electronic Device

Abstract

The present invention relates to the technical field of semiconductor devices, and specifically discloses a NAND flash memory storage device and an electronic device, comprising: a semiconductor substrate; the peripheral circuit includes a plurality of hybrid transistor block structures, and each hybrid transistor block structure includes a first-conductivity-type transistor region and a second-conductivity-type transistor region; the first-conductivity-type transistor region includes a first-conductivity-type transistor structure and a first-conductivity-type transistor parasitic structure, the second-conductivity-type transistor region includes a second-conductivity-type transistor structure and a second-conductivity-type transistor parasitic structure, the first-conductivity-type transistor structure and the first-conductivity-type transistor parasitic structure share the same second-conductivity-type electrode active layer, and the second-conductivity-type transistor structure and the second-conductivity-type transistor parasitic structure share the same first-conductivity-type electrode active layer. The NAND flash memory storage device provided by the present invention can improve the electrostatic capacitance of the capacitor within a given area.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a NAND flash memory storage device and an electronic device. Background Art

[0002] As the integration level of semiconductor devices of NAND flash memory increases and the device size decreases, it becomes increasingly difficult to satisfy the electrostatic capacity of capacitors required for device operation.

[0003] Currently, with the reduction in chip size and the increase in the integration of memory devices, capacitors with larger capacities are needed, that is, the capacitance value of the capacitor needs to be increased within a given area. However, in the prior art, if a capacitor is to achieve the required performance within a specific circuit field, the area occupied by the capacitor will increase, thereby leading to the problem of increased chip size.

[0004] Therefore, how to provide a capacitor that can improve the electrostatic capacitance of the capacitor within a given area to achieve the required performance has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The present invention provides a NAND flash memory storage device and an electronic device, which solves the problem in the related art that the electrostatic capacity of a capacitor cannot be increased within a given area.

[0006] As a first aspect of the present invention, a NAND flash memory storage device is provided, comprising:

[0007] A semiconductor substrate, wherein the semiconductor substrate is divided into a storage area and a peripheral area, wherein the storage area is used to form a storage unit, and the peripheral area is used to form a peripheral circuit, and the peripheral circuit is used to drive the operation of the storage unit;

[0008] The peripheral circuit includes a plurality of hybrid transistor block structures formed on the semiconductor substrate, each hybrid transistor block structure including a first conductivity type transistor region and a second conductivity type transistor region;

[0009] The first-conductivity-type transistor region includes a first-conductivity-type transistor structure and a first-conductivity-type transistor parasitic structure. The second-conductivity-type transistor region includes a second-conductivity-type transistor structure and a second-conductivity-type transistor parasitic structure. The first-conductivity-type transistor structure and the second-conductivity-type transistor structure are symmetrically arranged. The first-conductivity-type transistor parasitic structure and the second-conductivity-type transistor parasitic structure are symmetrically arranged. The first-conductivity-type transistor structure and the first-conductivity-type transistor parasitic structure share the same second-conductivity-type electrode active layer. The second-conductivity-type transistor structure and the second-conductivity-type transistor parasitic structure share the same first-conductivity-type electrode active layer;

[0010] When connected to a voltage, the first-conductivity-type transistor structure can form a first group of capacitor structures, and the first-conductivity-type transistor parasitic structure can form a first group of parasitic capacitor structures when connected to a voltage. The capacitance of the first group of capacitor structures and the capacitance of the first group of parasitic capacitor structures form the capacitance of the first-conductivity-type transistor region;

[0011] When connected to a voltage, the second-conductivity-type transistor structure can form a second group of capacitor structures, and the second-conductivity-type transistor parasitic structure can form a second group of parasitic capacitor structures when connected to a voltage. The capacitance of the second group of capacitor structures and the capacitance of the second group of parasitic capacitor structures form the capacitance of the second-conductivity-type transistor region.

[0012] Further, the first-conductivity-type transistor structure includes a second-conductivity-type electrode active layer formed on the semiconductor substrate, a first-conductivity-type first input / output electrode layer formed on the surface of the second-conductivity-type electrode active layer and extending into the second-conductivity-type electrode active layer, and a first control electrode layer formed on the second-conductivity-type electrode active layer;

[0013] The first-conductivity-type transistor parasitic structure includes a second-conductivity-type electrode active layer formed on the semiconductor substrate, a second-conductivity-type first input / output electrode layer formed on the surface of the second-conductivity-type electrode active layer and extending into the second-conductivity-type electrode active layer, and a second control electrode layer formed on the second-conductivity-type electrode active layer;

[0014] The second-conductivity-type transistor structure includes a first-conductivity-type electrode active layer formed on the semiconductor substrate, a second-conductivity-type second input / output electrode layer formed on the surface of the first-conductivity-type electrode active layer and extending into the first-conductivity-type electrode active layer, and a first control electrode layer formed on the first-conductivity-type electrode active layer;

[0015] The parasitic structure of the second conductivity type transistor includes a first conductivity type electrode active layer formed on the semiconductor substrate, a first conductivity type second input / output electrode layer formed on the surface of the first conductivity type electrode active layer and extending towards the inside of the first conductivity type electrode active layer, and a second control electrode layer formed on the first conductivity type electrode active layer.

[0016] Further, the second conductivity type electrode active layer is respectively formed as the second conductivity type first bulk electrode terminal of the first conductivity type transistor structure and the second conductivity type second bulk electrode terminal of the first conductivity type transistor parasitic structure;

[0017] The first conductivity type first input / output electrode layer is formed as the first conductivity type first source electrode terminal and the first conductivity type first drain electrode terminal of the first conductivity type transistor structure, and the first control electrode layer on the second conductivity type electrode active layer is formed as the control gate electrode terminal of the first conductivity type transistor structure;

[0018] The second conductivity type first input / output electrode layer is formed as the second conductivity type first source electrode terminal and the second conductivity type first drain electrode terminal of the first conductivity type transistor parasitic structure, and the second control electrode layer on the second conductivity type electrode active layer is formed as the control gate electrode terminal of the first conductivity type transistor parasitic structure.

[0019] Further, when both the first conductivity type transistor structure and the first conductivity type transistor parasitic structure are connected to a voltage:

[0020] A voltage difference is formed between the first conductivity type first source electrode terminal and the control gate electrode terminal of the first conductivity type transistor structure, between the first conductivity type first drain electrode terminal and the control gate electrode terminal of the first conductivity type transistor structure, and between the second conductivity type first bulk electrode terminal and the control gate electrode terminal of the first conductivity type transistor structure to generate a first group of capacitance structures;

[0021] A voltage difference is formed between the second conductivity type first source electrode terminal and the control gate electrode terminal of the first conductivity type transistor parasitic structure, between the second conductivity type first drain electrode terminal and the control gate electrode terminal of the first conductivity type transistor parasitic structure, and between the second conductivity type second bulk electrode terminal and the control gate electrode terminal of the first conductivity type transistor parasitic structure to generate a first group of parasitic capacitance structures.

[0022] Further, the first source electrode terminal of the first conduction type, the first drain electrode terminal of the first conduction type, and the first bulk electrode terminal of the second conduction type are all connected to a high-level voltage, and the control gate electrode terminal of the first conduction type transistor structure is connected to a low-level voltage;

[0023] The first source electrode terminal of the second conduction type, the first drain electrode terminal of the second conduction type, and the second bulk electrode terminal of the second conduction type are all connected to a low-level voltage, and the control gate electrode terminal of the parasitic structure of the first conduction type transistor is connected to a high-level voltage.

[0024] Further, the first conduction type electrode active layer is respectively formed as the first bulk electrode terminal of the first conduction type of the second conduction type transistor structure and the second bulk electrode terminal of the first conduction type of the second conduction type transistor structure;

[0025] The second input / output electrode layer of the second conduction type is formed as the second source electrode terminal of the second conduction type and the second drain electrode terminal of the second conduction type of the second conduction type transistor structure, and the first control electrode layer on the first conduction type electrode active layer is formed as the control gate electrode terminal of the second conduction type transistor structure;

[0026] The second input / output electrode layer of the first conduction type is formed as the second source electrode terminal of the first conduction type and the second drain electrode terminal of the first conduction type of the parasitic structure of the second conduction type transistor, and the second control electrode layer on the first conduction type electrode active layer is formed as the control gate electrode terminal of the parasitic structure of the second conduction type transistor.

[0027] Further, when both the second conduction type transistor structure and the parasitic structure of the second conduction type transistor are connected to a voltage:

[0028] Voltage differences are formed between the second source electrode terminal of the second conduction type and the control gate electrode terminal of the second conduction type transistor structure, between the second drain electrode terminal of the second conduction type and the control gate electrode terminal of the second conduction type transistor structure, and between the first bulk electrode terminal of the first conduction type and the control gate electrode terminal of the second conduction type transistor structure to generate a second group of capacitor structures;

[0029] Voltage differences are formed between the second source electrode terminal of the first conduction type and the control gate electrode terminal of the parasitic structure of the second conduction type transistor, between the second drain electrode terminal of the first conduction type and the control gate electrode terminal of the parasitic structure of the second conduction type transistor, and between the second bulk electrode terminal of the first conduction type and the control gate electrode terminal of the parasitic structure of the second conduction type transistor to generate a second group of parasitic capacitance structures.

[0030] Further, the second source electrode terminal of the second conduction type, the second drain electrode terminal of the second conduction type, and the first bulk electrode terminal of the first conduction type are all connected to a low-level voltage, and the control gate electrode terminal of the second conduction type transistor structure is connected to a high-level voltage;

[0031] A high-level voltage is connected between the second source electrode terminal of the first conduction type, the second drain electrode terminal of the first conduction type, and the second bulk electrode terminal of the first conduction type, and the control gate electrode terminal of the parasitic structure of the second conduction type transistor is connected to a low-level voltage.

[0032] Further, when the first conduction type is N-type, the second conduction type is P-type; when the first conduction type is P-type, the second conduction type is N-type.

[0033] As another aspect of the present invention, an electronic device is provided, which includes the NAND flash memory device described above.

[0034] The NAND flash memory device provided by the present invention can maximize the area of the capacitor in a given area by additionally adding a parasitic structure within the same active layer area of the semiconductor substrate, thereby achieving the purpose of improving the integration degree of the storage device of the chip and the electrostatic capacitance of the capacitor without increasing the chip size. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and are used to explain the present invention together with the following specific embodiments, but do not constitute a limitation to the present invention.

[0036] Figure 1 It is a structural block diagram of the NAND flash memory device provided by the present invention.

[0037] Figure 2 It is a layout schematic diagram of the hybrid transistor block structure in the NAND flash memory device provided by the present invention.

[0038] Figure 3 It is a layout schematic diagram of the bulk electrode provided by the present invention.

[0039] Figure 4a Provided by the present invention Figure 2 The vertical structure schematic diagram of the P-type transistor parasitic structure N100 after cutting the A-A' area in

[0040] Figure 4b It is a cross-sectional view of the P-type transistor structure provided by the present invention.

[0041] Figure 5aProvided by the present invention Figure 2 Schematic diagram of the vertical structure of the parasitic structure P100 of the N-type transistor after cutting the B-B' region in

[0042] Figure 5b Cross-sectional view of the N-type transistor structure provided by the present invention Detailed implementation manners

[0043] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments

[0044] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices

[0046] In the prior art, with the reduction of the chip size and the increase of the integration degree of the storage device, capacitors with more capacity are required, that is, the capacitance value of the capacitor needs to be increased within a given area. However, currently, capacitors that achieve the required performance in a specific circuit field usually increase the area occupied by the capacitor, thereby causing an increase in the chip size

[0047] Based on this, in this embodiment, a NAND flash memory storage device is provided. As shown in Figure 1 and Figure 2 the NAND flash memory storage device 10 includes

[0048] A semiconductor substrate, which is divided into a storage area 110 and a peripheral area 120. The storage area is used to form storage units, and the peripheral area is used to form peripheral circuits. The peripheral circuits are used to drive the operation of the storage units

[0049] The peripheral circuit includes a plurality of hybrid transistor block structures 200 formed on the semiconductor substrate, and each hybrid transistor block structure 200 includes a first-conductivity-type transistor region 210 and a second-conductivity-type transistor region 220;

[0050] The first-conductivity-type transistor region 210 includes a first-conductivity-type transistor structure 211 and a first-conductivity-type transistor parasitic structure 212, the second-conductivity-type transistor region 220 includes a second-conductivity-type transistor structure 221 and a second-conductivity-type transistor parasitic structure 222, the first-conductivity-type transistor structure 211 and the second-conductivity-type transistor structure 221 are symmetrically arranged, the first-conductivity-type transistor parasitic structure 212 and the second-conductivity-type transistor parasitic structure 222 are symmetrically arranged, the first-conductivity-type transistor structure 211 and the first-conductivity-type transistor parasitic structure 212 share the same second-conductivity-type electrode active layer, and the second-conductivity-type transistor structure 221 and the second-conductivity-type transistor parasitic structure 222 share the same first-conductivity-type electrode active layer;

[0051] When connected to a voltage, the first-conductivity-type transistor structure 211 can form a first group of capacitor structures, and when connected to a voltage, the first-conductivity-type transistor parasitic structure 212 can form a first group of parasitic capacitor structures. The capacitance of the first group of capacitor structures and the capacitance of the first group of parasitic capacitor structures form the capacitance of the first-conductivity-type transistor region;

[0052] When connected to a voltage, the second-conductivity-type transistor structure 221 can form a second group of capacitor structures, and when connected to a voltage, the second-conductivity-type transistor parasitic structure 222 can form a second group of parasitic capacitor structures. The capacitance of the second group of capacitor structures and the capacitance of the second group of parasitic capacitor structures form the capacitance of the second-conductivity-type transistor region.

[0053] In an embodiment of the present invention, a first-conductivity-type transistor structure 211 and a first-conductivity-type transistor parasitic structure 212 are provided within a first-conductivity-type transistor region 210. The first-conductivity-type transistor parasitic structure 212 shares the same second-conductivity-type electrode active layer with the first-conductivity-type transistor structure 211. Specifically, it can be understood that the first-conductivity-type transistor parasitic structure 212 is disposed on the second-conductivity-type electrode active layer where the first-conductivity-type transistor structure 211 is located. That is, a first set of parasitic capacitance structures is formed without increasing the area of the first-conductivity-type transistor region 210, so that the first-conductivity-type transistor region 210 adds the capacitance of the first set of parasitic capacitance structures on the basis of the capacitance of the current first set of capacitance structures, achieving the purpose of increasing the capacitor capacitance within a given area.

[0054] Similarly, a second-conductivity-type transistor structure 221 and a second-conductivity-type transistor parasitic structure 222 are provided within a second-conductivity-type transistor region 220. The second-conductivity-type transistor parasitic structure 222 shares the same first-conductivity-type electrode active layer with the second-conductivity-type transistor structure 221. Specifically, it can be understood that the second-conductivity-type transistor parasitic structure 222 is disposed on the first-conductivity-type electrode active layer where the second-conductivity-type transistor structure 221 is located. That is, a second set of parasitic capacitance structures is formed without increasing the area of the second-conductivity-type transistor region 220, so that the second-conductivity-type transistor region 220 adds the capacitance of the second set of parasitic capacitance structures on the basis of the capacitance of the current second set of capacitance structures, achieving the purpose of increasing the capacitor capacitance within a given area.

[0055] Therefore, the NAND flash memory storage device provided by the embodiment of the present invention can maximize the area of the capacitor within a given area by additionally adding parasitic structures within the same active layer area of the semiconductor substrate, thereby achieving the purpose of improving the integration degree of the storage device and the electrostatic capacitance of the capacitor of the chip without increasing the chip size.

[0056] In an embodiment of the present invention, the first-conductivity-type transistor structure 211 includes a second-conductivity-type electrode active layer formed on the semiconductor substrate, a first-conductivity-type first input / output electrode layer formed on the surface of the second-conductivity-type electrode active layer and extending into the second-conductivity-type electrode active layer, and a first control electrode layer formed on the second-conductivity-type electrode active layer;

[0057] The parasitic structure 212 of the transistor of the first conduction type includes a second-conduction-type electrode active layer formed on the semiconductor substrate, a second-conduction-type first input / output electrode layer formed on the surface of the second-conduction-type electrode active layer and extending toward the inside of the second-conduction-type electrode active layer, and a second control electrode layer formed on the second-conduction-type electrode active layer;

[0058] The transistor structure 221 of the second conduction type includes a first-conduction-type electrode active layer formed on the semiconductor substrate, a second-conduction-type second input / output electrode layer formed on the surface of the first-conduction-type electrode active layer and extending toward the inside of the first-conduction-type electrode active layer, and a first control electrode layer formed on the first-conduction-type electrode active layer;

[0059] The parasitic structure 222 of the transistor of the second conduction type includes a first-conduction-type electrode active layer formed on the semiconductor substrate, a first-conduction-type second input / output electrode layer formed on the surface of the first-conduction-type electrode active layer and extending toward the inside of the first-conduction-type electrode active layer, and a second control electrode layer formed on the first-conduction-type electrode active layer.

[0060] It should be understood that the first-conduction-type transistor structure 211 and the parasitic structure 212 of the first-conduction-type transistor share the same second-conduction-type electrode active layer, that is, the parasitic structure 212 of the first-conduction-type transistor is arranged on the existing second-conduction-type electrode active layer to realize the first group of capacitive parasitic structures, and the capacitance capacity is improved without increasing the current chip area. The transistor structure 221 of the second conduction type and the parasitic structure 222 of the second conduction type share the same first-conduction-type electrode active layer, that is, the parasitic structure 222 of the second conduction type transistor is arranged on the existing first-conduction-type electrode active layer to realize the second group of capacitive parasitic structures, and the capacitance capacity is improved without increasing the current chip area.

[0061] Specifically, the second-conduction-type electrode active layer is respectively formed as the second-conduction-type first bulk electrode terminal of the first-conduction-type transistor structure and the second-conduction-type second bulk electrode terminal of the parasitic structure of the first-conduction-type transistor;

[0062] The first-conduction-type first input / output electrode layer is formed as the first-conduction-type first source electrode terminal and the first-conduction-type first drain electrode terminal of the first-conduction-type transistor structure, and the first control electrode layer on the second-conduction-type electrode active layer is formed as the control gate electrode terminal of the first-conduction-type transistor structure;

[0063] The first input / output electrode layer of the second conductivity type is formed as the first source electrode terminal of the second conductivity type and the first drain electrode terminal of the second conductivity type of the parasitic structure of the first conductivity type transistor, and the second control electrode layer on the second conductivity type electrode active layer is formed as the control gate electrode terminal of the parasitic structure of the first conductivity type transistor.

[0064] It should be noted that in the embodiments of the present invention, the bulk electrode can play a role in maintaining the threshold voltage of each device after different voltages are applied. For example Figure 3 The transistor structure includes a source electrode 1-1 that provides carriers, a drain electrode 1-2 that attracts carriers to a high electric field, a control gate electrode 1-3 that functions as a switch, and a bulk electrode 1-4 that fixes the body to stabilize the transistor channel. In normal operation, the bulk electrode of the N-type transistor is connected to 0V or VSS, that is, a low voltage, while the bulk electrode of the P-type transistor is connected to VDD, that is, a high voltage. Different voltages are applied to the above-mentioned bulk electrodes according to N-type and P-type devices, so as to play a role in maintaining the threshold voltage of each device.

[0065] Therefore, based on the role of the bulk electrode in maintaining the threshold voltage of the transistor operation, when laying out in the NAND flash memory device, the bulk electrode needs to be set within a safe distance that can satisfy the normal operation of the transistor. This safe distance can ensure that the threshold voltage adjustment is not affected when the transistor operates. This safe distance is usually within dozens of micrometers, for example, usually less than 30μm.

[0066] In the embodiments of the present invention, when both the first conductivity type transistor structure 211 and the first conductivity type transistor parasitic structure 212 are connected to a voltage:

[0067] Voltage differences are formed between the first source electrode terminal of the first conductivity type and the control gate electrode terminal of the first conductivity type transistor structure, between the first drain electrode terminal of the first conductivity type and the control gate electrode terminal of the first conductivity type transistor structure, and between the first bulk electrode terminal of the second conductivity type and the control gate electrode terminal of the first conductivity type transistor structure to generate a first group of capacitor structures;

[0068] Voltage differences are formed between the first source electrode terminal of the second conductivity type and the control gate electrode terminal of the first conductivity type transistor parasitic structure, between the first drain electrode terminal of the second conductivity type and the control gate electrode terminal of the first conductivity type transistor parasitic structure, and between the second bulk electrode terminal of the second conductivity type and the control gate electrode terminal of the first conductivity type transistor parasitic structure to generate a first group of parasitic capacitor structures.

[0069] In an embodiment of the present invention, when forming the first group of capacitor structures, the first source electrode terminal of the first conductivity type, the first drain electrode terminal of the first conductivity type, and the first bulk electrode terminal of the second conductivity type are all connected to a high-level voltage, and the control gate electrode terminal of the first conductivity type transistor structure is connected to a low-level voltage:

[0070] When forming the first group of parasitic capacitor structures, the first source electrode terminal of the second conductivity type, the first drain electrode terminal of the second conductivity type, and the second bulk electrode terminal of the second conductivity type are all connected to a low-level voltage, and the control gate electrode terminal of the first conductivity type transistor parasitic structure is connected to a high-level voltage.

[0071] It should be understood that, as Figure 2 shown, by routing the control gate electrode terminal of the first conductivity type transistor parasitic structure onto the second conductivity type electrode active layer that generates the first bulk electrode terminal of the second conductivity type of the first conductivity type transistor structure and the second bulk electrode terminal of the second conductivity type of the first conductivity type transistor parasitic structure, additional semiconductor devices are generated in the same area, that is, the first parasitic capacitor structure is formed, realizing the capacity improvement of the current capacitor structure.

[0072] It should be noted that in an embodiment of the present invention, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.

[0073] The embodiment of the present invention takes the first conductivity type as P type and the second conductivity type as N type as an example.

[0074] The P-type transistor parasitic structure can specifically be composed of a source electrode N41, a drain electrode N42, and a control gate electrode N4G of an N-type bulk electrode active layer.

[0075] In this structure, a high voltage (usually VDD) is applied to the N-type source electrode terminal N41 and drain electrode terminal N42, and a low voltage (usually VSS) is applied to the N-type control gate electrode terminal N4G, forming the first parasitic capacitor structure.

[0076] It should be noted that the high voltage is usually the supply voltage, for example, 5V; the low voltage can be, for example, the ground terminal, for example, 0V.

[0077] Specifically, after cutting the P-type transistor parasitic structure N100 in the P-type region along Figure 2 the A-A' region, the vertical structure schematic diagram is as Figure 4aAs shown, in the parasitic structure N100 of the P-type transistor, the control gate electrode N4G is placed on the N-type bulk electrode wiring N43 with a low doping concentration, resulting in a device composed of a highly doped N+-type source electrode terminal N41, a highly doped N+-type drain electrode terminal N42, and an N-type control gate electrode terminal N4G. Therefore, the P-type transistor structure can achieve a parasitic capacitance structure by additionally configuring the P-type transistor parasitic structure N100. Thus, when a low voltage VSS is applied to the N-type control gate electrode terminal N4G and a high voltage VDD is applied to the N+-type source electrode terminal N41 and the N+-type drain electrode terminal N42, three parasitic capacitor devices AC1, AC2, and AC3 can be realized, enabling the capacitance required for the semiconductor device to be obtained.

[0078] As Figure 4b shown, it is a cross-sectional view of the P-type transistor structure. The highly doped P+-type source electrode terminal 3-1, the highly doped P+-type drain electrode terminal 3-2, and the low-doped N-type bulk electrode terminal 3-4 are connected to the VDD voltage, and the control gate electrode terminal 3-3 of the P-type transistor structure is connected to the VSS voltage. Due to the voltage difference, the first group of capacitance structures C3, C1, and C2 are generated. Based on Figure 4a and Figure 4b the formed capacitance structure, the capacitance capacity of the first conductive type transistor region is the sum of the capacitance capacities of C3, C1, and C2 plus the capacitance capacities of the three parasitic capacitor devices AC1, AC2, and AC3. Therefore, the purpose of increasing the capacitance capacity is achieved on a given area.

[0079] It should be noted that within a certain interval (usually less than 30 μm) of the N-type bulk electrode wiring N43, a P-type transistor parasitic structure N100 with the Figure 4a structure as in the embodiment of the present invention can be generated, and a structure with the maximum increase in the electrostatic capacitance of the capacitor can be formed in a specific region or a specific circuit region required.

[0080] As a specific embodiment of the present invention, the first conductive type electrode active layer is respectively formed as the first conductive type first bulk electrode terminal of the second conductive type transistor structure and the first conductive type second bulk electrode terminal of the second conductive type transistor structure;

[0081] The second conductive type second input / output electrode layer is formed as the second conductive type second source electrode terminal and the second conductive type second drain electrode terminal of the second conductive type transistor structure, and the first control electrode layer on the first conductive type electrode active layer is formed as the control gate electrode terminal of the second conductive type transistor structure;

[0082] The first-conductivity-type second input / output electrode layer is formed as the first-conductivity-type second source electrode terminal and the first-conductivity-type second drain electrode terminal of the second-conductivity-type transistor parasitic structure, and the second control electrode layer on the first-conductivity-type electrode active layer is formed as the control gate electrode terminal of the second-conductivity-type transistor parasitic structure.

[0083] In an embodiment of the present invention, when both the second-conductivity-type transistor structure 221 and the second-conductivity-type transistor parasitic structure 222 are connected to a voltage:

[0084] A voltage difference is formed between the second-conductivity-type second source electrode terminal and the control gate electrode terminal of the second-conductivity-type transistor structure, between the second-conductivity-type second drain electrode terminal and the control gate electrode terminal of the second-conductivity-type transistor structure, and between the first-conductivity-type first bulk electrode terminal and the control gate electrode terminal of the second-conductivity-type transistor structure to generate a second group of capacitor structures;

[0085] A voltage difference is formed between the first-conductivity-type second source electrode terminal and the control gate electrode terminal of the second-conductivity-type transistor parasitic structure, between the first-conductivity-type second drain electrode terminal and the control gate electrode terminal of the second-conductivity-type transistor parasitic structure, and between the first-conductivity-type second bulk electrode terminal and the control gate electrode terminal of the second-conductivity-type transistor parasitic structure to generate a second group of parasitic capacitance structures.

[0086] In an embodiment of the present invention, when forming the second group of capacitor structures, the second-conductivity-type second source electrode terminal, the second-conductivity-type second drain electrode terminal, and the first-conductivity-type first bulk electrode terminal are all connected to a low-level voltage, and the control gate electrode terminal of the second-conductivity-type transistor structure is connected to a high-level voltage;

[0087] When forming the second group of parasitic capacitance structures, the first-conductivity-type second source electrode terminal, the first-conductivity-type second drain electrode terminal, and the first-conductivity-type second bulk electrode terminal are all connected to a high-level voltage, and the control gate electrode terminal of the second-conductivity-type transistor parasitic structure is connected to a low-level voltage.

[0088] Specifically, as Figure 2 shown, in an embodiment of the present invention, taking the first conductivity type as P-type and the second conductivity type as N-type as an example, the N-type transistor parasitic structure may specifically be composed of a source electrode terminal P41 of a P-type bulk electrode active layer, a drain electrode terminal P42 of the P-type bulk electrode active layer, and a control gate electrode terminal P4G of the bulk electrode active layer.

[0089] In the transistor parasitic structure of the above structure, a low voltage (usually VSS) is applied to the source electrode terminal P41 of the P-type bulk electrode active layer and the drain electrode terminal P42 of the P-type bulk electrode active layer, and a high voltage (usually VDD) is applied to the control gate electrode terminal P4G of the bulk electrode active layer, forming a second parasitic capacitance structure.

[0090] It should be noted that the high voltage is usually the supply voltage, for example, 5V; the low voltage can be, for example, the ground terminal, for example, 0V.

[0091] Specifically, the vertical schematic diagram after cutting the N-type transistor parasitic structure P100 in the N-type region along Figure 2 the B-B' region is as shown in Figure 5a In this N-type transistor parasitic structure P100, the control gate electrode is placed on the P-type bulk electrode wiring P43 with a low doping concentration, and the resulting electrodes are composed of a P+-type source electrode terminal P41 with a high doping concentration, a P+-type drain electrode terminal P42 with a high doping concentration, and a P-type control gate electrode terminal P4G. Therefore, the N-type transistor structure can achieve a parasitic capacitance structure by additionally configuring the N-type transistor parasitic mechanism P100. When a low voltage VSS is applied to the P-type control gate electrode terminal P4G and a high voltage VDD is applied to the P+-type source electrode terminal P41 and the P+-type drain electrode terminal P42, three parasitic capacitor devices AC4, AC5, and AC6 can be formed, thereby obtaining the capacitance required for the semiconductor device.

[0092] As shown in Figure 5b the high-doping-concentration N+-type source electrode terminal 3-6, the high-doping-concentration N+-type drain electrode terminal 3-7, and the low-doping-concentration P-type bulk electrode terminal 3-8 are connected to the VSS voltage, and the control gate electrode terminal 3-5 of the N-type transistor structure is connected to the VDD voltage. Due to the voltage difference, a second group of capacitance structures C4, C5, and C6 are generated. Based on Figure 5a and Figure 5b the formed capacitance structure, it can be seen that the capacitance of the second-conductive-type transistor region is the sum of the capacitances of C4, C5, and C6 plus the capacitances of the three parasitic capacitor devices AC4, AC5, and AC6, so as to achieve the purpose of increasing the capacitance in a given area.

[0093] It should be noted that within a certain interval (usually less than 30μm) of the P-type bulk electrode wiring P43, an N-type transistor parasitic structure P100 with the structure as in the embodiment of the present invention is generated, and a structure with the largest electrostatic capacitance of the capacitor can be formed in a specific region or a required specific circuit region. Figure 5a

[0094] In summary, the NAND flash memory storage device provided by the present invention can increase the capacitance capacity of the current transistor structure by adding a transistor parasitic structure to the established areas of the current first-conductive-type electrode active layer and the second-conductive-type electrode active layer. Furthermore, a capacitor with the required performance can be realized within the current circuit area, thereby improving the security of chip operation and achieving the purpose of increasing the electrostatic capacitance of the capacitor without increasing the chip size.

[0095] As another aspect of the present invention, an electronic device is provided, which includes the NAND flash memory storage device described above.

[0096] In the embodiment of the present invention, since the electronic device adopts the above NAND flash memory storage device, by additionally adding a parasitic structure within the same active layer area of the semiconductor substrate, the area of the capacitor can be maximized on the established area, thereby achieving the purpose of increasing the integration degree of the storage device of the chip and the electrostatic capacitance of the capacitor without increasing the chip size. Furthermore, the competitive advantage of the NAND flash memory storage device can be improved. Similarly, the electronic device adopting this NAND flash memory storage device has the advantages of high integration degree and high electrostatic capacitance.

[0097] Specifically, the electronic device may specifically include a communication device or other electronic devices that need to use a storage startup code, such as a set-top box, a smart camera, and a smart home, etc.

[0098] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A NAND flash memory storage device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate is divided into a storage area and a peripheral area, wherein the storage area is used to form a storage unit, and the peripheral area is used to form a peripheral circuit, and the peripheral circuit is used to drive the operation of the storage unit; The peripheral circuit includes a plurality of hybrid transistor block structures formed on the semiconductor substrate, each hybrid transistor block structure including a first conductivity type transistor region and a second conductivity type transistor region; The first conductive type transistor region includes a first conductive type transistor structure and a first conductive type transistor parasitic structure, the second conductive type transistor region includes a second conductive type transistor structure and a second conductive type transistor parasitic structure, the first conductive type transistor structure and the second conductive type transistor parasitic structure are symmetrically arranged, the first conductive type transistor parasitic structure and the second conductive type transistor parasitic structure are symmetrically arranged, the first conductive type transistor structure and the first conductive type transistor parasitic structure share the same second conductive type electrode active layer, and the second conductive type transistor structure and the second conductive type transistor parasitic structure share the same first conductive type electrode active layer; The first conductive type transistor structure can form a first group of capacitor structures when connected to a voltage, and the first conductive type transistor parasitic structure can form a first group of parasitic capacitor structures when connected to a voltage, and the capacitance of the first group of capacitor structures and the capacitance of the first group of parasitic capacitor structures form the capacitance of the first conductive type transistor region; The second conductive type transistor structure can form a second group of capacitor structures when connected to a voltage, and the second conductive type transistor parasitic structure can form a second group of parasitic capacitor structures when connected to a voltage, and the capacitance of the second group of capacitor structures and the capacitance of the second group of parasitic capacitor structures form the capacitance of the second conductive type transistor region; The first conductive type transistor structure includes a second conductive type electrode active layer formed on the semiconductor substrate, a first conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a first control electrode layer formed on the second conductive type electrode active layer; The first conductive type transistor parasitic structure includes a second conductive type electrode active layer formed on the semiconductor substrate, a second conductive type first input-output electrode layer formed on the surface of the second conductive type electrode active layer and extending toward the inside of the second conductive type electrode active layer, and a second control electrode layer formed on the second conductive type electrode active layer; The second conductive type transistor structure includes a first conductive type electrode active layer formed on the semiconductor substrate, a second conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the inside of the first conductive type electrode active layer, and a first control electrode layer formed on the first conductive type electrode active layer; The second conductive type transistor parasitic structure includes a first conductive type electrode active layer formed on the semiconductor substrate, a first conductive type second input-output electrode layer formed on the surface of the first conductive type electrode active layer and extending toward the interior of the first conductive type electrode active layer, and a second control electrode layer formed on the first conductive type electrode active layer.

2. The NAND flash memory storage device according to claim 1, wherein: The second conductive type electrode active layer is formed as a second conductive type first bulk electrode terminal of the first conductive type transistor structure and a second conductive type second bulk electrode terminal of the first conductive type transistor parasitic structure respectively; The first conductive type first input-output electrode layer is formed as a first conductive type first source electrode terminal and a first conductive type first drain electrode terminal of the first conductive type transistor structure, and the first control electrode layer on the second conductive type electrode active layer is formed as a control gate electrode terminal of the first conductive type transistor structure; The second conductive type first input-output electrode layer is formed as the second conductive type first source electrode terminal and the second conductive type first drain electrode terminal of the first conductive type transistor parasitic structure, and the second control electrode layer on the second conductive type electrode active layer is formed as the control gate electrode terminal of the first conductive type transistor parasitic structure.

3. The NAND flash memory storage device according to claim 2, wherein: When the first conductive type transistor structure and the first conductive type transistor parasitic structure are both connected to a voltage: A voltage difference is formed between the first conductive type first source electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, between the first conductive type first drain electrode terminal and the control gate electrode terminal of the first conductive type transistor structure, and between the second conductive type first bulk electrode terminal and the control gate electrode terminal of the first conductive type transistor structure to generate a first group of capacitor structures; A voltage difference is formed between the first source electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, between the first drain electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor, and between the second bulk electrode terminal of the second conductive type and the control gate electrode terminal of the parasitic structure of the first conductive type transistor to generate a first group of parasitic capacitance structures.

4. The NAND flash memory storage device according to claim 3, wherein: The first conductive type first source electrode terminal, the first conductive type first drain electrode terminal and the second conductive type first bulk electrode terminal are all connected to a high level voltage, and the control gate electrode terminal of the first conductive type transistor structure is connected to a low level voltage; The second conductivity type first source electrode terminal, the second conductivity type first drain electrode terminal and the second conductivity type second bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the first conductivity type transistor parasitic structure is connected to a high level voltage.

5. The NAND flash memory storage device according to claim 1, wherein: The first conductive type electrode active layer is formed as a first conductive type first bulk electrode terminal of the second conductive type transistor structure and a first conductive type second bulk electrode terminal of the second conductive type transistor structure respectively; The second conductive type second input-output electrode layer is formed as a second conductive type second source electrode terminal and a second conductive type second drain electrode terminal of the second conductive type transistor structure, and the first control electrode layer on the first conductive type electrode active layer is formed as a control gate electrode terminal of the second conductive type transistor structure; The first conductive type second input-output electrode layer forms a first conductive type second source electrode terminal and a first conductive type second drain electrode terminal of the second conductive type transistor parasitic structure, and the second control electrode layer on the first conductive type electrode active layer forms a control gate electrode terminal of the second conductive type transistor parasitic structure.

6. The NAND flash memory storage device according to claim 5, characterized in that: When the second conductive type transistor structure and the second conductive type transistor parasitic structure are both connected to a voltage: a voltage difference is formed between the second conductive type second source electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, between the second conductive type second drain electrode terminal and the control gate electrode terminal of the second conductive type transistor structure, and between the first conductive type first bulk electrode terminal and the control gate electrode terminal of the second conductive type transistor structure to generate a second group of capacitor structures; A voltage difference is formed between the second source electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, between the second drain electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor, and between the second bulk electrode terminal of the first conductive type and the control gate electrode terminal of the parasitic structure of the second conductive type transistor to generate a second group of parasitic capacitance structures.

7. The NAND flash memory storage device according to claim 6, wherein: The second conductive type second source electrode terminal, the second conductive type second drain electrode terminal and the first conductive type first bulk electrode terminal are all connected to a low level voltage, and the control gate electrode terminal of the second conductive type transistor structure is connected to a high level voltage; The first conductive type second source electrode terminal, the first conductive type second drain electrode terminal and the first conductive type second bulk electrode terminal are all connected to a high level voltage, and the control gate electrode terminal of the second conductive type transistor parasitic structure is connected to a low level voltage.

8. The NAND flash memory storage device according to any one of claims 1 to 7, characterized in that: When the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.

9. An electronic device, characterized in that: A NAND flash memory storage device comprising any one of claims 1 to 8.

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