Method for manufacturing memory device

Abstract

The invention relates to a method for manufacturing a memory device. The fabrication techniques described herein may facilitate simultaneous build-up of two or more layers of memory cells disposed in a cross-point architecture. Each memory cell layer may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of the first access lines and the second access lines. The fabrication techniques may use a pattern of vias formed at the top layer of the composite stack, thereby may facilitate building a 3D memory array within the composite stack using a reduced number of processing steps. The manufacturing techniques may also be adapted to form a slot region where the 3D memory array may be coupled with other components of the memory device.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with application date of March 25, 2019, application number 201980027977.3, and invention name “Method for Manufacturing Memory Device”.

[0003] Cross Reference

[0004] This patent application claims priority to PCT Application No. PCT / US2019 / 023887, filed by CASTRO et al. on March 25, 2019, entitled “CROSS-POINT MEMORY ARRAY AND RELATED FABRICATION TECHNIQUES,” which claims priority to U.S. Patent Application No. 15 / 961,540, filed by CASTRO et al. on April 24, 2018, entitled “CROSS-POINT MEMORY ARRAY AND RELATED FABRICATION TECHNIQUES,” each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety.

[0005] The technical field relates to cross-point memory arrays and related manufacturing techniques. Background Art

[0006] The following relates generally to forming memory arrays, and more particularly to cross-point memory arrays and related fabrication techniques.

[0007] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, usually represented as a logical "1" or a logical "0". In other systems, more than two states can be stored. To access the stored information, a component of the electronic device can read or sense the stored states in the memory device. To store information, a component of the electronic device can write or program the states in the memory device.

[0008] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may include volatile memory cells or non-volatile memory cells. Non-volatile memory cells can maintain their stored logic state for a long period of time, even in the absence of external power. Volatile memory cells may lose their stored state over time unless they are periodically refreshed by an external power source.

[0009] Generally, improving memory devices may include increasing memory cell density, improving read / write speeds, enhancing reliability, extending data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. It may be desirable to build more memory cells per unit area to increase memory cell density and reduce the cost per bit without increasing the size of the memory device. It may also be desirable to have improved techniques (e.g., faster, lower cost) for manufacturing memory devices, including memory devices with increased memory cell density. Summary of the invention

[0010] A method is described. The method may include: forming a plurality of vias through a top layer of a stack, the stack including a first dielectric material at a first layer; forming a first trench in the first dielectric material, the first trench aligned with the plurality of vias; filling the first trench with an electrode material; forming a second trench narrower than the first trench in the electrode material within the first trench; and filling the second trench with the first dielectric material.

[0011] An apparatus is described. The apparatus may include: an upper layer of a stack, the upper layer including a plurality of holes each having a first width; a first electrode layer within the stack, the first electrode layer including a first electrode and a second electrode; and a dielectric channel aligned with the plurality of holes and separating the first electrode from the second electrode by a first distance greater than the first width.

[0012] Another method is described. The method may include: forming a through-hole extending through a stack to a conductive element, the stack including a target electrode; filling the through-hole with a conductive material; removing a portion of the conductive material from the through-hole to expose a dielectric buffer interposed between the through-hole and the target electrode; removing the dielectric buffer to expose the target electrode; and filling the through-hole with the conductive material to couple the target electrode to the conductive element.

[0013] Another apparatus is described. The apparatus may include: a stack including an electrode layer and a memory layer; a conductive element in contact with the stack; a conductive plug extending through the stack and coupled with the conductive element, the conductive plug having a first width at the memory layer and a second width at the electrode layer, the second width being greater than the first width; and a first electrode at the electrode layer, the first electrode coupled with the conductive plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Exemplary diagrams illustrating a memory device including a three-dimensional array of memory cells supporting a cross-point memory array and related fabrication techniques in accordance with embodiments of the present invention.

[0015] Figure 2 An example of a three dimensional memory array is described that supports a cross point memory array and related fabrication techniques according to embodiments of the present invention.

[0016] Figures 3A to 3C Exemplary fabrication techniques supporting cross-point memory arrays and related fabrication techniques in accordance with embodiments of the present invention are described.

[0017] Figures 4A to 4B Exemplary via patterns and structures that support cross-point memory arrays and related fabrication techniques in accordance with embodiments of the present invention are described.

[0018] Figures 5 to 7 Example methods of forming a three-dimensional cross-point memory array structure that supports a cross-point memory array and related fabrication techniques in accordance with embodiments of the present invention are described.

[0019] Figure 8 Exemplary via patterns and structures that support cross-point memory arrays and related fabrication techniques in accordance with embodiments of the present invention are described.

[0020] Figures 9 to 12 An example of a 3D cross point memory array and related fabrication techniques supporting a cross point memory array according to an embodiment of the present invention is described.

[0021] Fig.13 An exemplary layout of a socket area that supports a cross-point memory array and related manufacturing techniques according to embodiments of the present invention is described.

[0022] Fig.14 An example method of making connections in a socket region supporting a cross-point memory array and related manufacturing techniques according to embodiments of the present invention is described.

[0023] Figures 15 to 20 Methods of supporting cross-point memory arrays and related fabrication techniques according to embodiments of the present invention are described. DETAILED DESCRIPTION

[0024] Building more memory cells per unit area can increase the area density of memory cells within the memory device. The increased area density of memory cells can contribute to a lower per-bit cost and / or larger memory capacity at a fixed cost for the memory device. The three-dimensional (3D) integration of two or more two-dimensional (2D) memory cell arrays can increase the area density while also alleviating the difficulties associated with reducing the memory cells of various feature sizes. In some cases, a 2D memory cell array may be referred to as a memory cell layer, and the 3D integration of multiple memory cell layers may include repeated processing steps associated with building a single memory cell layer. For example, when each successive layer of memory cells is built on top of any previously built memory cell layer, at least some of the steps for building a memory cell layer may be repeated multiple times. For example, due to a relatively large amount of light shielding and other processing steps, such repetition of processing steps may cause increased manufacturing costs and may thereby deviate from the benefits that may otherwise be associated with 3D integration.

[0025] The techniques, methods, and related devices described herein may involve using a pattern of vias (e.g., access vias) formed at a top layer of a composite stack to facilitate the simultaneous construction of two or more memory cell layers along with associated structures (e.g., electrodes), which may facilitate the construction of a 3D memory device within a composite stack while using a reduced number of processing steps (e.g., light shielding steps). For example, the techniques, methods, and related devices described herein may provide for the formation of various structures (e.g., electrodes, memory cells, dielectric buffers, etc.) in a lower layer, which may be referred to as a buried layer, by selectively removing and replacing materials originally included at a buried layer based on a pattern of vias. Furthermore, the techniques, methods, and related devices described herein may facilitate the simultaneous formation of similar structures at multiple buried layers, thereby reducing the number of light shielding or other processing steps associated with manufacturing a 3D memory device, which may reduce the manufacturing cost of the 3D memory device and produce other benefits that may be understood by a person of ordinary skill in the art. As used herein, a via may refer to an opening or an opening that is later filled with a material that may be non-conductive.

[0026] The techniques, methods, and related devices described herein may be adapted to construct multiple memory cell layers disposed in a cross-point architecture. For example, each memory cell layer in the cross-point architecture may include a plurality of first access lines (e.g., word lines) in a first plane and a plurality of second access lines (e.g., bit lines) in a second plane, the first access lines and the second access lines extending in different directions—e.g., the first access lines may be substantially perpendicular to the second access lines. Each topological intersection of the first access lines and the second access lines may correspond to a memory cell. Thus, a memory cell layer in the cross-point architecture may include a memory array having a plurality of memory cells disposed at topological intersections of the access lines (e.g., a 3D grid structure of the access lines).

[0027] Various memory technologies may include various forms of memory components that may be suitable for a cross-point architecture (e.g., resistive components in phase change memory (PCM) technology or conductive bridging random access memory (CBRAM) technology, or capacitive components in ferroelectric random access memory (FeRAM) technology). In some cases, a memory cell in a cross-point architecture may include a selection component (e.g., a thin film switch device) and a memory component. In other cases, a memory cell in a cross-point architecture may not require a separate selection component - for example, the memory cell may be a self-selecting memory cell.

[0028] Techniques, methods, and related devices described herein may involve constructing a set of first access lines in a first layer of a composite stack and another set of second access lines in a second layer, the composite stack comprising the first layer and the second layer. The first access line and the second access line may intersect in a topological manner such that each intersection between the first access line and the second access line may include a space occupied by a memory component. For example, the composite stack may be configured to include a memory layer between the first layer and the second layer. The first layer may include a first dielectric material, and a portion of the first dielectric material may be replaced with a conductive material (e.g., an electrode material) to form a set of first access lines at the first layer. Similarly, another set of first access lines may be formed at the second layer according to the manufacturing techniques described herein.

[0029] In order to establish a set of first access lines at the first layer, a set of first through holes formed at the top layer of the stack can be used to form a through hole through the stack. The first through holes can be arranged in a row in a first direction (e.g., a horizontal direction within a plane). The through holes can provide access to a first dielectric material of the first layer located below the top layer. An isotropic etching step that selectively removes a portion of the first dielectric material through the through holes can establish a series of cavities at the first layer. When identical cavities (e.g., adjacent cavities) overlap, consistent cavities can merge to form a first channel at the first layer. Subsequently, a conductive material (e.g., an electrode material) can fill the first channel at the first layer through the through holes.

[0030] Next, a second trench may be formed in the electrode material within the first trench using the same set of first vias (and associated through-vias). Subsequently, the dielectric material may fill the second trench. The width of the second trench may be less than the width of the first trench, and thus a portion of the electrode material may remain along the edge of the first trench, thereby forming a strip (or elongated loop or track) of electrode material formed at the first layer. The strip of electrode material may then be cut (e.g., the shorter ends of the loop may be removed or otherwise separated from the long sides of the loop), thereby forming a set of first access lines (e.g., a set of word lines in a horizontal direction within a plane). One or more sets of first access lines (e.g., one or more sets of word lines, each set of word lines formed at a respective first layer) may be formed simultaneously using manufacturing techniques where the stack includes one or more first layers.

[0031] Similar processing steps may be repeated for building a set of second access lines at the second layer. The set of second vias may be arranged in a row in a different direction (e.g., a vertical direction within a plane) than the set of first vias, such that the second vias may be used to form a set of second access lines at the second layer that extend in a different direction than the first access lines (e.g., a set of bit lines at the second layer, where the bit lines in the set of bit lines are orthogonal to the word lines in the set of word lines at the first layer). One or more sets of second access lines (e.g., one or more sets of bit lines, each set of bit lines formed at the second layer) may be formed simultaneously using the manufacturing techniques described herein where the stack includes one or more second layers.

[0032] As described above, the composite stack may include a memory layer between the first layer and the second layer. In some cases, the memory layer included in the initial stack includes a thin sheet of memory material (e.g., a chalcogenide material). In other cases, the memory layer included in the initial stack may include a placeholder material (e.g., a dielectric material), a portion of which may be replaced with a memory material later in the manufacturing process (e.g., after forming a 3D grid structure for access lines in other layers of the stack).

[0033] When the memory layer included in the initial stack includes a thin sheet of memory material, the thin sheet of memory material can be modified by subsequent processing steps for forming a 3D cross-point array structure. In some cases, the thin sheet of memory material can be perforated with a plurality of dielectric plugs (e.g., through holes filled with dielectric material). The pattern of the plurality of dielectric plugs can correspond to the pattern of the first through hole and the second through hole-that is, the plurality of dielectric plugs can be the result of forming a first access line (e.g., a word line) using the first through hole and forming a second access line (e.g., a bit line) using the second through hole. In other cases, the thin sheet of memory material can be segmented into a plurality of memory material elements by forming a channel in the memory material using the first through hole and the second through hole. In some cases, each memory material element can be in the shape of a 3D rectangle. In addition, each memory element can also be coupled to at least four electrodes (e.g., two electrodes above and two electrodes below), thereby producing four memory cells per memory material element.

[0034] When the memory layer included in the initial stack includes a placeholder material (e.g., a dielectric material), the set of first through-holes or the set of second through-holes can be used to form tracks (e.g., strips) of memory material within the placeholder material at the memory layer. The processing steps associated with forming the strips of memory material at the memory layer can be similar to the processing steps associated with forming the strips of electrode material at the first (or second) layer, but wherein the first trench is filled with memory material (e.g., compared to being filled with electrode material). After the strips of memory material are formed at the memory layer (e.g., using the first through-holes), the strips of memory material can be segmented into a plurality of memory material elements by forming trenches using other sets of through-holes (e.g., using the second through-holes), wherein the trenches intersect the strips of memory material and thus divide the strips of memory material into a plurality of discrete memory material elements. In some cases, each memory material element can be in the shape of a 3D strip. In addition, each memory element can also be coupled with at least three electrodes (e.g., two electrodes above and one electrode below, or vice versa), thereby resulting in two memory cells per memory material element.

[0035] In some cases, when a memory layer included in the initial stack includes a placeholder material (e.g., a dielectric material), a set of common vias (e.g., a plurality of vias, each of which may be part of both a set of first vias arranged in a row in a first direction and a set of second vias arranged in a row in a second direction) may be used to form a set of 3D disks of memory material at the memory layer, wherein each common via is used to form one 3D disk of memory material at the memory layer. Subsequently, each of the 3D disks of memory material may be segmented into four discrete memory material elements using a set of first vias and a set of second vias including corresponding common vias. For example, the set of first vias may be used to form a first channel that divides (e.g., bisects) the 3D disk of memory material in a first direction, and the set of second vias may be used to form a second channel that divides (e.g., bisects) the 3D disk of memory material in a second direction. Each of the four discrete memory material elements may have a curved surface that may correspond to an outer surface of the 3D disk that forms the four discrete memory material elements. In some cases, each of the four discrete memory material elements may be in the shape of a 3D wedge (e.g., a fan). In addition, each memory element may be coupled with at least two electrodes (e.g., one electrode above and one electrode below), resulting in one memory cell per memory material element.

[0036] A subset of the first and second vias may be used in a socket region of a memory device. In the context of a 3D cross-point memory array architecture, the socket region may include structures configured to provide electrical connections between access lines of the memory array and other components of the memory device (e.g., decoders, sensing components). In some cases, the socket region may include structures having gaps for electrical isolation purposes.

[0037] In some cases, a subset of the first and second vias can be used to create such a gap in a target electrode (e.g., an access line, such as a word line or a bit line) by isotropically etching a portion of the target electrode material at the electrode layer. In some cases, a photomask having openings can be used to create such a gap by anisotropically etching through the target electrode material.

[0038] To make connections between access lines and other components of the memory device, a subset of the first or second vias may be used to form a through-hole extending through the stack. The through-hole may be filled with a conductive material, and the etching step may remove a portion of the conductive material to expose a dielectric buffer at the target layer. The dielectric buffer may correspond to a dielectric material that may be used to fill a second trench (e.g., a trench at a point surrounded by a band of electrode material) after partially removing electrode material from the first trench. The dielectric buffer may be removed, and the conductive material may fill the space in the through-hole to electrically couple the target electrode material at the target layer to nodes of other components of the memory device. Thus, a socket region including gaps and interconnects may be formed using a pattern of the first and second vias.

[0039] Features of the invention introduced above are further described below in the context of a memory array configured with a cross-point architecture. Specific examples of structures and techniques for fabricating a cross-point memory array are then described. These and other features of the invention are further illustrated by and described with reference to apparatus diagrams, methods of forming diagrams, and flow diagrams relating to a cross-point memory array and related fabrication techniques.

[0040] Figure 1 An example memory element 100 is illustrated that supports a cross-point memory array and related fabrication techniques in accordance with embodiments of the present invention. The memory device 100 may also be referred to as an electronic memory apparatus. Figure 1 1 is an illustrative representation of various components and features of memory device 100. Thus, it should be understood that the components and features of memory device 100 are shown to illustrate functional interrelationships rather than their actual physical locations within memory device 100. Figure 1 In the illustrative example of , the memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some embodiments, each memory cell 105 is programmable to store two states, which are represented as logic 0 and logic 1. In some embodiments, the memory cell 105 can be configured to store more than two logical states. In some embodiments, the memory cell 105 can include a self-select memory cell. It should be understood that the memory cell 105 can also include another type of memory cell - for example, a 3D XPoint TM Memory cells, PCM cells including storage components and selection components, CBRAM cells, FeRAM cells. Although included in Figure 1 Some elements in the drawings are labeled with numerical indicators, while other corresponding elements are not labeled, but are the same or will be understood to be similar in an effort to improve visibility and clarity of the features depicted.

[0041] The 3D memory array 102 may include two or more two-dimensional (2D) memory arrays formed on top of each other. This may increase the number of memory cells that may be placed or built on a single die or substrate compared to a single 2D array, which in turn may reduce production costs or increase the performance of the memory device, or both. Figure 1 In the example depicted in , the memory array 102 includes two levels of memory cells 105 (e.g., memory cells 105-a and memory cells 105-b) and can thus be considered a 3D memory array; however, the number of levels may not be limited to two, and other examples may include additional levels. Each level may be aligned or positioned so that the memory cells 105 may be aligned with each other (fully aligned, overlapping, or substantially aligned) across each level, thereby forming a memory cell stack 145.

[0042] In some embodiments, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. Both word lines 110 and bit lines 115 may also be generally referred to as access lines. In addition, an access line may serve as a word line 110 for one or more memory cells 105 at one layer of the memory device 100 (e.g., for memory cells 105 below the access line), and may serve as a bit line 115 for one or more memory cells 105 at another layer of the memory device (e.g., for memory cells 105 above the access line). Therefore, references to word lines and bit lines, or the like, are interchangeable without loss of understanding or operation. Word lines 110 and bit lines 115 may be substantially perpendicular to each other and may support an array of memory cells.

[0043] In general, one memory cell 105 may be located at the intersection of two access lines, such as a word line 110 and a bit line 115. This intersection may be referred to as the address of the memory cell 105. A target memory cell 105 may be a memory cell 105 located at the intersection of a powered (e.g., activated) word line 110 and a powered (e.g., activated) bit line 115; that is, the word line 110 and the bit line 115 may both be powered in order to read or write the memory cell 105 at their intersection. Other memory cells 105 that are in electronic communication with (e.g., connected to) the same word line 110 or bit line 115 may be referred to as non-target memory cells 105.

[0044] like Figure 1 , two memory cells 105 in a memory cell stack 145 may share a common conductor, such as a bit line 115. That is, the bit line 115 may be coupled with an upper memory cell 105-b and a lower memory cell 105-a. Other configurations may be possible, for example, a third layer (not shown) may share a word line 110 with an upper memory cell 105-b.

[0045] In some cases, an electrode may couple the memory cell 105 to a word line 110 or a bit line 115. The term electrode may refer to an electrical conductor, and may include a trace, wire, conductor, conductive layer, etc. that provides a conductive path between elements or components of the memory device 100. Thus, the term electrode may refer to an access line, such as a word line 110 or a bit line 115, in some cases, and may refer to an additional conductive element that serves as an electrical contact between the access line and the memory cell 105. In some embodiments, the memory cell 105 may include a chalcogenide material positioned between a first electrode and a second electrode. The first electrode may couple the chalcogenide material to the word line 110, and the second electrode may couple the chalcogenide material to the bit line 115. The first electrode and the second electrode may be the same material (e.g., carbon) or different materials. In other embodiments, the memory cell 105 may be directly coupled to one or more access lines, and electrodes other than the access lines may be omitted.

[0046] Operations such as reading and writing can be performed on the memory cell 105 by activating or selecting the word line 110 and the digit line 115. Activating or selecting the word line 110 or the digit line 115 can include applying a voltage to the corresponding line. The word line 110 and the digit line 115 can be made of a conductive material such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, a conductively doped semiconductor or other conductive material, alloy, compound, etc.

[0047] In some architectures, the logic storage device of the cell (e.g., a resistive component in a CBRAM cell, a capacitive component in a FeRAM cell) can be electrically isolated from the digital line by a selection component. The word line 110 can be connected to the selection component and can control the selection component. For example, the selection component can be a transistor, and the word line 110 can be connected to the gate of the transistor. Alternatively, the selection component can be a variable resistance component, which can include a chalcogenide material. Activating the word line 110 can create an electrical connection or closed circuit between the logic storage device of the memory cell 105 and its corresponding digital line 115. The digital line can then be accessed to read or write the memory cell 105. After selecting the memory cell 105, the resulting signal can be used to determine the stored logic state. In some cases, the first logic state can correspond to no current or a negligible small current passing through the memory cell 105, while the second logic state can correspond to a limited current.

[0048] In some cases, memory cell 105 may include a self-select memory cell having two terminals, and a separate selection component may be omitted. Thus, one terminal of the self-select memory cell may be electrically connected to word line 110, and the other terminal of the self-select memory cell may be electrically connected to digit line 115.

[0049] Access to the memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 may receive a column address from the memory controller 140 and activate the appropriate digit line 115. For example, the memory array 102 may include a plurality of word lines 110 labeled WL_1 to WL_M, and a plurality of digit lines 115 labeled DL_1 to DL_N, where M and N depend on the size of the array. Thus, by activating a word line 110 and a digit line 115, such as WL_2 and DL_3, the memory cells 105 may be accessed at their intersections.

[0050] After access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, a voltage may be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115) and the presence of the resulting current through the memory cell 105 may depend on the applied voltage and threshold voltage of the memory cell 105. In some cases, more than one voltage may be applied. In addition, if the applied voltage does not produce current, other voltages may be applied until the current is detected by the sensing component 125. By evaluating the voltage that produces the current, the stored logical state of the memory cell 105 may be determined. In some cases, the magnitude of the voltage may gradually increase until the current is detected. In other cases, predetermined voltages may be applied in sequence until the current is detected. Similarly, a current may be applied to the memory cell 105, and the magnitude of the voltage used to produce the current may depend on the resistance or threshold voltage of the memory cell 105.

[0051] In some cases, the memory cell 105 (e.g., a self-selected memory cell) may include a chalcogenide material. The chalcogenide material of the self-selected memory cell may remain in an amorphous state during the operation of the self-selected memory cell. In some cases, operating the self-selected memory cell may include applying programming pulses of various shapes to the self-selected memory cell to determine a specific threshold voltage of the self-selected memory cell-that is, the threshold voltage of the self-selected memory cell can be modified by changing the shape of the programming pulse, thereby changing the local composition of the chalcogenide material in the amorphous state. The specific threshold voltage of the self-selected memory cell can be determined by applying read pulses of various shapes to the self-selected memory cell. For example, when the applied voltage of the read pulse exceeds the specific threshold voltage of the self-selected memory cell, a limited amount of current can flow through the self-selected memory cell. Similarly, when the applied voltage of the read pulse is less than the specific threshold voltage of the self-selected memory cell, no significant amount of current can flow through the self-selected memory cell. In some embodiments, the sensing component 125 can read the information stored in the selected memory cell 105 by detecting the current or the absence thereof through the memory cell 105. In this manner, the memory cell 105 (e.g., a self-selected memory cell) can store one bit of data based on the threshold voltage levels (e.g., two threshold voltage levels) associated with the chalcogenide material, where the threshold voltage levels at which the current flows through the memory cell 105 indicate the logic state stored by the memory cell 105. In some cases, the memory cell 105 can exhibit a number of different threshold voltage levels (e.g., three or more threshold voltage levels), thereby storing more than one bit of data.

[0052] The sensing component 125 may include various transistors or amplifiers in order to detect and amplify the difference in the signal associated with the sensed memory cell 105, which may be referred to as a latch. The detected logic state of the memory cell 105 may then be output via the column decoder 130 as output 135. In some cases, the sensing component 125 may be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 may be connected to or in electronic communication with the column decoder 130 or the row decoder 120. Figure 1 An alternative option of arranging the sense component 125-a (in a dashed box) is also shown.One of ordinary skill in the art will appreciate that the sense component 125 can be associated with either a column decoder or a row decoder without losing its functional purpose.

[0053] Memory cell 105 may be set or written by similarly activating associated word line 110 and digit line 115, and at least one logic value may be stored in memory cell 105. Column decoder 130 or row decoder 120 may receive data to be written to memory cell 105, for example, input / output 135.

[0054] In some memory architectures, accessing a memory cell 105 may cause the stored logic state to decay or be destroyed, and a rewrite or refresh operation may be performed to transfer the original logic state back to the memory cell 105. In DRAM, for example, a capacitor may be partially or completely discharged during a sensing operation, thereby destroying the stored logic state, so the logic state may be rewritten after the sensing operation. In addition, in some memory architectures, activating a single word line 110 may produce a discharge of all memory cells in a row (e.g., coupled to the word line 110); therefore, some or all memory cells 105 in the row may need to be rewritten. However, in non-volatile memory such as self-select memory, PCM, CBRAM, FeRAM, or NAND memory, accessing a memory cell 105 does not destroy the logic state, and therefore, the memory cell 105 may not need to be rewritten after access.

[0055] The memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, discharging) of the memory cell 105 through various components such as the row decoder 120, the column decoder 130, and the sensing component 125. In some cases, one or more of the row decoder 120, the column decoder 130, and the sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row address signals and column address signals in order to activate the desired word lines 110 and digit lines 115. The memory controller 140 may also generate and control various voltages or currents used during the operation of the memory device 100. In general, the amplitude, shape, polarity, and / or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory device 100. Furthermore, one, multiple, or all memory cells 105 within memory array 102 may be accessed simultaneously; for example, multiple or all cells of memory array 102 may be accessed simultaneously during a reset operation that sets all or a group of memory cells 105 to a single logic state.

[0056] The fabrication techniques described herein may be used to simultaneously form aspects of the memory device 100, including some aspects. For example, the fabrication techniques described herein may be used to simultaneously form the lower word line 110 (in Figure 1 WL_B1 in the figure) and the upper word line 110 (in Figure 11), as well as word lines at any number of additional layers (not shown). The lower word line 110 and the upper word line 110 can both be disposed in a layer initially comprising the same dielectric material, and a single via pattern can be used for one or more processing steps—e.g., removing portions of the dielectric material and replacing them with conductive material—that simultaneously form the lower level word line 110 and the upper level word line 110 at the respective layers. Similarly, the fabrication techniques described herein can be used to simultaneously form the lower memory cells 105 (e.g., Figure 1 The memory cell 105 - a ) and the upper memory cell 105 (eg, Figure 1 Illustrated in FIG. 1 are white circular memory cells 105 - b ), as well as memory cells 105 at any number of additional memory cell layers (not shown).

[0057] Figure 2 An example of a 3D memory array 202 that supports a cross-point memory array and related manufacturing techniques according to an embodiment of the present invention is illustrated. The memory array 202 may be a reference Figure 1 1. An example of a portion of a memory array 102 is described. The memory array 202 can include a first array or layer 205-a of memory cells disposed above a substrate 204 and a second array or layer 205-b on top of the first array or layer 205-a. The memory array 202 can also include word lines 110-a and word lines 110-b and bit lines 115-a, which can be examples of word lines 110 and bit lines 115, as described with reference to FIG. Figure 1 As described in Figure 2 In the illustrative example depicted in FIG, the memory cells of the first layer 205-a and the second layer 205-b may each include a self-select memory cell. In some examples, the memory cells of the first layer 205-a and the second layer 205-b may each include another type of memory cell that may be suitable for a cross-point architecture—for example, a CBRAM cell or a FeRAM cell. Although included in Figure 2 Some elements in the drawings are labeled with numerical indicators, while other corresponding elements are not labeled, but are the same or will be understood to be similar in an effort to improve visibility and clarity of the features depicted.

[0058] In some cases, the self-selected memory cells of the first layer 205-a may each include a first electrode 215-a, a chalcogenide material 220-a, and a second electrode 225-a. Additionally, the self-selected memory cells of the second memory layer 205-b may each include a first electrode 215-b, a chalcogenide material 220-b, and a second electrode 225-b. In some embodiments, the access lines (e.g., word lines 110, bit lines 115) may include an electrode layer (e.g., a conformal layer) in place of the electrodes 215 or 225, and thus may include a multi-layer access line. In such embodiments, the electrode layer of the access line may interface with the memory material (e.g., chalcogenide material 220). In some embodiments, the access lines (e.g., word lines 110, bit lines 115) may directly interface with the memory material (e.g., chalcogenide material 220) without an electrode layer or electrode in between.

[0059] In some embodiments, the self-select memory cells of the first layer 205-a and the second layer 205-b may have a common conductor, so that the corresponding self-select memory cells (eg, vertically aligned in the y direction) of each layer 205-a and 205-b may share a common conductor. Figure 1 The bit line 115 or word line 110 is depicted. For example, the first electrode 215-b of the second layer 205-b and the second electrode 225-a of the first layer 205-a can both be coupled to the bit line 115-a so that the bit line 115-a is shared by vertically aligned and adjacent self-selected memory cells (in the y direction).

[0060] In some embodiments, the memory array 202 may include an additional bit line (not shown) such that the first electrode 215-b of the second layer 205-b may be coupled to the additional bit line and the second electrode 225-a of the first layer 205-a may be coupled to the bit line 115-a. The additional bit line may be electrically isolated from the bit line 115-a (e.g., an insulating material may be inserted between the additional bit line and the bit line 115-a). Thus, the first layer 205-a and the second layer 205-b may be separated and may operate independently of each other. In some cases, the access line (e.g., word line 110 or bit line 115) may include a selection component for the corresponding memory cell at each intersection (e.g., a two-terminal selector device, which may be configured as one or more thin film materials integrated with the access line). Thus, the access line and the selection component may together form a composite material layer that acts as both an access line and a selection component.

[0061] The architecture of the memory array 202 may in some cases be referred to as an example of a cross-point architecture because memory cells may be formed at topological cross-points between word lines 110 and bit lines 115, such as Figure 2This cross-point architecture can provide a relatively high density data storage device with a lower production cost than some other memory architectures. For example, a memory array with a cross-point architecture can have a reduced area memory cell and thus can support an increased memory cell density compared to some other architectures. For example, the cross-point architecture can provide a relatively high density data storage device with a lower production cost than some other memory architectures. 2 Other architectures with a memory cell area of ​​4F (such as other architectures with three-terminal selection components) may have 2 Memory cell area, where F is the minimum feature size. For example, a DRAM memory array may use a transistor that is a three-terminal device as a select element for each memory cell, and thus a DRAM memory array including a given number of memory cells may have a larger memory cell area than a memory array with a cross-point architecture including the same number of memory cells.

[0062] Although Figure 2 The example of shows two memory layers, but other configurations may include any number of layers. In some embodiments, one or more of the memory layers may include a self-select memory cell including a chalcogenide material 220. In other embodiments, one or more of the memory layers may include a FeRAM cell including a ferroelectric material. In yet another embodiment, one or more of the memory layers may include a CBRAM cell including a metal oxide or chalcogenide material. For example, the chalcogenide material 220 may include a chalcogenide glass, such as an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some embodiments, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy.

[0063] FIGS. 3-4 illustrate various aspects of the fabrication techniques of the present invention. For example, FIGS. 3-4 illustrate aspects of establishing a cavity at one or more buried target layers of a composite stack (e.g., simultaneously), each target layer comprising a target material. A via may be used to establish a cavity in the target material at the target buried layer, and the cavity may be sized so that adjacent (e.g., neighboring) cavities may overlap and thus may merge to form a channel (e.g., a tunnel) at the target buried layer. The channel may thus be aligned with the via—that is, the channel may intersect the longitudinal axis (e.g., an orthogonal direction relative to the substrate) of each via used to establish the channel. The channel may be filled with a filling material (e.g., a conductive material or a memory material), and in some cases, using similar cavity-etching and channel-establishment techniques, a narrower channel within the filling material at the target layer may be established using the same via. Establishing a narrower channel within the filling material may produce an elongated filling material loop (e.g., a band, ring, or track) surrounding the narrower channel, and the narrower channel may be filled with a second material (e.g., a dielectric insulating material or other insulating material). The fill material loops can then be cut to create discrete sections of fill material at the target buried layer. These sections can be configured as aspects of a 3D memory array, such as Figure 1 The memory array 102 or Figure 2 An example of a memory array 202 is illustrated in FIG.

[0064] For example, the fabrication techniques described herein can facilitate the simultaneous formation of similar structures at different lower layers—e.g., a collection of conductive lines (e.g., access lines, such as word lines 110 and bit lines 115) or a collection of memory material elements configured with a common layout in which each collection of conductive lines or collection of memory material elements is present in a different lower layer of the stack. Thus, the fabrication techniques described herein can facilitate the simultaneous formation of two or more layers of memory cells, each layer including access lines (e.g., word lines, bit lines) and a 3D cross-point structure of memory cells.

[0065] Figures 3A to 3C Exemplary manufacturing techniques according to the present invention are described. Figure 3A , process step 300 - a is depicted. Process step 300 - a may include one or more thin film deposition or growth steps to form stack 305 - a. Figure 3A 1. A side view of a stack 305-a is shown, which may be an initial stack of layers prior to applying other fabrication techniques as described herein. The stack 305-a may be formed on a substrate (e.g., a substrate such as ... Figure 2The stack 305-a may include multiple different layers of various materials, and thus may be referred to as a composite stack in some cases, where the specific materials are selected based on multiple factors - such as the desired type of memory technology (e.g., self-select memory, FeRAM, CBRAM), the desired number of layers of memory cells (e.g., two or more memory cell layers), etc. Figure 3A As depicted in the illustrative example of FIG. 3 , the stack 305 - a may include two sets suitable for manufacturing buried wires (e.g., the upper layer includes a plurality of layers as shown in FIG. 3 ). Figure 2 The stack 305-a may also include an initial stack of layers suitable for manufacturing a single set of buried wires at a layer (e.g., including a first set of buried wires at a layer 110-b and a second set of buried wires at a relatively lower layer including word lines 110-a), each set of buried wires at a layer initially comprising a first material. The stack 305-a may also include an initial stack of layers suitable for manufacturing a single set of buried wires at a layer (e.g., including a first set of buried wires at a layer 110-b and a second set of buried wires at a relatively lower layer including word lines 110-a). Figure 2 A single set of buried lines of the depicted bit lines 115 - a ) initially comprises the second material.

[0066] In some examples, stack 305-a may include layer 310, which may be the top layer of stack 305-a. In some embodiments, layer 310 includes a dielectric material. In some embodiments, layer 310 includes a hard mask material, so that layer 310 may be referred to as a hard mask layer. A via pattern may be formed in layer 310 due to, for example, a photolithography step.

[0067] The stack 305-a may also include a layer 315. Figure 3A In the illustrative example of , stack 305 - a includes two layers 315 , namely layer 315 - a and layer 315 - b . In some embodiments, layers 315 may each include a first dielectric material. Figure 5 , each layer 315 may ultimately be modified to include a set of first conductive lines, each of which includes an electrode material. Thus, layer 315 may be referred to as a first electrode layer. In some cases, the first conductive lines may be referred to as buried conductive lines because the first conductive lines are positioned below a surface layer (e.g., below layer 310). The first conductive lines may extend in a first direction. Electrodes at two or more first electrode layers—that is, electrodes formed within two or more layers, each of which includes a first dielectric material—may be formed simultaneously according to the manufacturing techniques described herein.

[0068] The stack 305-a may also include a layer 320. Figure 3AIn the illustrative example of FIG. 3 , stack 305 - a includes two layers 320, namely layer 320 - a and layer 320 - b, but any number of layers 320 is possible. In some embodiments, each layer 320 may include a memory material (e.g., chalcogenide material 220) formed as part of stack 305 - a. In other embodiments, each layer 320 may include a placeholder material that may be later partially removed and replaced by a memory material (e.g., reference numeral 220). Figure 2 The chalcogenide material 220 described above is replaced. Figures 9 to 12 As illustrated in FIG. 1 , each layer 320 may ultimately include memory cells formed simultaneously according to the fabrication techniques described herein. Thus, a layer 320 may be referred to as a memory layer regardless of whether it initially includes memory material or a placeholder material that is later replaced by memory material.

[0069] The stack 305-a may also include a layer 325. Figure 3A In the illustrative example of , stack 305 - a includes a single layer 325 , but any number of layers 325 are possible. In some embodiments, each layer 325 may include a second dielectric material. Figure 5 As described in , layer 325 may ultimately be modified to include a set of second conductive lines including electrode material. Therefore, each layer 325 may be referred to as a second electrode layer. In some cases, the second conductive lines may be referred to as buried conductive lines because the second conductive lines are positioned below the surface layer (e.g., below layer 310). The second conductive lines may extend in a second direction, which may be different from the first direction. In some embodiments, the second direction may be substantially perpendicular to the first direction along which the first conductive lines extend. Electrodes at two or more second electrode layers - that is, electrodes formed within two or more layers, each of which includes a second dielectric material - are formed simultaneously according to the manufacturing techniques described herein.

[0070] Stack 305-a may include layer 330. In some cases, layer 330 may include an etch stop material to withstand the various etching processes described herein. Layer 330 may include the same hard mask material as layer 310 in some cases, or may include a different material. In some cases, layer 330 may provide a hard mask material for a substrate (e.g., a substrate having ... Figure 2 204) or other layers (not shown) that may be below layer 330. In some cases, layer 330 may provide a buffer layer for one or more layers of memory cells fabricated in previous processing steps.

[0071] exist Figure 3B , process step 300 - b is depicted. Figure 3BA side view of stack 305-b and via 335 is illustrated (e.g., a top view of via 335) is illustrated. When processing step 300-b is complete, stack 305-b may correspond to stack 305-a. Processing step 300-b may include a photolithography step that transfers the shape of via 335 onto stack 305-a. In some examples, the photolithography step may include forming a photoresist layer (not shown) having the shape of via 335 (e.g., defined by the lack of photoresist material inside via 335) on top of layer 310. In some examples, an etching processing step may follow the photolithography step used to transfer the shape of via 335 onto layer 310, so that the shape of via 335 created within layer 310 can be reused as an access via during subsequent processing steps - that is, layer 310 including the shape of via 335 can act as a hard mask layer that provides an access via in the shape of via 335 for subsequent processing steps.

[0072] Processing step 300-b may further include an anisotropic etching step that may remove material from stack 305-a based on the shape of via 335. In some cases, processing step 300-b may include a single anisotropic etching step that etches through hard mask layer 310 and additional underlying layers based on the shape of via 335 in a photoresist layer over hard mask layer 310. In other cases, via 335 may exist in hard mask layer 310, and a subsequent anisotropic etching step may etch through additional underlying layers based on the shape of via 335 in hard mask layer 310.

[0073] The anisotropic etching step may remove a target material in one direction (e.g., an orthogonal direction relative to the substrate) by applying an etchant (e.g., a mixture of one or more chemical elements) to the target material. Moreover, the etchant may exhibit selectivity (e.g., chemical selectivity) with respect to removing only the target material (e.g., layer 310) while leaving other materials (e.g., photoresist) exposed to the etchant. The anisotropic etching step may use one or more etchants during a single anisotropic etching step when removing one or more material layers. In some cases, the anisotropic etching step may use an etchant that exhibits selectivity for targeting a group of materials (e.g., oxides and nitrides) while leaving other groups of materials (e.g., metals) exposed to the etchant.

[0074] During processing step 300-b, an anisotropic etching step may produce a hole (e.g., through-hole 345) through stack 305-a, wherein the shape and width 340 (e.g., diameter) of through-hole 345 substantially corresponds to the width of through-hole 335 in the stack. Figure 3B, the anisotropic etching step in process step 300-b may include four different kinds of etchants - for example, different etchants for layer 310, layer 315, layer 320, and layer 325, respectively. The anisotropic etching step may terminate at layer 330. In some examples, width 340 is the same (substantially the same) at each layer of stack 305-b.

[0075] exist Figure 3C , process step 300 - c is depicted. Figure 3C A top view of a cavity 336 and a side view of stack 305-c are illustrated. When processing step 300-c is complete, stack 305-c may correspond to stack 305-b. Cavity 336 may represent a top view of one or more cavities formed in one or more buried layers (e.g., layer 315-a and layer 315-b) of stack 305-c. Each cavity 336 may share a common center with via 335 - for example, via 335 and each cavity 336 may be concentric about a longitudinal axis (e.g., an orthogonal direction relative to the substrate) of via 335, such as Figure 3C The through-hole 345 may expose target material (e.g., the first dielectric material of layer 315) within one or more target layers (e.g., layers 315-a and 315-b), and the processing step 300-c may include an isotropic etching step that removes the target material from each target layer to produce a cavity 336 formed within each target layer and around the through-hole 345 (e.g., the through-hole 345 passing through the stack 305-b).

[0076] An isotropic etching step may remove a target material in all directions. An isotropic etching step may apply an etchant (e.g., a mixture of one or more chemical elements) that exhibits selectivity (e.g., chemical selectivity) with respect to removing only the target material while preserving other materials exposed to the etchant. An isotropic etching step may use different etchants during a single isotropic etching step when removing one or more layers of material. In some cases, an isotropic etchant (e.g., an etchant used in an isotropic etching step) may have chemical selectivity between a first dielectric material and at least one other material in the stack.

[0077] As in Figure 3CIn the example depicted in , the isotropic etching step may, for example, simultaneously remove a portion of the first dielectric material from each layer 315 (e.g., from both layer 315-a and layer 315-b) while retaining (or substantially retaining) other materials in the stack 305-b that were exposed to the etchant (e.g., at other layers) based at least in part on the selectivity of the etchant that targets the removal of the first dielectric material of layer 315. Due to the isotropic etching step, the outer width (e.g., width 350) of each cavity 336 may be greater than the width (e.g., width 340) of the through-hole 345. Thus, the outer width (e.g., width 350) of each cavity 336 may be determined by the width of the through-hole 335 (e.g., the width of the through-hole 345) and the amount of target material removed from each target layer during the processing step 300-c. Additionally, each cavity 336 may be referred to as a buried cavity 336 because it may be formed in one or more buried layers—for example, in one or more layers 315 that include the first dielectric material and are positioned below layer 310 in stack 305 - c .

[0078] It should be understood that any number of buried cavities 336 may be formed, and in some cases, the buried cavities may be formed simultaneously within the stack of layers using processing steps 300-a to 300-c. The number of different target layers - that is, the number of different layers that include a target material (e.g., a first dielectric material initially included in layer 315) and are separated by other layers - may determine the number of buried cavities 336 that are simultaneously established within stack 305-c using an isotropic etching step based on vias 335. Through-vias 345 established using vias 335 and passing through the stack may provide access (e.g., a path) to an etchant during the isotropic etching step, such that the isotropic etching step may remove a portion of each buried target layer through through-vias 345 to establish a buried cavity 336 at each target layer. Thus, through-vias 335 may be referred to as access vias in some cases.

[0079] Figures 4A to 4B Exemplary via patterns and structures that support cross-point memory arrays and related fabrication techniques in accordance with the present invention are described. Figure 4A A through-hole 410 and an associated first cavity 415 are illustrated. The through-hole 410 may be an example of the through-hole 335 described with reference to FIG3 . The first cavity 415 may be an example of the cavity 336 described with reference to FIG3 . The first cavity 415 may represent a cavity (e.g., a buried cavity) in a target material that is concentric about a longitudinal axis (e.g., relative to a longitudinal axis of a substrate) of the through-hole 410 and is formed at a buried layer of a stack (e.g., stack 305).

[0080] As an example, Figure 4A Also illustrated is a channel 420, which may be formed using a plurality of through holes 410 arranged in a linear configuration (e.g., five through holes 410, such as Figure 4A4 (described in ). A first cavity 415 corresponding to each through-hole 410 may be formed in the target material at the buried layer. The distance between through-holes 410 and the amount of target material removed when forming each first cavity 415 may be configured so that adjacent or neighboring first cavities 415 may merge (e.g., may overlap, as represented by an elliptical shape 425 within the channel 420) to form the channel 420. Thus, the channel 420 may be aligned with the set of through-holes 410 corresponding to the first cavities 415 merged to form the channel 420—e.g., the channel 420 may intersect the longitudinal axis of each through-hole 410 (e.g., relative to the longitudinal axis of the substrate). The channel 420 may have a width that is the same as the width of each first cavity 415 and a length determined by the number of merged first cavities 415 (e.g., the number of through-holes 410 arranged in a linear manner, which may be any number).

[0081] Figure 4A Also illustrated is a filled trench 430. Filled trench 430 may correspond to trench 420 after completing at least two subsequent processing steps—such as a first processing step of depositing a fill material in trench 420 and associated through-holes, followed by a second processing step of removing the fill material from the associated through-holes using an etching process (e.g., an anisotropic etching step, such as processing step 300-b described with reference to FIG. 3). In other words, filled trench 430 may include the fill material in trench 420. Although trench 420 and filled trench 430 are illustrated as having a linear configuration corresponding to the linear configuration of the associated set of through-holes 410, it should be understood that trench 420 and filled trench 430 may be in any arbitrary shape (e.g., an L-shape, an X-shape, a T-shape, an S-shape) corresponding to the spatial configuration of the associated set of through-holes 410. Thus, the set of vias 410 may be positioned to define a profile having any desired shape, wherein the spacing between adjacent vias is configured such that adjacent cavities at the same target layer merge to form a channel having any desired shape at the target layer, each cavity corresponding to a via 410. Furthermore, in some embodiments, a plurality of channels 420 and filled channels 430 may be combined to form various shapes of buried lines or interconnects (e.g., when the set of filled channels 430 includes a conductive material).

[0082] Figure 4AAlso illustrated is a through-hole 410 and an associated second cavity 435. The second cavity 435 may be an example of the cavity 336 described with reference to FIG. 3. The width of the second cavity 435 may be less than the width of the first cavity 415. As described above, the size of the cavity associated with the through-hole 410 may vary depending on the width of the through-hole 410 and the amount of target material removed during the isotropic etching step. The second cavity 435 may represent a cavity (e.g., a buried cavity) that is concentric about the longitudinal axis of the through-hole 410 (e.g., relative to the longitudinal axis of the substrate) and is formed in the target material at the buried layer of the stack (e.g., formed in the filling material within the filled trench 430).

[0083] As an example, Figure 4A Also illustrated is a channel 440, which may be formed using a plurality of through-holes 410 arranged in a linear configuration (e.g., five through-holes 410, such as Figure 4A 4 (described in ). A second cavity 435 corresponding to each through-hole 410 may be formed in a target material at the buried layer, which may be a filling material deposited to form the filled trench 430. The distance between the through-holes 410 and the amount of target material removed when forming each second cavity 435 may be configured so that adjacent or neighboring second cavities 435 may merge to form a trench 440. Thus, the trench 440 may be aligned with the set of through-holes 410 corresponding to the second cavities 435 merged to form the trench 440—for example, the trench 440 may intersect the longitudinal axis of each through-hole 410 (for example, relative to the longitudinal axis of the substrate). The trench 440 may have a width that is the same as the width of each second cavity 435 and a length determined by the number of merged second cavities 435 (for example, the number of through-holes 410 arranged in a linear manner, which may be any number).

[0084] Figure 4AAlso illustrated is an intermediate pattern 445, which may correspond to a channel 440 formed within the filled channel 430. The intermediate pattern 445 may illustrate the result of one or more processing steps, wherein a portion of the filling material present in the filled channel 430 is removed to form the second cavity 435 and thus form the channel 440 within the filled channel 430. The channel 440 may be formed using the same set of vias 410 used to form the channel 420 and the filled channel 430, but may have a narrower width (due to the width of the merged second cavity 435 being less than the width of the merged first cavity 415), and wherein the filling material within the filled channel 430 acts as a target material during the formation of the channel 440. Because the width of the channel 440 may be less than the width of the filled channel 430, a portion of the filling material within the filled channel 430 may remain along the outer boundary of the filled channel 430, surrounding the channel 440. Thus, after forming the trench 440, a loop of fill material from the filled trench 430 may remain at the target layer; the loop may be elongated, with the length being greater than the width, and may also be referred to as a track or a strip.

[0085] Figure 4A Also illustrated is a loop 450, which may correspond to a trench 440 filled with a dielectric material using a corresponding set of vias 410. Thus, loop 450 may include a loop of fill material filling trench 420 (i.e., fill material used to form filled trench 430) surrounding the dielectric material filling trench 440. In some cases, the dielectric material surrounded by loop 450 may be the same material as the target material comprising the target layer (e.g., dielectric material layer 315 or 325 described with reference to FIG. 3) in which trench 420 is formed, and the fill material may be a conductive material, and thus loop 450 may be a loop of conductive material. Loop 450 of conductive material may be cut into a plurality of discrete segments, which may serve as electrodes (e.g., access lines). Loop 450 of memory material may be cut into a plurality of discrete segments, which may serve as one or more memory cells (e.g., each discrete segment of memory material, which may be referred to as a memory material element, may be configured to include one or more memory cells 105).

[0086] although Figure 4A Although five through-holes 410 are used to successively form five first cavities 415 (which merge to form channel 420), filled channel 430, five second cavities 435 (which merge to form channel 440), and thus form loop 450, it should be understood that similar techniques may be applied using any number of through-holes 410. Similarly, although Figure 4AIt is illustrated that five first cavities 415 (which merge to form channel 420), filled channel 430, five second cavities 435 (which merge to form channel 440) are successively formed at a single target layer of the stack, but it should be understood that the stack may include a plurality of different target layers, each of which includes the same target material, and it should be understood that reference is made to Figure 4A The described techniques may thus produce multiple loops 450, one at each target layer in the stack.

[0087] Figure 4B FIG. 401 is illustrated, which illustrates a top view of a first plurality of loops 455 (e.g., loops 455-a through 455-d) extending in a first direction (e.g., as drawn on the page, the x-direction) and a second plurality of loops 460 (e.g., loops 460-a through 460-d) extending in a second direction (e.g., as drawn on the page, the y-direction). The first plurality of loops 455 may be formed at one or more first layers (e.g., layer 315) of a stack (e.g., stack 305), and the second plurality of loops 460 may be formed at one or more second layers (e.g., layer 325) of a stack (e.g., stack 305).

[0088] Figure 4B Each loop in the first plurality of loops 455 and the second plurality of loops 460 may be Figure 4A 401 illustrates an example of a loop 450 of FIG. Thus, each of the horizontal loops (e.g., loops 455-a to 455-d extending in the x-direction) can be formed using a set of through holes (not shown) arranged in a row in the horizontal direction (x-direction). Additionally, each of the vertical loops (e.g., loops 460-a to 460-d extending in the y-direction) can be formed using a set of through holes (not shown) arranged in a row in the vertical direction (y-direction). FIG. 401 illustrates a first plurality of loops 455 and a second plurality of loops 460 in a substantially vertical arrangement—that is, the first plurality of loops 455 are substantially perpendicular to the second plurality of loops 460. It should be understood that the first plurality of loops and the second plurality of loops can be arranged at any angle.

[0089] In some cases, each loop in the first plurality of loops 455 and the second plurality of loops 460 may have a conductive material (e.g., as described in reference Figure 1 and 2 The ends (e.g., shorter sides) of each loop 455, 460 may be removed or otherwise severed from the sides (e.g., longer sides) of the loop 455, 460 in subsequent processing steps, and the remaining portions (e.g., longer sides) of each loop 455, 460 may serve as access lines for a memory device (e.g., as described in reference Figure 1 and 23 ). In some embodiments, the first plurality of loops 455 may exist in one or more first layers (e.g., layer 315 as described with reference to FIG. 3 ), and the second plurality of loops 460 may exist in one or more second layers (e.g., layer 325 as described with reference to FIG. 3 ). Thus, the first plurality of loops 455 and the second plurality of loops 460 may form a circuit as described with reference to FIG. Figure 1 and 2 The described 3D cross-point configuration includes a matrix of access lines (e.g., a grid structure of access lines). Each topological cross-point of the access lines (e.g., cross-point 465 formed between loop 455-d and loop 460-a) may correspond to a memory cell (e.g., as described in reference Figure 1 105), and the memory cells can be inserted between intersecting access lines. Thus, exemplary diagram 401 can support 64 memory cells in a single layer of memory cells. It should be understood that any number of layers of memory cells, each including any number of access lines, can be placed on top of each other and formed simultaneously using a single via pattern.

[0090] Figures 5 to 8 The construction of an exemplary three-dimensional structure of access lines (e.g., a grid structure of access lines) according to the manufacturing techniques of the present invention is described. As described above, the manufacturing techniques described herein may use a through-hole pattern, and Figures 5 to 8 Methods are described that use via patterns to facilitate simultaneous construction of a three-dimensional structure of access lines, such as a grid structure of access lines, so that two or more layers of a 3D memory array can be formed simultaneously.

[0091] Figure 5 An example method of forming a 3D cross-point memory array structure that may include two or more memory cell layers according to the present invention is described. As an illustrative example of the manufacturing techniques described herein, Figure 5 Two sets of access lines may be shown being formed simultaneously - that is, the upper layer may include one set of word lines 531-a and 531-b, and the lower layer may include another set of word lines 531-c and 531-d. Word line 531 may be used as shown in FIG. Figure 1 Two sets of word lines 110 for two layers of the memory array 102 are described (eg, a set of word lines WL_T1 to WL_TM and another set of word lines WL_B1 to WL_BM) or for use as described in reference to Figure 2 An example of a pair of word lines 110-a for a first layer 205-a of memory cells and a pair of word lines 110-b for a second layer 205-b of memory cells is depicted.

[0092] Figure 5The stack of layers in may correspond to stack 305 as described with reference to FIG. 3 . For example, a hard mask (HM) layer may correspond to layer 310 (e.g., a top layer of stack 305 ), a dielectric 1 (D1) layer may correspond to layers 315-a and 315-b, a dielectric 2 (D2) layer may correspond to layer 325, and a placeholder dielectric or memory material (DM) layer may correspond to layers 320-a and 320-b, respectively. The DM layer may include a memory material (e.g., a memory material formed as part of the initial stack 305-a) or a placeholder material within which a memory material may be deposited later. In some cases, the placeholder material may be a third dielectric material. In some cases, the DM layer may be referred to as a memory layer or a placeholder layer. In some cases, the D1 layer may be referred to as a first dielectric layer, and the D2 layer may be referred to as a second dielectric layer.

[0093] Figure 5 Also included are diagrams 501, 502, and 503. As an illustrative example, diagram 501 may depict a top view of a stack including three rows of vias (e.g., via 335 or via 410 as described with reference to FIG. 3 or FIG. 4) and six access lines (e.g., word lines) formed using the rows of vias, wherein each row of vias is used to form a loop (e.g., loop 455-a as described with reference to FIG. 4) (ends of the loop not shown in diagram 501) and thus form two access lines (e.g., as described with reference to FIG. 4) with the rows of vias interposed therebetween. Figure 1 and 2 501 ). FIG. 502 illustrates a cross-sectional side view of the stack at various processing stages (e.g., processing steps 505-530), the stack corresponding to the center of the via of FIG. 501, the center as represented by reference line AA in FIG. 501. FIG. 503 illustrates a cross-sectional side view of the stack at various processing stages (e.g., processing steps 505-530), the stack corresponding to the space between the vias of FIG. 501, the space as represented by reference line BB.

[0094] At processing step 505, a photolithography step (such as the photolithography step described with reference to FIG. 3) may transfer the via pattern illustrated in FIG. 501 onto a stack (such as stack 305). In some cases, a plurality of holes (such as the holes associated with the via pattern illustrated in FIG. 501) each having a first width (such as width 506) may be formed at a top layer (such as the HM layer) of the stack. The first width (such as width 506) may correspond to the width of vias 335 or 410 as described with reference to FIGS. 3 and 4. Subsequently, an anisotropic etching step may remove some material from the stack, thereby creating a through-hole through the stack. FIG. 502 at processing step 505 illustrates one of the through-holes and a corresponding through-hole that passes through the stack and exposes a buried layer of the stack to subsequent processing steps. FIG. 503 at processing step 505 may illustrate that between the through-holes, the initial stack (such as stack 305) may remain unchanged during processing step 505. Processing step 505 may be an example of processing step 300 - b as described with reference to FIG. 3 .

[0095] At process step 510, the isotropic etching step may selectively remove a portion of the dielectric material at each D1 layer (e.g., layer 315-a and layer 315-b) in the stack that is exposed to the isotropic etching etchant. The dielectric material at each D1 layer may be referred to as a first dielectric material. The isotropic etching etchant at process step 510 may exhibit selectivity with respect to other materials of the stack (e.g., materials at other layers of the stack). That is, the isotropic etching etchant at process step 510 may remove a portion of the first dielectric material at each D1 layer while retaining (or substantially retaining) other materials (e.g., materials at other layers, such as DM layers, D2 layers, or HM layers of the stack). Selectively removing a portion of the first dielectric material from each D1 layer (e.g., layer 315-a and layer 315-b) may create a cavity (e.g., cavity 336 or first cavity 415 described with reference to FIGS. 3 and 4) at each D1 layer. While the through vias through the stack may expose the sidewalls of both D1 layers (eg, layer 315 - a and layer 315 - b ), the isotropic etch may simultaneously create a cavity at each D1 layer (eg, layer 315 - a and layer 315 - b ).

[0096] Diagram 502 illustrates that processing step 510 simultaneously creates cavities at two D1 layers (e.g., cavities are simultaneously formed at layer 315-a and layer 315-b), while the width of the through-holes at other layers remains unchanged. Width 511 may represent the final width of the cavities formed in the two D1 layers. Additionally, diagram 503 at processing step 510 illustrates that cavities formed at the same layer using adjacent through-holes may be merged due to the isotropic nature of the isotropic etching step, thereby expanding the size of each cavity in all directions, forming channels (e.g., channel 420 described with reference to FIG. 4 ) within the first dielectric material at two D1 layers (e.g., layer 315-a and layer 315-b). The channel width (e.g., width 512) at reference line BB as depicted in diagram 503 at processing step 510 may relate to the overlapping elliptical shape 425 described with reference to FIG. 4 . In some cases, width 512 may be approximately the same as width 511. In other cases, width 512 may be less than width 511.

[0097] At processing step 515, the trenches and associated through-holes may be filled with electrode material, which may be a conductive material. In some cases, excess electrode material may form on top of the stack (e.g., on top of the HM layer (e.g., layer 310)) and may be removed by an etch-back process or a chemical mechanical polishing process. As used herein, a through-hole filled with a material (e.g., a conductive material) may be referred to as a hole after it has been filled with the material. Diagram 503 at processing step 515 illustrates that electrode material may flow into portions of the trenches between the through-holes and thus simultaneously fill each trench created at processing step 510.

[0098] At process step 520, an anisotropic etching step may use the vias to remove a portion of the electrode material, thereby creating new through-vias corresponding to the vias. The anisotropic etching step may use the same through-hole pattern of the hard mask layer as process step 505 (e.g., the through-hole pattern depicted in FIG. 501 ), and create through-holes that expose the sidewalls of the electrode material deposited at process step 515 at each D1 layer for subsequent processing. At process step 520, the top view of a portion of FIG. 501 depicting a single row of vias may correspond to the top view of the filled trench 430 as described with reference to FIG. 4 .

[0099] At process step 525, the isotropic etching step may selectively remove a portion of the electrode material from each D1 layer - for example, a portion of the electrode material deposited at process step 515 and thus filling the trenches established at each D1 layer (e.g., layer 315-a and layer 315-b) at process step 510. The etchant of the isotropic etching at process step 525 may exhibit selectivity with respect to other materials (e.g., materials at other layers of the stack). That is, the etchant of the isotropic etching at process step 525 may remove the electrode material while retaining (or substantially retaining) other materials (e.g., materials at other layers, such as DM layers, D2 layers, or HM layers of the stack). The selective removal of the electrode material from the cavities at the D1 layers (e.g., layers 315-a and layer 315-b) may leave a portion of the electrode material in the trenches as illustrated in Figures 502 and 503 at process step 525, and the remaining portion of the electrode material may form the loop 450 as described with reference to Figure 4. In other words, width 526 may be smaller than width 511. In some cases, the width of the remaining portion of the electrode material (e.g., width 527) (e.g., the width of an access line including the electrode material) may be smaller than the minimum feature size for a given technology generation, such as determined by the minimum width of a line (or the minimum space between lines) that may be defined by a photoshielding step.

[0100] Diagram 503 illustrates that processing step 525 simultaneously creates cavities at two D1 layers (e.g., simultaneously forms cavities at layer 315-a and layer 315-b by selectively removing a portion of the electrode material formed at processing step 515), while the width of the through-holes at other layers remains unchanged (not shown in diagram 503). Width 526 may represent the final size of the cavities formed in the two D1 layers. Additionally, diagram 503 at processing step 525 illustrates that cavities formed at the same layer using adjacent vias may merge (e.g., abut) due to the isotropic nature of the isotropic etching step, thereby expanding the size of each cavity in all directions, forming channels (e.g., channels 440 described with reference to FIG. 4) within the dielectric material at two D1 layers (e.g., layers 315-a and 315-b). The width of the channel at reference line BB as depicted in diagram 503 at processing step 525 (e.g., width 528) may be related to the width of channel 440 described with reference to FIG. 4. In some cases, width 528 can be approximately the same as width 526. In other cases, width 528 can be less than width 526.

[0101] At processing step 530, the trenches and associated through-holes at each D1 layer may be filled with a dielectric material. In some cases, the dielectric material may be the same as the first dielectric material at each D1 layer. In other cases, the dielectric material may be different from the second dielectric material. As used herein, a through-hole filled with a material (e.g., a dielectric material) may be referred to as a hole after it has been filled with the material. Figures 502 and 503 at processing step 530 may illustrate that two loops 450 of electrode material have been formed simultaneously using the same row of through-holes, the two loops being a first loop at an upper D1 layer (e.g., layer 315-a) and a second loop at a lower D1 layer (e.g., layer 315-b). It should be understood that in other examples, the stack may include any number of D1 layers, wherein the loops 450 of electrode material are formed using reference numerals. Figure 5 The described processing steps are formed simultaneously at each D1 layer.After processing step 530, the top view of a portion of diagram 501 depicting a single row of vias may correspond to the top view of a portion of loop 455-a described with reference to FIG.

[0102] In some cases, upon completion of processing step 530, the first electrode layer (e.g., layer 315 or D1 layer as described with reference to FIG. 3 or 5) may include a first electrode (e.g., word line 531-a), a second electrode (e.g., word line 531-b), and a dielectric trench (e.g., a dielectric trench that may be formed by filling a trench associated with width 526 with a dielectric material) that separates the first electrode from the second electrode by a first distance (e.g., width 526). The first distance (e.g., width 526) may be greater than the first width (e.g., width 506). Furthermore, the dielectric trench may be aligned with a plurality of holes formed at a top layer (e.g., HM layer) of the stack, where one of the plurality of holes having a first width (e.g., width 506) is depicted. In some cases, the first electrode layer may include an immediately adjacent electrode (not shown) that is proximate to the second electrode, wherein the second electrode separates the first electrode from the immediately adjacent electrode and the second electrode is closer to the immediately adjacent electrode than the first electrode. For example, as shown in diagram 501, two electrodes formed by a single loop (e.g., with a single column of vias inserted therebetween) may be separated by a distance that is different from (e.g., larger than) the distance between adjacent loops and, therefore, different from the distance between two electrodes formed by different loops.

[0103] Figure 6 An example method of forming a 3D cross-point memory array structure that may include two or more memory cell layers according to the present invention is described. As an illustrative example of the manufacturing techniques described herein, Figure 6 A set of access lines 631-a and 631-b may be shown to be formed between two layers of memory cells - that is, the upper layer and the lower layer may share a set of bit lines 631-a and 631-b. Bit line 631 may be for example a reference Figure 1 The two layers of the memory array 102 are described as common bit lines 115 or for reference Figure 2 The depicted first layer 205 - a of memory cells and the second layer 205 - b of memory cells are examples of a common pair of bit lines 115 - a . Figure 6 The stack of layers in may correspond to the reference Figure 5 A stack as described (eg, stack 305 as described with reference to FIG. 3 ).

[0104] Figure 6 Also included are diagrams 601, 602, and 603. As an illustrative example, diagram 601 may depict a top view of a stack including three rows of vias (e.g., via 335 or via 410 as described with reference to FIG. 3 or FIG. 4) and six access lines (e.g., bit lines) formed using the rows of vias, wherein each row of vias is used to form a loop (e.g., loop 460-a as described with reference to FIG. 4) (loop ends not shown in diagram 601) and thus form two access lines (e.g., as described with reference to FIG. 4) between which the row of vias is inserted. Figure 1 and 2 602 illustrates a cross-sectional side view of the stack at various processing stages (e.g., processing steps 605-630), the stack corresponding to the center of the via of FIG. 601, the center as represented by reference line AA in FIG. 601. FIG. 603 illustrates a cross-sectional side view of the stack at various processing stages (e.g., processing steps 605-630), the stack corresponding to the space between the vias of FIG. 601, the space as represented by reference line BB.

[0105] At process step 605, a photolithography step (e.g., the photolithography step described with reference to FIG. 3 ) may transfer the pattern of vias illustrated in FIG. 601 onto a stack (e.g., stack 305). In some cases, a plurality of second holes (e.g., holes associated with the pattern of vias illustrated in FIG. 601 ) each having a second width (e.g., width 606) may be formed at a top layer (e.g., HM layer) of the stack. The second width (e.g., width 606) may correspond to the width of vias 335 or 410 as described with reference to FIGS. 3 and 4 . In some cases, a subset of the vias in FIGS. 501 and 601 may be common, as described later. Figure 8 . Subsequently, an anisotropic etching step may remove some material from the stack, thereby creating a through-hole through the stack. Diagram 602 at process step 605 illustrates one of the through-holes and a corresponding through-hole that passes through the stack and exposes a buried layer of the stack to subsequent process steps. Diagram 603 at process step 605 may illustrate that between the through-holes, the initial stack (e.g., stack 305) may remain unchanged during process step 605. Process step 605 may be an example of process step 300-b as described with reference to FIG.

[0106] At process step 610, the isotropic etch may selectively remove a portion of the dielectric material at the D2 layer (e.g., layer 325) in the stack that is exposed to the isotropic etch etchant. The dielectric material at the D2 layer may be referred to as a second dielectric material. The isotropic etch etchant at process step 610 may exhibit selectivity with respect to other materials of the stack (e.g., materials at other layers of the stack). That is, the isotropic etch etchant at process step 610 may remove a portion of the second dielectric material at the D2 layer while retaining (or substantially retaining) other materials (e.g., materials at other layers, such as the DM layer, D1 layer, or HM layer of the stack). Selectively removing a portion of the second dielectric material from the D2 layer (e.g., layer 325) may create a cavity at the D2 layer (e.g., cavity 336 or first cavity 415 described with reference to FIGS. 3 and 4).

[0107] Graph 602 illustrates that processing step 610 creates a cavity at the D2 layer (e.g., a cavity formed at layer 325), while the width of the through-hole at other layers remains unchanged. Width 611 may represent the final width of the cavity formed at the D2 layer. Additionally, graph 603 at processing step 610 illustrates that cavities formed at the same layer using adjacent through-holes may be merged due to the isotropic nature of the isotropic etching step, thereby expanding the size of each cavity in all directions, forming a channel (e.g., channel 420 described with reference to FIG. 4) within the second dielectric material at the D2 layer (e.g., layer 325). The channel width (e.g., width 612) at reference line BB as depicted in graph 603 at processing step 610 may relate to the overlapping elliptical shape 425 described with reference to FIG. 4. In some cases, width 612 may be approximately the same as width 611. In other cases, width 612 may be less than width 611.

[0108] At process step 615, the trenches and associated through-holes may be filled with electrode material, which may be a conductive material. In some cases, the electrode material used at process step 615 may be the same as the electrode material used at process step 515. In some cases, excess electrode material may be formed on top of the stack (e.g., on top of the HM layer (e.g., layer 310)) and may be removed by an etch-back process or a chemical mechanical polishing process. As used herein, a through-hole filled with a material (e.g., a conductive material) may be referred to as a hole after it has been filled with the material. Diagram 603 at process step 615 illustrates that electrode material may flow into portions of the trenches between the through-holes and thus simultaneously fill each trench established at process step 610.

[0109] At process step 620, an anisotropic etch may use the vias to remove a portion of the electrode material, thereby creating new through-vias corresponding to the vias. The anisotropic etch step may use the same through-hole pattern of the hard mask layer as process step 605 (e.g., the through-hole pattern depicted in FIG. 601 ), and create through-holes that expose the sidewalls of the electrode material deposited at process step 615 at the D2 layer for subsequent processing. At process step 620, the top view of a portion of FIG. 601 depicting a single row of vias may correspond to the top view of the filled trench 430 as described with reference to FIG. 4 .

[0110] At process step 625, the isotropic etch may selectively remove a portion of the electrode material from the D2 layer - e.g., a portion of the electrode material deposited at process step 615 thereby filling the trench established at the D2 layer (e.g., layer 325) at process step 610. The etchant of the isotropic etch at process step 625 may exhibit selectivity with respect to other materials (e.g., materials at other layers of the stack). That is, the etchant of the isotropic etch at process step 625 may remove the electrode material while retaining (or substantially retaining) other materials (e.g., materials at other layers, such as the DM layer, D1 layer, or HM layer of the stack). The selective removal of the electrode material from the cavity at the D2 layer (e.g., layer 325) may leave a portion of the electrode material in the trench as illustrated in Figures 602 and 603 at process step 625, and the remaining portion of the electrode material may form the loop 460 as described with reference to Figure 4. In other words, the width 626 may be less than the width 611. In some cases, the width of the remaining portion of the electrode material (e.g., width 627) (e.g., the width of an access line that includes the electrode material) may be less than the minimum feature size for a given technology generation, such as the minimum feature size determined by the minimum width of a line (or the minimum space between lines) that can be defined by a photoshielding step.

[0111] Graph 603 illustrates that processing step 625 creates a cavity at the D2 layer (e.g., by selectively removing a portion of the electrode material formed at processing step 615 to form a cavity at layer 325), while the width of the through-holes at other layers remain unchanged (not shown in graph 603). Width 626 may represent the final size of the cavity formed in the D2 layer. Additionally, graph 603 at processing step 625 illustrates that cavities formed at the same layer using adjacent vias may merge (e.g., abut) due to the isotropic nature of the isotropic etching step, thereby expanding the size of each cavity in all directions, forming a channel (e.g., channel 440 described with reference to FIG. 4) within the electrode material at the D2 layer (e.g., layer 325). The channel width at reference line BB (e.g., width 628) as depicted in graph 603 at processing step 625 may be related to the width of channel 440 described with reference to FIG. 4. In some cases, width 628 may be approximately the same as width 626. In other cases, width 628 may be smaller than width 626 .

[0112] At processing step 630, the trenches and associated through-holes at the D2 layer may be filled with a dielectric material. In some cases, the dielectric material may be the same as the second dielectric material at the D2 layer. In other cases, the dielectric material may be different from the second dielectric material. As used herein, a through-hole filled with a material (e.g., a dielectric material) may be referred to as a hole after it has been filled with the material. Figures 602 and 603 at processing step 630 may illustrate that a loop 460 of electrode material has been formed using the row of through-holes (e.g., the through-holes depicted in Figure 601). It should be understood that in other examples, the stack may include any number of D2 layers, where the loop 460 of electrode material uses reference Figure 6 The described processing steps are formed simultaneously at each D2 layer.After processing step 630, the top view of a portion of diagram 601 depicting a single row of vias may correspond to the top view of loop 460-a described with reference to FIG.

[0113] In some cases, upon completion of processing step 630, the second electrode layer (e.g., layer 325 or D2 layer as described with reference to FIG. 3 or 6) may include a third electrode (e.g., bit line 631-a), a fourth electrode (e.g., bit line 631-b), and a second dielectric channel (e.g., a dielectric channel that may be formed by filling a channel associated with width 626 with a dielectric material), the second dielectric channel separating the third electrode from the fourth electrode by a second distance (e.g., width 626). The second distance (e.g., width 626) may be greater than the second width (e.g., width 606). In addition, the second dielectric channel may be aligned with a plurality of second holes formed at a top layer of the stack (e.g., HM layer), where one of the plurality of second holes having a second width (e.g., width 606) is depicted. In some cases, the second electrode layer may include an immediately adjacent electrode (not shown) proximate to the fourth electrode, wherein the fourth electrode separates the third electrode from the immediately adjacent electrode and the fourth electrode is closer to the immediately adjacent electrode than the third electrode. For example, as shown in diagram 601, two electrodes formed by a single loop (e.g., with a single row of vias inserted therebetween) can be separated by a distance that is different from (e.g., larger than) the distance between adjacent loops and therefore different from the distance between two electrodes formed by different loops.

[0114] In some cases, a 3D cross-point memory array (e.g., using reference Figure 5 and 6 A device of the invention (a 3D cross-point memory array constructed using the fabrication techniques described herein) may include: an upper layer of a stack, the upper layer including a plurality of holes each having a first width; a first electrode layer within the stack, the first electrode layer including a first electrode and a second electrode; and a dielectric channel aligned with the plurality of holes and separating the first electrode from the second electrode by a first distance greater than the first width. In some examples of the devices described above, the first electrode has at least one dimension less than a minimum feature size. In some examples of the devices described above, the upper layer includes a hard mask material. In some examples of the devices described above, a conformal liner (e.g., a dielectric channel described herein) may include: a plurality of holes each having a first width; a first electrode layer within the stack, the first electrode layer including a first electrode and a second electrode; and a dielectric channel aligned with the plurality of holes and separating the first electrode from the second electrode by a first distance greater than the first width. Figure 7 The conformal liner described herein is in contact with multiple surfaces of the first electrode.

[0115]

[0013] In some cases, an apparatus described above may further include a memory layer within the stack, the memory layer comprising a sheet of memory material perforated by a plurality of dielectric plugs.

[0116] In some cases, the apparatus described above may further include: a second electrode layer within the stack, the second electrode layer including a third electrode and a fourth electrode; and a memory layer within the stack, the memory layer including a memory material element coupled to the first electrode, the second electrode, and the third electrode. In some examples of the apparatus described above, the memory material element is coupled to the fourth electrode.

[0117]

[0013] In some cases, an apparatus described above may further include a memory layer within the stack, the memory layer comprising a plurality of memory material elements, each memory material element having a curved surface.

[0118] In some cases, the apparatus described above may further include: a plurality of second holes in the upper layer, each second hole having a second width; a second electrode layer within the stack, the second electrode layer including a third electrode and a fourth electrode; and a second dielectric channel aligned with the plurality of second holes and separating the third electrode from the fourth electrode by a second distance greater than the second width. In some examples of the apparatus described above, the first electrode and the second electrode are disposed in a first direction, and the third electrode and the fourth electrode are disposed in a second direction. In some cases, the apparatus described above may further include an adjacent electrode at the first electrode layer, wherein the second electrode separates the first electrode from the adjacent electrode, and the second electrode is closer to the adjacent electrode than the first electrode.

[0119] Figure 7 Includes Figures 701, 702 and 703. Figure 7 An example method of forming a 3D cross-point memory array structure that may include two or more memory cell layers according to the present invention is described. As an illustrative example of the manufacturing techniques described herein, Figure 7 Methods of forming dual-layer electrodes, such as dual-layer access lines, may be presented. Figure 7 Some aspects of the method described in may be similar to Figure 5 For example, in some cases, processing step 705, processing step 710, processing step 715, and processing step 730 may be respectively the same as reference step 706. Figure 5 Processing step 505, processing step 510, processing step 515, and processing step 530 are described as being the same.

[0120] As illustrated in process step 712, a first electrode material (EM1) may be formed on the surfaces exposed by process step 710 (e.g., on the surfaces of the trenches and through-holes created at process step 710). In some cases, EM1 may be formed as a conformal liner on the surfaces exposed by process step 710. In some cases, EM1 may be a carbon-based material. At process step 715, a second electrode material (EM2) may fill the remaining volume of the trenches and through-holes, as described with reference to process step 515. In some cases, EM2 may be a carbon-based material. Figure 5 and 6As used herein, a through hole filled with a material (e.g., a double-layer material including a first electrode material and a second electrode material) may be referred to as a hole after being filled with the material. Thus, a conformal liner (e.g., a carbon-based electrode material) may be inserted between a first dielectric material (e.g., a first dielectric material at layer 315 (e.g., D1 layer)) and a second electrode material (e.g., EM2). In some cases, the conformal liner (e.g., a carbon-based electrode material) may contact multiple surfaces of the first electrode (e.g., an electrode including EM2).

[0121] Subsequently, the anisotropic etching step included in process step 720 can remove both the EM1 material and the EM2 material. The anisotropic etching at process step 720 can be a variation of the anisotropic etching step in process step 520 (or process step 620) because process step 720 can remove both the EM1 material and the EM2 material, while process step 520 can only remove the EM2 material. Additionally, the isotropic etching step included in process step 725 can remove both the EM1 material and the EM2 material. The isotropic etching at process step 725 can be a variation of the isotropic etching step in process step 525 (or process step 625) because process step 725 can remove both the EM1 material and the EM2 material, while process step 525 can only remove the EM2 material.

[0122] Graphs 702 and 703 illustrate that processing step 712 may result in EM1 material being inserted between EM2 material and DM layers at all locations where EM2 material in the D1 layer would otherwise be in contact with the DM layer. In some cases, EM1 material (e.g., carbon-based material) may serve as a material between EM2 material (e.g., tungsten-based material) and each DM layer (e.g., reference 712). Figure 2 In some cases, each memory material element—e.g., a memory material element including a memory material at the DM layer (e.g., chalcogenide material 220) or a memory material element including a memory material that is subsequently formed by partially replacing a placeholder dielectric material at the DM layer (e.g., chalcogenide material 220)—can be coupled to the at least one first electrode via a conformal liner that can contact three surfaces of the at least one first electrode.

[0123] Although it has Figure 7 The processing steps are described and described as a reference for modification Figure 5 described processing steps, it should be understood that Figure 6The processing steps of may also be similarly modified (not shown) to form access lines that include a dual-layer electrode at each D2 layer (e.g., a dual-layer access line). Thus, both the upper and lower surfaces of the material at the DM layer may interface with the EM1 material rather than the EM2 material - thus, the memory cell at the DM layer may interface with two dual-layer electrodes (e.g., word line 110 and bit line 115). In some cases, only one access line for a memory cell (e.g., word line 110 or bit line 115) may include a dual-layer electrode, so that the asymmetric electrode configuration between the two access lines may facilitate asymmetric operation of the memory cell.

[0124] Figure 8 Exemplary via patterns and structures supporting cross-point memory arrays and related manufacturing techniques according to the present invention are described. The manufacturing techniques can be used to form a 3D cross-point memory array structure that can include two or more memory cell layers. As an illustrative example of the manufacturing techniques described herein, Figure 8 Diagrams 801 and 802 are included and may each represent a top view of the layout of a portion of a 3D cross-point memory array.

[0125] Diagram 801 includes layouts 805, 810, 815, and 820. Layout 805 is a composite plot depicting a via pattern, a set of first access lines, and a set of second access lines. As an illustrative example, layout 805 may depict 16 memory cells in a single layer of a memory array—e.g., one memory cell at each of the 16 intersections between four first access lines and four second access lines.

[0126] Layout 810 illustrates a subset of elements of layout 805, including: two sets of first through-holes, each set of first through-holes arranged in a row in a first direction (e.g., on a page, horizontally, or in the x-direction); and four first access lines extending in the first direction. The two sets of first through-holes may be separated in a second direction (e.g., on a page, vertically, or in the y-direction) by a distance 825, which may represent a distance from a center of one set of first through-holes to a center of another set of first through-holes. In some cases, the first access lines may have a conductive material (e.g., as described in reference to FIG. 1 ). Figure 1 and 2 The electrode material described above) and may be a word line (e.g., as described in reference Figure 1 and 23 ). The four first access lines may represent portions (e.g., longer sides) of two loops of electrode material with ends (e.g., shorter sides) removed, and each loop of electrode material may be formed using a set of first vias surrounded by the loop of electrode material. Thus, for example, layout 810 illustrates a set of four first access lines formed using two sets of first vias, each set of first vias being arranged in a row in a first direction. Furthermore, using layout 810, the set of four first access lines may be simultaneously formed in any number of first layers (e.g., layers initially including a first dielectric material, e.g., layers 315-a, 315-b) of a composite stack (e.g., stack 305-a) as described with reference to FIG. 3 .

[0127] Similarly, layout 815 illustrates another subset of elements of layout 805, including: two sets of second through holes, each set of second through holes arranged in a row in a second direction (e.g., on the page, vertical direction, or y direction); and four second access lines extending in the second direction. The two sets of second through holes can be separated in a first direction (e.g., on the page, horizontal direction, or x direction) by a distance 825, which can represent a distance from a center of one set of second through holes to a center of another set of second through holes. In some cases, the second access lines can have a conductive material (e.g., as described in reference to Figure 1 and 2 The electrode material described herein) and may be a bit line (e.g., as described in reference Figure 1 and 2 3 ). The four second access lines may represent portions (e.g., longer sides) of two loops of electrode material with ends (e.g., shorter sides) removed, and each loop of electrode material may be formed using a set of second vias surrounded by the loops of electrode material. Thus, for example, layout 815 illustrates a set of four second access lines formed using two sets of second vias, each set of second vias being arranged in a row in the second direction. Furthermore, using layout 815, the set of four second access lines may be simultaneously formed in any number of second layers (e.g., layers initially including a second dielectric material, such as layer 325) of a composite stack (e.g., stack 305-a) as described with reference to FIG. 3 .

[0128] Layout 820 illustrates another subset of elements of layout 805, including four first access lines in a first direction (e.g., horizontal or x-direction) and four second access lines in a second direction (e.g., vertical or y-direction). Memory components may be disposed at each location where the first access lines and the second access lines topologically intersect each other. As described above, one or more sets of first access lines (e.g., word lines) may be formed in one or more first layers of a composite stack, and one or more sets of second access lines (e.g., bit lines) may be formed in one or more second layers of a composite stack. Thus, layout 820 may be a representation of a 3D cross-point array of memory cells, where each memory cell layer includes four word lines, four bit lines, and sixteen memory cells.

[0129] Layout 820 also illustrates a unit cell 840. In the context of memory technology, a unit cell may refer to a single memory cell that includes a complete set of its components (e.g., word lines, bit lines, selection components, memory components). Repetition of the unit cell of a memory may build a memory cell array of any size. Additionally, layout 820 illustrates a cell area 841. In the context of a cross-point memory architecture, a cell area 841 may refer to an area corresponding to the area of ​​the topological intersection of access lines (e.g., word lines and bit lines). In other words, the width of a word line multiplied by the width of a bit line may define a cell area 841.

[0130] In some cases, as illustrated, in layout 820, an electrode layer—that is, a first electrode layer that may form a set of first access lines (e.g., access lines that include electrode material) here—may include a plurality of first electrodes. In some cases, a separation distance (e.g., distance 842) between first electrodes within the plurality of first electrodes may be non-uniform. In some cases, an immediately adjacent electrode (e.g., access line 843-a) may exist close to an electrode (e.g., access line 843-b), wherein the electrode (e.g., access line 843-b) separates another electrode (e.g., access line 843-c) from the immediately adjacent electrode (e.g., access line 843-a), and the electrode (e.g., access line 843-b) may be closer to the immediately adjacent electrode (e.g., access line 843-a) than another electrode (e.g., access line 843-c).

[0131] Furthermore, it should be understood that a subset of through holes may be common between a set of first through holes arranged in a row in a horizontal direction (x-direction) and a set of second through holes arranged in a row in a vertical direction (y-direction) - that is, one or more through holes may be included in both the horizontal row of first through holes and the vertical row of second through holes. Such through holes may be referred to as common through holes (e.g., common through holes 830). Common through holes 830 may be used to form a set of first access lines and to form a set of second access lines. In other words, both a processing step of forming a first access line (e.g., a word line) and a processing step of forming a second access line (e.g., a bit line) may use common through holes 830. In other words, common through holes 830 may be subjected to the same conditions as described in reference to FIG. Figure 5 and 6 505-530 and 605-630 are described. In contrast, other vias may be used to form a first access line (e.g., process steps 505-530 to form a word line) or a second access line (e.g., process steps 605-630 to form a bit line) rather than both. Such vias may be referred to as non-common vias (e.g., non-common via 835). The size of the vias, the distance between the vias, and the size of the cavity associated with the vias may be varied to obtain various layouts of the memory array - e.g., layout 805 and layout 845.

[0132] Diagram 802 illustrates a variation of layout 805 as an example of achieving a different layout of a memory array by modifying dimensions associated with vias (e.g., the size of the vias, the distance between vias, the size of the cavities associated with the vias, etc.). Diagram 802 includes layouts 845, 850, 855, and 860. Layout 845 is a composite plot depicting a pattern of vias, a set of first access lines, and a set of second access lines. As an illustrative example similar to layout 805, layout 845 may depict 16 memory cells in a single layer of a memory array—e.g., one memory cell at each of the 16 intersections between four first access lines and four second access lines.

[0133] The difference between layout 845 and layout 805 may be that the vias may be square or rectangular in layout 845. In some cases, layout 845 may have common vias 870 that are square and non-common vias 875 that are rectangular. The two sets of vias depicted in layout 850 may be separated by a distance 865 in a second direction (e.g., in the page, vertical, or y-direction), which may represent the distance from the center of one set of vias to the center of the other set of vias. Similarly, the two sets of vias may be separated by a distance 865 in a first direction (e.g., in the page, horizontal, or x-direction), which may represent the distance from the center of one set of vias to the center of the other set of vias.

[0134] As a result of using square and / or rectangular vias (e.g., square common vias 870 and / or rectangular non-common vias 875), layout 860 (e.g., when compared to layout 820) illustrates uniformly distributed access lines and constant distances between active cell areas. Layout 860 also illustrates unit cells 880, and the area of ​​unit cells 880 may be larger than the area of ​​unit cells 840. Additionally, layout 860 illustrates cell area 881, and where the width of the access lines remains constant between layout 845 and layout 805, the area of ​​cell area 881 may correspond to the area of ​​cell area 841. In some cases, more uniformly distributed access lines, and therefore more uniform distances between active cell areas, may contribute to more efficient operation of a memory array, while non-uniformly distributed access lines, and therefore non-uniform distances between active cell areas, may promote greater memory cell density within a memory array. These and other benefits and trade-offs may be apparent to one of ordinary skill in the art.

[0135] Figures 9 to 12 Various aspects of constructing memory material elements according to the fabrication techniques of the present invention are described, which can be used, for example, to fabricate 3D memory arrays, such as Figure 1 The memory array 102 and Figure 2 . The manufacturing techniques described herein may include using a single via pattern in a top (e.g., exposed) layer of a composite stack to form one or more memory material elements in one or more lower (e.g., buried) layers of the composite stack. As used herein, a via may refer to an opening that is later filled with a material that may not be conductive. In some cases, such lower layers in which memory material elements are formed may be referred to as memory layers—e.g., as described with reference to Figure 5 and 6 In some embodiments, the DM layers (e.g., layers 320-a and 320-b) may initially include memory materials (e.g., chalcogenide material 220). In other embodiments, the DM layers (e.g., layers 320-a and 320-b) may initially include placeholder materials (e.g., as described in reference Figure 5 The third dielectric material described herein).

[0136] Fig. 9An example of a 3D cross point memory array structure 905 that may include two or more layers of memory cells and that may be formed according to the fabrication techniques of the present invention is illustrated. The array structure 905 may include two layers of memory cells (e.g., an upper layer 945-a and a lower layer 945-b). The two layers of memory cells collectively include two sets of first access lines that may be formed simultaneously (e.g., the upper layer 945-a includes one set of word lines 910-a and 910-b, and the lower layer 945-b includes another set of word lines 910-c and 910-d), two memory layers of memory material that may be formed simultaneously (e.g., memory layers 920-a and 920-b), and one set of second access lines (e.g., bit lines 915) that are common to both layers of memory cells. The first access lines (e.g., word lines 910) may extend in a first direction (e.g., the x-direction), while the second access lines (e.g., bit lines 915) may extend in a second, different direction (e.g., the z-direction). Each first access line in a set of first access lines (e.g., word lines 910) can be parallel to each other first access line in the set of first access lines, and each second access line in a set of second access lines (e.g., bit lines 915) can be parallel to each other second access line in the set of second access lines. The first access lines (e.g., word lines 910) can be substantially orthogonal to the second access lines (e.g., bit lines 915) as depicted in the array structure 905.

[0137] The upper layer 945-a may include word lines 910-a and 910-b, memory layer 920-a, and bit lines 915, and the lower layer 945-b may include word lines 910-c and 910-d, memory layer 920-b, and bit lines 915. Thus, the bit lines 915 may be common to the upper layer 945-a and the lower layer 945-b in the array structure 905. In addition, the word lines 910 may be formed in the first electrode layer (e.g., layers 315-a and 315-b as described with reference to FIG. 3, as described with reference to FIG. 3). Figures 5 to 7 Similarly, the bit line 915 may be formed in a second electrode layer (eg, layer 325 as described in reference FIG. 3 , as described in reference FIG. 3 ). Figures 5 to 7 Finally, memory layer 920 may be a memory layer (eg, layer 320-a and layer 320-b as described with reference to FIG. 3 , as described with reference to FIG. 3 ). Figures 5 to 7 Thus, upper layer 945-a may correspond to an upper layer of memory cells formed in a first subset of composite stack 305-a including layer 315-a, layer 320-a, and layer 325, while lower layer 945-b may correspond to a lower layer of memory cells formed in a second subset of composite stack 305-a including layer 325, layer 320-b, and layer 315-b.

[0138] Array structure 905 shows horizontal (x or z direction) spaces between structures within a layer (e.g., the space between word line 910-a and word line 910-b within the first electrode layer), which can be filled with dielectric material. Array structure 905 also shows vertical (y direction) spaces between layers - for example, the space between memory layer 920-a and the first electrode layer including word lines 910-a and 910-b - for illustration purposes only. Such vertical spaces shown in array structure 905 may not exist in actual embodiments. In some cases, a portion of the interface between the memory layer and the electrode layer may include other materials, such as as described in reference to FIG. Figure 7 Additional electrode materials described (eg, carbon).

[0139] The array structure 905 includes two memory layers 920-a and 920-b, the first memory layer 920-a being included in the upper layer 945-a and the second memory layer 920-b being included in the lower layer 945-b. An initial layer stack (e.g., stack 305-a described with reference to FIG. 3 ) may include one or more memory layers 920, which may each include a thin sheet of memory material (e.g., chalcogenide material 220). Including one or more memory layers as part of the initial stack may provide benefits in terms of reduced manufacturing time and cost due to fewer processing steps associated with manufacturing the array structure 905. In some cases, reference may be made to the memory layer 305-a described with reference to FIG. 3 . Figure 5 and 6 The described processing steps may be used to build the array structure 905 and may produce each memory layer including a thin sheet of memory material perforated by a plurality of dielectric plugs, such as dielectric plug 930. Perforating the thin sheet of memory material with dielectric plugs may, for example, produce a thin sheet of memory material having a plurality of dielectric plugs, such as dielectric plug 930. Figure 5 and 6 Processing steps 530 and 630 are described.

[0140] Fig. 9 Figure 906 is included, which illustrates an isolated memory layer 920-c, which includes a thin sheet of memory material perforated by multiple dielectric plugs (e.g., dielectric plugs 930-c to 930-e). Some portions of the memory layer 920-c may include memory cells 105 and may operate in conjunction with a first access line and a second access line. Such portions of the memory layer 920-c may be referred to as cell regions 925 (e.g., cell regions 925-a) and may be located where a first access line (e.g., word line 910-a) and a second access line (e.g., bit line 915-a) intersect topologically. The cell region 925 may correspond to the intersection 465 (e.g., the area of ​​the intersection associated with the width of the access line) as described with reference to Figure 4. In addition, the cell region 925 may be as described with reference to Figure 4. Figure 8 An example of cell region 841 or cell region 881 is depicted.

[0141] In addition, the thickness of the cell region 925 and the memory layer 920 (e.g., the thickness of the memory material sheet perforated by the plurality of dielectric plugs) may define a cell volume 926. The cell volume 926 may refer to the volume of the memory material that serves as the memory cell 105 (e.g., serves as a portion of the memory material configured to store a logical state). In some cases, the memory material may include different crystalline phases, and the different crystalline phases may correspond to different logical states. In other cases, the memory material may include different local compositions, and the different local compositions may correspond to different logical states. In some cases, electrical operations associated with access lines (e.g., the voltage difference between a word line and a bit line) may change the crystalline phase of the memory material (or the local composition of the memory material) contained in the cell volume 926 without changing the rest of the memory layer 920 (e.g., the memory material sheet perforated by the plurality of dielectric plugs). Such electrical delimitation between the memory material contained in the cell volume 926 and the rest of the memory layer may be referred to as electrical confinement of the effective cell volume. In some cases, the cell volume 926 of the memory cell 105 may be referred to as the effective cell volume of the memory cell 105 .

[0142] Fig. 9 Also illustrated is a top view 907 of an isolated memory layer 920-d, such as a thin sheet of memory material perforated by a plurality of dielectric plugs. Memory layer 920-d may be an example of memory layers 920-a to 920-c. Memory layer 920-d may be positioned in a plane defined by an x-axis and a z-axis. Memory layer 920-d may include a pattern of dielectric plugs corresponding to a pattern of vias. The pattern of dielectric plugs may, for example, correspond to the pattern of vias depicted in layout 805.

[0143] In some cases, a first subset of vias can be used to create one or more sets of first access lines (e.g., word lines 910) and arrange the first subset of dielectric plugs in a row in a horizontal direction (e.g., an x-direction in an xz plane defined by an x-axis and a z-axis). Additionally, a second subset of vias can be used to create one or more sets of second access lines (e.g., bit lines 915) and arrange the second subset of dielectric plugs in a row in a vertical direction (e.g., a z-direction in an xz plane defined by an x-axis and a z-axis). For example, the first subset of dielectric plugs can be created from a plurality of first access lines (e.g., word lines 910) and arrange the first subset of dielectric plugs in a row in a vertical direction (e.g., a z-direction in an xz plane defined by an x-axis and a z-axis). Figure 5 The processing step 530 described above and the second subset of dielectric plugs may be produced from the reference Figure 6907. Thus, in some cases, a first subset of dielectric plugs arranged in a row in a horizontal direction (e.g., corresponding through-holes disposed in a first linear configuration having a first direction) may include a first dielectric material, and a second subset of dielectric plugs arranged in a row in a vertical direction (e.g., corresponding through-holes disposed in a second linear configuration having a second direction intersecting the first direction) may include a second dielectric material. In some cases, a dielectric plug (e.g., dielectric plug 930-e, which is illustrated as a dark shaded dielectric plug in FIG. 907, like other common dielectric plugs) may be common to the rows of dielectric plugs (e.g., the first subset of dielectric plugs and the second subset of dielectric plugs).

[0144] In some cases, the size of the vias and the distance between the vias can be varied to achieve various memory array configurations (e.g., see Figure 8 805 or layout 845 as described). Thus, the pattern of dielectric plugs in one or more memory layers 920, each including a thin sheet of memory material, can be varied so that a thin sheet of memory material can be perforated by multiple dielectric plugs having various sizes and distances between dielectric plugs.

[0145] Fig.10 An example of a 3D cross point memory array structure 1005 that may include two or more layers of memory cells and that may be formed according to the fabrication techniques of the present invention is illustrated. The array structure 1005 may include two layers of memory cells (e.g., upper layer 1060-a and lower layer 1060-b). The two layers of memory cells collectively include two sets of first access lines that may be formed simultaneously (e.g., upper layer 1060-a includes one set of word lines 1010-a and 1010-b, and lower layer 1060-b includes another set of word lines 1010-c and 1010-d), two memory layers of memory material that may be formed simultaneously (e.g., memory layers 1020-a and 1020-b), and one set of second access lines (e.g., bit lines 1015) that are common to both layers of memory cells. The first access lines (e.g., word lines 1010) may extend in a first direction (e.g., the x-direction), while the second access lines (e.g., bit lines 1015) may extend in a second, different direction (e.g., the z-direction). Each first access line in a set of first access lines (e.g., word lines 1010) can be parallel to each other first access line in the set of first access lines, and each second access line in a set of second access lines (e.g., bit lines 1015) can be parallel to each other second access line in the set of second access lines. The first access lines (e.g., word lines 1010) can be substantially orthogonal to the second access lines (e.g., bit lines 1015) as depicted in array structure 1005.

[0146] The upper layer 1060-a may include word lines 1010-a and 1010-b, memory layer 1020-a, and bit line 1015, and the lower layer 1060-b may include word lines 1010-c and 1010-d, memory layer 1020-b, and bit line 1015. Thus, bit line 1015 may be common to upper layer 1060-a and lower layer 1060-b in array structure 1005. In addition, word line 1010 may be formed in a first electrode layer (e.g., layer 315-a and layer 315-b as described with reference to FIG. 3, as described with reference to FIG. 3). Figures 5 to 7 Similarly, the bit line 1015 may be formed in a second electrode layer (eg, layer 325 as described in reference FIG. 3 , as described in reference FIG. 3 ). Figures 5 to 7 Finally, each of the memory layers 1020 including memory material elements (e.g., memory layer 1020-a including memory material element 1035-a, memory layer 1020-b including memory material element 1035-b) may be a memory layer (e.g., layer 320-a and layer 320-b as described with reference to FIG. 3, as described with reference to FIG. 3). Figures 5 to 7 Thus, upper layer 1060-a may correspond to an upper layer of memory cells formed in a first subset of composite stack 305-a including layer 315-a, layer 320-a, and layer 325, while lower layer 1060-b may correspond to a lower layer of memory cells formed in a second subset of composite stack 305-a including layer 325, layer 320-b, and layer 315-b.

[0147] Array structure 1005 shows horizontal (x or z direction) spaces between structures within a layer (e.g., the space between word line 1010-a and word line 1010-b within the first electrode layer), which can be filled with a dielectric material. Array structure 1005 also shows vertical (y direction) spaces between layers - for example, the space between memory layer 1020-a and the first electrode layer including word lines 1010-a and 1010-b - for illustrative purposes only. Such vertical spaces shown in array structure 1005 may not exist in actual embodiments. In some cases, a portion of the interface between the memory layer and the electrode layer may include other materials, such as as described in reference to FIG. Figure 7 Additional electrode materials described (eg, carbon).

[0148] Array structure 1005 includes two memory layers 1020-a and 1020-b, the first memory layer 1020-a is included in the upper layer 1060-a and the second memory layer 1020-b is included in the lower layer 1060-b. An initial layer stack (such as stack 305-a described with reference to FIG. 3) may include one or more memory layers 1020, which may each include a thin sheet of memory material (such as chalcogenide material 220). In some cases, each memory layer 1020 may include a plurality of memory material elements 1035, each memory material element 1035 being in a 3D rectangular shape as illustrated in FIG. 1006.

[0149] Fig.10 A diagram 1006 is included illustrating an isolated memory layer 1020 that includes four 3D rectangular shaped memory material elements (e.g., 1035-c to 1035-f). It should be understood that the memory layer 1020 may include any number of memory material elements 1035. The 3D rectangular shaped memory material elements 1035-c and 1035-d of diagram 1006 may correspond to the two 3D rectangular shaped memory material elements depicted in the memory layer 1020-a of the array structure 1005. Furthermore, the multiple memory material elements 1035 depicted in diagram 1006 may at some time be part of a single memory material sheet included in a composite stack.

[0150] Some portions of each 3D rectangular shaped memory material element 1035 may include memory cells 105 and may operate in conjunction with a first access line and a second access line. Such portions of the memory material element 1035 may be referred to as a cell region 1025 (e.g., a cell region 1025-a of an upper layer 1060-a), and may be located within a memory layer 1020 where a first access line (e.g., a word line 1010-a) and a second access line (e.g., a bit line 1015-a) intersect topologically. The cell region 1025 may correspond to an intersection 465 as described with reference to FIG. 4 (e.g., an area of ​​an intersection associated with a width of an access line). Additionally, the cell region 1025 may be a cell region 1025 of the memory layer 1020. Figure 8 An example of cell region 841 or cell region 881 is depicted.

[0151] In addition, the thickness of the cell region 1025 and the memory layer 1020 (e.g., the thickness of the 3D rectangular shaped memory material element 1035-a) can define a cell volume 1026. The cell volume 1026 can refer to the volume of the memory material (e.g., a portion of the memory material configured to store a logic state) that serves as the memory cell 105. In some cases, the memory material can include different crystalline phases, and the different crystalline phases can correspond to different logic states. In other cases, the memory material can include different local compositions, and the different local compositions can correspond to different logic states. In some cases, electrical operations associated with access lines (e.g., a voltage difference between a word line and a bit line) can change the crystalline phase of the memory material (or the local composition of the memory material) contained in the cell volume 1026 without changing the remainder of the memory material element 1035. Such electrical delimitation between the memory material contained in the cell volume 1026 and the remainder of the memory material element 1035 can be referred to as electrical confinement of the effective cell volume. In some cases, the cell volume 1026 of the memory cell 105 may be referred to as the effective cell volume of the memory cell 105 .

[0152] Additionally, one or more physical partitions (e.g., trenches 1036-a or 1036-b filled with dielectric material as illustrated in FIG. 1006) separating each 3D rectangular shaped memory material element from one another may also define the cell volume 1026 and provide physical separation on at least two surfaces of the memory cell 105 (e.g., two surfaces of the cell volume 1026). In some cases, such physical separation may be referred to as a physical limitation of the effective cell volume—e.g., as compared to an electrical limitation of the effective cell volume.

[0153] In the illustrative example of cell volumes 1026, each cell volume 1026 includes two interfaces defined by electrical limitations and another two interfaces defined by physical limitations. In some cases, a memory cell 105 including memory materials defined by physical limitations of an effective cell volume may be less prone to various non-ideal phenomena (e.g., interference) during memory cell operation. For example, a memory cell 105 of array structure 1005 includes an effective cell volume defined by two interfaces of physical limitations and two interfaces of electrical limitations. In contrast, a memory cell 105 of array structure 905 includes an effective cell volume defined by four interfaces of electrical limitations. Therefore, a memory cell 105 of array structure 1005 may be less prone to non-ideal phenomena than a memory cell 105 of array structure 905.

[0154] Fig.10 A top view of layout 1007 is also shown. Layout 1007 may be used as a reference. Figure 8The example of the layout 845 described herein can illustrate how a via pattern can simultaneously form one or more 3D rectangular shaped memory material elements 1035 within each of a plurality of memory layers (e.g., layers 320-a, 320-b described with reference to FIG. 3 ) included in a stack. Figure 4A As illustrated, a collection of through holes arranged in a row can be used to form a channel (e.g., channel 420) in a target material at a target layer. Forming such a channel (e.g., channel 420) at a target layer can cut (e.g., divide, separate) the target material at the target layer into two different sections of the target material. Similarly, forming multiple channels at a target layer can cut the target material at the target layer into more than two different sections of the target material.

[0155] In an illustrative example using layout 1007, one or more sets of first vias may be formed at a top layer (e.g., layer 310) of a composite stack (e.g., stack 305-a) including a sheet of memory material at a memory layer (e.g., layer 320-a), with each set of first vias (e.g., vias 1040-a to 1040-e) arranged in a row in a horizontal direction (e.g., the first vias may be disposed linearly in the x-direction). Additionally, one or more sets of second vias may be formed at a top layer of the composite stack, with each set of second vias (e.g., vias 1040-a and vias 1040-f to 1040-i) arranged in a row in a vertical direction (e.g., the second vias may be disposed linearly in the z-direction).

[0156] The set of first through holes can be used to form a group of first channels in the horizontal direction (x-direction) in the memory material at the memory layer, wherein each first channel is aligned with the set of first through holes. In addition, the set of second through holes can be used to form a group of second channels in the vertical direction (z-direction) in the memory material at the same memory layer, so that each second channel can intersect with the group of first channels. Each of the first channels and each of the second channels can be filled with a dielectric material (e.g., channels 1036-a or 1036-b are filled with a dielectric material as illustrated in FIG. 1006). Forming a first channel filled with a dielectric material at a memory layer (e.g., extending in the x-direction) can divide (e.g., separate, cut) a thin sheet of memory material at a memory layer (e.g., layer 320-a) into a first plurality of discrete segments of memory material at the memory layer (e.g., horizontal bands extending in the x-direction). Additionally, forming a second trench filled with dielectric material at the memory layer (e.g., extending in the z-direction) can further divide (e.g., separate, cut) each of the first plurality of discrete segments into a second plurality of discrete sub-segments of memory material at the memory layer (e.g., rectangles of memory material elements 1045-a to 1045-d of layout 1007). The rectangles of memory material (e.g., rectangles of memory material elements 1045-a to 1045-d of layout 1007) can correspond to 3D rectangular-shaped memory material elements 1035 (e.g., memory material elements 1035-c to 1035-f of FIG. 1006).

[0157] Thus, two sets of through holes - for example, a first set of through holes and a second set of through holes - can be used to simultaneously divide a 3D memory material sheet at one or more memory layers (e.g., layer 320-a, layer 320-b) within a layer stack (e.g., stack 305-a) into multiple 3D rectangular-shaped memory material elements within each of the memory layers.

[0158] In some cases, the top layer (e.g., layer 310) of the stack (e.g., stack 305-a) may include a pattern of vias, so a set of vias in a two-dimensional matrix is ​​formed by a photolithography step and an anisotropic etching step that establishes a 2D matrix pattern of vias in the top layer, the vias including a set of first vias and a set of second vias. In some cases, the top layer may include a hard mask material that can preserve the pattern of vias (e.g., vias in a 2D matrix) throughout the various processing steps described in Figures 3-7. Thus, the processing steps for forming the channels can form channels (e.g., channels 1036-a or 1036-b filled with dielectric material) in two directions (e.g., horizontal and vertical directions, i.e., x-direction and z-direction) at the same time and can produce a variety of 3D rectangular shapes of memory materials at the same time.

[0159] It should be understood that the same set of through holes (e.g., the set of first through holes and the set of second through holes) used to form a plurality of rectangular shaped memory material elements (e.g., memory material element 1035 of FIG. 1006, memory material element 1045 of layout 1007) can also be used to form a plurality of rectangular shaped memory material elements (e.g., memory material element 1035 of FIG. 1006, memory material element 1045 of layout 1007) in a similar manner as described in reference to FIG. Figure 8 850 and 855 of the present invention form a set of access lines (e.g., word line 1010 and bit line 1015) at the electrode layer described by the layout 850 and the layout 855 of the present invention. For example, a set of first vias arranged in a row in the horizontal direction (e.g., vias 1040-a to 1040-e disposed linearly in the x-direction) can be used to form a first number of trenches filled with a dielectric material at a memory layer (e.g., memory layer 320-a) including a sheet of memory material and can be used to form a first number of loops of electrode material at an electrode layer (e.g., electrode layer 315-a or electrode layer 315-b) to form a first access line (e.g., word line 1010).

[0160] Furthermore, each rectangular-shaped memory material element (e.g., memory material elements 1045-a to 1045-d) of the layout 1007 may include four corner regions (e.g., regions 1050-a) where word lines (e.g., 1010-e) and bit lines (e.g., 1015-b) intersect in a topological manner, and portions of the memory material elements at the topological intersection points may be configured to serve as memory cells 105. Thus, the area of ​​intersecting access lines (e.g., word lines 1010-e and bit lines 1015-b) corresponding to the corner regions of each rectangular-shaped memory material element (e.g., memory material element 1045-b) of the layout 1007 may be equal to the cell region 1025 of the array structure 1005. In other words, each rectangular-shaped memory material element may support four memory cells 105. In addition, each rectangular-shaped memory material element (e.g., memory material element 1045-b) can be coupled to four electrodes - for example, bit line 1015-b, bit line 1015-c, word line 1010-e and word line 1010-f as described in layout 1007 or word line 1010-a, word line 1010-b, bit line 1015-a and bit line 1015-b as described in array structure 1005.

[0161] Fig.11An example of a 3D cross-point memory array structure 1105 that may include two or more layers of memory cells and that may be formed according to the fabrication techniques of the present invention is illustrated. The array structure 1105 may include two layers of memory cells (e.g., an upper layer 1160-a and a lower layer 1160-b). The two layers of memory cells collectively include two sets of first access lines that may be formed simultaneously (e.g., the upper layer 1160-a includes one set of word lines 1110-a and 1110-b, and the lower layer 1160-b includes another set of word lines 1110-c and 1110-d), two memory layers of memory material that may be formed simultaneously (e.g., memory layers 1120-a and 1120-b), and one set of second access lines (e.g., bit lines 1115) that are common to both layers of memory cells. The first access lines (e.g., word lines 1110) may extend in a first direction (e.g., an x-direction), while the second access lines (e.g., bit lines 1115) may extend in a second, different direction (e.g., a z-direction). Each first access line in a set of first access lines (e.g., word lines 1110) can be parallel to each other first access line in the set of first access lines, and each second access line in a set of second access lines (e.g., bit lines 1115) can be parallel to each other second access line in the set of second access lines. The first access lines (e.g., word lines 1110) can be substantially orthogonal to the second access lines (e.g., bit lines 1115) as depicted in array structure 1105.

[0162] The upper layer 1160-a includes word lines 1110-a and 1110-b, memory layer 1120-a, and bit line 1115, and the lower layer 1160-b includes word lines 1110-c and 1110-d, memory layer 1120-b, and bit line 1115. Therefore, bit line 1115 is common to both upper layer 1160-a and lower layer 1160-b. In addition, word line 1110 may be formed in the first electrode layer (e.g., layer 315-a and layer 315-b as described with reference to FIG. 3, as described with reference to FIG. 3). Figures 5 to 7 Similarly, the bit line 1115 may be formed in a second electrode layer (eg, layer 325 as described in reference FIG. 3 , as described in reference FIG. 3 ). Figures 5 to 7 Finally, memory layer 1120 may be a memory layer (e.g., layer 320-a and layer 320-b as described in reference FIG. 3, as described in reference FIG. 3). Figures 5 to 7Thus, upper layer 1160-a may correspond to an upper layer of memory cells formed in a first subset of composite stack 305-a including layer 315-a, layer 320-a, and layer 325, while lower layer 1160-b may correspond to a lower layer of memory cells formed in a second subset of composite stack 305-a including layer 325, layer 320-b, and layer 315-b.

[0163] Array structure 1105 shows horizontal (x or z direction) spaces between structures within a layer (e.g., space between word line 1110-a and word line 1110-b within a first electrode layer), which space may be filled with a dielectric material. Array structure 1105 also shows vertical (y direction) spaces between layers—e.g., space between memory layer 1120-a and a first electrode layer including word lines 1110-a and 1110-b—for illustrative purposes only. Such vertical spaces shown in array structure 1105 may not exist in actual embodiments. In some cases, a portion of the interface between the memory layer and the electrode layer may include other materials, such as as described in reference to FIG. Figure 7 Additional electrode materials described (eg, carbon).

[0164] The array structure 1105 includes memory layers 1120-a and 1120-b corresponding to two respective layers of memory cells. An initial layer stack (e.g., stack 305-a described with reference to FIG. 3) may include one or more memory layers 1120. As part of the initial stack, one or more memory layers 1120 may include a sheet of placeholder material. In some cases, the placeholder material may be a sheet of placeholder material as described with reference to FIG. Figure 5 In some cases, after completing the processing steps to build array structure 1105, memory layer 1120 may include a plurality of memory material elements, each memory material element being in the shape of a 3D strip as illustrated in diagram 1106.

[0165] Fig.11 Included is a diagram 1106 illustrating an isolated memory layer 1120 that includes eight 3D strip-shaped memory material elements, such as strip-shaped memory material elements 1135. The 3D strip-shaped memory material elements 1135-a to 1135-d of Figure 1106 may correspond to four of the 3D strip-shaped memory material elements depicted in the memory layer 1120-a of the array structure 1105.

[0166] One or more portions of each 3D strip-shaped memory material element (e.g., memory material element 1135-a) may include a memory cell 105 and may operate in conjunction with a first access line and a second access line. Such a portion of the memory material element 1135-a may be referred to as a cell region 1125 (e.g., cell region 1125-a) and may be positioned within the memory layer 1120 where a first access line (e.g., word line 1110-a) and a second access line (e.g., bit line 1115-a) intersect topologically. The cell region 1125 may correspond to the intersection 465 described with reference to FIG. 4 (e.g., the area of ​​the intersection associated with the width of the access line). In addition, the cell region 1125 may be as described with reference to FIG. Figure 8 An example of cell region 841 or cell region 881 is depicted.

[0167] In addition, the thickness of the cell region 1125 and the memory layer 1120 (e.g., the thickness of the memory material element 1135-a) can define a cell volume 1126. The cell volume 1126 can refer to the volume of the memory material that serves as the memory cell 105 (e.g., serves as a portion of the memory material configured to store a logical state). In some cases, the memory material can include different crystalline phases, and the different crystalline phases can correspond to different logical states. In other cases, the memory material can include different local compositions, and the different local compositions can correspond to different logical states. In some cases, electrical operations associated with access lines (e.g., the voltage difference between a word line and a bit line) can change the crystalline phase of the memory material (or the local composition of the memory material) contained in the cell volume 1126 without changing the remainder of the memory material element 1135. Such electrical delimitation between the memory material contained in the cell volume 1126 and the remainder of the memory material element 1135 can be referred to as electrical confinement of the effective cell volume. In some cases, the cell volume 1126 of the memory cell 105 may be referred to as the effective cell volume of the memory cell 105 .

[0168] Additionally, one or more physical partitions (e.g., trenches 1136-a or 1136-b filled with dielectric material as illustrated in FIG. 1106) that separate each 3D strip-shaped memory material element from one another may also define the cell volume 1126 and provide physical partitions on at least three surfaces of the memory cell 105 (e.g., three surfaces of the cell volume 1126). In some cases, such physical partitions may be referred to as physical limitations of the effective cell volume—e.g., as compared to electrical limitations of the effective cell volume.

[0169] In the illustrative example of cell volumes 1126, each cell volume 1126 includes one interface defined by electrical limitations and three other interfaces defined by physical limitations. In some cases, a memory cell 105 including memory materials defined by physical limitations of an effective cell volume may be less prone to various non-ideal phenomena (e.g., interference) during memory cell operation. For example, a memory cell 105 of array structure 1105 includes an effective cell volume defined by three interfaces of physical limitations and two interfaces of electrical limitations. In contrast, a memory cell 105 of array structure 1005 includes an effective cell volume defined by two interfaces of physical limitations and two interfaces of electrical limitations. Therefore, a memory cell 105 of array structure 1105 may be less prone to non-ideal phenomena than a memory cell 105 of array structure 1005 (and a memory cell 105 of array structure 905).

[0170] Fig.11 Also illustrated is a layout 1107. The layout 1107 may be as shown in FIG. Figure 8 The example of the layout 805 described herein can illustrate how a via pattern can simultaneously form one or more 3D strip-shaped memory material elements 1135 in each of a plurality of memory layers (e.g., layers 320-a, 320-b described with reference to FIG. 3 ) included in a stack. Figure 4A As illustrated, a collection of vias arranged in a row can be used to form a loop of fill material (such as loop 450) at a target layer. Figure 4A and for example Figure 5 and 6 In the context of , the fill material may be a conductive material, such as an electrode material. But similar techniques may also be used to form a loop of memory material (e.g., chalcogenide material 220) in each memory layer (e.g., layer 320-a, layer 320-b) by using the memory material as the fill material—that is, a portion of the placeholder material (e.g., third dielectric material) at each memory layer may be replaced by a loop of memory material (e.g., chalcogenide material 220). Subsequently, the loop of memory material may be cut (e.g., separated) into any number of segments by using another set of vias to form channels (e.g., channels of channel 420) at the memory layer, where the channels intersect (and thereby separate, divide, cut the loop of memory material into multiple memory material elements). The channels that cut the loop of memory material may be filled with dielectric material.

[0171] In an illustrative example using layout 1107, one or more sets of first vias may be used to simultaneously form a first number of loops of memory material (e.g., two loops of memory material) in each of one or more memory layers (e.g., memory layers 320-a or 320-b) in some cases, each set of first vias being arranged in a row in the vertical direction (z direction) - for example, any of the groups of five vias 1140-a and 1140-b. As a result of the photolithography steps and the anisotropic etching steps, the set of first vias may be formed at the top layer (e.g., layer 310) of the composite stack (e.g., stack 305-a). A portion of the placeholder material may be removed from the memory layer by the set of first vias to form a first channel using one of the set of first vias at the memory layer. Thus, the first channel may be aligned with the set of first vias. Subsequently, the memory material may fill the first channel. Then, a second channel may be formed within the first channel filled with the memory material by removing a portion of the memory material using the same set of first vias. The second trench can be narrower than the first trench and can be filled with a dielectric material. Filling the second trench with a dielectric material can create a loop (eg, a strip, ring, or track) of memory material surrounding the dielectric material in the second trench.

[0172] Subsequently, one or more sets of second vias can be used to simultaneously form a second number of horizontal channels (e.g., two horizontal channels) filled with dielectric material at each of the one or more memory layers including the first number of loops of memory material in some cases, each set of second vias arranged in a row in the horizontal direction (x-direction) - for example, any of the groups of five vias 1140-c and 1140-d. As a result of the photolithography steps and the anisotropic etching steps, the set of second vias can be formed at the top layer (e.g., layer 310) of the composite stack (e.g., stack 305-a). As depicted in layout 1107, the sets of second vias arranged in a row in the horizontal direction (x-direction) can each intersect the set of first vias arranged in a row in the vertical direction (z-direction). Forming a horizontal (x-direction) trench filled with dielectric material (e.g., the third trench) can divide (e.g., cut or separate) a loop of memory material at a memory layer (e.g., layer 320-a) to produce multiple discrete segments (e.g., strips) of memory material (e.g., memory materials 1145-a to 1145-d) at the memory layer. In other words, the third trench can separate the memory material (e.g., memory material strip) within the first trench into multiple memory material elements (e.g., memory material element 1135 of FIG. 1106).

[0173] Thus, two sets of through holes - for example, a first set of through holes and a second set of through holes - can be used to form multiple loops of memory material (for example, using the first set of through holes) at one or more memory layers (for example, layer 320-a, layer 320-b) that initially include placeholder material and to divide the loops of memory material into multiple 3D strip-shaped memory material elements (for example, using the second set of through holes), respectively.

[0174] It should be understood that the same set of through holes (eg, a set of first through holes and a set of second through holes) used to form a plurality of 3D strip-shaped memory material elements at the memory layer can also be used in the example of reference Figure 8 850 and 855 of the present invention form a set of access lines, such as word lines 1110 and bit lines 1115, at an electrode layer as described in the layout 850 and the layout 855 of the present invention. For example, a first set of vias, such as a group of five vias 1140-a and 1140-b, can be used to form a first number of loops of memory material at a memory layer, such as memory layer 320-a, and to form a first number of loops of electrode material at an electrode layer, such as electrode layer 315-a or electrode layer 315-b.

[0175] In addition, each strip-shaped memory material element (e.g., memory material element 1145) of the layout 1107 may include two end regions (e.g., region 1150-a) where word lines (e.g., 1110-e) and bit lines (e.g., 1115-b) intersect in a topological manner, and the portion of the memory material element at the topological intersection point may be configured to serve as a memory cell 105. Therefore, the intersecting access lines (e.g., word lines 1110-e and bit lines 1115-b) corresponding to the end regions of each strip-shaped memory material element of the layout 1107 may be equal to the cell area 1125 of the array structure 1105. In other words, each strip-shaped memory material element may support two memory cells 105. In addition, each strip-shaped memory material element (e.g., 1145-a) can be coupled to at least three electrodes - for example, word line 1110-f, word line 1110-g and bit line 1115-b as illustrated in layout 1107 or word line 1110-a, word line 1110-b and bit line 1115-a as illustrated in array structure 1105.

[0176] In some cases, a 3D cross-point memory array structure (e.g., using reference Fig.10 and 11The device of the array structure 1005 or 1105) constructed by the described manufacturing technology may include: a stack comprising a first electrode layer, a second electrode layer, and a memory layer between the first electrode layer and the second electrode layer; a plurality of first electrodes in the first electrode layer; a plurality of second electrodes in the second electrode layer; and a plurality of memory material elements at the memory layer, each memory material element coupling at least one first electrode among the plurality of first electrodes and at least two second electrodes among the plurality of second electrodes.

[0177] In some instances of the apparatus described above, each memory material element is coupled to two first electrodes and one second electrode. In some instances of the apparatus described above, each memory material element is coupled to two first electrodes and two second electrodes. In some instances of the apparatus described above, each memory material element is coupled to at least one first electrode via a conformal liner in contact with three surfaces of at least one first electrode. In some instances of the apparatus described above, a separation distance between first electrodes within a plurality of first electrodes is non-uniform. In some instances of the apparatus described above, a subset of the plurality of first electrodes has a common longitudinal axis. In some instances of the apparatus described above, a first electrode has at least one dimension that is less than a minimum feature size. In some instances of the apparatus described above, each memory material element comprises a chalcogenide material.

[0178] In some cases, a 3D cross-point memory array structure (e.g., using reference Figures 9 to 11 The device of the array structure 905, 1005 or 1105) constructed by the described manufacturing technology may include: a stack comprising a first electrode layer, a second electrode layer, and a memory layer between the first electrode layer and the second electrode layer; a plurality of first electrodes in the first electrode layer; a plurality of second electrodes in the second electrode layer; and a memory material element at the memory layer, wherein the memory material element is configured to include a plurality of memory cells.

[0179] In some instances of the apparatus described above, the memory material element is configured to include two memory cells. In some instances of the apparatus described above, the memory material element is configured to include four memory cells. In some instances of the apparatus described above, the memory material element includes a thin sheet of memory material perforated by a plurality of dielectric plugs. In some instances of the apparatus described above, the plurality of dielectric plugs include a first row of dielectric plugs in a first direction and a second row of dielectric plugs in a second direction different from the first direction. In some instances of the apparatus described above, the dielectric plugs are common to the first row of dielectric plugs and the second row of dielectric plugs. In some instances of the apparatus described above, the memory material element includes a chalcogenide material.

[0180] Fig.12 An example of a 3D cross point memory array structure 1205 that may include two or more layers of memory cells and that may be formed according to the fabrication techniques of the present invention is illustrated. The array structure 1205 may include two layers of memory cells (e.g., an upper layer 1260-a and a lower layer 1260-b). The two layers of memory cells collectively include two sets of first access lines that may be formed simultaneously (e.g., the upper layer 1260-a includes one set of word lines 1210-a and 1210-b, and the lower layer 1260-b includes another set of word lines 1210-c and 1210-d), two memory layers of memory material that may be formed simultaneously (e.g., memory layers 1220-a and 1220-b), and one set of second access lines (e.g., bit lines 1215) that are common to both layers of memory cells. The first access lines (e.g., word lines 1210) may extend in a first direction (e.g., the x-direction), while the second access lines (e.g., bit lines 1215) may extend in a second, different direction (e.g., the z-direction). Each first access line in a set of first access lines (e.g., word lines 1210) can be parallel to each other first access line in the set of first access lines, and each second access line in a set of second access lines (e.g., bit lines 1215) can be parallel to each other second access line in the set of second access lines. The first access lines (e.g., word lines 1210) can be substantially orthogonal to the second access lines (e.g., bit lines 1215) as depicted in array structure 1205.

[0181] The upper layer 1260-a includes word lines 1210-a and 1210-b, memory layer 1220-a, and bit line 1215, and the lower layer 1260-b includes word lines 1210-c and 1210-d, memory layer 1220-b, and bit line 1215. Therefore, bit line 1215 is common to both upper layer 1260-a and lower layer 1260-b. In addition, word line 1210 may be formed in the first electrode layer (e.g., layer 315-a and layer 315-b as described with reference to FIG. 3, as described with reference to FIG. 3). Figures 5 to 7 Similarly, the bit line 1215 may be formed in a second electrode layer (eg, layer 325 as described in reference FIG. 3 , as described in reference FIG. 3 ). Figures 5 to 7 Finally, memory layer 1220 may be a memory layer (eg, layer 320-a and layer 320-b as described in reference FIG. 3 , as described in reference FIG. 3 ). Figures 5 to 7Thus, upper layer 1260-a may correspond to an upper layer of memory cells formed in a first subset of composite stack 305-a including layer 315-a, layer 320-a, and layer 325, while lower layer 1260-b may correspond to a lower layer of memory cells formed in a second subset of composite stack 305-a including layer 325, layer 320-b, and layer 315-b.

[0182] Array structure 1205 shows horizontal (x or z direction) spaces between structures within a layer (e.g., the space between word line 1210-a and word line 1210-b within the first electrode layer), which may be filled with a dielectric material. Array structure 1205 also shows vertical (y direction) spaces between layers - for example, the space between memory layer 1220-a and the first electrode layer including word lines 1210-a and 1210-b - for illustrative purposes only. Such vertical spaces shown in array structure 1205 may not exist in actual embodiments. In some cases, a portion of the interface between the memory layer and the electrode layer may include other materials, such as as described in reference to FIG. Figure 7 Additional electrode materials described (eg, carbon).

[0183] The array structure 1205 includes memory layers 1220-a and 1220-b corresponding to two respective layers of memory cells. An initial layer stack (e.g., stack 305-a described with reference to FIG. 3) may include one or more memory layers 1220. As part of the initial stack, one or more memory layers 1220 may include a sheet of placeholder material. In some cases, the placeholder material may be a sheet of placeholder material as described with reference to FIG. Figure 5 In some cases, after completing the processing steps to build array structure 1205, memory layer 1220 may include a plurality of memory material elements, each memory material element being in the shape of a 3D wedge as illustrated in diagram 1206.

[0184] Fig.12 Included is a diagram 1206 illustrating an isolated memory layer 1220 that includes sixteen 3D wedge-shaped (e.g., at least two flat surfaces and at least one curved surface) memory material elements, such as memory material element 1235. The 3D wedge-shaped memory material elements 1235-a to 1235-h of diagram 1206 may correspond to the eight 3D wedge-shaped memory material elements as depicted in memory layer 1220-a of array structure 1205.

[0185] Each entire (or substantially entire) 3D wedge-shaped memory material element may include a memory cell 105 and may operate in conjunction with a first access line and a second access line. Thus, an area of ​​the entire memory material element 1235-a (e.g., an area corresponding to a top view of the 3D wedge-shaped memory material element) may be referred to as a cell area 1225 (e.g., cell area 1225-a) and may be located within the memory layer 1220 where a first access line (e.g., word line 1210-a) and a second access line (e.g., bit line 1215-a) intersect in a topological manner. The cell area 1225 may correspond to the intersection 465 described with reference to FIG. 4 (e.g., an area of ​​an intersection associated with an access line width). Additionally, the cell area 1225 may be as described with reference to FIG. Figure 8 An example of cell region 841 or cell region 881 is depicted.

[0186] In addition, the thickness of the cell region 1225 and the memory layer 1220 (e.g., the thickness of the 3D wedge-shaped memory material element 1235-a) can define a cell volume 1226. The cell volume 1226 can refer to the volume of the memory material that serves as the memory cell 105. In some cases, the memory material can include different crystalline phases, and the different crystalline phases can correspond to different logical states. In other cases, the memory material can include different local compositions, and the different local compositions can correspond to different logical states. In some cases, electrical operations associated with access lines (e.g., a voltage difference between a word line and a bit line) can change the crystalline phase of the memory material (or the local composition of the memory material) included in the entire cell volume 1226 (or substantially the entire cell volume 1226). In some cases, the cell volume 1226 of the memory cell 105 can be referred to as the effective cell volume of the memory cell 105.

[0187] Each of the 3D wedge-shaped memory material elements may be physically separated on all sides except the surfaces coupled to the word lines and bit lines (e.g., each of the trenches 1236-a to 1236-d filled with dielectric material as illustrated in FIG. 1206) or as illustrated in reference Figure 7 The intermediate electrode material (e.g., carbon) described surrounds - that is, each 3D wedge-shaped memory material element can be substantially physically confined (e.g., negligible electrical limitation of the effective cell volume). In addition, the area of ​​the 3D wedge-shaped memory material element (e.g., the area corresponding to the top view of the 3D wedge-shaped memory material element 1235) can roughly correspond to the area corresponding to the intersecting access lines (e.g., word lines and bit lines).

[0188] In some cases, a memory cell 105 including memory materials defined by physical limitations of an effective cell volume may be less prone to various non-ideal phenomena (e.g., disturbances) during memory cell operation. For example, a memory cell 105 of array structure 1205 includes an effective cell volume defined by four interfaces that are physically limited (e.g., completely physically limited) and not limited by any (or negligible) interfaces that are electrically limited. In contrast, a memory cell 105 of array structure 1105 includes an effective cell volume defined by three interfaces that are physically limited and one interface that is electrically limited. Thus, a memory cell 105 of array structure 1205 may be less prone to non-ideal phenomena than a memory cell 105 of array structure 1105 (and a memory cell 105 of array structure 1005 or a memory cell 105 of array structure 905).

[0189] Fig.12 Also illustrated is a layout 1207. The layout 1207 may be as described with reference to Figure 8 The example of the layout 805 described herein can illustrate how a via pattern can form one or more 3D wedge-shaped memory material elements within each of a plurality of memory layers (e.g., layers 320-a, 320-b described with reference to FIG. 3). Figure 4A As described, vias (e.g., via 410) may be used to form cavities (e.g., cavity 415) in placeholder materials (e.g., dielectric materials) at a memory layer, and the cavities may be filled with filler materials (e.g., memory materials). Thus, when the filler material is a memory material, a 3D disk of memory material (e.g., chalcogenide material 220) may be formed in a memory layer (e.g., layer 320-a, layer 320-b)—that is, a portion of the placeholder material (e.g., third dielectric material) at a memory layer may be replaced by a disk of memory material (e.g., chalcogenide material 220). Subsequently, the disk of memory material may be cut (e.g., separated) into any number of segments by using a collection of vias to form channels (e.g., channels such as channel 420) at a memory layer, where the channels intersect (and thereby separate, divide, cut the disk of memory material into a plurality of discrete memory material elements). The channels that cut the disk of memory material may be filled with dielectric material.

[0190] In an illustrative example using layout 1207, vias that are common to multiple sets (e.g., columns) of vias (e.g., via 1240-a, like other common vias, which are illustrated as dark shaded vias in layout 1207) can be used to form cavities at each of one or more memory layers (e.g., memory layer 320-a or 320-b), in some cases simultaneously. In other words, the vias can be used to form cavities within a memory layer that includes placeholder material. The size of the cavity can be configured (e.g., by determining an associated via width along with an amount of placeholder material to be removed by an isotropic etching step as described with reference to FIGS. 3-7) so that a portion of the cavity can overlap in the x or z direction with a cross-sectional area of ​​a word line and a bit line (e.g., an area of ​​a topologically intersecting portion of a word line and a bit line), which can be above and below the cavity, respectively, in the y direction. Subsequently, the memory material (e.g., chalcogenide material 220) may fill the cavities, thereby creating a 3D disk 1245 of memory material (e.g., a 3D disk filled with memory material) within each cavity. Thus, the size of each 3D disk 1245 (e.g., 3D disks 1245-a to 1245-d) may account for the size of the cavity that is filled to create the 3D disk 1245.

[0191] Subsequently, one or more sets of first vias can be used to simultaneously form a first number of first trenches filled with dielectric material (e.g., using the techniques described with reference to FIG. 4 ) within a memory layer (e.g., memory layer 320-a or 320-b) that includes a 3D disk 1245 in some cases, each set of first vias being arranged in a row in a vertical direction (z direction)—e.g., any of the groups of five vias 1241-a and 1241-b. Forming the first trenches can include removing a portion of the memory material from each 3D disk 1245 using a corresponding set of first vias. Thus, each of the 3D disks can be separated (e.g., equally divided) into two portions. In other words, the first trenches can separate the 3D disk of memory material into discrete memory material elements at the memory layer along the z-axis.

[0192] In some cases, a portion of the memory material of the 3D disk 1245 of memory material may be removed using a through hole used to form the 3D disk 1245 and the previous cavity before forming the first trench so that a ring of memory material may be formed at the memory layer. The ring of memory material may surround the longitudinal axis (e.g., y-direction, relative to the longitudinal axis of the substrate) of the through hole used to form the 3D disk 1245. Subsequently, forming the first trench may separate (e.g., bisect) the ring of memory material along the z-axis into discrete memory material elements at the memory layer.

[0193] Additionally, one or more sets of second vias may be used to simultaneously form a second number of horizontal trenches filled with dielectric material within the memory layer in some cases (e.g., using the techniques described with reference to FIG. 4 ), with each set of second vias arranged in a row in the horizontal direction (x-direction)—e.g., a group of five vias 1241-c and 1241-d. Forming the second trenches may include removing additional portions of memory material from each 3D disk 1245 using a corresponding set of second vias. Thus, each of the two discrete portions (e.g., segments) of the 3D disk 1245 resulting from forming the corresponding first trenches may be further separated (e.g., bisected) along the x-axis, thereby creating four discrete wedge-shaped memory material elements from each disk 1245 (or ring, as applicable) of memory material. In other words, the second trenches filled with dielectric material further separate (e.g., bisect) the memory material of the 3D disk 1245 filled with memory material along the x-axis into additional discrete memory material elements at the memory layer.

[0194] Thus, using two sets of vias, such as a first set of vias and a second set of vias, to form vertical (z-direction) and horizontal (x-direction) channels filled with dielectric material can divide (e.g., separate, cut, split) each of the 3D disks 1245 into four 3D wedge-shaped memory material elements. Each of the four 3D wedge-shaped memory material elements can have a curved surface, such as layer 1260 as illustrated in FIG. 1206. The curved surface of the memory material can be the result of having a cavity that can have a curved outer surface filled with memory material. Additionally, each of the four 3D wedge-shaped memory material elements can have one or more planarized surfaces, such as surface 1265 as illustrated in FIG. 1206.

[0195] In some cases, a top layer (e.g., layer 310) of a stack (e.g., stack 305-a) may include a pattern of vias, so a set of vias in a two-dimensional matrix, including a set of first vias and a set of second vias, is formed by a photolithography step and an anisotropic etching step that establishes a 2D matrix pattern of vias in the top layer. In some cases, the top layer may include a hard mask material that may preserve the pattern of vias (e.g., vias in a 2D matrix) throughout the various processing steps described as in FIGS. 3-7. Thus, the processing steps for forming the channels may simultaneously form channels (e.g., channels 1236-a to 1236-d filled with dielectric material) in two directions (e.g., horizontal and vertical directions, i.e., x-direction and z-direction) and may produce four 3D wedge-shaped memory material elements (e.g., memory material element 1235) from each of the 3D disks of memory material (e.g., 3D disk 1245). It should be appreciated that the same set of through holes (e.g., a set of first through holes and a set of second through holes) used to form multiple 3D wedge-shaped memory material elements (e.g., memory material element 1235 of FIG. 1206, memory material element 1250-a of layout 1207) can be used in, for example, reference to Figure 8 850 and 855 of the present invention form a set of access lines (e.g., word line 1210 and bit line 1215) at an electrode layer as described in the layout 850 and layout 855 of the present invention. For example, a set of first vias arranged in a row in a horizontal direction (e.g., a group of five vias 1241-c and 1241-d) can be used to separate a 3D disk of memory material at a memory layer (e.g., memory layer 320-a) and form a first number of loops of electrode material at an electrode layer (e.g., electrode layer 315-a or electrode layer 315-b) to form a first access line (e.g., word line 1210).

[0196] Furthermore, each 3D wedge-shaped memory material element (e.g., memory material element 1250-a) of layout 1207 may correspond to an area where a word line (1210-e) and a bit line (e.g., 1215-b) intersect topologically, and the entire (substantially the entire) memory material element may be configured to function as a memory cell 105. Thus, an area corresponding to intersecting access lines (e.g., word line 1210-e and bit line 1215-b) may correspond to (substantially correspond to) a cell area 1225 of array structure 1205. In other words, each wedge-shaped memory material element may support one memory cell 105. Additionally, each wedge-shaped memory material element (e.g., memory material element 1235 or 1250) may be coupled to two electrodes, e.g., word line 1210-e and bit line 1215-b as illustrated in layout 1207 or word line 1210-a and bit line 1215-a as illustrated in array structure 1205. In some cases, each wedge-shaped memory material element may be formed by a conformal liner (e.g., as described in reference Figure 7The carbon-based material described herein is coupled to a first electrode and a second electrode.

[0197] In some cases, a 3D cross-point memory array structure (e.g., using reference Fig.12 The device of the array structure 1205) built by the described manufacturing technology may include: a stack, which includes a first layer, a memory layer and a second layer; a memory layer between the first layer and the second layer; a plurality of first electrodes in the first layer; a plurality of second electrodes in the second layer; and a plurality of memory material elements in the memory layer, each memory material element having a curved surface.

[0198] In some instances of the apparatus described above, each memory material element has a planarized surface. In some instances of the apparatus described above, each memory material element is coupled to a first electrode and a second electrode. In some instances of the apparatus described above, the memory material element is coupled to a first electrode and a second electrode through a conformal liner. In some instances of the apparatus described above, each memory material element is configured to include a single memory cell. In some instances of the apparatus described above, each memory material element includes a chalcogenide material. In some instances of the apparatus described above, each first electrode of the plurality of first electrodes is parallel to each other first electrode of the plurality of first electrodes, and each second electrode of the plurality of second electrodes is parallel to each other second electrode of the plurality of second electrodes.

[0199] Figures 13 to 14 Various aspects of forming a socket according to the manufacturing technique of the present invention are described, which can be used, for example, to manufacture a 3D memory array, such as Figure 2 . In the context of a 3D memory array architecture, a slot area may include a memory array and other components in a memory device (e.g., as described in reference Figure 1 The various interconnections between the row decoder 120, sense component 125, or column decoder 130 described herein. In some cases, the socket region may include features (e.g., gaps) established for electrical isolation purposes (e.g., separating the loop 450 of conductive material into a plurality of distinct sections, which may be configured as access lines).

[0200] The fabrication techniques described herein may include using a subset of patterns of vias (e.g., access vias) where the via patterns may also be used to simultaneously form two or more memory cell layers, each layer including a 3D cross-point structure including access lines and memory cells. A subset of the patterns of vias may be used to separate loops of access line material (e.g., reference Figure 4BThe loop 455 or loop 460 described above (e.g., divided into a plurality of different portions) such that each loop of access line material can form at least two different access lines. In some cases, a subset of vias can also be used to connect the access lines (e.g., word lines, bit lines) to various nodes of other components of the memory device (e.g., row decoder 120, sense component 125, or column decoder 130).

[0201] Fig.13 An exemplary layout 1301 of a socket area of ​​a 3D cross-point memory array that may include two or more memory cell layers according to the present invention is illustrated. Layout 1301 illustrates a 2D matrix of through holes, which includes: groups of first through holes, each group of which is arranged in a row in the horizontal direction (x direction) (e.g., groups of first through holes 1340-a, 1340-b, 1340-c); and groups of second through holes, each group of which is arranged in a row in the vertical direction (y direction) (e.g., groups of second through holes 1341-a, 1341-b, 1341-c). Layout 1301 also illustrates a pattern of first openings (e.g., openings 1350-a to 1350-c) and a pattern of second openings (e.g., openings 1360-a to 1360-b).

[0202] Each group of first vias may be used to form access lines (e.g., word lines 1310-a and word lines 1310-b) extending in a horizontal direction (x-direction) at each first layer of the stack (e.g., layers 315-a and 315-b as described in FIG. 3 ). For example, a group of first vias 1340-a may be used to form word lines 1310-a and word lines 1310-b at each first layer of the stack. Thus, exemplary layout 1301 may depict a slot region for word lines (e.g., access lines extending in a horizontal direction). In some cases, access lines (e.g., bit lines) extending in a vertical direction (y-direction) may not be present in the slot region for word lines. Similarly, slot regions for bit lines may be formed in different regions of a 3D cross-point memory array (not shown) using similar techniques. In some cases, word lines may not be present in the slot region for bit lines.

[0203] The first openings, such as openings 1350-a, can be part of a pattern of first openings established using a first slot mask, such as an SM1 mask. The SM1 mask can be used to form a plurality of first openings (e.g., each opening corresponding to an absence of photoresist or an absence of hard mask material) in a top (e.g., exposed) layer of the stack, which can facilitate formation of structures in one or more lower (e.g., buried) layers of the stack. The stack can include any number of electrode layers and memory layers. The first openings, such as openings 1350-a, can overlap with vias, such as vias 1342-a. As illustrated in layout 1301, the first openings can have relaxed design rules when compared to the first and second vias - for example, the size of the first openings or the distance between the first openings can be larger than the size of the vias or the distance between the vias.

[0204] The first opening may serve as a via with a different geometry for the purpose of socket formation (e.g., serving as a via that is larger than the first or second via), or may isolate one or more of the first or second vias (e.g., making one or more of the first or second vias available for a subsequent processing step while making one or more other first or second vias unavailable for a subsequent processing step). In some cases, the first opening may be used to form a gap in a target electrode by anisotropically etching through the target electrode, thereby dividing the target electrode into two different electrodes (e.g., two different access lines). For example, opening 1350-a may establish a gap in word line 1310-c and word line 1310-d by anisotropically etching through electrode material of word line 1310-c and electrode material of word line 1310-d. Word line 1310-c may be formed using a group of first vias 1340-b, and word line 1310-d may be formed using a group of first vias 1340-c. Word line 1310 - c may be parallel (or substantially parallel) to word line 1310 - d .

[0205] In other cases, a first opening (e.g., opening 1350-a) may facilitate forming a gap in a target electrode by forming a second through-hole through a through-hole (e.g., through-hole 1342-a, which may be included in a group of second through-holes 1341-c) that overlaps the first opening. A second through-hole (e.g., a second through-hole corresponding to through-hole 1342-a) may extend through the stack to a target layer that includes a target electrode having a gap established therein. Subsequently, a portion of the target electrode may be removed, for example, through the second through-hole and through the overlapping first opening using an isotropic etching step. Thus, a target electrode (e.g., an access line at a target layer) may be separated into at least two different sections that are isolated from each other.

[0206] As a result of creating a gap in the target electrode, using a first opening (e.g., opening 1350) to anisotropically etch through the target electrode material at the electrode layer or using the first opening (e.g., opening 1350) to create a second through hole (e.g., a second through hole corresponding to through hole 1342-a) that overlaps the first opening and isotropically etching the target electrode material at the electrode layer (e.g., an electrode layer including the target electrode material), an access line (e.g., an electrode including the target electrode material) can become isolated from a co-linear access line at the electrode layer. For example, word line 1310-c (e.g., an access line) can have at least two segments, namely a left segment (e.g., word line segment 1310-c1) and a right segment (e.g., word line segment 1310-c2) relative to opening 1350-a, and the left segment can be isolated from the right segment and co-linear (e.g., can be a co-linear access line). In some cases, a subset of a plurality of first electrodes (e.g., word lines) can have a common longitudinal axis as a result of creating a gap in the first electrodes.

[0207] The second openings (e.g., openings 1360-a) may be part of a pattern of second openings established using a second slot mask (SM2 mask) that defines a plurality of second openings (e.g., lack of photoresist or lack of hard mask material). The SM2 mask may be used to form a plurality of second openings (e.g., each opening corresponding to a lack of photoresist or lack of hard mask material) in a top (e.g., exposed) layer of the stack, which may facilitate formation of structures in one or more lower (e.g., buried) layers of the stack. The stack may include any number of electrode layers and memory layers. The second openings (e.g., openings 1360-a) may overlap with one or more vias (e.g., vias 1342-b, vias 1342-c) that may be used to form a pair of access lines. For example, vias 1342-b (and vias 1342-c) may be part of a group of first vias (e.g., a group of first vias 1340-b) that may be used to form word lines 1310-c and 1310-e. As illustrated in layout 1301 , the first opening may have a relaxed design rule when compared to the first and second vias—eg, the size of the second opening or the distance between the second openings may be larger than the size of the vias or the distance between the vias.

[0208] In some cases, the second opening can be used to make connections (e.g., interconnects) between multiple access lines (e.g., electrodes) within the stack and a conductive element, which can be positioned below the stack and can be in contact with the stack (e.g., can be in contact with a lowest layer of the stack, which can include an etch stop material, such as a hard mask material). The stack can include an electrode layer and a memory layer, the electrode layer including a target electrode material (e.g., the electrode layer can include an access line, the access line including an electrode material). The conductive element can correspond to a node of a circuit component of the memory device (e.g., an output node of a row decoder 120, an input node of a sensing component 125). In some cases, this circuit component can be placed on a substrate below the stack (e.g., a reference layer). Figure 2 The conductive elements may be connected to circuit components through multiple metal layers and interconnects between the metal layers.

[0209] In some cases, the second opening (e.g., opening 1360-a) may help form a through hole that extends through the stack to the conductive element. The through hole may correspond to a through hole (e.g., through hole 1342-b, through hole 1342-c) that may overlap with the second opening (e.g., opening 1360-a). A conductive material may fill the through hole to form a conductive plug coupled to the conductive element. In addition, the conductive plug may be coupled to a target electrode (e.g., word line, bit line) within the stack, so that the target electrode can be electrically coupled to the conductive element of the circuit component of the memory device through the conductive plug.

[0210] Fig.14 An example method of making a connection between a target electrode and a conductive element at a target layer in a stack according to the manufacturing techniques of the present invention is described. The stack may include a 3D cross-point memory array structure, which may include two or more memory cell layers according to the present invention. As an illustrative example of the manufacturing techniques described herein, Fig.14 Describe Figures 1401, 1402 and 1403. Fig.14 The stack of layers in may correspond to, for example, reference Figure 5 and 6 A stack of stacks described (e.g., stack 305 described with reference to FIG. 3 ). For example, Fig.14 The layer stack in may include two layers of memory cells, and each memory cell layer may include a set of word lines (e.g., word lines 910-a and 910-b of the upper layer 945-a or word lines 910-c and 910-d of the lower layer 945-b) and a set of bit lines (e.g., bit line 915, which may be common to the two layers of memory cells).

[0211] The fabrication techniques described herein may be used to make connections between any target electrode and a conductive element at any target layer in a stack, such as stack 305. For example, FIG. 1401 illustrates making connections between a word line of an upper layer, such as word line 910-a of upper layer 945-a, and a conductive element, such as conductive element 1405, while FIG. 1403 illustrates making connections between a word line of a lower layer, such as word line 910-c of lower layer 945-b, and a conductive element, such as conductive element 1405. Similarly, FIG. 1402 illustrates making connections between a bit line, such as bit line 915, which may be common to both upper layer 945-a and lower layer 945-b, and a conductive element, such as conductive element 1405. In some cases, a socket region for word lines (e.g., a region where connections are made between word lines and conductive elements) may be located in a different area of ​​a 3D cross-point memory array than an area where a socket region for bit lines (e.g., a region where connections are made between bit lines and conductive elements) may be located.

[0212] Diagram 1401 illustrates a method of making a connection between a target electrode, such as target electrode 1416-a at D1 layer 1415-a, and a conductive element, such as conductive element 1405. Target electrode 1416-a may be an example of a word line 910, such as word line 910-a, of an upper layer of a memory cell—for example, the upper layer of a memory cell may be above one or more other layers of memory cells in a memory device.

[0213] At process step 1450, a through hole may be formed through the stack. The through hole may be formed by using a through hole pattern (e.g., as shown in reference Figure 5 and 6 The through hole shape in the HM layer described above is formed by forming a through hole in the HM layer, and the second opening (for example, the through hole shape in the HM layer described above) ... Fig.13 The described opening 1360-a) may overlap with a through hole used to form a through hole. The through hole may extend through the stack to the conductive element 1405. A conductive material may subsequently fill the through hole. In some cases, the conductive material filling the through hole may be the same as the electrode material - for example, the conductive material filling the through hole and the target electrode in the stack may include the same conductive material in some cases. In some cases, the through hole filled with a conductive material may be referred to as a conductive plug (e.g., plug 1421). After the through hole is subsequently formed and filled with a conductive material, the structure illustrated at processing step 1450 of Figure 1401 may correspond to the structure illustrated at processing step 530 of Figure 502.

[0214] At processing step 1455, an etching step may remove a portion of the conductive material from the through-hole to expose a dielectric buffer (e.g., buffer 1430) interposed between the through-hole and the target electrode (e.g., target electrode 1416-a). Subsequently, an etching step (e.g., an isotropic etching step) may remove (e.g., by chemical selectivity) dielectric buffer 1430 to expose the target electrode (e.g., target electrode 1416-a). Removing dielectric buffer 1430 that exposes the target electrode (e.g., target electrode 1416-a) may simultaneously expose a second target electrode (e.g., target electrode 1416-b) within the target electrode layer (e.g., D1 layer 1415-a). In addition, the second target electrode (e.g., target electrode 1416-b) may be located on an opposite side of the through-hole relative to the target electrode (e.g., target electrode 1416-a). For example, the through-holes used to form the through-holes at process step 1450 may have been previously used to form the target electrode and the second target electrode (eg, target electrode 1416-a and target electrode 1416-b, which may be described above with reference to Figure 5 14), and thus the through-hole formed at process step 1450 may be inserted between the target electrode and the second target electrode.

[0215] At process step 1460, the conductive material may fill the space in the through-hole created at process step 1455, thereby coupling the target electrode 1416-a (and the second target electrode 1416-b) with the conductive element 1405 through the conductive plug (e.g., plug 1421-a). Upon completion of process step 1460, the conductive plug 1421-a (e.g., through-hole filled with conductive material) may have a first width (e.g., diameter 1422-a) at the memory layer (e.g., memory layer 1420) and a second width (e.g., diameter 1423-a) at the electrode layer (e.g., D1 layer 1415-a). The second width (e.g., diameter 1423-a) may be greater than the first width (e.g., diameter 1422-a).

[0216] In some cases, upon completion of processing step 1460, a target electrode (e.g., an electrode of a word line of an upper layer of a memory array) may be connected to a node of a circuit component (e.g., a row decoder 120) via a conductive plug (e.g., plug 1421-a), such that a memory controller (e.g., memory controller 140) may activate a target electrode (e.g., word line 910-a) of an upper layer (e.g., upper layer 945-a) of a memory cell.

[0217] Diagram 1402 illustrates a method of making a connection between a target electrode, such as target electrode 1426-a at D2 layer 1425, and a conductive element, such as conductive element 1405. Target electrode 1426-a may be an example of a bit line (or other type of access line), such as bit line 915-a, that is common to both an upper layer and a lower layer of a memory cell—for example, an upper layer of a memory cell may be above one or more other layers of memory cells in a memory device, including a lower layer of memory cells.

[0218] At process step 1451, a through hole can be formed through the stack. The through hole can be formed by using a through hole pattern (e.g., as shown in reference Figure 5 and 6 The through hole shape in the HM layer described above is formed by forming a through hole in the HM layer, and the second opening (for example, the through hole shape in the HM layer described above) ... Fig.13 The described opening 1360-a) may overlap with a through hole for forming a through hole. The through hole may extend through the stack to the conductive element 1405. A conductive material may subsequently fill the through hole. In some cases, the conductive material filling the through hole may be the same as the electrode material - for example, the conductive material filling the through hole and the target electrode in the stack may include the same conductive material in some cases. In some cases, the through hole filled with a conductive material may be referred to as a conductive plug (e.g., plug 1421-b). After the through hole is subsequently formed and filled with a conductive material, the structure illustrated at processing step 1451 of Figure 1402 may correspond to the structure illustrated at processing step 630 of Figure 602. In some cases, processing step 1450 and processing step 1451 may be performed simultaneously - that is, plug 1421 and plug 1421-b may be formed simultaneously.

[0219] At process step 1465, an etching step may remove a portion of the conductive material from the through-holes such that the dielectric layer (e.g., D1 layer 1415-a) may be exposed. Subsequently, a layer of a conformal liner (e.g., liner 1435) may be formed at the exposed surface of the dielectric layer (e.g., D1 layer 1415-a). The conformal liner (e.g., liner 1435) may include any material configured to protect the exposed surface of the dielectric layer (e.g., D1 layer 1415-a) from a subsequent etching step removing the dielectric material of the D1 layer 1415-a. In some cases, if the selectivity associated with the subsequent etching step may be sufficient to retain (substantially retain) the dielectric material of the D1 layer 1415-a, then forming the conformal liner may be omitted.

[0220] At processing step 1470, an etching step may remove additional portions of the conductive material from the through-hole to expose another dielectric buffer (e.g., buffer 1431) interposed between the through-hole and the target electrode (e.g., target electrode 1426-a). Subsequently, an etching step (e.g., an isotropic etching step) may remove (e.g., by chemical selectivity) dielectric buffer 1431 to expose the target electrode (e.g., target electrode 1426-a). Removing dielectric buffer 1431 that exposes the target electrode (e.g., target electrode 1426-a) may simultaneously expose a second target electrode (e.g., target electrode 1426-b) within the target electrode layer (e.g., D2 layer 1425). In addition, the second target electrode (e.g., target electrode 1426-b) may be located on an opposite side of the through-hole relative to the target electrode (e.g., target electrode 1426-a). For example, the through-holes used to form the through-holes at process step 1451 may have been previously used to form the target electrode and the second target electrode (eg, target electrode 1426-a and target electrode 1426-b, which may be described above with reference to Figure 6 1450 and 1451, and thus the through hole formed at process step 1451 may be inserted between the target electrode and the second target electrode.

[0221] At process step 1475, the conductive material may fill the space in the through-hole created at process step 1470, thereby coupling the target electrode 1426-a (and the second target electrode 1426-b) with the conductive element 1405 through the conductive plug (e.g., plug 1421-c). Upon completion of process step 1475, the conductive plug 1421-c (e.g., through-hole filled with conductive material) may have a second width (e.g., diameter 1424) at the memory layer (e.g., memory layer 1420) (e.g., diameter 1422-b or diameter 1422-c) and at the electrode layer (e.g., D2 layer 1425). The second width (e.g., diameter 1424) may be greater than the first width (e.g., diameter 1422-b or diameter 1422-c). In addition, when the processing step 1475 is completed, the conformal liner 1435 can be inserted between the conductive plug 1421-c (e.g., a through hole filled with a conductive material) and the dielectric material (e.g., the first dielectric material of the D1 layer 1415-a). Therefore, the conductive plug 1421-c can have a third width (e.g., diameter 1423-b) at another electrode layer (e.g., D1 layer 1415-a). In some cases, the third width (e.g., diameter 1423-b) can be smaller than the first width (e.g., diameter 1422-a or diameter 1422-b).

[0222] In some cases, upon completion of processing step 1475, a target electrode (e.g., an electrode of a common bit line for the upper and lower layers of the memory array) may be connected to (e.g., coupled to) a node of a circuit component (e.g., column decoder 130) via a conductive plug (e.g., plug 1421-c) such that a memory controller (e.g., memory controller 140) may activate the target electrode (e.g., bit line 915) for both the upper and lower layers of the memory cell.

[0223] Diagram 1403 illustrates a method of making a connection between a target electrode, such as a target electrode 1416-c at another D1 layer 1415-b, and a conductive element, such as conductive element 1405. Target electrode 1416-c may be an example of a word line 910, such as word line 910-c, of a lower layer of a memory cell—for example, the lower layer of a memory cell may be below one or more other layers of memory cells in a memory device.

[0224] Aspects of processing step 1450 of Figure 1403 may be the same as processing step 1450 of Figure 1401. The via structure illustrated in Figure 1401 may then be used to make a connection between target electrode 1416-a at D1 layer 1415-a and conductive element 1405, while the via structure illustrated in Figure 1403 may then be used to make a connection between target electrode 1416-c at D1 layer 1415-b and conductive element 1405.

[0225] At process step 1480, an etching step may remove a portion of the conductive material from the through-holes such that the dielectric layer (e.g., D1 layer 1415-a) may be exposed. The exposed dielectric layer may be the same layer that includes the dielectric buffer 1430 depicted in FIG. 1401. Subsequently, a layer of a conformal liner (e.g., liner 1435) may be formed at the exposed surface of the dielectric buffer (e.g., buffer 1430 at D1 layer 1415-a). The conformal liner (e.g., liner 1435) may include any material configured to protect the exposed surface of the dielectric buffer (e.g., buffer 1430 at D1 layer 1415-a) from removing the dielectric buffer (e.g., buffer 1430 at D1 layer 1415-a) by a subsequent etching step. In some cases, if the selectivity associated with the subsequent etching step may be sufficient to retain (substantially retain) the dielectric buffer (e.g., buffer 1430 at D1 layer 1415-a), then forming the conformal liner may be omitted.

[0226] At processing step 1485, an etching step may remove additional portions of the conductive material from the through-hole to expose another dielectric buffer (e.g., buffer 1432 at D1 layer 1415-b) interposed between the through-hole and the target electrode (e.g., target electrode 1416-c). Subsequently, an etching step (e.g., an isotropic etching step) may remove (e.g., by chemical selectivity) dielectric buffer 1432 to expose the target electrode (e.g., target electrode 1416-c). Removing dielectric buffer 1432 that exposes the target electrode (e.g., target electrode 1416-c) may simultaneously expose a second target electrode (e.g., target electrode 1416-d) within the target electrode layer (e.g., D1 layer 1415-b).

[0227] At process step 1490, the conductive material may fill the space in the through-hole created at process step 1485, thereby coupling the target electrode 1416-c (and the second target electrode 1416-d) with the conductive element 1405 through the conductive plug (e.g., plug 1421-d). Upon completion of process step 1490, the conductive plug 1421-d (e.g., through-hole filled with conductive material) may have a first width (e.g., diameter 1422-d) at the memory layer (e.g., memory layer 1420) and a second width (e.g., diameter 1423-c) at the target electrode layer (e.g., D1 layer 1415-b). The second width (e.g., diameter 1423-c) may be greater than the first width (e.g., diameter 1422-d). In addition, when the processing step 1490 is completed, the conformal liner 1435 can be inserted between the conductive plug 1421-d (e.g., a through hole filled with a conductive material) and the dielectric material (e.g., the dielectric buffer 1430 at the D1 layer 1415-a). Therefore, the conductive plug 1421-d can have a third width (e.g., diameter 1423-d) at another electrode layer (e.g., D1 layer 1415-a). In some cases, the third width (e.g., diameter 1423-d) can be smaller than the first width (e.g., 1422-d).

[0228] In some cases, upon completion of processing step 1490, a target electrode (e.g., an electrode of a word line of a lower layer of a memory array) may be connected to a node of a circuit component (e.g., a row decoder 120) via a conductive plug (e.g., plug 1421-d) so that a memory controller (e.g., memory controller 140) may activate a target electrode (e.g., word line 910-c) of a lower layer (e.g., lower layer 945-b) of a memory cell.

[0229] In some cases, a slot region comprising a 3D cross-point memory array (e.g., using reference Fig.13 and 14An apparatus (or device) constructed using the described manufacturing technology in a slot area may include: a stack including an electrode layer and a memory layer; a conductive element in contact with the stack; a conductive plug extending through the stack and coupled to the conductive element, the conductive plug having a first width at the memory layer and a second width at the electrode layer, the second width being greater than the first width; and a first electrode at the electrode layer, the first electrode being coupled to the conductive plug.

[0230] In some cases, the apparatus described above may further include a second electrode at the electrode layer, the second electrode being coupled to the conductive plug. In some examples of the apparatus described above, the second electrode is isolated from the co-linear electrode at the electrode layer. In some examples of the apparatus described above, the first electrode is parallel to the second electrode.

[0231] In some cases, the apparatus described above may further include a conformal liner at the second electrode layer within the stack, the conformal liner interposed between the conductive plug and the dielectric material. In some examples of the apparatus described above, the dielectric material is interposed between the conformal liner and the third electrode at the second electrode layer.

[0232] Fig.15 A flow chart illustrating a method 1500 for a cross-point memory array and related fabrication techniques according to an embodiment of the invention is shown. The operations of method 1500 may be implemented by, for example, the methods described herein with reference to FIGS.

[0233] At block 1505, a plurality of vias may be formed through a top layer of a stack, the stack comprising a first dielectric material at a first layer. The operations of block 1505 may be performed according to methods described herein. In some examples, aspects of the operations of block 1505 may be performed as part of one or more processes as described with reference to FIGS. 3-8.

[0234] At block 1510, a first trench may be formed in a first dielectric material, the first trench being aligned with a plurality of vias. The operations of block 1510 may be performed according to methods described herein. In some examples, aspects of the operations of block 1510 may be performed as part of one or more processes as described with reference to FIGS. 3-8.

[0235] At block 1515, the first trench may be filled with an electrode material. The operations of block 1515 may be performed according to methods described herein. In certain examples, aspects of the operations of block 1515 may be performed as part of one or more processes as described with reference to FIGS. 3-8.

[0236] At block 1520, a second channel narrower than the first channel may be formed in the electrode material within the first channel. The operations of block 1520 may be performed according to methods described herein. In some examples, aspects of the operations of block 1520 may be performed as part of one or more processes as described with reference to FIGS. 3-8.

[0237] At block 1525, the second trench may be filled with the first dielectric material. The operations of block 1525 may be performed according to methods described herein. In certain examples, aspects of the operations of block 1525 may be performed as part of one or more processes as described with reference to FIGS. 3-8.

[0238] In some cases, an apparatus described herein may perform one or more methods, such as method 1500. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a plurality of vias through a top layer of a stack, the stack comprising a first dielectric material at a first layer; forming a first trench in the first dielectric material, the first trench aligned with the plurality of vias; filling the first trench with an electrode material; forming a second trench narrower than the first trench in the electrode material within the first trench; and filling the second trench with the first dielectric material.

[0239] Some examples of methods 1500 and apparatus described herein may further include operations, features, means, or instructions for forming a conformal liner within the first trench, the conformal liner interposed between the first dielectric material and the electrode material. In some cases, methods 1500 and apparatus described herein may further include operations, features, means, or instructions for forming a plurality of second vias through the top layer of the stack, wherein the plurality of second vias form a second row of vias that intersects the first row of vias formed by the plurality of vias, and wherein the stack includes a second dielectric material at the second layer.

[0240] Some examples of the method 1500 described above may further include operations, features, components, or instructions for forming a third trench in the second dielectric material that may be aligned with the plurality of second vias. Some examples of the method 1500 and apparatus described above may further include operations, features, components, or instructions for: filling the third trench with an electrode material; forming a fourth trench in the electrode material within the third trench that may be narrower than the third trench; and filling the fourth trench with the second dielectric material. In some examples of the method 1500 and apparatus described herein, forming the first trench includes forming a plurality of first cavities in the first dielectric material.

[0241] Some examples of the methods 1500 and apparatus described herein may further include operations, features, components, or instructions for: forming a plurality of first cavities, including removing a portion of a first dielectric material from the first layer through a plurality of vias. In some examples of the methods 1500 and apparatus described above, removing the portion of the first dielectric material includes applying an isotropic etchant that is chemically selective between the first dielectric material and at least one other material in the stack. In some examples of the methods 1500 and apparatus described above, forming a second channel includes forming a plurality of second cavities in the electrode material within the first channel.

[0242] In some examples of the methods 1500 and apparatus described above, forming the plurality of second cavities comprises removing a portion of the electrode material from the first trench through the plurality of through holes. In some examples of the methods 1500 and apparatus described above, removing the portion of the electrode material comprises applying an isotropic etchant that can be chemically selective between the electrode material and at least one other material in the stack. In some examples of the methods 1500 and apparatus described above, the stack further comprises a second layer and a third layer between the first layer and the second layer, the second layer comprising a second dielectric material, the third layer comprising a chalcogenide material. In some examples of the methods described above, filling the second trench with the first dielectric material establishes a loop of the electrode material at the first layer.

[0243] Fig.16 A flow chart illustrating a method 1600 for a cross-point memory array and related fabrication techniques according to an embodiment of the invention is shown. The operations of method 1600 may be implemented by the methods described herein, for example, with reference to FIGS.

[0244] At block 1605, a through-hole extending through a stack to a conductive element may be formed, the stack including a target electrode. The operations of block 1605 may be performed according to methods described herein. In some examples, aspects of the operations of block 1605 may be performed as part of one or more processes as described with reference to FIGS. 3 to 7, 13, and 14.

[0245] At block 1610, the through-holes may be filled with a conductive material. The operations of block 1610 may be performed according to methods described herein. In some examples, aspects of the operations of block 1610 may be performed as part of one or more processes as described with reference to FIGS. 3 to 7, 13, and 14.

[0246] At block 1615, a portion of the conductive material from the through-hole may be removed to expose the dielectric buffer interposed between the through-hole and the target electrode. The operations of block 1615 may be performed according to the methods described herein. In certain examples, aspects of the operations of block 1615 may be performed as part of one or more processes as described with reference to FIGS. 3-7, 13, and 14.

[0247] At block 1620, the dielectric buffer may be removed to expose the target electrode. The operations of block 1620 may be performed according to the methods described herein. In certain examples, aspects of the operations of block 1620 may be performed as part of one or more processes as described with reference to FIGS. 3-7, 13, and 14.

[0248] At block 1625, the through-holes may be filled with a conductive material to couple the target electrode with the conductive element. The operations of block 1625 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1625 may be performed as part of one or more processes as described with reference to FIGS. 3 to 7, 13, and 14.

[0249] In some cases, an apparatus described herein may perform one or more methods, such as method 1600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a through-hole extending through a stack to a conductive element, the stack including a target electrode; filling the through-hole with a conductive material; removing a portion of the conductive material from the through-hole to expose a dielectric buffer inserted between the through-hole and the target electrode; removing the dielectric buffer to expose the target electrode; and filling the through-hole with the conductive material to couple the target electrode with the conductive element.

[0250] In some cases, the methods 1600 and apparatus described herein may further include operations, features, components, or instructions for forming a conformal liner at different electrode layers within the stack. In some cases, the methods 1600 and apparatus described herein may further include operations, features, components, or instructions for forming a gap in the target electrode.

[0251] In some examples of the method 1600 and apparatus described above, removing the dielectric buffer to expose the target electrode simultaneously exposes a second target electrode within the target electrode layer including the target electrode, the second target electrode being on an opposite side of the through-hole relative to the target electrode. In some examples of the method 1600 and apparatus described above, filling the through-hole with a conductive material to couple the target electrode with the conductive element further includes coupling the target electrode with the second target electrode. In some examples of the method 1600 and apparatus described above, forming a gap in the target electrode includes anisotropically etching through the target electrode. In some examples of the method 1600 and apparatus described above, forming a gap in the target electrode includes forming a second through-hole extending through the stack to at least one target layer including the target electrode and isotropically removing a portion of the target electrode through the second through-hole.

[0252] Fig.17 A flow chart illustrating a method 1700 for a cross-point memory array and related fabrication techniques according to an embodiment of the invention is shown. The operations of method 1700 may be implemented by, for example, the methods described herein with reference to FIGS.

[0253] At block 1705, a stack including memory material at the memory layer may be formed. The operations of block 1705 may be performed according to methods described herein. In some examples, aspects of the operations of block 1705 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 9.

[0254] At block 1710, a plurality of through-vias may be formed through the stack. The operations of block 1710 may be performed according to methods described herein. In some examples, aspects of the operations of block 1710 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 9.

[0255] At block 1715, a sheet of memory material perforated by a plurality of dielectric plugs may be formed by filling a plurality of through-holes with dielectric material. The operations of block 1715 may be performed according to methods described herein. In certain examples, aspects of the operations of block 1715 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 9.

[0256] In some cases, the method 1700 may also include forming a plurality of second through-holes through the stack, and filling the plurality of second through-holes with a second dielectric material to form an additional dielectric plug in the memory material sheet. In some cases, the method 1700 may also include: forming a first trench in the dielectric material at the first layer of the stack, the first trench aligned with the plurality of through-holes; forming a second trench in the electrode material within the first trench that may be narrower than the first trench; and filling the second trench with a dielectric material.

[0257] In some cases, the method 1700 may also include: forming a plurality of second through holes through the stack, wherein the plurality of second through holes form a second row of through holes corresponding to a first row of through holes formed by the plurality of through holes in a second direction intersecting the first direction, and wherein the stack includes a second dielectric material at the second layer; forming a third trench in the second dielectric material, the third trench being aligned with the plurality of second through holes; filling the third trench with an electrode material; forming a fourth trench narrower than the third trench in the electrode material within the third trench; and filling the fourth trench with the second dielectric material.

[0258] In some examples of the method 1700 described above, the plurality of through-holes may be arranged in a first linear configuration having a first direction. In some examples of the method 1700 described above, the plurality of second through-holes may be arranged in a second linear configuration having a second direction intersecting the first direction. In some examples of the method 1700 described above, the second direction may be orthogonal to the first direction. In some examples of the method 1700 described above, the memory material sheet includes several rows of dielectric plugs. In some examples of the method 1700 described above, the dielectric plugs may be common to the several rows of dielectric plugs.

[0259] In some examples of the method 1700 described above, forming the first channel includes forming a plurality of first cavities in the dielectric material, wherein adjacent first cavities in the plurality of first cavities merge to form the first channel. In some examples of the method 1700 described above, forming the plurality of first cavities includes removing a portion of the dielectric material from the first layer through a plurality of through holes. In some examples of the method 1700 described above, the memory material includes a chalcogenide material.

[0260] Fig.18 A flow chart illustrating a method 1800 for a cross-point memory array and related fabrication techniques according to an embodiment of the invention is shown. The operations of method 1800 may be implemented by, for example, the methods described herein with reference to FIGS.

[0261] At block 1805, a plurality of first vias may be formed through a top layer of a stack including a memory material at a memory layer, each plurality of first vias being disposed linearly in a first direction. The operations of block 1805 may be performed according to methods described herein. In some examples, aspects of the operations of block 1805 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 10.

[0262] At block 1810, a plurality of second vias may be formed through the top layer of the stack, each plurality of second vias being linearly disposed in a second direction different from the first direction. The operations of block 1810 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1810 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 10.

[0263] At block 1815, a plurality of first channels may be formed in the memory material, each first channel being aligned with a plurality of first vias. The operations of block 1815 may be performed according to methods described herein. In some examples, aspects of the operations of block 1815 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 10.

[0264] At block 1820, a plurality of second channels may be formed in the memory material, each second channel intersecting the plurality of first channels. The operations of block 1820 may be performed according to the methods described herein. In some examples, aspects of the operations of block 1820 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 10.

[0265] At block 1825, the plurality of first trenches and the plurality of second trenches may be filled with a dielectric material. The operations of block 1825 may be performed according to methods described herein. In certain examples, aspects of the operations of block 1825 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 10.

[0266] In some examples of the method 1800 described above, a plurality of second channels are formed while a plurality of memory material elements are formed at the memory layer, each memory material element being coupled to at least four electrodes. In some examples of the method 1800 described above, forming a plurality of first channels includes forming a plurality of first cavities in the memory material, each first cavity corresponding to a first through-hole, wherein adjacent first cavities corresponding to the plurality of first through-holes form a first channel.

[0267] Fig.19 A flow chart illustrating a method 1900 for a cross-point memory array and related fabrication techniques according to an embodiment of the invention is shown. The operations of method 1900 may be implemented by, for example, the methods described herein with reference to FIGS.

[0268] At block 1905, a plurality of first vias may be formed through a top layer of a stack that includes a placeholder material at a placeholder layer. The operations of block 1905 may be performed according to methods described herein. In some examples, aspects of the operations of block 1905 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 11.

[0269] At block 1910, a first channel may be formed in the placeholder material, the first channel being aligned with the plurality of first vias. The operations of block 1910 may be performed according to methods described herein. In some examples, aspects of the operations of block 1910 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 11.

[0270] At block 1915, the first trench may be filled with a memory material. The operations of block 1915 may be performed according to methods described herein. In certain examples, aspects of the operations of block 1915 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 11.

[0271] At block 1920, a second channel narrower than the first channel may be formed in the memory material within the first channel. The operations of block 1920 may be performed according to methods described herein. In some examples, aspects of the operations of block 1920 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 11.

[0272] At block 1925, the second trench may be filled with a dielectric material. The operations of block 1925 may be performed according to methods described herein. In certain examples, aspects of the operations of block 1925 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 11.

[0273] In some cases, the method 1900 may also include forming a third channel at the placeholder layer, wherein the third channel extends in a different direction from the first channel and separates the memory material within the first channel into a plurality of memory material elements.

[0274] In some examples of the method 1900 described above, forming the first channel includes forming a plurality of first cavities in the placeholder material, wherein adjacent first cavities merge to form the first channel. In some examples of the method 1900 described above, forming the plurality of first cavities includes removing a portion of the placeholder material from the placeholder layer through a plurality of first vias. In some examples of the method 1900 described above, forming the second channel includes removing a portion of the memory material from the first channel through the plurality of first vias. In some examples of the method 1900 described above, filling the second channel with a dielectric material creates a band of memory material surrounding the dielectric material in the second channel.

[0275] In some examples of the method 1900 described above, forming the third channel includes forming a plurality of second vias through the top layer of the stack, wherein the plurality of second vias forms a second row of vias that intersects a first row of vias formed by the plurality of first vias. In some examples of the method 1900 described above, each memory material element in the plurality of memory material elements may be coupled to at least three electrodes. In some examples of the method 1900 described above, the memory material includes a chalcogenide material.

[0276] Fig. 20 A flow chart illustrating a method 2000 for a cross-point memory array and related fabrication techniques according to an embodiment of the invention is shown. The operations of method 2000 may be implemented by, for example, the methods described herein with reference to FIGS.

[0277] At block 2005, a via may be formed through the top layer of the stack including the placeholder layer. The operations of block 2005 may be performed according to the methods described herein. In some examples, aspects of the operations of block 2005 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 12.

[0278] At block 2010, a cavity within the placeholder layer may be formed through the via. The operations of block 2010 may be performed according to methods described herein. In some examples, aspects of the operations of block 2010 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 12.

[0279] At block 2015, the cavity may be filled with a memory material. The operations of block 2015 may be performed according to methods described herein. In certain examples, aspects of the operations of block 2015 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 12.

[0280] At block 2020, a first channel may be formed in the memory material, the first channel separating the memory material into discrete elements at the placeholder layer along a first axis. The operations of block 2020 may be performed according to methods described herein. In some examples, aspects of the operations of block 2020 may be performed as part of one or more processes as described with reference to FIGS. 3-7 and 12.

[0281] In some cases, the method 2000 may also include removing a portion of the memory material through the via before forming the first channel to form a ring of memory material at the placeholder layer, the ring of memory material surrounding a longitudinal axis of the via (e.g., an orthogonal direction relative to the substrate). In some cases, the method 2000 may also include forming a second channel in the memory material, the second channel separating the memory material into additional discrete elements at the placeholder layer along a second axis different from the first axis.

[0282] In some examples of the method 2000 described above, forming the first channel includes removing a portion of the memory material from the placeholder layer through a plurality of vias including vias. In some examples of the method 2000 described above, forming the second channel establishes four memory material elements, each memory material element having a curved surface. In some examples of the method 2000 described above, the memory material includes a chalcogenide material.

[0283] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments of the methods may be combined.

[0284] In some cases, an apparatus is described. The apparatus can be formed using a method such as the method described herein. The apparatus can include: an upper layer of a stack, the upper layer including a plurality of holes each having a first width; a first electrode layer within the stack, the first electrode layer including a first electrode and a second electrode; and a dielectric channel aligned with the plurality of holes and separating the first electrode from the second electrode by a first distance greater than the first width. In some examples, the upper layer can include a hard mask material, and in some examples, the first electrode can have at least one dimension less than a minimum feature size.

[0285] In some cases, the apparatus may further include a memory layer within the stack, the memory layer including a thin sheet of memory material perforated by a plurality of dielectric plugs. In some examples, the apparatus may further include: a second electrode layer within the stack, the second electrode layer including a third electrode and a fourth electrode; and a memory layer within the stack, the memory layer including a memory material element coupled to the first electrode, the second electrode, and the third electrode. In some cases, the memory material element may be coupled to the fourth electrode.

[0286] Additionally, in some cases, the apparatus may include a memory layer within the stack, the memory layer including a plurality of memory material elements, each memory material element having a curved surface. In some examples, the apparatus may include: a plurality of second holes in the upper layer, each second hole having a second width; a second electrode layer within the stack, the second electrode layer including a third electrode and a fourth electrode; and a second dielectric channel aligned with the plurality of second holes and separating the third electrode from the fourth electrode by a second distance greater than the second width.

[0287] In some examples, the first electrode and the second electrode are disposed along a first direction; and the third electrode and the fourth electrode are disposed along a second direction. In some cases, the apparatus further includes an adjacent electrode at the first electrode layer, wherein: the second electrode separates the first electrode from the adjacent electrode; and the second electrode is closer to the adjacent electrode than the first electrode. In some examples, the apparatus may further include a conformal liner in contact with multiple surfaces of the first electrode.

[0288] In some cases, an apparatus is described. The apparatus can be formed using a method such as the method described herein. The apparatus can include: a stack including an electrode layer and a memory layer; a conductive element in contact with the stack; a conductive plug extending through the stack and coupled with the conductive element, the conductive plug having a first width at the memory layer and a second width at the electrode layer, the second width being greater than the first width; and a first electrode at the electrode layer, the first electrode coupled with the conductive plug.

[0289] In some cases, the apparatus may further include a second electrode at the electrode layer, the second electrode coupled to the conductive plug. In some cases, the second electrode may be isolated from the co-linear electrode at the electrode layer, and in some cases, the first electrode is parallel to the second electrode. In some examples, the apparatus may further include a conformal liner at the second electrode layer within the stack, the conformal liner interposed between the conductive plug and a dielectric material, wherein the dielectric material is interposed between the conformal liner and a third electrode at the second electrode layer.

[0290] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0291] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components, or may include intermediate components. Components that are in electronic communication or coupled to each other may actively exchange electrons or signals (e.g., in an energized circuit), may not actively exchange electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals when the circuit is energized. As an example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

[0292] As used herein, the term "substantially" means that the modified property (such as a verb or adjective modified by the term substantially) is not necessarily in absolute value but is close enough so as to achieve the advantage of the property.

[0293] As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may be used as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductor, conductive layer, etc. that provides a conductive path between elements or components of memory device 100.

[0294] The chalcogenide material may be a material or alloy containing at least one of the elements S, Se, and Te. The chalcogenide material may include alloys of S, Se, Te, Ge, As, Al, Si, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include (but are not limited to): Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge -As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te- Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, hyphenated chemical composition designations indicate elements included in a particular compound or alloy and are intended to represent all stoichiometric amounts involving the indicated elements. For example, Ge-Te may include Ge x Te y, where x and y may be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxides including two or more metals (e.g., transition metals, alkaline earth metals, and / or rare earth metals). Embodiments are not limited to a particular variable resistance material associated with a memory component of a memory cell. For example, other examples of variable resistance materials may be used to form a memory component and may include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, among others.

[0295] The term "isolation" refers to a relationship between components between which electrons cannot currently flow; components are isolated from each other when there is a break between them. For example, two components physically connected by a switch can be isolated from each other when the switch is open.

[0296] The devices discussed herein, including memory device 100, may be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0297] One or more transistors discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include a heavily doped (e.g., metamorphic) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0298] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "preferred" or "superior to other examples". The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0299] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0300] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0301] The various illustrative blocks and modules described in connection with the present invention may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0302] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or program codes. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Moreover, as used herein (included in the claims), "or" indicates an inclusive list when used in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of"), such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be considered as a reference to a closed conditional set. For example, without departing from the scope of the present invention, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0303] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer, or a general or special processor. Any other non-transitory media. Moreover, any connection is properly referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0304] The description herein is provided to enable one skilled in the art to make or use the invention. Various modifications to the invention will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but should be consistent with the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for semiconductor manufacturing, comprising: forming a through hole extending through a stack to a conductive element, the stack including a first electrode; Filling the through hole with a conductive material; removing a portion of the conductive material from the through-hole to expose a dielectric buffer interposed between the through-hole and the first electrode; removing the dielectric buffer to expose the first electrode; as well as The through hole is filled with the conductive material to couple the first electrode with the conductive element, wherein the conductive material includes a conductive plug. 2 . The method of claim 1 , wherein the dielectric buffer is removed to expose the first electrode while exposing a second electrode at an electrode layer including the first electrode, the second electrode being on an opposite side of the through hole relative to the first electrode.

3. The method according to claim 2, wherein filling the through hole with the conductive material to couple the first electrode with the conductive element further comprises: The first electrode is coupled to the second electrode.

4. The method of claim 1 , wherein the first electrode is an electrode layer within the stack, further comprising: A conformal liner is formed at different electrode layers within the stack.

5. The method according to claim 1, further comprising: A gap is formed in the first electrode.

6. The method of claim 5, wherein forming the gap in the first electrode comprises: Anisotropic etching is performed through the first electrode.

7. The method of claim 5, wherein forming the gap in the first electrode comprises: forming a second through hole extending through the stack to at least one target layer including the first electrode; as well as A portion of the first electrode is isotropically removed through the second through hole. The method of claim 1 , wherein the conductive material and the first electrode comprise the same material.

9. The method of claim 1 , wherein removing the dielectric buffer comprises: The isotropic etch is performed on the dielectric buffer based at least in part on a chemical selectivity of the isotropic etch.

10. A memory device comprising: a stack comprising an electrode layer and a memory layer; a conductive element in contact with the stack; a conductive plug extending through the stack and coupled to the conductive element, the conductive plug having a first width at the memory layer and a second width at the electrode layer, the second width being greater than the first width; and A first electrode is located at the electrode layer, and the first electrode is coupled to the conductive plug.

11. The memory device of claim 10, further comprising: A second electrode is located at the electrode layer, and the second electrode is coupled to the conductive plug. 12 . The memory device of claim 11 , wherein the second electrode is isolated from a common-line electrode at the electrode layer.

13. The memory device of claim 11, wherein the first electrode is parallel to the second electrode.

14. The memory device of claim 10, further comprising: A conformal liner is located at the second electrode layer within the stack, the conformal liner being interposed between the conductive plug and the dielectric material.

15. The memory device of claim 14, wherein the dielectric material is interposed between the conformal liner and a third electrode at the second electrode layer. 16 . The memory device of claim 10 , wherein the conductive plug and the first electrode comprise a same material.

17. The memory device of claim 10, wherein the first electrode comprises a gap.

18. The memory device of claim 17, wherein the gap segments the first electrode into a first access line and a second access line.

19. A memory device comprising: a stack comprising an electrode layer and a memory layer; a conductive element in contact with the stack; a conductive plug extending through the stack and coupled to the conductive element, the conductive plug being formed by filling a through hole extending through the stack to the conductive element with a conductive material; as well as A first electrode is located at the electrode layer, and the first electrode is coupled to the conductive plug by removing a portion of the conductive material from the through hole to expose a dielectric buffer inserted between the through hole and the first electrode, removing the dielectric buffer to expose the first electrode, and filling the through hole with the conductive material, wherein the conductive material includes the conductive plug.

20. The memory device of claim 19, further comprising: A second electrode is located at the electrode layer, the second electrode is coupled to the conductive plug, wherein the dielectric buffer is removed to expose the first electrode while exposing the second electrode at the electrode layer including the first electrode, the second electrode is on the opposite side of the through hole relative to the first electrode.

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