Display mother board, preparation method of display panel and display panel

Abstract

The embodiment of the invention provides a display mother board, a preparation method of a display panel and the display panel, the display mother board comprises a plurality of display units and cutting lines, each display unit comprises a display area and a non-display area at least partially surrounding the display area, and the non-display area comprises a first clock signal group, a second clock signal group and connecting lines. Each of the first clock signal group and the second clock signal group comprises a plurality of clock signal lines, the plurality of clock signal lines in the first clock signal group are located on the same side of the second clock signal group, and the second clock signal group further comprises a short-circuit line electrically connected with the two clock signal lines in the group; the clock signal lines in the at least one first clock signal group are electrically connected with the clock signal lines in the at least one second clock signal group through connecting lines.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display motherboard, a method for preparing a display panel, and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a display motherboard, a method for preparing a display panel, and a display panel, aiming to improve the performance of the display motherboard.

[0005] An embodiment of the first aspect of the present application provides a display motherboard, which includes multiple display units, the display unit includes a display area and a non-display area that at least partially surrounds the display area, the non-display area includes a first clock signal group, a second clock signal group and a connecting line, the first clock signal group and the second clock signal group each include multiple clock signal lines, the multiple clock signal lines in the first clock signal group are located on the same side of the second clock signal group, the second clock signal group also includes a short-circuit line that electrically connects two clock signal lines in the group, and at least one clock signal line in the first clock signal group and at least one clock signal line in the second clock signal group are electrically connected via the connecting line.

[0006] According to an implementation of the first aspect of the present application, at least two of the clock signal lines in the second clock signal group are electrically connected through the short-circuit line, and are electrically connected to the two clock signal lines in the first clock signal group through the two connecting lines.

[0007] According to an implementation of the first aspect of the present application, the number of connecting lines, the clock signal lines of the first clock signal group, and the clock signal lines of the second clock signal group are the same and correspond one to one.

[0008] According to an implementation manner of the first aspect of the present application, the first clock signal group includes a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; the second clock signal group includes a fifth clock signal line, a sixth clock signal line, a seventh clock signal line and an eighth clock signal line; the connecting line includes a first connecting line, a second connecting line, a third connecting line and a fourth connecting line, the first connecting line connects the first clock signal line and the fifth clock signal line, the second connecting line connects the second clock signal line and the sixth clock signal line, the third connecting line connects the third clock signal line and the seventh clock signal line, and the fourth connecting line connects the fourth clock signal line and the eighth clock signal line.

[0009] According to an implementation of the first aspect of the present application, the short-circuit line includes a first short-circuit line and a second short-circuit line, the first short-circuit line electrically connects the fifth clock signal line and the seventh clock signal line, and the second short-circuit line electrically connects the sixth clock signal line and the eighth clock signal line.

[0010] According to an implementation of the first aspect of the present application, along a direction away from the display area, the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are arranged in sequence.

[0011] According to an implementation of the first aspect of the present application, along a direction away from the display area, the fifth clock signal line, the sixth clock signal line, the seventh clock signal line and the eighth clock signal line are arranged in sequence.

[0012] According to an implementation scheme of the first aspect of the present application, the second clock signal group is located on a side of the first clock signal group away from the display area; optionally, the non-display area includes a first sub-area and a binding area, the first clock signal group and the second clock signal group are both located in the first sub-area, the first sub-area and the binding area are respectively located on both sides of the display area in a first direction, and the first direction is arranged to intersect with the thickness direction of the display motherboard.

[0013] An embodiment of the second aspect of the present application also provides a method for preparing a display panel, comprising the following steps: providing a display motherboard as provided in any of the above-mentioned embodiments of the first aspect; cutting the display motherboard along a preset cutting line, wherein the preset cutting line is located between adjacent display units or between a first clock signal group and a second clock signal group within the same display unit.

[0014] The embodiment of the third aspect of the present application further provides a display panel, which is prepared by the preparation method provided by the embodiment of the second aspect above.

[0015] In the display motherboard provided in the embodiment of the present application, the display motherboard includes multiple display units, the display unit includes a display area and a non-display area that at least partially surrounds the display area, the non-display area includes a first clock signal group, a second clock signal group and a connecting line, the first clock signal group and the second clock signal group each include multiple clock signal lines, the multiple clock signal lines in the first clock signal group are located on the same side of the second clock signal group, the second clock signal group also includes a short-circuit line that electrically connects two clock signal lines in the group, and at least one clock signal line in the first clock signal group and at least one clock signal line in the second clock signal group are electrically connected via the connecting line. The present application sets two clock signal groups in the display unit, and the display motherboard can select the cutting line as needed. When the connecting line between the two clock signal groups is cut so that the display unit only retains the first clock signal group, the number of clock signal lines actually possessed by the cut display unit is the same as the number of clock signal lines in the first clock signal group. When the unit retains two clock signal groups after cutting, since at least one connecting line connects the clock signal lines in the two clock signal groups, the second clock signal group includes at least one short-circuit line connecting the two clock signal lines in the group. The number of clock signal lines actually possessed by the cut display unit is less than the number of clock signal lines in the first clock signal group, so that the display motherboard can be used to prepare display units containing different numbers of clock signal lines, thereby improving the application scope and performance of the display motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0017] Figure 1 is a top view of a display motherboard provided in an embodiment of the present application;

[0018] Figure 2 is a top view of an exemplary display unit;

[0019] Figure 3 It is an example Figure 2 A schematic diagram of a local enlarged structure at position A;

[0020] Figure 4 Another example is Figure 2 A schematic diagram of a local enlarged structure at position A;

[0021] Figure 5 is a top view of another exemplary display unit.

[0022] Description of reference numerals:

[0023] 10. Display motherboard; 20. Display unit; 101. Clock signal line;

[0024] 100, first clock signal group; 110, first clock signal line; 120, second clock signal line; 130, third clock signal line; 140, fourth clock signal line;

[0025] 200, second clock signal group; 210, short-circuit line; 211, first short-circuit line; 212, second short-circuit line; 220, fifth clock signal line; 230, sixth clock signal line; 240, seventh clock signal line; 250, eighth clock signal line;

[0026] 300, connecting line; 310, first connecting line; 320, second connecting line; 330, third connecting line; 340, fourth connecting line;

[0027] AA, display area; NA, non-display area; NA1, first sub-area; BA, binding area;

[0028] C1, first cutting line; C2, second cutting line;

[0029] x, first direction; y, second direction. DETAILED DESCRIPTION

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0031] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0032] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0033] In order to better understand this application, Figures 1 to 5 The display motherboard, the display panel manufacturing method and the display device of the embodiment of the present application are described in detail, wherein the x direction is the first direction and the y direction is the second direction.

[0034] Please also read Figures 1 to 3 , Figure 1 is a top view of a display motherboard provided in an embodiment of the present application; Figure 2 is a top view of an exemplary display unit; Figure 3 It is an example Figure 2 Schematic diagram of the local enlarged structure at position A.

[0035] like Figures 1 to 3 As shown, an embodiment of the first aspect of the present application provides a display motherboard 10, the display motherboard 10 includes a plurality of display units 20, the display unit 20 includes a display area AA and a non-display area NA that at least partially surrounds the display area AA, the non-display area NA includes a first clock signal group 100, a second clock signal group 200 and a connecting line 300, the first clock signal group 100 and the second clock signal group 200 both include a plurality of clock signal lines 101, the plurality of clock signal lines 101 in the first clock signal group 100 are located on the same side of the second clock signal group 200, the second clock signal group 200 also includes a short-circuit line 210 electrically connecting two clock signal lines 101 in the group, and at least one clock signal line 101 in the first clock signal group 100 and at least one clock signal line 101 in the second clock signal group 200 are electrically connected via the connecting line 300.

[0036] Optionally, the display unit 20 also includes a pixel circuit (not shown) and a gate drive circuit GIP, the gate drive circuit GIP can be used to provide a scan signal SCAN for the pixel circuit, and the clock signal line 101 can be used to provide a clock signal for the gate drive circuit GIP. It should be noted that when the clock signal lines 101 in a clock signal group are insulated from each other, the low-potential pulses output by each clock signal line 101 to the gate drive circuit GIP do not overlap, and the initial pulses appear in sequence. Therefore, when the number of clock signal lines 101 insulated from each other in the clock signal group increases, the refresh rate of the display unit 20 increases, the display is smoother, and the display effect is better. When the number of clock signal lines 101 insulated from each other in the clock signal group decreases, the refresh rate of the display unit 20 decreases, the energy consumption is also lower, and the display unit 20 is more energy-saving and power-saving. In this embodiment, the clock signal line 101 in the first clock signal group 100 is electrically connected to the gate drive circuit GIP, and the clock signal line 101 in the second clock signal group 200 can only be indirectly connected to the gate drive circuit GIP through the connecting line 300 and the clock signal line 101 in the first clock signal group 100.

[0037] Optionally, at least two clock signal lines 101 in the second clock signal group 200 are electrically connected through the short-circuit line 210, and are electrically connected to the two clock signal lines 101 in the first clock signal group 100 through two connecting lines 300. When the gap between the first clock signal group 100 and the second clock signal group 200 in the same display unit 20 is used as a cutting line (the first cutting line C1 in the figure), the cutting line simultaneously cuts off the connecting line 300 between the first clock signal group 100 and the second clock signal group 200. When the display unit 20 includes only the first clock signal group 100 after cutting, the clock signal lines 101 in the first clock signal group 100 are insulated, and the number of clock signal lines actually possessed by the display unit 20 is equal to the number of clock signal lines 101 in the first clock signal group 100. When the gap between adjacent display units 20 is used as a cutting line (the second cutting line C2 in the figure), when the display unit 20 includes a first clock signal group 100 and a second clock signal group 200, since at least two clock signal lines 101 in the first clock signal group 100 are respectively connected to the clock signal lines 101 in the second clock signal group 200 through the connecting line 300, and then electrically connected through the short-circuit line 210, it is equivalent to at least two clock signal lines 101 in the first clock signal group 100 being short-circuited, and the actual number of clock signal lines possessed by the display unit 20 is less than the number of clock signal lines 101 in the first clock signal group 100. Therefore, the display motherboard 10 in the present application can be cut according to the demand, so that the cut display unit 20 can include the first clock signal group 100, the second clock signal group 200, or only the first clock signal group 100, so that the cut display unit 20 has different numbers of clock signal lines 101, and the refresh rate and energy consumption are also different.

[0038] The display motherboard 10 provided in the present application, by setting two clock signal groups in the display unit 20, the display motherboard 10 can select the cutting line as needed, when the connecting line between the two clock signal groups is cut so that the display unit 20 only retains the first clock signal group, the number of clock signal lines 101 actually possessed by the cut display unit 20 is the same as the number of clock signal lines 101 in the first clock signal group 100, when the cut display unit 20 retains two clock signal groups, because at least one connecting line 300 connects the clock signal lines 101 in the two clock signal groups, the second clock signal group 200 includes at least one short-circuit line 210 connecting the two clock signal lines 101 in the group, the number of clock signal lines 101 actually possessed by the cut display unit 20 is less than the number of clock signal lines 101 in the first clock signal group 100, so that the display motherboard 10 can prepare display units 20 containing different numbers of clock signal lines 101, thereby improving the application range and performance of the display motherboard 10.

[0039] In some optional embodiments, the number of the connecting lines 300 , the clock signal lines 101 of the first clock signal group 100 , and the clock signal lines 101 of the second clock signal group 200 are the same and correspond one to one.

[0040] Optionally, each clock signal line 101 in the first clock signal group 100 is electrically connected to a clock signal line 101 in the second clock signal group 200 via a connecting line 300. The number of short-circuit lines 210 is half the number of clock signal lines 101 in the second clock signal group 200, and the clock signal lines 101 in the second clock signal group 200 are electrically connected to each other via short-circuit lines 210.

[0041] Optionally, the number of clock signal lines 101 in the first clock signal group 100 is 4 or more.

[0042] Please refer to Figure 3 and Figure 4 , Figure 3 It is an example Figure 2 A schematic diagram of a local enlarged structure at position A; Figure 4 Another example is Figure 2 A schematic diagram of the local enlarged structure at position A. Among them, Figure 3 The display unit is obtained by cutting along the second cutting line, Figure 4 The display unit is obtained by cutting along a first cutting line.

[0043] In some optional embodiments, the first clock signal group 100 includes a first clock signal line 110, a second clock signal line 120, a third clock signal line 130, and a fourth clock signal line 140. The second clock signal group 200 includes a fifth clock signal line 220, a sixth clock signal line 230, a seventh clock signal line 240, and an eighth clock signal line 250. The connecting line 300 includes a first connecting line 310, a second connecting line 320, a third connecting line 330, and a fourth connecting line 340, wherein the first connecting line 310 connects the first clock signal line 110 and the fifth clock signal line 220, the second connecting line 320 connects the second clock signal line 120 and the sixth clock signal line 230, the third connecting line 330 connects the third clock signal line 130 and the seventh clock signal line 240, and the fourth connecting line 340 connects the fourth clock signal line 140 and the eighth clock signal line 250.

[0044] Optionally, the short-circuit line 210 includes a first short-circuit line 211 and a second short-circuit line 212 , wherein the first short-circuit line 211 electrically connects the fifth clock signal line 220 and the seventh clock signal line 240 , and the second short-circuit line 212 electrically connects the sixth clock signal line 230 and the eighth clock signal line 250 .

[0045] Optionally, along a direction away from the display area AA, the first clock signal line 110, the second clock signal line 120, the third clock signal line 130 and the fourth clock signal line 140 are arranged in sequence.

[0046] Optionally, along a direction away from the display area AA, the fifth clock signal line 220 , the sixth clock signal line 230 , the seventh clock signal line 240 and the eighth clock signal line 250 are arranged in sequence.

[0047] The display motherboard 10 provided by the present application has the first clock signal group 100 including four clock signal lines 101. When the display unit 20 is cut along the first cutting line C1 (eg Figure 4 As shown in FIG. 1 ), the connecting line 300 is cut, and the four clock signal lines 101 in the first clock signal group 100 are insulated from each other. Then, the number of clock signal lines 101 actually possessed by the cut display unit 20 is 4. When the display unit 20 is cut by the second cutting line C2 (as shown in FIG. 1 ), the connecting line 300 is cut, and the four clock signal lines 101 in the first clock signal group 100 are insulated from each other. Figure 3 As shown), the connecting line 300 and the second clock signal group 200 are retained. Due to the electrical connection between the first short-circuit line 211, the second short-circuit line 212 and the connecting line 300, the first clock signal line 110 and the third clock signal line 130 in the first clock signal group 100 are short-circuited, and the second clock signal line 120 and the fourth clock signal line 14 are short-circuited. Then, the number of clock signal lines 101 actually possessed by the display unit 20 after being cut is 2.

[0048] Please refer to Figure 3 and Figure 5 , Figure 5 is a top view of another exemplary display unit.

[0049] like Figure 3 and Figure 5 As shown, in some optional embodiments, the second clock signal group 200 is located on a side of the first clock signal group 100 away from the display area AA.

[0050] Optionally, the non-display area NA includes a first sub-area NA1 and a binding area BA, the first clock signal group 100 and the second clock signal group 200 are both located in the first sub-area NA1, the first sub-area NA1 and the binding area BA are respectively located on both sides of the display area AA in a first direction (x direction in the figure), and the first direction x is arranged to intersect with the thickness direction of the display motherboard 10.

[0051] Optionally, the first direction x is a pixel column direction, that is, the first sub-area NA1 is an upper frame area of ​​the display unit 20. The second direction y is a pixel row direction, and at least part of the gate driving circuit GIP is located in the non-display area NA on both sides of the display area AA in the second direction y, that is, at least part of the gate driving circuit GIP is located in the left and right frame areas of the display unit 20.

[0052] Optionally, the clock signal line 101 , the first cutting line C1 , and the second cutting line C2 all extend along the second direction y, and the connecting line 300 and the short-circuit line 210 extend along the first direction x.

[0053] The display motherboard 10 provided in the present application is beneficial to the consistency of the frame size around the display unit 20 by locating the first clock signal group 100 and the second clock signal group 200 on the upper frame of the display unit 20, and the gate drive circuit GIP on the left and right frames of the display unit 20, and the other wiring harnesses in the binding area BA on the lower frame are dispersedly arranged.

[0054] The second aspect of the present application also provides a method for preparing a display panel, comprising the following steps:

[0055] Step S01: provide a display motherboard 10 according to any one of the first aspect embodiments described above.

[0056] Step S02 , cutting the display motherboard 10 along a preset cutting line, where the preset cutting line is located between adjacent display units 20 or between the first clock signal group 100 and the second clock signal group 200 in the same display unit 20 .

[0057] The embodiment of the third aspect of the present application also provides a display panel, which is prepared by the preparation method of the embodiment of the second aspect. Since the display panel provided by the embodiment of the third aspect of the present application is prepared by the preparation method of the embodiment of the second aspect, the display panel provided by the embodiment of the third aspect of the present application has the beneficial effects of the second embodiment, which will not be repeated here.

[0058] The display panel in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles and other devices with display functions.

[0059] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display motherboard, characterized in that: include: A plurality of display units, wherein the display units include a display area and a non-display area at least partially surrounding the display area, the non-display area includes a first clock signal group, a second clock signal group and a connecting line, the first clock signal group and the second clock signal group each include a plurality of clock signal lines, the plurality of clock signal lines in the first clock signal group are located on the same side of the second clock signal group, the second clock signal group also includes a short-circuit line electrically connecting two of the clock signal lines in the group, and at least one of the clock signal lines in the first clock signal group and at least one of the clock signal lines in the second clock signal group are electrically connected via the connecting line.

2. The display panel according to claim 1, characterized in that: At least two of the clock signal lines in the second clock signal group are electrically connected through the short-circuit line, and are also electrically connected to the two clock signal lines in the first clock signal group through the two connecting lines.

3. The display panel according to claim 2, characterized in that: The connecting lines, the clock signal lines of the first clock signal group, and the clock signal lines of the second clock signal group are all the same in number and correspond one to one.

4. The display panel according to claim 3, characterized in that: The first clock signal group includes a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line which are independent of each other; The second clock signal group includes a fifth clock signal line, a sixth clock signal line, a seventh clock signal line and an eighth clock signal line; The connecting wires include a first connecting wire, a second connecting wire, a third connecting wire and a fourth connecting wire, the first connecting wire connects the first clock signal wire and the fifth clock signal wire, the second connecting wire connects the second clock signal wire and the sixth clock signal wire, the third connecting wire connects the third clock signal wire and the seventh clock signal wire, and the fourth connecting wire connects the fourth clock signal wire and the eighth clock signal wire.

5. The display panel according to claim 4, characterized in that: The short-circuit line includes a first short-circuit line and a second short-circuit line, the first short-circuit line electrically connects the fifth clock signal line and the seventh clock signal line, and the second short-circuit line electrically connects the sixth clock signal line and the eighth clock signal line.

6. The display panel according to claim 4, characterized in that: Along a direction away from the display area, the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are arranged in sequence.

7. The display panel according to claim 4, characterized in that: Along a direction away from the display area, the fifth clock signal line, the sixth clock signal line, the seventh clock signal line and the eighth clock signal line are arranged in sequence.

8. The display panel according to claim 2, characterized in that: The second clock signal group is located at a side of the first clock signal group away from the display area; Optionally, the non-display area includes a first sub-area and a binding area, the first clock signal group and the second clock signal group are both located in the first sub-area, the first sub-area and the binding area are respectively located on both sides of the display area in a first direction, and the first direction is intersected with the thickness direction of the display motherboard.

9. A method for preparing a display panel, characterized in that: The steps include: Providing a display motherboard as claimed in any one of claims 1 to 8; The display motherboard is cut along a preset cutting line, where the preset cutting line is located between adjacent display units or between the first clock signal group and the second clock signal group in the same display unit.

10. A display panel, characterized in that: The method according to claim 9 is used to prepare the present invention.

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